From dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f Mon Sep 17 00:00:00 2001
From: Ataberk <olgunataberk@gmail.com>
Date: Sun, 25 Sep 2022 17:22:03 +0200
Subject: Initial commit

---
 projects/U200/U200.hw/U200.lpr                     |      6 +
 projects/U200/U200.ip_user_files/README.txt        |      1 +
 .../axis_clock_converter/axis_clock_converter.veo  |     78 +
 .../axis_clock_converter/axis_clock_converter.vho  |    101 +
 .../axis_clock_converter_stub.v                    |     35 +
 .../axis_clock_converter_stub.vhdl                 |     43 +
 .../ip/instr_blk_mem/instr_blk_mem.veo             |     70 +
 .../ip/instr_blk_mem/instr_blk_mem.vho             |     85 +
 .../ip/instr_blk_mem/instr_blk_mem_stub.v          |     25 +
 .../ip/instr_blk_mem/instr_blk_mem_stub.vhdl       |     35 +
 .../ip/instr_blk_mem_sim/instr_blk_mem_sim.veo     |     70 +
 .../ip/instr_blk_mem_sim/instr_blk_mem_sim.vho     |     85 +
 .../ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v  |     25 +
 .../instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl  |     35 +
 .../U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo    |    116 +
 .../U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho    |    177 +
 .../U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v |     76 +
 .../ip/phy_ddr4/phy_ddr4_stub.vhdl                 |     79 +
 .../ip/phy_ddr4_udimm/phy_ddr4_udimm.veo           |    115 +
 .../ip/phy_ddr4_udimm/phy_ddr4_udimm.vho           |    175 +
 .../ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v        |     76 +
 .../ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl     |     79 +
 .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo     |    117 +
 .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho     |    179 +
 .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v  |     77 +
 .../phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl  |     80 +
 .../ip/pr_read_mem/pr_read_mem.veo                 |     70 +
 .../ip/pr_read_mem/pr_read_mem.vho                 |     85 +
 .../ip/pr_read_mem/pr_read_mem_stub.v              |     25 +
 .../ip/pr_read_mem/pr_read_mem_stub.vhdl           |     35 +
 .../ip/pr_ref_mem/pr_ref_mem.veo                   |     70 +
 .../ip/pr_ref_mem/pr_ref_mem.vho                   |     85 +
 .../ip/pr_ref_mem/pr_ref_mem_stub.v                |     25 +
 .../ip/pr_ref_mem/pr_ref_mem_stub.vhdl             |     35 +
 .../ip/rdback_fifo/rdback_fifo.veo                 |     77 +
 .../ip/rdback_fifo/rdback_fifo.vho                 |     99 +
 .../ip/rdback_fifo/rdback_fifo_stub.v              |     33 +
 .../ip/rdback_fifo/rdback_fifo_stub.vhdl           |     42 +
 .../ip/scratchpad/scratchpad.veo                   |     70 +
 .../ip/scratchpad/scratchpad.vho                   |     85 +
 .../ip/scratchpad/scratchpad_stub.v                |     25 +
 .../ip/scratchpad/scratchpad_stub.vhdl             |     35 +
 projects/U200/U200.ip_user_files/ip/xdma/xdma.veo  |     95 +
 projects/U200/U200.ip_user_files/ip/xdma/xdma.vho  |    135 +
 .../U200/U200.ip_user_files/ip/xdma/xdma_stub.v    |     56 +
 .../U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl |     60 +
 .../ip/zq_calib_mem/zq_calib_mem.veo               |     70 +
 .../ip/zq_calib_mem/zq_calib_mem.vho               |     85 +
 .../ip/zq_calib_mem/zq_calib_mem_stub.v            |     25 +
 .../ip/zq_calib_mem/zq_calib_mem_stub.vhdl         |     35 +
 .../hdl/axis_clock_converter_v1_1_vl_rfs.v         |   1198 +
 .../ipstatic/hdl/axis_infrastructure_v1_1_0.vh     |    337 +
 .../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v |   1324 +
 .../ipstatic/hdl/fifo_generator_v13_2_rfs.v        |   7777 ++
 .../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd      |  18837 +++
 .../hdl/gtwizard_ultrascale_v1_7_bit_sync.v        |     88 +
 .../hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v    |    608 +
 .../gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v   |    224 +
 .../hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v  |    748 +
 .../gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v   |    224 +
 .../hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v  |    346 +
 .../gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v   |   1091 +
 .../gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v   |   1175 +
 ...twizard_ultrascale_v1_7_gthe4_delay_powergood.v |    170 +
 .../gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v |    245 +
 .../gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v |    258 +
 .../hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v     |    766 +
 .../gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v    |    140 +
 .../gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v    |    140 +
 .../gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v   |    219 +
 .../gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v   |    249 +
 .../gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v   |    224 +
 .../hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v  |    346 +
 .../gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v   |   1091 +
 .../gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v   |   1175 +
 ...twizard_ultrascale_v1_7_gtye4_delay_powergood.v |    170 +
 .../hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v  |     98 +
 .../hdl/gtwizard_ultrascale_v1_7_reset_sync.v      |     98 +
 .../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd          |  10899 ++
 .../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd              |   1263 +
 .../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd |   4463 +
 .../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd           |    288 +
 .../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd       | 130122 ++++++++++++++++++
 .../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd    |   1646 +
 .../hdl/verilog/axi_infrastructure_header.vh       |    138 +
 .../ipstatic/hdl/verilog/axidma_fifo.vh            |   1287 +
 .../ipstatic/hdl/verilog/dma_defines.svh           |    387 +
 .../ipstatic/hdl/verilog/dma_defines.vh            |     33 +
 .../ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh   |     35 +
 .../ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh   |     35 +
 .../ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh   |     35 +
 .../ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh   |     35 +
 .../ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh  |     42 +
 .../ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh    |     20 +
 .../ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh   |     28 +
 .../hdl/verilog/dma_pcie_fabric_input_if.svh       |     29 +
 .../hdl/verilog/dma_pcie_fabric_output_if.svh      |     64 +
 .../ipstatic/hdl/verilog/dma_pcie_gic_if.svh       |     13 +
 .../ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh  |     42 +
 .../verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh   |     43 +
 .../hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh     |     40 +
 .../verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh    |     41 +
 .../verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh  |     44 +
 .../verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh   |     44 +
 .../verilog/dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh  |     44 +
 .../verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh   |     44 +
 .../verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh   |     44 +
 .../verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh    |     41 +
 .../hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh        |     71 +
 .../hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh        |     41 +
 .../hdl/verilog/dma_pcie_misc_input_if.svh         |    157 +
 .../hdl/verilog/dma_pcie_misc_output_if.svh        |    158 +
 .../ipstatic/hdl/verilog/dma_soft_defines.vh       |      6 +
 .../ipstatic/hdl/verilog/pcie_dma_attr_defines.svh |    162 +
 .../ipstatic/hdl/verilog/pciedmacoredefines.vh     |    453 +
 .../ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh |    202 +
 .../ipstatic/hdl/xdma_v4_1_vl_rfs.sv               |  41208 ++++++
 .../ipstatic/simulation/blk_mem_gen_v8_4.v         |   4522 +
 .../ipstatic/simulation/fifo_generator_vlog_beh.v  |  10519 ++
 .../custom_parts_ddr4_2016_4_and_above.csv         |      9 +
 .../mem_init_files/instr_blk_mem_sim.mif           |    396 +
 .../U200.ip_user_files/mem_init_files/phy_ddr4.h   |    472 +
 .../mem_init_files/phy_ddr4_sc.h                   |     94 +
 .../mem_init_files/phy_ddr4_udimm.h                |    467 +
 .../mem_init_files/phy_ddr4_udimm_sc.h             |     94 +
 .../mem_init_files/phy_rdimm_x8_dual.h             |    477 +
 .../mem_init_files/phy_rdimm_x8_dual_sc.h          |     94 +
 .../U200.ip_user_files/mem_init_files/pr_read.coe  |     15 +
 .../mem_init_files/pr_read_mem.mif                 |     13 +
 .../U200.ip_user_files/mem_init_files/pr_ref.coe   |     51 +
 .../mem_init_files/pr_ref_mem.mif                  |     49 +
 .../U200.ip_user_files/mem_init_files/pr_zq.coe    |     42 +
 .../mem_init_files/sim_ddr_v2_0.h                  |    221 +
 .../U200.ip_user_files/mem_init_files/simmem.coe   |    398 +
 .../U200.ip_user_files/mem_init_files/summary.log  |     20 +
 .../mem_init_files/zq_calib_mem.mif                |     40 +
 .../sim_scripts/axis_clock_converter_1/README.txt  |     83 +
 .../axis_clock_converter_1/activehdl/README.txt    |     49 +
 .../activehdl/axis_clock_converter.sh              |    152 +
 .../activehdl/axis_clock_converter.udo             |      0
 .../axis_clock_converter_1/activehdl/compile.do    |     46 +
 .../axis_clock_converter_1/activehdl/file_info.txt |     17 +
 .../axis_clock_converter_1/activehdl/glbl.v        |     84 +
 .../axis_clock_converter_1/activehdl/simulate.do   |     17 +
 .../axis_clock_converter_1/activehdl/wave.do       |      2 +
 .../axis_clock_converter_1/ies/README.txt          |     48 +
 .../ies/axis_clock_converter.sh                    |    178 +
 .../axis_clock_converter_1/ies/file_info.txt       |     17 +
 .../sim_scripts/axis_clock_converter_1/ies/glbl.v  |     84 +
 .../sim_scripts/axis_clock_converter_1/ies/run.f   |     32 +
 .../axis_clock_converter_1/modelsim/README.txt     |     49 +
 .../modelsim/axis_clock_converter.sh               |    167 +
 .../modelsim/axis_clock_converter.udo              |      0
 .../axis_clock_converter_1/modelsim/compile.do     |     46 +
 .../axis_clock_converter_1/modelsim/file_info.txt  |     17 +
 .../axis_clock_converter_1/modelsim/glbl.v         |     84 +
 .../axis_clock_converter_1/modelsim/simulate.do    |     16 +
 .../axis_clock_converter_1/modelsim/wave.do        |      2 +
 .../axis_clock_converter_1/questa/README.txt       |     49 +
 .../questa/axis_clock_converter.sh                 |    174 +
 .../questa/axis_clock_converter.udo                |      0
 .../axis_clock_converter_1/questa/compile.do       |     46 +
 .../axis_clock_converter_1/questa/elaborate.do     |      1 +
 .../axis_clock_converter_1/questa/file_info.txt    |     17 +
 .../axis_clock_converter_1/questa/glbl.v           |     84 +
 .../axis_clock_converter_1/questa/simulate.do      |     16 +
 .../axis_clock_converter_1/questa/wave.do          |      2 +
 .../axis_clock_converter_1/riviera/README.txt      |     49 +
 .../riviera/axis_clock_converter.sh                |    153 +
 .../riviera/axis_clock_converter.udo               |      0
 .../axis_clock_converter_1/riviera/compile.do      |     46 +
 .../axis_clock_converter_1/riviera/file_info.txt   |     17 +
 .../axis_clock_converter_1/riviera/glbl.v          |     84 +
 .../axis_clock_converter_1/riviera/simulate.do     |     17 +
 .../axis_clock_converter_1/riviera/wave.do         |      2 +
 .../axis_clock_converter_1/vcs/README.txt          |     49 +
 .../vcs/axis_clock_converter.sh                    |    251 +
 .../axis_clock_converter_1/vcs/file_info.txt       |     17 +
 .../sim_scripts/axis_clock_converter_1/vcs/glbl.v  |     84 +
 .../axis_clock_converter_1/vcs/simulate.do         |      2 +
 .../axis_clock_converter_1/xcelium/README.txt      |     48 +
 .../xcelium/axis_clock_converter.sh                |    178 +
 .../axis_clock_converter_1/xcelium/file_info.txt   |     17 +
 .../axis_clock_converter_1/xcelium/glbl.v          |     84 +
 .../axis_clock_converter_1/xcelium/run.f           |     32 +
 .../axis_clock_converter_1/xsim/README.txt         |     49 +
 .../axis_clock_converter_1/xsim/U200.smi           |     30 +
 .../xsim/axis_clock_converter.sh                   |    212 +
 .../axis_clock_converter_1/xsim/cmd.tcl            |     12 +
 .../axis_clock_converter_1/xsim/file_info.txt      |      2 +
 .../sim_scripts/axis_clock_converter_1/xsim/glbl.v |     84 +
 .../xsim/protoinst_files/bd_9f2c.protoinst         |      9 +
 .../xsim/protoinst_files/bd_afa8.protoinst         |      9 +
 .../xsim/protoinst_files/bd_ba6a.protoinst         |      9 +
 .../axis_clock_converter_1/xsim/vlog.prj           |      6 +
 .../sim_scripts/instr_blk_mem/README.txt           |     83 +
 .../sim_scripts/instr_blk_mem/activehdl/README.txt |     49 +
 .../sim_scripts/instr_blk_mem/activehdl/compile.do |     41 +
 .../instr_blk_mem/activehdl/file_info.txt          |     16 +
 .../sim_scripts/instr_blk_mem/activehdl/glbl.v     |     84 +
 .../instr_blk_mem/activehdl/instr_blk_mem.sh       |    152 +
 .../instr_blk_mem/activehdl/instr_blk_mem.udo      |      0
 .../instr_blk_mem/activehdl/simulate.do            |     17 +
 .../instr_blk_mem/activehdl/summary.log            |     20 +
 .../sim_scripts/instr_blk_mem/activehdl/wave.do    |      2 +
 .../sim_scripts/instr_blk_mem/ies/README.txt       |     48 +
 .../sim_scripts/instr_blk_mem/ies/file_info.txt    |     16 +
 .../sim_scripts/instr_blk_mem/ies/glbl.v           |     84 +
 .../sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh |    176 +
 .../sim_scripts/instr_blk_mem/ies/run.f            |     29 +
 .../sim_scripts/instr_blk_mem/ies/summary.log      |     20 +
 .../sim_scripts/instr_blk_mem/modelsim/README.txt  |     49 +
 .../sim_scripts/instr_blk_mem/modelsim/compile.do  |     41 +
 .../instr_blk_mem/modelsim/file_info.txt           |     16 +
 .../sim_scripts/instr_blk_mem/modelsim/glbl.v      |     84 +
 .../instr_blk_mem/modelsim/instr_blk_mem.sh        |    167 +
 .../instr_blk_mem/modelsim/instr_blk_mem.udo       |      0
 .../sim_scripts/instr_blk_mem/modelsim/simulate.do |     16 +
 .../sim_scripts/instr_blk_mem/modelsim/summary.log |     20 +
 .../sim_scripts/instr_blk_mem/modelsim/wave.do     |      2 +
 .../sim_scripts/instr_blk_mem/questa/README.txt    |     49 +
 .../sim_scripts/instr_blk_mem/questa/compile.do    |     41 +
 .../sim_scripts/instr_blk_mem/questa/elaborate.do  |      1 +
 .../sim_scripts/instr_blk_mem/questa/file_info.txt |     16 +
 .../sim_scripts/instr_blk_mem/questa/glbl.v        |     84 +
 .../instr_blk_mem/questa/instr_blk_mem.sh          |    174 +
 .../instr_blk_mem/questa/instr_blk_mem.udo         |      0
 .../sim_scripts/instr_blk_mem/questa/simulate.do   |     16 +
 .../sim_scripts/instr_blk_mem/questa/summary.log   |     20 +
 .../sim_scripts/instr_blk_mem/questa/wave.do       |      2 +
 .../sim_scripts/instr_blk_mem/riviera/README.txt   |     49 +
 .../sim_scripts/instr_blk_mem/riviera/compile.do   |     41 +
 .../instr_blk_mem/riviera/file_info.txt            |     16 +
 .../sim_scripts/instr_blk_mem/riviera/glbl.v       |     84 +
 .../instr_blk_mem/riviera/instr_blk_mem.sh         |    153 +
 .../instr_blk_mem/riviera/instr_blk_mem.udo        |      0
 .../sim_scripts/instr_blk_mem/riviera/simulate.do  |     17 +
 .../sim_scripts/instr_blk_mem/riviera/summary.log  |     20 +
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 .../sim_scripts/instr_blk_mem/vcs/README.txt       |     49 +
 .../sim_scripts/instr_blk_mem/vcs/file_info.txt    |     16 +
 .../sim_scripts/instr_blk_mem/vcs/glbl.v           |     84 +
 .../sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh |    247 +
 .../sim_scripts/instr_blk_mem/vcs/simulate.do      |      2 +
 .../sim_scripts/instr_blk_mem/vcs/summary.log      |     20 +
 .../sim_scripts/instr_blk_mem/xcelium/README.txt   |     48 +
 .../instr_blk_mem/xcelium/file_info.txt            |     16 +
 .../sim_scripts/instr_blk_mem/xcelium/glbl.v       |     84 +
 .../instr_blk_mem/xcelium/instr_blk_mem.sh         |    176 +
 .../sim_scripts/instr_blk_mem/xcelium/run.f        |     29 +
 .../sim_scripts/instr_blk_mem/xcelium/summary.log  |     20 +
 .../sim_scripts/instr_blk_mem/xsim/README.txt      |     49 +
 .../sim_scripts/instr_blk_mem/xsim/U200.smi        |     30 +
 .../sim_scripts/instr_blk_mem/xsim/cmd.tcl         |     12 +
 .../sim_scripts/instr_blk_mem/xsim/file_info.txt   |      2 +
 .../sim_scripts/instr_blk_mem/xsim/glbl.v          |     84 +
 .../instr_blk_mem/xsim/instr_blk_mem.sh            |    212 +
 .../xsim/protoinst_files/bd_9f2c.protoinst         |      9 +
 .../xsim/protoinst_files/bd_afa8.protoinst         |      9 +
 .../xsim/protoinst_files/bd_ba6a.protoinst         |      9 +
 .../sim_scripts/instr_blk_mem/xsim/summary.log     |     20 +
 .../sim_scripts/instr_blk_mem/xsim/vlog.prj        |      6 +
 .../sim_scripts/instr_blk_mem_sim/README.txt       |     83 +
 .../instr_blk_mem_sim/activehdl/README.txt         |     49 +
 .../instr_blk_mem_sim/activehdl/compile.do         |     41 +
 .../instr_blk_mem_sim/activehdl/file_info.txt      |     16 +
 .../sim_scripts/instr_blk_mem_sim/activehdl/glbl.v |     84 +
 .../activehdl/instr_blk_mem_sim.mif                |    396 +
 .../activehdl/instr_blk_mem_sim.sh                 |    152 +
 .../activehdl/instr_blk_mem_sim.udo                |      0
 .../instr_blk_mem_sim/activehdl/simmem.coe         |    398 +
 .../instr_blk_mem_sim/activehdl/simulate.do        |     17 +
 .../instr_blk_mem_sim/activehdl/summary.log        |     20 +
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 .../sim_scripts/instr_blk_mem_sim/ies/README.txt   |     48 +
 .../instr_blk_mem_sim/ies/file_info.txt            |     16 +
 .../sim_scripts/instr_blk_mem_sim/ies/glbl.v       |     84 +
 .../instr_blk_mem_sim/ies/instr_blk_mem_sim.mif    |    396 +
 .../instr_blk_mem_sim/ies/instr_blk_mem_sim.sh     |    176 +
 .../sim_scripts/instr_blk_mem_sim/ies/run.f        |     29 +
 .../sim_scripts/instr_blk_mem_sim/ies/simmem.coe   |    398 +
 .../sim_scripts/instr_blk_mem_sim/ies/summary.log  |     20 +
 .../instr_blk_mem_sim/modelsim/README.txt          |     49 +
 .../instr_blk_mem_sim/modelsim/compile.do          |     41 +
 .../instr_blk_mem_sim/modelsim/file_info.txt       |     16 +
 .../sim_scripts/instr_blk_mem_sim/modelsim/glbl.v  |     84 +
 .../modelsim/instr_blk_mem_sim.mif                 |    396 +
 .../modelsim/instr_blk_mem_sim.sh                  |    167 +
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 .../instr_blk_mem_sim/modelsim/simmem.coe          |    398 +
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 .../instr_blk_mem_sim/questa/README.txt            |     49 +
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 .../bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci        |   1032 +
 .../bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml        |  27445 ++++
 .../ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci   |     96 +
 .../ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml   |    691 +
 .../bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci         |    309 +
 .../bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml         |   8812 ++
 .../ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci    |    159 +
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 .../ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci    |    165 +
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 .../phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml |   4011 +
 .../phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci |    189 +
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 .../phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci |    298 +
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 .../bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci   |    189 +
 .../bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml   |   4011 +
 .../bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci   |    189 +
 .../bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml   |   4011 +
 .../bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci   |    298 +
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 .../ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci   |    172 +
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 .../sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci    |    667 +
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 .../U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci   |    500 +
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 .../phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig   |    313 +
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 .../bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci        |   1032 +
 .../bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml        |  27445 ++++
 .../bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci               |     96 +
 .../bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml               |    691 +
 .../bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci         |    309 +
 .../bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml         |   8812 ++
 .../phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci |    159 +
 .../phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml |   3532 +
 .../phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci |    165 +
 .../phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml |   3536 +
 .../bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci          |    189 +
 .../bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml          |   4011 +
 .../bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci          |    189 +
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 .../bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci          |    298 +
 .../bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml          |   4151 +
 .../bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci   |    189 +
 .../bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml   |   4011 +
 .../bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci   |    189 +
 .../bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml   |   4011 +
 .../bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci   |    298 +
 .../bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml   |   4151 +
 .../ip_0/phy_ddr4_udimm_microblaze_mcs.xci         |    172 +
 .../ip_0/phy_ddr4_udimm_microblaze_mcs.xml         |   2227 +
 .../ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci  |    665 +
 .../ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml  |   4890 +
 .../sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xci |    474 +
 .../sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xml |   8655 ++
 .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig            |    313 +
 .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej             |    124 +
 .../rtl/cal/ddr4_v2_2_cal_write.sv.rej             |     31 +
 .../sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd |    513 +
 .../ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml         |    100 +
 .../phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v   |    173 +
 .../bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci        |   1032 +
 .../bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xml        |  27445 ++++
 .../bd_0/ip/ip_1/bd_afa8_rst_0_0.xci               |     96 +
 .../bd_0/ip/ip_1/bd_afa8_rst_0_0.xml               |    691 +
 .../bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xci         |    309 +
 .../bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml         |   8812 ++
 .../bd_0/ip/ip_2/bd_afa8_ilmb_0.xci                |    159 +
 .../bd_0/ip/ip_2/bd_afa8_ilmb_0.xml                |   3532 +
 .../bd_0/ip/ip_3/bd_afa8_dlmb_0.xci                |    165 +
 .../bd_0/ip/ip_3/bd_afa8_dlmb_0.xml                |   3536 +
 .../bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci          |    189 +
 .../bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml          |   4011 +
 .../bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xci          |    189 +
 .../bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xml          |   4011 +
 .../bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci          |    298 +
 .../bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml          |   4151 +
 .../bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xci   |    189 +
 .../bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xml   |   4011 +
 .../bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci   |    189 +
 .../bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xml   |   4011 +
 .../bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci   |    298 +
 .../bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml   |   4151 +
 .../ip_0/phy_rdimm_x8_dual_microblaze_mcs.xci      |    172 +
 .../ip_0/phy_rdimm_x8_dual_microblaze_mcs.xml      |   2227 +
 .../ip_1/phy_rdimm_x8_dual_phy.xci                 |    665 +
 .../ip_1/phy_rdimm_x8_dual_phy.xml                 |   4897 +
 .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xci     |    478 +
 .../ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xml     |   8686 ++
 .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig            |    313 +
 .../rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej             |    124 +
 .../rtl/cal/ddr4_v2_2_cal_write.sv.rej             |     31 +
 .../sources_1/ip/pr_read_mem/pr_read_mem.xci       |    329 +
 .../sources_1/ip/pr_read_mem/pr_read_mem.xml       |   4182 +
 .../sources_1/ip/pr_ref_mem/pr_ref_mem.xci         |    330 +
 .../sources_1/ip/pr_ref_mem/pr_ref_mem.xml         |   4185 +
 .../sources_1/ip/rdback_fifo/rdback_fifo.xci       |    580 +
 .../sources_1/ip/rdback_fifo/rdback_fifo.xml       |  10791 ++
 .../sources_1/ip/scratchpad/scratchpad.xci         |    327 +
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 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xml
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xci
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xci
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xml
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci
 create mode 100644 projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml
 create mode 100644 projects/U200/U200.xpr
 create mode 100644 projects/U200/alveo-u200-master.xdc
 create mode 100755 projects/U200/apply_patches.sh
 create mode 100644 projects/U200/coe/pr_read.coe
 create mode 100644 projects/U200/coe/pr_ref.coe
 create mode 100644 projects/U200/coe/pr_zq.coe
 create mode 100644 projects/U200/coe/simmem.coe
 create mode 100644 projects/U200/constraints/C1_RDIMM_X8_DUAL.xdc
 create mode 100644 projects/U200/constraints/U200_C1_UDIMM.xdc
 create mode 100644 projects/U200/constraints/U200_c1.xdc
 create mode 100644 projects/U200/custom_parts_ddr4_2016_4_and_above.csv
 create mode 100644 projects/U200/patches/rd_en.patch
 create mode 100644 projects/U200/patches/write.patch
 create mode 100644 projects/U200/verilog/ddr4_adapter.v
 create mode 100644 projects/U200/verilog/ddr4_mc_odt.v
 create mode 100644 projects/U200/verilog/project.vh
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(limited to 'projects/U200')

diff --git a/projects/U200/U200.hw/U200.lpr b/projects/U200/U200.hw/U200.lpr
new file mode 100644
index 0000000..fd04c85
--- /dev/null
+++ b/projects/U200/U200.hw/U200.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/projects/U200/U200.ip_user_files/README.txt b/projects/U200/U200.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo
new file mode 100755
index 0000000..40c827c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo
@@ -0,0 +1,78 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:axis_clock_converter:1.1
+// IP Revision: 23
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+axis_clock_converter your_instance_name (
+  .s_axis_aresetn(s_axis_aresetn),  // input wire s_axis_aresetn
+  .m_axis_aresetn(m_axis_aresetn),  // input wire m_axis_aresetn
+  .s_axis_aclk(s_axis_aclk),        // input wire s_axis_aclk
+  .s_axis_tvalid(s_axis_tvalid),    // input wire s_axis_tvalid
+  .s_axis_tready(s_axis_tready),    // output wire s_axis_tready
+  .s_axis_tdata(s_axis_tdata),      // input wire [255 : 0] s_axis_tdata
+  .s_axis_tkeep(s_axis_tkeep),      // input wire [31 : 0] s_axis_tkeep
+  .s_axis_tlast(s_axis_tlast),      // input wire s_axis_tlast
+  .m_axis_aclk(m_axis_aclk),        // input wire m_axis_aclk
+  .m_axis_tvalid(m_axis_tvalid),    // output wire m_axis_tvalid
+  .m_axis_tready(m_axis_tready),    // input wire m_axis_tready
+  .m_axis_tdata(m_axis_tdata),      // output wire [255 : 0] m_axis_tdata
+  .m_axis_tkeep(m_axis_tkeep),      // output wire [31 : 0] m_axis_tkeep
+  .m_axis_tlast(m_axis_tlast)      // output wire m_axis_tlast
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file axis_clock_converter.v when simulating
+// the core, axis_clock_converter. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho
new file mode 100755
index 0000000..bd502d6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho
@@ -0,0 +1,101 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axis_clock_converter:1.1
+-- IP Revision: 23
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT axis_clock_converter
+  PORT (
+    s_axis_aresetn : IN STD_LOGIC;
+    m_axis_aresetn : IN STD_LOGIC;
+    s_axis_aclk : IN STD_LOGIC;
+    s_axis_tvalid : IN STD_LOGIC;
+    s_axis_tready : OUT STD_LOGIC;
+    s_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    s_axis_tkeep : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axis_tlast : IN STD_LOGIC;
+    m_axis_aclk : IN STD_LOGIC;
+    m_axis_tvalid : OUT STD_LOGIC;
+    m_axis_tready : IN STD_LOGIC;
+    m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    m_axis_tkeep : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_tlast : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : axis_clock_converter
+  PORT MAP (
+    s_axis_aresetn => s_axis_aresetn,
+    m_axis_aresetn => m_axis_aresetn,
+    s_axis_aclk => s_axis_aclk,
+    s_axis_tvalid => s_axis_tvalid,
+    s_axis_tready => s_axis_tready,
+    s_axis_tdata => s_axis_tdata,
+    s_axis_tkeep => s_axis_tkeep,
+    s_axis_tlast => s_axis_tlast,
+    m_axis_aclk => m_axis_aclk,
+    m_axis_tvalid => m_axis_tvalid,
+    m_axis_tready => m_axis_tready,
+    m_axis_tdata => m_axis_tdata,
+    m_axis_tkeep => m_axis_tkeep,
+    m_axis_tlast => m_axis_tlast
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file axis_clock_converter.vhd when simulating
+-- the core, axis_clock_converter. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v
new file mode 100644
index 0000000..e808aed
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v
@@ -0,0 +1,35 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:24:15 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter_stub.v
+// Design      : axis_clock_converter
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2" *)
+module axis_clock_converter(s_axis_aresetn, m_axis_aresetn, s_axis_aclk, 
+  s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_aclk, 
+  m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tlast)
+/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast" */;
+  input s_axis_aresetn;
+  input m_axis_aresetn;
+  input s_axis_aclk;
+  input s_axis_tvalid;
+  output s_axis_tready;
+  input [255:0]s_axis_tdata;
+  input [31:0]s_axis_tkeep;
+  input s_axis_tlast;
+  input m_axis_aclk;
+  output m_axis_tvalid;
+  input m_axis_tready;
+  output [255:0]m_axis_tdata;
+  output [31:0]m_axis_tkeep;
+  output m_axis_tlast;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl
new file mode 100644
index 0000000..8c8a8ae
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl
@@ -0,0 +1,43 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:24:15 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter_stub.vhdl
+-- Design      : axis_clock_converter
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity axis_clock_converter is
+  Port ( 
+    s_axis_aresetn : in STD_LOGIC;
+    m_axis_aresetn : in STD_LOGIC;
+    s_axis_aclk : in STD_LOGIC;
+    s_axis_tvalid : in STD_LOGIC;
+    s_axis_tready : out STD_LOGIC;
+    s_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
+    s_axis_tkeep : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axis_tlast : in STD_LOGIC;
+    m_axis_aclk : in STD_LOGIC;
+    m_axis_tvalid : out STD_LOGIC;
+    m_axis_tready : in STD_LOGIC;
+    m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    m_axis_tkeep : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_axis_tlast : out STD_LOGIC
+  );
+
+end axis_clock_converter;
+
+architecture stub of axis_clock_converter is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo
new file mode 100755
index 0000000..7b3bf48
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+instr_blk_mem your_instance_name (
+  .clka(clka),    // input wire clka
+  .ena(ena),      // input wire ena
+  .wea(wea),      // input wire [0 : 0] wea
+  .addra(addra),  // input wire [10 : 0] addra
+  .dina(dina),    // input wire [63 : 0] dina
+  .douta(douta)  // output wire [63 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file instr_blk_mem.v when simulating
+// the core, instr_blk_mem. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho
new file mode 100755
index 0000000..53ad1c8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho
@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT instr_blk_mem
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : instr_blk_mem
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file instr_blk_mem.vhd when simulating
+-- the core, instr_blk_mem. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v
new file mode 100644
index 0000000..a5c7dc9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:24:42 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.v
+// Design      : instr_blk_mem
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module instr_blk_mem(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [10:0]addra;
+  input [63:0]dina;
+  output [63:0]douta;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl
new file mode 100644
index 0000000..1814cbd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:24:43 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.vhdl
+-- Design      : instr_blk_mem
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity instr_blk_mem is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end instr_blk_mem;
+
+architecture stub of instr_blk_mem is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo
new file mode 100755
index 0000000..ec5eb2b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.veo
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+instr_blk_mem_sim your_instance_name (
+  .clka(clka),    // input wire clka
+  .ena(ena),      // input wire ena
+  .wea(wea),      // input wire [0 : 0] wea
+  .addra(addra),  // input wire [9 : 0] addra
+  .dina(dina),    // input wire [63 : 0] dina
+  .douta(douta)  // output wire [63 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file instr_blk_mem_sim.v when simulating
+// the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho
new file mode 100755
index 0000000..ae225e5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim.vho
@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT instr_blk_mem_sim
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : instr_blk_mem_sim
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file instr_blk_mem_sim.vhd when simulating
+-- the core, instr_blk_mem_sim. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v
new file mode 100644
index 0000000..9fbadc8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:24:43 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.v
+// Design      : instr_blk_mem_sim
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module instr_blk_mem_sim(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [9:0]addra;
+  input [63:0]dina;
+  output [63:0]douta;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl
new file mode 100644
index 0000000..12c1912
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:24:43 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim_stub.vhdl
+-- Design      : instr_blk_mem_sim
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity instr_blk_mem_sim is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end instr_blk_mem_sim;
+
+architecture stub of instr_blk_mem_sim is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[63:0],douta[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo
new file mode 100755
index 0000000..10d8dbe
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.veo
@@ -0,0 +1,116 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:ddr4:2.2
+// IP Revision: 10
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+phy_ddr4 your_instance_name (
+  .c0_init_calib_complete(c0_init_calib_complete),    // output wire c0_init_calib_complete
+  .dbg_clk(dbg_clk),                                  // output wire dbg_clk
+  .c0_sys_clk_p(c0_sys_clk_p),                        // input wire c0_sys_clk_p
+  .c0_sys_clk_n(c0_sys_clk_n),                        // input wire c0_sys_clk_n
+  .dbg_bus(dbg_bus),                                  // output wire [511 : 0] dbg_bus
+  .c0_ddr4_parity(c0_ddr4_parity),                    // output wire c0_ddr4_parity
+  .c0_ddr4_ui_clk(c0_ddr4_ui_clk),                    // output wire c0_ddr4_ui_clk
+  .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),  // output wire c0_ddr4_ui_clk_sync_rst
+  .addn_ui_clkout1(addn_ui_clkout1),                  // output wire addn_ui_clkout1
+  .sys_rst(sys_rst),                                  // input wire sys_rst
+  .rdDataEn(rdDataEn),                                // output wire [0 : 0] rdDataEn
+  .rdDataEnd(rdDataEnd),                              // output wire [0 : 0] rdDataEnd
+  .per_rd_done(per_rd_done),                          // output wire [0 : 0] per_rd_done
+  .rmw_rd_done(rmw_rd_done),                          // output wire [0 : 0] rmw_rd_done
+  .wrDataEn(wrDataEn),                                // output wire [0 : 0] wrDataEn
+  .mc_ACT_n(mc_ACT_n),                                // input wire [7 : 0] mc_ACT_n
+  .mcCasSlot(mcCasSlot),                              // input wire [1 : 0] mcCasSlot
+  .mcCasSlot2(mcCasSlot2),                            // input wire [0 : 0] mcCasSlot2
+  .mcRdCAS(mcRdCAS),                                  // input wire [0 : 0] mcRdCAS
+  .mcWrCAS(mcWrCAS),                                  // input wire [0 : 0] mcWrCAS
+  .winInjTxn(winInjTxn),                              // input wire [0 : 0] winInjTxn
+  .winRmw(winRmw),                                    // input wire [0 : 0] winRmw
+  .gt_data_ready(gt_data_ready),                      // input wire gt_data_ready
+  .winRank(winRank),                                  // input wire [1 : 0] winRank
+  .tCWL(tCWL),                                        // output wire [5 : 0] tCWL
+  .wrData(wrData),                                    // input wire [575 : 0] wrData
+  .rdData(rdData),                                    // output wire [575 : 0] rdData
+  .mc_ADR(mc_ADR),                                    // input wire [143 : 0] mc_ADR
+  .mc_BA(mc_BA),                                      // input wire [15 : 0] mc_BA
+  .mc_CKE(mc_CKE),                                    // input wire [7 : 0] mc_CKE
+  .mc_CS_n(mc_CS_n),                                  // input wire [7 : 0] mc_CS_n
+  .mc_ODT(mc_ODT),                                    // input wire [7 : 0] mc_ODT
+  .dBufAdr(dBufAdr),                                  // input wire [4 : 0] dBufAdr
+  .rdDataAddr(rdDataAddr),                            // output wire [4 : 0] rdDataAddr
+  .wrDataAddr(wrDataAddr),                            // output wire [4 : 0] wrDataAddr
+  .winBuf(winBuf),                                    // input wire [4 : 0] winBuf
+  .ddr4_act_n(ddr4_act_n),                            // output wire ddr4_act_n
+  .ddr4_adr(ddr4_adr),                                // output wire [17 : 0] ddr4_adr
+  .ddr4_ba(ddr4_ba),                                  // output wire [1 : 0] ddr4_ba
+  .ddr4_bg(ddr4_bg),                                  // output wire [1 : 0] ddr4_bg
+  .ddr4_par(ddr4_par),                                // output wire ddr4_par
+  .ddr4_cke(ddr4_cke),                                // output wire [0 : 0] ddr4_cke
+  .ddr4_odt(ddr4_odt),                                // output wire [0 : 0] ddr4_odt
+  .ddr4_cs_n(ddr4_cs_n),                              // output wire [0 : 0] ddr4_cs_n
+  .ddr4_ck_t(ddr4_ck_t),                              // output wire ddr4_ck_t
+  .ddr4_ck_c(ddr4_ck_c),                              // output wire ddr4_ck_c
+  .ddr4_reset_n(ddr4_reset_n),                        // output wire ddr4_reset_n
+  .ddr4_parity(ddr4_parity),                          // output wire ddr4_parity
+  .ddr4_dq(ddr4_dq),                                  // inout wire [71 : 0] ddr4_dq
+  .ddr4_dqs_c(ddr4_dqs_c),                            // inout wire [17 : 0] ddr4_dqs_c
+  .ddr4_dqs_t(ddr4_dqs_t),                            // inout wire [17 : 0] ddr4_dqs_t
+  .mc_BG(mc_BG)                                      // input wire [15 : 0] mc_BG
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file phy_ddr4.v when simulating
+// the core, phy_ddr4. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho
new file mode 100755
index 0000000..24c61fa
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4.vho
@@ -0,0 +1,177 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:ddr4:2.2
+-- IP Revision: 10
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT phy_ddr4
+  PORT (
+    c0_init_calib_complete : OUT STD_LOGIC;
+    dbg_clk : OUT STD_LOGIC;
+    c0_sys_clk_p : IN STD_LOGIC;
+    c0_sys_clk_n : IN STD_LOGIC;
+    dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+    c0_ddr4_parity : OUT STD_LOGIC;
+    c0_ddr4_ui_clk : OUT STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC;
+    addn_ui_clkout1 : OUT STD_LOGIC;
+    sys_rst : IN STD_LOGIC;
+    rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gt_data_ready : IN STD_LOGIC;
+    winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    wrData : IN STD_LOGIC_VECTOR(575 DOWNTO 0);
+    rdData : OUT STD_LOGIC_VECTOR(575 DOWNTO 0);
+    mc_ADR : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
+    mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    mc_CKE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_CS_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_ODT : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    ddr4_act_n : OUT STD_LOGIC;
+    ddr4_adr : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
+    ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_par : OUT STD_LOGIC;
+    ddr4_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_ck_t : OUT STD_LOGIC;
+    ddr4_ck_c : OUT STD_LOGIC;
+    ddr4_reset_n : OUT STD_LOGIC;
+    ddr4_parity : OUT STD_LOGIC;
+    ddr4_dq : INOUT STD_LOGIC_VECTOR(71 DOWNTO 0);
+    ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0);
+    ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0);
+    mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : phy_ddr4
+  PORT MAP (
+    c0_init_calib_complete => c0_init_calib_complete,
+    dbg_clk => dbg_clk,
+    c0_sys_clk_p => c0_sys_clk_p,
+    c0_sys_clk_n => c0_sys_clk_n,
+    dbg_bus => dbg_bus,
+    c0_ddr4_parity => c0_ddr4_parity,
+    c0_ddr4_ui_clk => c0_ddr4_ui_clk,
+    c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst,
+    addn_ui_clkout1 => addn_ui_clkout1,
+    sys_rst => sys_rst,
+    rdDataEn => rdDataEn,
+    rdDataEnd => rdDataEnd,
+    per_rd_done => per_rd_done,
+    rmw_rd_done => rmw_rd_done,
+    wrDataEn => wrDataEn,
+    mc_ACT_n => mc_ACT_n,
+    mcCasSlot => mcCasSlot,
+    mcCasSlot2 => mcCasSlot2,
+    mcRdCAS => mcRdCAS,
+    mcWrCAS => mcWrCAS,
+    winInjTxn => winInjTxn,
+    winRmw => winRmw,
+    gt_data_ready => gt_data_ready,
+    winRank => winRank,
+    tCWL => tCWL,
+    wrData => wrData,
+    rdData => rdData,
+    mc_ADR => mc_ADR,
+    mc_BA => mc_BA,
+    mc_CKE => mc_CKE,
+    mc_CS_n => mc_CS_n,
+    mc_ODT => mc_ODT,
+    dBufAdr => dBufAdr,
+    rdDataAddr => rdDataAddr,
+    wrDataAddr => wrDataAddr,
+    winBuf => winBuf,
+    ddr4_act_n => ddr4_act_n,
+    ddr4_adr => ddr4_adr,
+    ddr4_ba => ddr4_ba,
+    ddr4_bg => ddr4_bg,
+    ddr4_par => ddr4_par,
+    ddr4_cke => ddr4_cke,
+    ddr4_odt => ddr4_odt,
+    ddr4_cs_n => ddr4_cs_n,
+    ddr4_ck_t => ddr4_ck_t,
+    ddr4_ck_c => ddr4_ck_c,
+    ddr4_reset_n => ddr4_reset_n,
+    ddr4_parity => ddr4_parity,
+    ddr4_dq => ddr4_dq,
+    ddr4_dqs_c => ddr4_dqs_c,
+    ddr4_dqs_t => ddr4_dqs_t,
+    mc_BG => mc_BG
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file phy_ddr4.vhd when simulating
+-- the core, phy_ddr4. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v
new file mode 100644
index 0000000..2543dd3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v
@@ -0,0 +1,76 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:28:29 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4_stub.v
+// Design      : phy_ddr4
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ddr4_v2_2_10,Vivado 2020.2" *)
+module phy_ddr4(sys_rst, c0_sys_clk_p, c0_sys_clk_n, 
+  c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, 
+  c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, 
+  c0_ddr4_reset_n, c0_ddr4_parity, c0_ddr4_dq, c0_ddr4_dqs_c, c0_ddr4_dqs_t, 
+  c0_init_calib_complete, addn_ui_clkout1, dBufAdr, wrData, rdData, rdDataAddr, rdDataEn, 
+  rdDataEnd, per_rd_done, rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, mc_BG, mc_CKE, 
+  mc_CS_n, mc_ODT, mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, gt_data_ready, winBuf, 
+  winRank, tCWL, dbg_bus)
+/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[17:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dq[71:0],c0_ddr4_dqs_c[17:0],c0_ddr4_dqs_t[17:0],c0_init_calib_complete,addn_ui_clkout1,dBufAdr[4:0],wrData[575:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[143:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */;
+  input sys_rst;
+  input c0_sys_clk_p;
+  input c0_sys_clk_n;
+  output c0_ddr4_ui_clk;
+  output c0_ddr4_ui_clk_sync_rst;
+  output dbg_clk;
+  output c0_ddr4_act_n;
+  output [17:0]c0_ddr4_adr;
+  output [1:0]c0_ddr4_ba;
+  output [1:0]c0_ddr4_bg;
+  output [0:0]c0_ddr4_cke;
+  output [0:0]c0_ddr4_odt;
+  output [0:0]c0_ddr4_cs_n;
+  output [0:0]c0_ddr4_ck_t;
+  output [0:0]c0_ddr4_ck_c;
+  output c0_ddr4_reset_n;
+  output c0_ddr4_parity;
+  inout [71:0]c0_ddr4_dq;
+  inout [17:0]c0_ddr4_dqs_c;
+  inout [17:0]c0_ddr4_dqs_t;
+  output c0_init_calib_complete;
+  output addn_ui_clkout1;
+  input [4:0]dBufAdr;
+  input [575:0]wrData;
+  output [575:0]rdData;
+  output [4:0]rdDataAddr;
+  output [0:0]rdDataEn;
+  output [0:0]rdDataEnd;
+  output [0:0]per_rd_done;
+  output [0:0]rmw_rd_done;
+  output [4:0]wrDataAddr;
+  output [0:0]wrDataEn;
+  input [7:0]mc_ACT_n;
+  input [143:0]mc_ADR;
+  input [15:0]mc_BA;
+  input [15:0]mc_BG;
+  input [7:0]mc_CKE;
+  input [7:0]mc_CS_n;
+  input [7:0]mc_ODT;
+  input [1:0]mcCasSlot;
+  input [0:0]mcCasSlot2;
+  input [0:0]mcRdCAS;
+  input [0:0]mcWrCAS;
+  input [0:0]winInjTxn;
+  input [0:0]winRmw;
+  input gt_data_ready;
+  input [4:0]winBuf;
+  input [1:0]winRank;
+  output [5:0]tCWL;
+  output [511:0]dbg_bus;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl
new file mode 100644
index 0000000..8cec2be
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl
@@ -0,0 +1,79 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:28:29 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4_stub.vhdl
+-- Design      : phy_ddr4
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity phy_ddr4 is
+  Port ( 
+    sys_rst : in STD_LOGIC;
+    c0_sys_clk_p : in STD_LOGIC;
+    c0_sys_clk_n : in STD_LOGIC;
+    c0_ddr4_ui_clk : out STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : out STD_LOGIC;
+    dbg_clk : out STD_LOGIC;
+    c0_ddr4_act_n : out STD_LOGIC;
+    c0_ddr4_adr : out STD_LOGIC_VECTOR ( 17 downto 0 );
+    c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_reset_n : out STD_LOGIC;
+    c0_ddr4_parity : out STD_LOGIC;
+    c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
+    c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
+    c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
+    c0_init_calib_complete : out STD_LOGIC;
+    addn_ui_clkout1 : out STD_LOGIC;
+    dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrData : in STD_LOGIC_VECTOR ( 575 downto 0 );
+    rdData : out STD_LOGIC_VECTOR ( 575 downto 0 );
+    rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 );
+    per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ADR : in STD_LOGIC_VECTOR ( 143 downto 0 );
+    mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_CKE : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_CS_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ODT : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winRmw : in STD_LOGIC_VECTOR ( 0 to 0 );
+    gt_data_ready : in STD_LOGIC;
+    winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    winRank : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 )
+  );
+
+end phy_ddr4;
+
+architecture stub of phy_ddr4 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[17:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dq[71:0],c0_ddr4_dqs_c[17:0],c0_ddr4_dqs_t[17:0],c0_init_calib_complete,addn_ui_clkout1,dBufAdr[4:0],wrData[575:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[143:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_10,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.veo b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.veo
new file mode 100755
index 0000000..6d449e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.veo
@@ -0,0 +1,115 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:ddr4:2.2
+// IP Revision: 10
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+phy_ddr4_udimm your_instance_name (
+  .c0_init_calib_complete(c0_init_calib_complete),    // output wire c0_init_calib_complete
+  .dbg_clk(dbg_clk),                                  // output wire dbg_clk
+  .c0_sys_clk_p(c0_sys_clk_p),                        // input wire c0_sys_clk_p
+  .c0_sys_clk_n(c0_sys_clk_n),                        // input wire c0_sys_clk_n
+  .dbg_bus(dbg_bus),                                  // output wire [511 : 0] dbg_bus
+  .c0_ddr4_ui_clk(c0_ddr4_ui_clk),                    // output wire c0_ddr4_ui_clk
+  .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),  // output wire c0_ddr4_ui_clk_sync_rst
+  .sys_rst(sys_rst),                                  // input wire sys_rst
+  .rdDataEn(rdDataEn),                                // output wire [0 : 0] rdDataEn
+  .rdDataEnd(rdDataEnd),                              // output wire [0 : 0] rdDataEnd
+  .per_rd_done(per_rd_done),                          // output wire [0 : 0] per_rd_done
+  .rmw_rd_done(rmw_rd_done),                          // output wire [0 : 0] rmw_rd_done
+  .wrDataEn(wrDataEn),                                // output wire [0 : 0] wrDataEn
+  .mc_ACT_n(mc_ACT_n),                                // input wire [7 : 0] mc_ACT_n
+  .mcCasSlot(mcCasSlot),                              // input wire [1 : 0] mcCasSlot
+  .mcCasSlot2(mcCasSlot2),                            // input wire [0 : 0] mcCasSlot2
+  .mcRdCAS(mcRdCAS),                                  // input wire [0 : 0] mcRdCAS
+  .mcWrCAS(mcWrCAS),                                  // input wire [0 : 0] mcWrCAS
+  .winInjTxn(winInjTxn),                              // input wire [0 : 0] winInjTxn
+  .winRmw(winRmw),                                    // input wire [0 : 0] winRmw
+  .gt_data_ready(gt_data_ready),                      // input wire gt_data_ready
+  .winRank(winRank),                                  // input wire [1 : 0] winRank
+  .tCWL(tCWL),                                        // output wire [5 : 0] tCWL
+  .wrData(wrData),                                    // input wire [511 : 0] wrData
+  .wrDataMask(wrDataMask),                            // input wire [63 : 0] wrDataMask
+  .rdData(rdData),                                    // output wire [511 : 0] rdData
+  .mc_ADR(mc_ADR),                                    // input wire [135 : 0] mc_ADR
+  .mc_BA(mc_BA),                                      // input wire [15 : 0] mc_BA
+  .mc_CKE(mc_CKE),                                    // input wire [7 : 0] mc_CKE
+  .mc_CS_n(mc_CS_n),                                  // input wire [7 : 0] mc_CS_n
+  .mc_ODT(mc_ODT),                                    // input wire [7 : 0] mc_ODT
+  .dBufAdr(dBufAdr),                                  // input wire [4 : 0] dBufAdr
+  .rdDataAddr(rdDataAddr),                            // output wire [4 : 0] rdDataAddr
+  .wrDataAddr(wrDataAddr),                            // output wire [4 : 0] wrDataAddr
+  .winBuf(winBuf),                                    // input wire [4 : 0] winBuf
+  .ddr4_act_n(ddr4_act_n),                            // output wire ddr4_act_n
+  .ddr4_adr(ddr4_adr),                                // output wire [16 : 0] ddr4_adr
+  .ddr4_ba(ddr4_ba),                                  // output wire [1 : 0] ddr4_ba
+  .ddr4_bg(ddr4_bg),                                  // output wire [1 : 0] ddr4_bg
+  .ddr4_par(ddr4_par),                                // output wire ddr4_par
+  .ddr4_cke(ddr4_cke),                                // output wire [0 : 0] ddr4_cke
+  .ddr4_odt(ddr4_odt),                                // output wire [0 : 0] ddr4_odt
+  .ddr4_cs_n(ddr4_cs_n),                              // output wire [0 : 0] ddr4_cs_n
+  .ddr4_ck_t(ddr4_ck_t),                              // output wire ddr4_ck_t
+  .ddr4_ck_c(ddr4_ck_c),                              // output wire ddr4_ck_c
+  .ddr4_reset_n(ddr4_reset_n),                        // output wire ddr4_reset_n
+  .ddr4_dm_dbi_n(ddr4_dm_dbi_n),                      // inout wire [7 : 0] ddr4_dm_dbi_n
+  .ddr4_dq(ddr4_dq),                                  // inout wire [63 : 0] ddr4_dq
+  .ddr4_dqs_c(ddr4_dqs_c),                            // inout wire [7 : 0] ddr4_dqs_c
+  .ddr4_dqs_t(ddr4_dqs_t),                            // inout wire [7 : 0] ddr4_dqs_t
+  .mc_BG(mc_BG)                                      // input wire [15 : 0] mc_BG
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file phy_ddr4_udimm.v when simulating
+// the core, phy_ddr4_udimm. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.vho b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.vho
new file mode 100755
index 0000000..6c9bb1d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm.vho
@@ -0,0 +1,175 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:ddr4:2.2
+-- IP Revision: 10
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT phy_ddr4_udimm
+  PORT (
+    c0_init_calib_complete : OUT STD_LOGIC;
+    dbg_clk : OUT STD_LOGIC;
+    c0_sys_clk_p : IN STD_LOGIC;
+    c0_sys_clk_n : IN STD_LOGIC;
+    dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+    c0_ddr4_ui_clk : OUT STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC;
+    sys_rst : IN STD_LOGIC;
+    rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gt_data_ready : IN STD_LOGIC;
+    winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    wrData : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+    wrDataMask : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    rdData : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+    mc_ADR : IN STD_LOGIC_VECTOR(135 DOWNTO 0);
+    mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    mc_CKE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_CS_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_ODT : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    ddr4_act_n : OUT STD_LOGIC;
+    ddr4_adr : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
+    ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_par : OUT STD_LOGIC;
+    ddr4_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_ck_t : OUT STD_LOGIC;
+    ddr4_ck_c : OUT STD_LOGIC;
+    ddr4_reset_n : OUT STD_LOGIC;
+    ddr4_dm_dbi_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    ddr4_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+    ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : phy_ddr4_udimm
+  PORT MAP (
+    c0_init_calib_complete => c0_init_calib_complete,
+    dbg_clk => dbg_clk,
+    c0_sys_clk_p => c0_sys_clk_p,
+    c0_sys_clk_n => c0_sys_clk_n,
+    dbg_bus => dbg_bus,
+    c0_ddr4_ui_clk => c0_ddr4_ui_clk,
+    c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst,
+    sys_rst => sys_rst,
+    rdDataEn => rdDataEn,
+    rdDataEnd => rdDataEnd,
+    per_rd_done => per_rd_done,
+    rmw_rd_done => rmw_rd_done,
+    wrDataEn => wrDataEn,
+    mc_ACT_n => mc_ACT_n,
+    mcCasSlot => mcCasSlot,
+    mcCasSlot2 => mcCasSlot2,
+    mcRdCAS => mcRdCAS,
+    mcWrCAS => mcWrCAS,
+    winInjTxn => winInjTxn,
+    winRmw => winRmw,
+    gt_data_ready => gt_data_ready,
+    winRank => winRank,
+    tCWL => tCWL,
+    wrData => wrData,
+    wrDataMask => wrDataMask,
+    rdData => rdData,
+    mc_ADR => mc_ADR,
+    mc_BA => mc_BA,
+    mc_CKE => mc_CKE,
+    mc_CS_n => mc_CS_n,
+    mc_ODT => mc_ODT,
+    dBufAdr => dBufAdr,
+    rdDataAddr => rdDataAddr,
+    wrDataAddr => wrDataAddr,
+    winBuf => winBuf,
+    ddr4_act_n => ddr4_act_n,
+    ddr4_adr => ddr4_adr,
+    ddr4_ba => ddr4_ba,
+    ddr4_bg => ddr4_bg,
+    ddr4_par => ddr4_par,
+    ddr4_cke => ddr4_cke,
+    ddr4_odt => ddr4_odt,
+    ddr4_cs_n => ddr4_cs_n,
+    ddr4_ck_t => ddr4_ck_t,
+    ddr4_ck_c => ddr4_ck_c,
+    ddr4_reset_n => ddr4_reset_n,
+    ddr4_dm_dbi_n => ddr4_dm_dbi_n,
+    ddr4_dq => ddr4_dq,
+    ddr4_dqs_c => ddr4_dqs_c,
+    ddr4_dqs_t => ddr4_dqs_t,
+    mc_BG => mc_BG
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file phy_ddr4_udimm.vhd when simulating
+-- the core, phy_ddr4_udimm. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v
new file mode 100644
index 0000000..d128321
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v
@@ -0,0 +1,76 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 15:10:27 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.v
+// Design      : phy_ddr4_udimm
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ddr4_v2_2_10,Vivado 2020.2" *)
+module phy_ddr4_udimm(sys_rst, c0_sys_clk_p, c0_sys_clk_n, 
+  c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, 
+  c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, 
+  c0_ddr4_reset_n, c0_ddr4_dm_dbi_n, c0_ddr4_dq, c0_ddr4_dqs_c, c0_ddr4_dqs_t, 
+  c0_init_calib_complete, dBufAdr, wrData, wrDataMask, rdData, rdDataAddr, rdDataEn, rdDataEnd, 
+  per_rd_done, rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, mc_BG, mc_CKE, mc_CS_n, 
+  mc_ODT, mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, gt_data_ready, winBuf, winRank, 
+  tCWL, dbg_bus)
+/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_dm_dbi_n[7:0],c0_ddr4_dq[63:0],c0_ddr4_dqs_c[7:0],c0_ddr4_dqs_t[7:0],c0_init_calib_complete,dBufAdr[4:0],wrData[511:0],wrDataMask[63:0],rdData[511:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */;
+  input sys_rst;
+  input c0_sys_clk_p;
+  input c0_sys_clk_n;
+  output c0_ddr4_ui_clk;
+  output c0_ddr4_ui_clk_sync_rst;
+  output dbg_clk;
+  output c0_ddr4_act_n;
+  output [16:0]c0_ddr4_adr;
+  output [1:0]c0_ddr4_ba;
+  output [1:0]c0_ddr4_bg;
+  output [0:0]c0_ddr4_cke;
+  output [0:0]c0_ddr4_odt;
+  output [0:0]c0_ddr4_cs_n;
+  output [0:0]c0_ddr4_ck_t;
+  output [0:0]c0_ddr4_ck_c;
+  output c0_ddr4_reset_n;
+  inout [7:0]c0_ddr4_dm_dbi_n;
+  inout [63:0]c0_ddr4_dq;
+  inout [7:0]c0_ddr4_dqs_c;
+  inout [7:0]c0_ddr4_dqs_t;
+  output c0_init_calib_complete;
+  input [4:0]dBufAdr;
+  input [511:0]wrData;
+  input [63:0]wrDataMask;
+  output [511:0]rdData;
+  output [4:0]rdDataAddr;
+  output [0:0]rdDataEn;
+  output [0:0]rdDataEnd;
+  output [0:0]per_rd_done;
+  output [0:0]rmw_rd_done;
+  output [4:0]wrDataAddr;
+  output [0:0]wrDataEn;
+  input [7:0]mc_ACT_n;
+  input [135:0]mc_ADR;
+  input [15:0]mc_BA;
+  input [15:0]mc_BG;
+  input [7:0]mc_CKE;
+  input [7:0]mc_CS_n;
+  input [7:0]mc_ODT;
+  input [1:0]mcCasSlot;
+  input [0:0]mcCasSlot2;
+  input [0:0]mcRdCAS;
+  input [0:0]mcWrCAS;
+  input [0:0]winInjTxn;
+  input [0:0]winRmw;
+  input gt_data_ready;
+  input [4:0]winBuf;
+  input [1:0]winRank;
+  output [5:0]tCWL;
+  output [511:0]dbg_bus;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl
new file mode 100644
index 0000000..e598825
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl
@@ -0,0 +1,79 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 15:10:28 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm_stub.vhdl
+-- Design      : phy_ddr4_udimm
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity phy_ddr4_udimm is
+  Port ( 
+    sys_rst : in STD_LOGIC;
+    c0_sys_clk_p : in STD_LOGIC;
+    c0_sys_clk_n : in STD_LOGIC;
+    c0_ddr4_ui_clk : out STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : out STD_LOGIC;
+    dbg_clk : out STD_LOGIC;
+    c0_ddr4_act_n : out STD_LOGIC;
+    c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
+    c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_reset_n : out STD_LOGIC;
+    c0_ddr4_dm_dbi_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
+    c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
+    c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 7 downto 0 );
+    c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 7 downto 0 );
+    c0_init_calib_complete : out STD_LOGIC;
+    dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrData : in STD_LOGIC_VECTOR ( 511 downto 0 );
+    wrDataMask : in STD_LOGIC_VECTOR ( 63 downto 0 );
+    rdData : out STD_LOGIC_VECTOR ( 511 downto 0 );
+    rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 );
+    per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ADR : in STD_LOGIC_VECTOR ( 135 downto 0 );
+    mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_CKE : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_CS_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ODT : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winRmw : in STD_LOGIC_VECTOR ( 0 to 0 );
+    gt_data_ready : in STD_LOGIC;
+    winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    winRank : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 )
+  );
+
+end phy_ddr4_udimm;
+
+architecture stub of phy_ddr4_udimm is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_dm_dbi_n[7:0],c0_ddr4_dq[63:0],c0_ddr4_dqs_c[7:0],c0_ddr4_dqs_t[7:0],c0_init_calib_complete,dBufAdr[4:0],wrData[511:0],wrDataMask[63:0],rdData[511:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_10,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo
new file mode 100755
index 0000000..4848a52
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.veo
@@ -0,0 +1,117 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:ddr4:2.2
+// IP Revision: 10
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+phy_rdimm_x8_dual your_instance_name (
+  .c0_init_calib_complete(c0_init_calib_complete),    // output wire c0_init_calib_complete
+  .dbg_clk(dbg_clk),                                  // output wire dbg_clk
+  .c0_sys_clk_p(c0_sys_clk_p),                        // input wire c0_sys_clk_p
+  .c0_sys_clk_n(c0_sys_clk_n),                        // input wire c0_sys_clk_n
+  .dbg_bus(dbg_bus),                                  // output wire [511 : 0] dbg_bus
+  .c0_ddr4_parity(c0_ddr4_parity),                    // output wire c0_ddr4_parity
+  .c0_ddr4_ui_clk(c0_ddr4_ui_clk),                    // output wire c0_ddr4_ui_clk
+  .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),  // output wire c0_ddr4_ui_clk_sync_rst
+  .sys_rst(sys_rst),                                  // input wire sys_rst
+  .rdDataEn(rdDataEn),                                // output wire [0 : 0] rdDataEn
+  .rdDataEnd(rdDataEnd),                              // output wire [0 : 0] rdDataEnd
+  .per_rd_done(per_rd_done),                          // output wire [0 : 0] per_rd_done
+  .rmw_rd_done(rmw_rd_done),                          // output wire [0 : 0] rmw_rd_done
+  .wrDataEn(wrDataEn),                                // output wire [0 : 0] wrDataEn
+  .mc_ACT_n(mc_ACT_n),                                // input wire [7 : 0] mc_ACT_n
+  .mcCasSlot(mcCasSlot),                              // input wire [1 : 0] mcCasSlot
+  .mcCasSlot2(mcCasSlot2),                            // input wire [0 : 0] mcCasSlot2
+  .mcRdCAS(mcRdCAS),                                  // input wire [0 : 0] mcRdCAS
+  .mcWrCAS(mcWrCAS),                                  // input wire [0 : 0] mcWrCAS
+  .winInjTxn(winInjTxn),                              // input wire [0 : 0] winInjTxn
+  .winRmw(winRmw),                                    // input wire [0 : 0] winRmw
+  .gt_data_ready(gt_data_ready),                      // input wire gt_data_ready
+  .winRank(winRank),                                  // input wire [1 : 0] winRank
+  .tCWL(tCWL),                                        // output wire [5 : 0] tCWL
+  .wrData(wrData),                                    // input wire [575 : 0] wrData
+  .wrDataMask(wrDataMask),                            // input wire [71 : 0] wrDataMask
+  .rdData(rdData),                                    // output wire [575 : 0] rdData
+  .mc_ADR(mc_ADR),                                    // input wire [135 : 0] mc_ADR
+  .mc_BA(mc_BA),                                      // input wire [15 : 0] mc_BA
+  .mc_CKE(mc_CKE),                                    // input wire [7 : 0] mc_CKE
+  .mc_CS_n(mc_CS_n),                                  // input wire [7 : 0] mc_CS_n
+  .mc_ODT(mc_ODT),                                    // input wire [7 : 0] mc_ODT
+  .dBufAdr(dBufAdr),                                  // input wire [4 : 0] dBufAdr
+  .rdDataAddr(rdDataAddr),                            // output wire [4 : 0] rdDataAddr
+  .wrDataAddr(wrDataAddr),                            // output wire [4 : 0] wrDataAddr
+  .winBuf(winBuf),                                    // input wire [4 : 0] winBuf
+  .ddr4_act_n(ddr4_act_n),                            // output wire ddr4_act_n
+  .ddr4_adr(ddr4_adr),                                // output wire [16 : 0] ddr4_adr
+  .ddr4_ba(ddr4_ba),                                  // output wire [1 : 0] ddr4_ba
+  .ddr4_bg(ddr4_bg),                                  // output wire [1 : 0] ddr4_bg
+  .ddr4_par(ddr4_par),                                // output wire ddr4_par
+  .ddr4_cke(ddr4_cke),                                // output wire [0 : 0] ddr4_cke
+  .ddr4_odt(ddr4_odt),                                // output wire [0 : 0] ddr4_odt
+  .ddr4_cs_n(ddr4_cs_n),                              // output wire [0 : 0] ddr4_cs_n
+  .ddr4_ck_t(ddr4_ck_t),                              // output wire ddr4_ck_t
+  .ddr4_ck_c(ddr4_ck_c),                              // output wire ddr4_ck_c
+  .ddr4_reset_n(ddr4_reset_n),                        // output wire ddr4_reset_n
+  .ddr4_parity(ddr4_parity),                          // output wire ddr4_parity
+  .ddr4_dm_dbi_n(ddr4_dm_dbi_n),                      // inout wire [8 : 0] ddr4_dm_dbi_n
+  .ddr4_dq(ddr4_dq),                                  // inout wire [71 : 0] ddr4_dq
+  .ddr4_dqs_c(ddr4_dqs_c),                            // inout wire [8 : 0] ddr4_dqs_c
+  .ddr4_dqs_t(ddr4_dqs_t),                            // inout wire [8 : 0] ddr4_dqs_t
+  .mc_BG(mc_BG)                                      // input wire [15 : 0] mc_BG
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file phy_rdimm_x8_dual.v when simulating
+// the core, phy_rdimm_x8_dual. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho
new file mode 100755
index 0000000..e5803d2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.vho
@@ -0,0 +1,179 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:ddr4:2.2
+-- IP Revision: 10
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT phy_rdimm_x8_dual
+  PORT (
+    c0_init_calib_complete : OUT STD_LOGIC;
+    dbg_clk : OUT STD_LOGIC;
+    c0_sys_clk_p : IN STD_LOGIC;
+    c0_sys_clk_n : IN STD_LOGIC;
+    dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+    c0_ddr4_parity : OUT STD_LOGIC;
+    c0_ddr4_ui_clk : OUT STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC;
+    sys_rst : IN STD_LOGIC;
+    rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gt_data_ready : IN STD_LOGIC;
+    winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    wrData : IN STD_LOGIC_VECTOR(575 DOWNTO 0);
+    wrDataMask : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
+    rdData : OUT STD_LOGIC_VECTOR(575 DOWNTO 0);
+    mc_ADR : IN STD_LOGIC_VECTOR(135 DOWNTO 0);
+    mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    mc_CKE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_CS_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mc_ODT : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    ddr4_act_n : OUT STD_LOGIC;
+    ddr4_adr : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
+    ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_par : OUT STD_LOGIC;
+    ddr4_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ddr4_ck_t : OUT STD_LOGIC;
+    ddr4_ck_c : OUT STD_LOGIC;
+    ddr4_reset_n : OUT STD_LOGIC;
+    ddr4_parity : OUT STD_LOGIC;
+    ddr4_dm_dbi_n : INOUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    ddr4_dq : INOUT STD_LOGIC_VECTOR(71 DOWNTO 0);
+    ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+    mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : phy_rdimm_x8_dual
+  PORT MAP (
+    c0_init_calib_complete => c0_init_calib_complete,
+    dbg_clk => dbg_clk,
+    c0_sys_clk_p => c0_sys_clk_p,
+    c0_sys_clk_n => c0_sys_clk_n,
+    dbg_bus => dbg_bus,
+    c0_ddr4_parity => c0_ddr4_parity,
+    c0_ddr4_ui_clk => c0_ddr4_ui_clk,
+    c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst,
+    sys_rst => sys_rst,
+    rdDataEn => rdDataEn,
+    rdDataEnd => rdDataEnd,
+    per_rd_done => per_rd_done,
+    rmw_rd_done => rmw_rd_done,
+    wrDataEn => wrDataEn,
+    mc_ACT_n => mc_ACT_n,
+    mcCasSlot => mcCasSlot,
+    mcCasSlot2 => mcCasSlot2,
+    mcRdCAS => mcRdCAS,
+    mcWrCAS => mcWrCAS,
+    winInjTxn => winInjTxn,
+    winRmw => winRmw,
+    gt_data_ready => gt_data_ready,
+    winRank => winRank,
+    tCWL => tCWL,
+    wrData => wrData,
+    wrDataMask => wrDataMask,
+    rdData => rdData,
+    mc_ADR => mc_ADR,
+    mc_BA => mc_BA,
+    mc_CKE => mc_CKE,
+    mc_CS_n => mc_CS_n,
+    mc_ODT => mc_ODT,
+    dBufAdr => dBufAdr,
+    rdDataAddr => rdDataAddr,
+    wrDataAddr => wrDataAddr,
+    winBuf => winBuf,
+    ddr4_act_n => ddr4_act_n,
+    ddr4_adr => ddr4_adr,
+    ddr4_ba => ddr4_ba,
+    ddr4_bg => ddr4_bg,
+    ddr4_par => ddr4_par,
+    ddr4_cke => ddr4_cke,
+    ddr4_odt => ddr4_odt,
+    ddr4_cs_n => ddr4_cs_n,
+    ddr4_ck_t => ddr4_ck_t,
+    ddr4_ck_c => ddr4_ck_c,
+    ddr4_reset_n => ddr4_reset_n,
+    ddr4_parity => ddr4_parity,
+    ddr4_dm_dbi_n => ddr4_dm_dbi_n,
+    ddr4_dq => ddr4_dq,
+    ddr4_dqs_c => ddr4_dqs_c,
+    ddr4_dqs_t => ddr4_dqs_t,
+    mc_BG => mc_BG
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file phy_rdimm_x8_dual.vhd when simulating
+-- the core, phy_rdimm_x8_dual. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v
new file mode 100644
index 0000000..224a6a3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v
@@ -0,0 +1,77 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:28:11 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.v
+// Design      : phy_rdimm_x8_dual
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ddr4_v2_2_10,Vivado 2020.2" *)
+module phy_rdimm_x8_dual(sys_rst, c0_sys_clk_p, c0_sys_clk_n, 
+  c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, 
+  c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, 
+  c0_ddr4_reset_n, c0_ddr4_parity, c0_ddr4_dm_dbi_n, c0_ddr4_dq, c0_ddr4_dqs_c, 
+  c0_ddr4_dqs_t, c0_init_calib_complete, dBufAdr, wrData, wrDataMask, rdData, rdDataAddr, 
+  rdDataEn, rdDataEnd, per_rd_done, rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, 
+  mc_BG, mc_CKE, mc_CS_n, mc_ODT, mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, 
+  gt_data_ready, winBuf, winRank, tCWL, dbg_bus)
+/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dm_dbi_n[8:0],c0_ddr4_dq[71:0],c0_ddr4_dqs_c[8:0],c0_ddr4_dqs_t[8:0],c0_init_calib_complete,dBufAdr[4:0],wrData[575:0],wrDataMask[71:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */;
+  input sys_rst;
+  input c0_sys_clk_p;
+  input c0_sys_clk_n;
+  output c0_ddr4_ui_clk;
+  output c0_ddr4_ui_clk_sync_rst;
+  output dbg_clk;
+  output c0_ddr4_act_n;
+  output [16:0]c0_ddr4_adr;
+  output [1:0]c0_ddr4_ba;
+  output [1:0]c0_ddr4_bg;
+  output [0:0]c0_ddr4_cke;
+  output [0:0]c0_ddr4_odt;
+  output [0:0]c0_ddr4_cs_n;
+  output [0:0]c0_ddr4_ck_t;
+  output [0:0]c0_ddr4_ck_c;
+  output c0_ddr4_reset_n;
+  output c0_ddr4_parity;
+  inout [8:0]c0_ddr4_dm_dbi_n;
+  inout [71:0]c0_ddr4_dq;
+  inout [8:0]c0_ddr4_dqs_c;
+  inout [8:0]c0_ddr4_dqs_t;
+  output c0_init_calib_complete;
+  input [4:0]dBufAdr;
+  input [575:0]wrData;
+  input [71:0]wrDataMask;
+  output [575:0]rdData;
+  output [4:0]rdDataAddr;
+  output [0:0]rdDataEn;
+  output [0:0]rdDataEnd;
+  output [0:0]per_rd_done;
+  output [0:0]rmw_rd_done;
+  output [4:0]wrDataAddr;
+  output [0:0]wrDataEn;
+  input [7:0]mc_ACT_n;
+  input [135:0]mc_ADR;
+  input [15:0]mc_BA;
+  input [15:0]mc_BG;
+  input [7:0]mc_CKE;
+  input [7:0]mc_CS_n;
+  input [7:0]mc_ODT;
+  input [1:0]mcCasSlot;
+  input [0:0]mcCasSlot2;
+  input [0:0]mcRdCAS;
+  input [0:0]mcWrCAS;
+  input [0:0]winInjTxn;
+  input [0:0]winRmw;
+  input gt_data_ready;
+  input [4:0]winBuf;
+  input [1:0]winRank;
+  output [5:0]tCWL;
+  output [511:0]dbg_bus;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl
new file mode 100644
index 0000000..cfc2b35
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl
@@ -0,0 +1,80 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:28:12 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual_stub.vhdl
+-- Design      : phy_rdimm_x8_dual
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity phy_rdimm_x8_dual is
+  Port ( 
+    sys_rst : in STD_LOGIC;
+    c0_sys_clk_p : in STD_LOGIC;
+    c0_sys_clk_n : in STD_LOGIC;
+    c0_ddr4_ui_clk : out STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : out STD_LOGIC;
+    dbg_clk : out STD_LOGIC;
+    c0_ddr4_act_n : out STD_LOGIC;
+    c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
+    c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_reset_n : out STD_LOGIC;
+    c0_ddr4_parity : out STD_LOGIC;
+    c0_ddr4_dm_dbi_n : inout STD_LOGIC_VECTOR ( 8 downto 0 );
+    c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
+    c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 8 downto 0 );
+    c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 8 downto 0 );
+    c0_init_calib_complete : out STD_LOGIC;
+    dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrData : in STD_LOGIC_VECTOR ( 575 downto 0 );
+    wrDataMask : in STD_LOGIC_VECTOR ( 71 downto 0 );
+    rdData : out STD_LOGIC_VECTOR ( 575 downto 0 );
+    rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 );
+    per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ADR : in STD_LOGIC_VECTOR ( 135 downto 0 );
+    mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_CKE : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_CS_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ODT : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winRmw : in STD_LOGIC_VECTOR ( 0 to 0 );
+    gt_data_ready : in STD_LOGIC;
+    winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    winRank : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 )
+  );
+
+end phy_rdimm_x8_dual;
+
+architecture stub of phy_rdimm_x8_dual is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dm_dbi_n[8:0],c0_ddr4_dq[71:0],c0_ddr4_dqs_c[8:0],c0_ddr4_dqs_t[8:0],c0_init_calib_complete,dBufAdr[4:0],wrData[575:0],wrDataMask[71:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[7:0],mc_CS_n[7:0],mc_ODT[7:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_10,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.veo b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.veo
new file mode 100755
index 0000000..ed7e7bf
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.veo
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+pr_read_mem your_instance_name (
+  .clka(clka),    // input wire clka
+  .ena(ena),      // input wire ena
+  .wea(wea),      // input wire [0 : 0] wea
+  .addra(addra),  // input wire [3 : 0] addra
+  .dina(dina),    // input wire [63 : 0] dina
+  .douta(douta)  // output wire [63 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file pr_read_mem.v when simulating
+// the core, pr_read_mem. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.vho b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.vho
new file mode 100755
index 0000000..26d3686
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem.vho
@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT pr_read_mem
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : pr_read_mem
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file pr_read_mem.vhd when simulating
+-- the core, pr_read_mem. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v
new file mode 100644
index 0000000..3121946
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:26:29 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.v
+// Design      : pr_read_mem
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module pr_read_mem(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[3:0],dina[63:0],douta[63:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [3:0]addra;
+  input [63:0]dina;
+  output [63:0]douta;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl
new file mode 100644
index 0000000..2e73c55
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_read_mem/pr_read_mem_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:26:29 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem_stub.vhdl
+-- Design      : pr_read_mem
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity pr_read_mem is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end pr_read_mem;
+
+architecture stub of pr_read_mem is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[3:0],dina[63:0],douta[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo
new file mode 100755
index 0000000..f8828d2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.veo
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+pr_ref_mem your_instance_name (
+  .clka(clka),    // input wire clka
+  .ena(ena),      // input wire ena
+  .wea(wea),      // input wire [0 : 0] wea
+  .addra(addra),  // input wire [5 : 0] addra
+  .dina(dina),    // input wire [63 : 0] dina
+  .douta(douta)  // output wire [63 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file pr_ref_mem.v when simulating
+// the core, pr_ref_mem. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho
new file mode 100755
index 0000000..f319d1e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem.vho
@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT pr_ref_mem
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : pr_ref_mem
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file pr_ref_mem.vhd when simulating
+-- the core, pr_ref_mem. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v
new file mode 100644
index 0000000..277b54f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:26:58 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.v
+// Design      : pr_ref_mem
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module pr_ref_mem(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [5:0]addra;
+  input [63:0]dina;
+  output [63:0]douta;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl
new file mode 100644
index 0000000..0709d2a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/pr_ref_mem/pr_ref_mem_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:26:58 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem_stub.vhdl
+-- Design      : pr_ref_mem
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity pr_ref_mem is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end pr_ref_mem;
+
+architecture stub of pr_ref_mem is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.veo b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.veo
new file mode 100755
index 0000000..f460ca0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.veo
@@ -0,0 +1,77 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+rdback_fifo your_instance_name (
+  .clk(clk),                  // input wire clk
+  .srst(srst),                // input wire srst
+  .din(din),                  // input wire [511 : 0] din
+  .wr_en(wr_en),              // input wire wr_en
+  .rd_en(rd_en),              // input wire rd_en
+  .dout(dout),                // output wire [255 : 0] dout
+  .full(full),                // output wire full
+  .empty(empty),              // output wire empty
+  .valid(valid),              // output wire valid
+  .prog_full(prog_full),      // output wire prog_full
+  .prog_empty(prog_empty),    // output wire prog_empty
+  .wr_rst_busy(wr_rst_busy),  // output wire wr_rst_busy
+  .rd_rst_busy(rd_rst_busy)  // output wire rd_rst_busy
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file rdback_fifo.v when simulating
+// the core, rdback_fifo. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.vho b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.vho
new file mode 100755
index 0000000..b2312a7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo.vho
@@ -0,0 +1,99 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT rdback_fifo
+  PORT (
+    clk : IN STD_LOGIC;
+    srst : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    valid : OUT STD_LOGIC;
+    prog_full : OUT STD_LOGIC;
+    prog_empty : OUT STD_LOGIC;
+    wr_rst_busy : OUT STD_LOGIC;
+    rd_rst_busy : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : rdback_fifo
+  PORT MAP (
+    clk => clk,
+    srst => srst,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty,
+    valid => valid,
+    prog_full => prog_full,
+    prog_empty => prog_empty,
+    wr_rst_busy => wr_rst_busy,
+    rd_rst_busy => rd_rst_busy
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file rdback_fifo.vhd when simulating
+-- the core, rdback_fifo. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v
new file mode 100644
index 0000000..2467ff2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v
@@ -0,0 +1,33 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:26:56 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.v
+// Design      : rdback_fifo
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *)
+module rdback_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty, valid, 
+  prog_full, prog_empty, wr_rst_busy, rd_rst_busy)
+/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy" */;
+  input clk;
+  input srst;
+  input [511:0]din;
+  input wr_en;
+  input rd_en;
+  output [255:0]dout;
+  output full;
+  output empty;
+  output valid;
+  output prog_full;
+  output prog_empty;
+  output wr_rst_busy;
+  output rd_rst_busy;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl
new file mode 100644
index 0000000..b6ee5dd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl
@@ -0,0 +1,42 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:26:56 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.vhdl
+-- Design      : rdback_fifo
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity rdback_fifo is
+  Port ( 
+    clk : in STD_LOGIC;
+    srst : in STD_LOGIC;
+    din : in STD_LOGIC_VECTOR ( 511 downto 0 );
+    wr_en : in STD_LOGIC;
+    rd_en : in STD_LOGIC;
+    dout : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    full : out STD_LOGIC;
+    empty : out STD_LOGIC;
+    valid : out STD_LOGIC;
+    prog_full : out STD_LOGIC;
+    prog_empty : out STD_LOGIC;
+    wr_rst_busy : out STD_LOGIC;
+    rd_rst_busy : out STD_LOGIC
+  );
+
+end rdback_fifo;
+
+architecture stub of rdback_fifo is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.veo b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.veo
new file mode 100755
index 0000000..94ad2db
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.veo
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+scratchpad your_instance_name (
+  .clka(clka),    // input wire clka
+  .ena(ena),      // input wire ena
+  .wea(wea),      // input wire [0 : 0] wea
+  .addra(addra),  // input wire [9 : 0] addra
+  .dina(dina),    // input wire [31 : 0] dina
+  .douta(douta)  // output wire [31 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file scratchpad.v when simulating
+// the core, scratchpad. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.vho b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.vho
new file mode 100755
index 0000000..9f4ca48
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad.vho
@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT scratchpad
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : scratchpad
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file scratchpad.vhd when simulating
+-- the core, scratchpad. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v
new file mode 100644
index 0000000..9db516d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:28:30 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad_stub.v
+// Design      : scratchpad
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module scratchpad(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [9:0]addra;
+  input [31:0]dina;
+  output [31:0]douta;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl
new file mode 100644
index 0000000..5714675
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/scratchpad/scratchpad_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:28:30 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad_stub.vhdl
+-- Design      : scratchpad
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity scratchpad is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end scratchpad;
+
+architecture stub of scratchpad is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma.veo b/projects/U200/U200.ip_user_files/ip/xdma/xdma.veo
new file mode 100755
index 0000000..3ea245b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma.veo
@@ -0,0 +1,95 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:xdma:4.1
+// IP Revision: 8
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+xdma your_instance_name (
+  .sys_clk(sys_clk),                                    // input wire sys_clk
+  .sys_clk_gt(sys_clk_gt),                              // input wire sys_clk_gt
+  .sys_rst_n(sys_rst_n),                                // input wire sys_rst_n
+  .user_lnk_up(user_lnk_up),                            // output wire user_lnk_up
+  .pci_exp_txp(pci_exp_txp),                            // output wire [7 : 0] pci_exp_txp
+  .pci_exp_txn(pci_exp_txn),                            // output wire [7 : 0] pci_exp_txn
+  .pci_exp_rxp(pci_exp_rxp),                            // input wire [7 : 0] pci_exp_rxp
+  .pci_exp_rxn(pci_exp_rxn),                            // input wire [7 : 0] pci_exp_rxn
+  .axi_aclk(axi_aclk),                                  // output wire axi_aclk
+  .axi_aresetn(axi_aresetn),                            // output wire axi_aresetn
+  .usr_irq_req(usr_irq_req),                            // input wire [0 : 0] usr_irq_req
+  .usr_irq_ack(usr_irq_ack),                            // output wire [0 : 0] usr_irq_ack
+  .msi_enable(msi_enable),                              // output wire msi_enable
+  .msi_vector_width(msi_vector_width),                  // output wire [2 : 0] msi_vector_width
+  .cfg_mgmt_addr(cfg_mgmt_addr),                        // input wire [18 : 0] cfg_mgmt_addr
+  .cfg_mgmt_write(cfg_mgmt_write),                      // input wire cfg_mgmt_write
+  .cfg_mgmt_write_data(cfg_mgmt_write_data),            // input wire [31 : 0] cfg_mgmt_write_data
+  .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),          // input wire [3 : 0] cfg_mgmt_byte_enable
+  .cfg_mgmt_read(cfg_mgmt_read),                        // input wire cfg_mgmt_read
+  .cfg_mgmt_read_data(cfg_mgmt_read_data),              // output wire [31 : 0] cfg_mgmt_read_data
+  .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),  // output wire cfg_mgmt_read_write_done
+  .s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),              // input wire [255 : 0] s_axis_c2h_tdata_0
+  .s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),              // input wire s_axis_c2h_tlast_0
+  .s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),            // input wire s_axis_c2h_tvalid_0
+  .s_axis_c2h_tready_0(s_axis_c2h_tready_0),            // output wire s_axis_c2h_tready_0
+  .s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0),              // input wire [31 : 0] s_axis_c2h_tkeep_0
+  .m_axis_h2c_tdata_0(m_axis_h2c_tdata_0),              // output wire [255 : 0] m_axis_h2c_tdata_0
+  .m_axis_h2c_tlast_0(m_axis_h2c_tlast_0),              // output wire m_axis_h2c_tlast_0
+  .m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0),            // output wire m_axis_h2c_tvalid_0
+  .m_axis_h2c_tready_0(m_axis_h2c_tready_0),            // input wire m_axis_h2c_tready_0
+  .m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0)              // output wire [31 : 0] m_axis_h2c_tkeep_0
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file xdma.v when simulating
+// the core, xdma. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma.vho b/projects/U200/U200.ip_user_files/ip/xdma/xdma.vho
new file mode 100755
index 0000000..35829f6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma.vho
@@ -0,0 +1,135 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:xdma:4.1
+-- IP Revision: 8
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT xdma
+  PORT (
+    sys_clk : IN STD_LOGIC;
+    sys_clk_gt : IN STD_LOGIC;
+    sys_rst_n : IN STD_LOGIC;
+    user_lnk_up : OUT STD_LOGIC;
+    pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    axi_aclk : OUT STD_LOGIC;
+    axi_aresetn : OUT STD_LOGIC;
+    usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    msi_enable : OUT STD_LOGIC;
+    msi_vector_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+    cfg_mgmt_write : IN STD_LOGIC;
+    cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    cfg_mgmt_read : IN STD_LOGIC;
+    cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    cfg_mgmt_read_write_done : OUT STD_LOGIC;
+    s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    s_axis_c2h_tlast_0 : IN STD_LOGIC;
+    s_axis_c2h_tvalid_0 : IN STD_LOGIC;
+    s_axis_c2h_tready_0 : OUT STD_LOGIC;
+    s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    m_axis_h2c_tlast_0 : OUT STD_LOGIC;
+    m_axis_h2c_tvalid_0 : OUT STD_LOGIC;
+    m_axis_h2c_tready_0 : IN STD_LOGIC;
+    m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : xdma
+  PORT MAP (
+    sys_clk => sys_clk,
+    sys_clk_gt => sys_clk_gt,
+    sys_rst_n => sys_rst_n,
+    user_lnk_up => user_lnk_up,
+    pci_exp_txp => pci_exp_txp,
+    pci_exp_txn => pci_exp_txn,
+    pci_exp_rxp => pci_exp_rxp,
+    pci_exp_rxn => pci_exp_rxn,
+    axi_aclk => axi_aclk,
+    axi_aresetn => axi_aresetn,
+    usr_irq_req => usr_irq_req,
+    usr_irq_ack => usr_irq_ack,
+    msi_enable => msi_enable,
+    msi_vector_width => msi_vector_width,
+    cfg_mgmt_addr => cfg_mgmt_addr,
+    cfg_mgmt_write => cfg_mgmt_write,
+    cfg_mgmt_write_data => cfg_mgmt_write_data,
+    cfg_mgmt_byte_enable => cfg_mgmt_byte_enable,
+    cfg_mgmt_read => cfg_mgmt_read,
+    cfg_mgmt_read_data => cfg_mgmt_read_data,
+    cfg_mgmt_read_write_done => cfg_mgmt_read_write_done,
+    s_axis_c2h_tdata_0 => s_axis_c2h_tdata_0,
+    s_axis_c2h_tlast_0 => s_axis_c2h_tlast_0,
+    s_axis_c2h_tvalid_0 => s_axis_c2h_tvalid_0,
+    s_axis_c2h_tready_0 => s_axis_c2h_tready_0,
+    s_axis_c2h_tkeep_0 => s_axis_c2h_tkeep_0,
+    m_axis_h2c_tdata_0 => m_axis_h2c_tdata_0,
+    m_axis_h2c_tlast_0 => m_axis_h2c_tlast_0,
+    m_axis_h2c_tvalid_0 => m_axis_h2c_tvalid_0,
+    m_axis_h2c_tready_0 => m_axis_h2c_tready_0,
+    m_axis_h2c_tkeep_0 => m_axis_h2c_tkeep_0
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file xdma.vhd when simulating
+-- the core, xdma. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.v b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.v
new file mode 100644
index 0000000..2267a77
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.v
@@ -0,0 +1,56 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:33:03 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/xdma/xdma_stub.v
+// Design      : xdma
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "xdma_core_top,Vivado 2020.2" *)
+module xdma(sys_clk, sys_clk_gt, sys_rst_n, user_lnk_up, 
+  pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, 
+  usr_irq_ack, msi_enable, msi_vector_width, cfg_mgmt_addr, cfg_mgmt_write, 
+  cfg_mgmt_write_data, cfg_mgmt_byte_enable, cfg_mgmt_read, cfg_mgmt_read_data, 
+  cfg_mgmt_read_write_done, s_axis_c2h_tdata_0, s_axis_c2h_tlast_0, s_axis_c2h_tvalid_0, 
+  s_axis_c2h_tready_0, s_axis_c2h_tkeep_0, m_axis_h2c_tdata_0, m_axis_h2c_tlast_0, 
+  m_axis_h2c_tvalid_0, m_axis_h2c_tready_0, m_axis_h2c_tkeep_0)
+/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]" */;
+  input sys_clk;
+  input sys_clk_gt;
+  input sys_rst_n;
+  output user_lnk_up;
+  output [7:0]pci_exp_txp;
+  output [7:0]pci_exp_txn;
+  input [7:0]pci_exp_rxp;
+  input [7:0]pci_exp_rxn;
+  output axi_aclk;
+  output axi_aresetn;
+  input [0:0]usr_irq_req;
+  output [0:0]usr_irq_ack;
+  output msi_enable;
+  output [2:0]msi_vector_width;
+  input [18:0]cfg_mgmt_addr;
+  input cfg_mgmt_write;
+  input [31:0]cfg_mgmt_write_data;
+  input [3:0]cfg_mgmt_byte_enable;
+  input cfg_mgmt_read;
+  output [31:0]cfg_mgmt_read_data;
+  output cfg_mgmt_read_write_done;
+  input [255:0]s_axis_c2h_tdata_0;
+  input s_axis_c2h_tlast_0;
+  input s_axis_c2h_tvalid_0;
+  output s_axis_c2h_tready_0;
+  input [31:0]s_axis_c2h_tkeep_0;
+  output [255:0]m_axis_h2c_tdata_0;
+  output m_axis_h2c_tlast_0;
+  output m_axis_h2c_tvalid_0;
+  input m_axis_h2c_tready_0;
+  output [31:0]m_axis_h2c_tkeep_0;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl
new file mode 100644
index 0000000..45c3cdc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/xdma/xdma_stub.vhdl
@@ -0,0 +1,60 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:33:04 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/xdma/xdma_stub.vhdl
+-- Design      : xdma
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity xdma is
+  Port ( 
+    sys_clk : in STD_LOGIC;
+    sys_clk_gt : in STD_LOGIC;
+    sys_rst_n : in STD_LOGIC;
+    user_lnk_up : out STD_LOGIC;
+    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    axi_aclk : out STD_LOGIC;
+    axi_aresetn : out STD_LOGIC;
+    usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
+    usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
+    msi_enable : out STD_LOGIC;
+    msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 );
+    cfg_mgmt_write : in STD_LOGIC;
+    cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    cfg_mgmt_read : in STD_LOGIC;
+    cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    cfg_mgmt_read_write_done : out STD_LOGIC;
+    s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 255 downto 0 );
+    s_axis_c2h_tlast_0 : in STD_LOGIC;
+    s_axis_c2h_tvalid_0 : in STD_LOGIC;
+    s_axis_c2h_tready_0 : out STD_LOGIC;
+    s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    m_axis_h2c_tlast_0 : out STD_LOGIC;
+    m_axis_h2c_tvalid_0 : out STD_LOGIC;
+    m_axis_h2c_tready_0 : in STD_LOGIC;
+    m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end xdma;
+
+architecture stub of xdma is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "xdma_core_top,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo
new file mode 100755
index 0000000..6dac95b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.veo
@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+zq_calib_mem your_instance_name (
+  .clka(clka),    // input wire clka
+  .ena(ena),      // input wire ena
+  .wea(wea),      // input wire [0 : 0] wea
+  .addra(addra),  // input wire [5 : 0] addra
+  .dina(dina),    // input wire [63 : 0] dina
+  .douta(douta)  // output wire [63 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file zq_calib_mem.v when simulating
+// the core, zq_calib_mem. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho
new file mode 100755
index 0000000..2763f20
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem.vho
@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT zq_calib_mem
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : zq_calib_mem
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file zq_calib_mem.vhd when simulating
+-- the core, zq_calib_mem. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v
new file mode 100644
index 0000000..21c89b3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Tue Mar  8 14:28:50 2022
+// Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.v
+// Design      : zq_calib_mem
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu200-fsgd2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module zq_calib_mem(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [5:0]addra;
+  input [63:0]dina;
+  output [63:0]douta;
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl
new file mode 100644
index 0000000..cc5c23a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ip/zq_calib_mem/zq_calib_mem_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+-- Date        : Tue Mar  8 14:28:51 2022
+-- Host        : machine running 64-bit Ubuntu 20.04.4 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem_stub.vhdl
+-- Design      : zq_calib_mem
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcu200-fsgd2104-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity zq_calib_mem is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end zq_calib_mem;
+
+architecture stub of zq_calib_mem is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[5:0],dina[63:0],douta[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.2";
+begin
+end;
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v
new file mode 100755
index 0000000..a095c8e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v
@@ -0,0 +1,1198 @@
+//  (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+//   Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axic_sync_clock_converter
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_clock_converter_v1_1_23_axisc_sync_clock_converter # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter C_FAMILY     = "virtex6",
+  parameter integer C_PAYLOAD_WIDTH = 32,
+  parameter integer C_S_ACLK_RATIO = 1,
+  parameter integer C_M_ACLK_RATIO = 1,
+  parameter integer C_MODE = 1  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)
+  )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input wire                         SAMPLE_CYCLE_EARLY,
+  input wire                         SAMPLE_CYCLE,
+  // Slave side
+  input  wire                        S_ACLK,
+  input  wire                        S_ARESETN,
+  input  wire [C_PAYLOAD_WIDTH-1:0]  S_PAYLOAD,
+  input  wire                        S_VALID,
+  output wire                        S_READY,
+
+  // Master side
+  input  wire                        M_ACLK,
+  input  wire                        M_ARESETN,
+  output wire [C_PAYLOAD_WIDTH-1:0]  M_PAYLOAD,
+  output wire                        M_VALID,
+  input  wire                        M_READY
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam [1:0] ZERO = 2'b10;
+localparam [1:0] ONE  = 2'b11;
+localparam [1:0] FULL = 2'b01;
+localparam [1:0] INIT = 2'b00;
+localparam integer P_LIGHT_WT = 0;
+localparam integer P_FULLY_REG = 1;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+generate
+  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru
+    assign M_PAYLOAD = S_PAYLOAD;
+    assign M_VALID   = S_VALID;
+    assign S_READY   = M_READY;      
+  end else begin : gen_sync_clock_converter
+    wire s_sample_cycle;
+    wire s_sample_cycle_early;
+    wire m_sample_cycle;
+    wire m_sample_cycle_early;
+
+    wire slow_aclk;
+    wire slow_areset;
+    reg  s_areset_r;
+    reg  m_areset_r;
+   
+    reg  s_ready_r; 
+    wire s_ready_ns; 
+    reg  m_valid_r; 
+    wire m_valid_ns; 
+    reg  [C_PAYLOAD_WIDTH-1:0] m_payload_r;
+    reg  [C_PAYLOAD_WIDTH-1:0] m_storage_r;
+    wire [C_PAYLOAD_WIDTH-1:0] m_payload_ns; 
+    wire [C_PAYLOAD_WIDTH-1:0] m_storage_ns; 
+    reg  m_ready_hold;
+    wire m_ready_sample;
+    wire load_payload;
+    wire load_storage;
+    wire load_payload_from_storage;
+    reg [1:0] state;
+    reg [1:0] next_state;
+    
+    always @(posedge S_ACLK) begin
+      s_areset_r <= ~(S_ARESETN & M_ARESETN);
+    end
+  
+    always @(posedge M_ACLK) begin
+      m_areset_r <= ~(S_ARESETN & M_ARESETN);
+    end
+
+    assign slow_aclk   = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? M_ACLK   : S_ACLK;
+    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;
+    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;
+    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;
+    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;
+    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;
+
+    // Output flop for S_READY, value is encoded into state machine.
+    assign s_ready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];
+
+    always @(posedge S_ACLK) begin 
+      if (s_areset_r) begin
+        s_ready_r <= 1'b0;
+      end
+      else begin
+        s_ready_r <= s_sample_cycle_early ? s_ready_ns : 1'b0;
+      end
+    end
+
+    assign S_READY = s_ready_r;
+
+    // Output flop for M_VALID
+    assign m_valid_ns = next_state[0];
+
+    always @(posedge M_ACLK) begin 
+      if (m_areset_r) begin
+        m_valid_r <= 1'b0;
+      end
+      else begin
+        m_valid_r <= m_sample_cycle ? m_valid_ns : m_valid_r & ~M_READY;
+      end
+    end
+
+    assign M_VALID = m_valid_r;
+
+    // Hold register for M_READY when M_ACLK is fast.
+    always @(posedge M_ACLK) begin 
+      if (m_areset_r) begin
+        m_ready_hold <= 1'b0;
+      end
+      else begin
+        m_ready_hold <= m_sample_cycle ? 1'b0 : m_ready_sample;
+      end
+    end
+
+    assign m_ready_sample = (M_READY ) | m_ready_hold;
+    // Output/storage flops for PAYLOAD
+    assign m_payload_ns = ~load_payload ? m_payload_r :
+                           load_payload_from_storage ? m_storage_r : 
+                           S_PAYLOAD;
+
+    assign m_storage_ns = (C_MODE == P_FULLY_REG) ? (load_storage ? S_PAYLOAD : m_storage_r) : {C_PAYLOAD_WIDTH{1'b0}};
+
+    always @(posedge slow_aclk) begin 
+      m_payload_r <= m_payload_ns;
+      m_storage_r <= (C_MODE == P_FULLY_REG) ? m_storage_ns : 0;
+    end
+
+    assign M_PAYLOAD = m_payload_r;
+
+    // load logic
+    assign load_storage = (C_MODE == P_FULLY_REG) && (state != FULL);
+    assign load_payload = m_ready_sample || (state == ZERO);
+    assign load_payload_from_storage = (C_MODE == P_FULLY_REG) && (state == FULL) && m_ready_sample;
+    
+    // State machine
+    always @(posedge slow_aclk) begin 
+      state <= next_state;
+    end
+
+    always @* begin 
+      if (slow_areset) begin 
+        next_state = INIT;
+      end else begin
+        case (state)
+          INIT: begin
+            next_state = ZERO;
+          end
+          // No transaction stored locally
+          ZERO: begin
+            if (S_VALID) begin
+              next_state = (C_MODE == P_FULLY_REG) ? ONE : FULL; // Push from empty
+            end
+            else begin
+              next_state = ZERO;
+            end
+          end
+
+          // One transaction stored locally
+          ONE: begin
+            if (m_ready_sample & ~S_VALID) begin 
+              next_state = ZERO; // Read out one so move to ZERO
+            end
+            else if (~m_ready_sample & S_VALID) begin
+              next_state = FULL;  // Got another one so move to FULL
+            end
+            else begin
+              next_state = ONE;
+            end
+          end
+
+          // Storage registers full
+          FULL: begin 
+            if (m_ready_sample) begin
+              next_state = (C_MODE == P_FULLY_REG) ? ONE : ZERO; // Pop from full
+            end
+            else begin
+              next_state = FULL;
+            end
+          end
+          default: begin
+            next_state = ZERO;
+          end
+        endcase // case (state)
+      end
+    end
+  end // gen_sync_clock_converter
+  endgenerate
+endmodule // axisc_sync_clock_converter
+
+`default_nettype wire
+
+
+//  (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+//   Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axic_sync_clock_converter
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_clock_converter_v1_1_23_axisc_async_clock_converter # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_PAYLOAD_WIDTH      = 32,
+  parameter integer C_SYNCHRONIZER_STAGE = 3,
+  parameter integer C_FIFO_DEPTH         = 32
+
+  )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave side
+  input  wire                        s_aclk,
+  input  wire                        s_aresetn,
+  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,
+  input  wire                        s_valid,
+  output wire                        s_ready,
+
+  // Master side
+  input  wire                        m_aclk,
+  input  wire                        m_aresetn,
+  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,
+  output wire                        m_valid,
+  input  wire                        m_ready
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam integer LP_COUNT_WIDTH = f_clogb2(C_FIFO_DEPTH) + 1; // Set to 1 + Depth.
+localparam integer LP_PROG_FULL = C_FIFO_DEPTH - 5; // Set to valid value to avoid DRC error.
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire m_areset_i;
+reg s_and_m_areset_r = 1'b0;
+wire s_full;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+// Synchronize reset into s_aclk domain and combine with s_aresetn.
+xpm_cdc_sync_rst #(
+  .DEST_SYNC_FF    ( C_SYNCHRONIZER_STAGE ) 
+)
+inst_xpm_cdc_sync_rst (
+  .src_rst  ( ~m_aresetn ) ,
+  .dest_rst ( m_areset_i     ) ,
+  .dest_clk ( s_aclk     ) 
+);
+
+always @(posedge s_aclk) begin 
+  s_and_m_areset_r <= ~s_aresetn | m_areset_i;
+end
+
+/*
+XPM_FIFO instantiation template for Asynchronous FIFO configurations
+Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation
+=======================================================================================================================
+
+Parameter usage table, organized as follows:
++---------------------------------------------------------------------------------------------------------------------+
+| Parameter name          | Data type          | Restrictions, if applicable                                          |
+|---------------------------------------------------------------------------------------------------------------------|
+| Description                                                                                                         |
++---------------------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------------------------+
+| FIFO_MEMORY_TYPE        | String             | Must be "auto", "block", or "distributed"                            |
+|---------------------------------------------------------------------------------------------------------------------|
+| Designate the fifo memory primitive (resource type) to use:                                                         |
+|   "auto": Allow Vivado Synthesis to choose                                                                          |
+|   "block": Block RAM FIFO                                                                                           |
+|   "distributed": Distributed RAM FIFO                                                                               |
++---------------------------------------------------------------------------------------------------------------------+
+| FIFO_WRITE_DEPTH        | Integer            | Must be between 16 and 4194304                                       |
+|---------------------------------------------------------------------------------------------------------------------|
+| Defines the FIFO Write Depth, must be power of two                                                                  |
+| In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH-1                                                     |
+| In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+1                                      |
++---------------------------------------------------------------------------------------------------------------------+
+| RELATED_CLOCKS          | Integer            | Must be 0 or 1                                                       |
+|---------------------------------------------------------------------------------------------------------------------|
+| Specifies if the wr_clk and rd_clk are related having the same source but different clock ratios                    |
++---------------------------------------------------------------------------------------------------------------------+
+| WRITE_DATA_WIDTH        | Integer            | Must be between 1 and 4096                                           |
+|---------------------------------------------------------------------------------------------------------------------|
+| Defines the width of the write data port, din                                                                       |
++---------------------------------------------------------------------------------------------------------------------+
+| WR_DATA_COUNT_WIDTH     | Integer            | Must be between 1 and log2(FIFO_WRITE_DEPTH)+1                       |
+|---------------------------------------------------------------------------------------------------------------------|
+| Specifies the width of wr_data_count                                                                                |
++---------------------------------------------------------------------------------------------------------------------+
+| READ_MODE               | String             | Must be "std" or "fwft"                                              |
+|---------------------------------------------------------------------------------------------------------------------|
+|  "std": standard read mode                                                                                          |
+|  "fwft": First-Word-Fall-Through read mode                                                                          |
++---------------------------------------------------------------------------------------------------------------------+
+| FIFO_READ_LATENCY       | Integer            | Must be >= 0                                                         |
+|---------------------------------------------------------------------------------------------------------------------|
+|  Number of output register stages in the read data path                                                             |
+|  If READ_MODE = "fwft", then the only applicable value is 0.                                                        |
++---------------------------------------------------------------------------------------------------------------------+
+| FULL_RESET_VALUE        | Integer            | Must be 0 or 1                                                       |
+|---------------------------------------------------------------------------------------------------------------------|
+|---------------------------------------------------------------------------------------------------------------------|
+|  Sets FULL, PROG_FULL and ALMOST_FULL to FULL_RESET_VALUE during reset                                              |
++---------------------------------------------------------------------------------------------------------------------+
+| USE_ADV_FEATURES        | String             | Must be between "0000" and "1F1F"                                    |
+|---------------------------------------------------------------------------------------------------------------------|
+|  Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count,        |
+|  prog_full, overflow features                                                                                       |
+|    Setting USE_ADV_FEATURES[0]  to 1 enables overflow flag;     Default value of this bit is 1                      |
+|    Setting USE_ADV_FEATURES[1]  to 1 enables prog_full flag;    Default value of this bit is 1                      |
+|    Setting USE_ADV_FEATURES[2]  to 1 enables wr_data_count;     Default value of this bit is 1                      |
+|    Setting USE_ADV_FEATURES[3]  to 1 enables almost_full flag;  Default value of this bit is 0                      |
+|    Setting USE_ADV_FEATURES[4]  to 1 enables wr_ack flag;       Default value of this bit is 0                      |
+|    Setting USE_ADV_FEATURES[8]  to 1 enables underflow flag;    Default value of this bit is 1                      |
+|    Setting USE_ADV_FEATURES[9]  to 1 enables prog_empty flag;   Default value of this bit is 1                      |
+|    Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count;     Default value of this bit is 1                      |
+|    Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0                      |
+|    Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag;   Default value of this bit is 0                      |
++---------------------------------------------------------------------------------------------------------------------+
+| READ_DATA_WIDTH         | Integer            | Must be between >= 1                                                 |
+|---------------------------------------------------------------------------------------------------------------------|
+| Defines the width of the read data port, dout                                                                       |
++---------------------------------------------------------------------------------------------------------------------+
+| RD_DATA_COUNT_WIDTH     | Integer            | Must be between 1 and log2(FIFO_READ_DEPTH)+1                        |
+|---------------------------------------------------------------------------------------------------------------------|
+| Specifies the width of rd_data_count                                                                                |
+| FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH                                                 |
++---------------------------------------------------------------------------------------------------------------------+
+| CDC_SYNC_STAGES         | Integer            | Must be between 2 to 8                                               |
+|---------------------------------------------------------------------------------------------------------------------|
+| Specifies the number of synchronization stages on the CDC path                                                      |
+| Must be < 5 if FIFO_WRITE_DEPTH = 16                                                                                |
++---------------------------------------------------------------------------------------------------------------------+
+| ECC_MODE                | String             | Must be "no_ecc" or "en_ecc"                                         |
+|---------------------------------------------------------------------------------------------------------------------|
+| "no_ecc" : Disables ECC                                                                                             |
+| "en_ecc" : Enables both ECC Encoder and Decoder                                                                     |
++---------------------------------------------------------------------------------------------------------------------+
+| PROG_FULL_THRESH        | Integer            | Must be between "Min_Value" and "Max_Value"                          |
+|---------------------------------------------------------------------------------------------------------------------|
+| Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted.                    |
+| Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))+CDC_SYNC_STAGES                                |
+| Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))                             |
+| If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1                                           |
++---------------------------------------------------------------------------------------------------------------------+
+| PROG_EMPTY_THRESH       | Integer            | Must be between "Min_Value" and "Max_Value"                          |
+|---------------------------------------------------------------------------------------------------------------------|
+| Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted                     |
+| Min_Value = 3 + (READ_MODE_VAL*2)                                                                                   |
+| Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2)                                                                |
+| If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1                                           |
++---------------------------------------------------------------------------------------------------------------------+
+| DOUT_RESET_VALUE        | String             | Must be >="0". Valid hexa decimal value                              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Reset value of read data path.                                                                                      |
++---------------------------------------------------------------------------------------------------------------------+
+| WAKEUP_TIME             | Integer            | Must be 0 or 2                                                       |
+|---------------------------------------------------------------------------------------------------------------------|
+| 0 : Disable sleep.                                                                                                  |
+| 2 : Use Sleep Pin.                                                                                                  |
++---------------------------------------------------------------------------------------------------------------------+
+
+Port usage table, organized as follows:
++---------------------------------------------------------------------------------------------------------------------+
+| Port name      | Direction | Size, in bits                         | Domain | Sense       | Handling if unused      |
+|---------------------------------------------------------------------------------------------------------------------|
+| Description                                                                                                         |
++---------------------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------------------------+
+| sleep          | Input     | 1                                     |        | Active-high | Tie to 1'b0             |
+|---------------------------------------------------------------------------------------------------------------------|
+| Dynamic power saving: If sleep is High, the memory/fifo block is in power saving mode.                              |
+| Synchronous to the slower of wr_clk and rd_clk.                                                                     |
++---------------------------------------------------------------------------------------------------------------------+
+| rst            | Input     | 1                                     | wr_clk | Active-high | Required                |
++---------------------------------------------------------------------------------------------------------------------+
+| Reset: Must be synchronous to wr_clk. Must be applied only when wr_clk and rd_clk are stable and free-running.      |
+| Once reset is applied to FIFO, the subsequent reset must be applied only when wr_rst_busy becomes zero from one.    |
++---------------------------------------------------------------------------------------------------------------------+
+| wr_clk         | Input     | 1                                     |        | Rising edge | Required                |
+|---------------------------------------------------------------------------------------------------------------------|
+| Write clock: Used for write operation. wr_clk must be a free running clock.                                         |
++---------------------------------------------------------------------------------------------------------------------+
+| wr_en          | Input     | 1                                     | wr_clk | Active-high | Required                |
+|---------------------------------------------------------------------------------------------------------------------|
+| Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO.        |
+| Must be held active-low when rst or wr_rst_busy or rd_rst_busy is active high.                                      |
++---------------------------------------------------------------------------------------------------------------------+
+| din            | Input     | WRITE_DATA_WIDTH                      | wr_clk |             | Required                |
+|---------------------------------------------------------------------------------------------------------------------|
+| Write Data: The input data bus used when writing the FIFO.                                                          |
++---------------------------------------------------------------------------------------------------------------------+
+| full           | Output    | 1                                     | wr_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Full Flag: When asserted, this signal indicates that the FIFO is full.                                              |
+| Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive       |
+| to the contents of the FIFO.                                                                                        |
++---------------------------------------------------------------------------------------------------------------------+
+| overflow       | Output    | 1                                     | wr_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected,              |
+| because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO.                      |
++---------------------------------------------------------------------------------------------------------------------+
+| wr_rst_busy    | Output    | 1                                     | wr_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state.                   |
++---------------------------------------------------------------------------------------------------------------------+
+| almost_full    | Output    | 1                                     | wr_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.|
++---------------------------------------------------------------------------------------------------------------------+
+| wr_ack         | Output    | 1                                     | wr_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded.    |
++---------------------------------------------------------------------------------------------------------------------+
+| rd_clk         | Input     | 1                                     |        | Rising edge | Required                |
+|---------------------------------------------------------------------------------------------------------------------|
+| Read clock: Used for read operation. rd_clk must be a free running clock.                                           |
++---------------------------------------------------------------------------------------------------------------------+
+| rd_en          | Input     | 1                                     | rd_clk | Active-high | Required                |
+|---------------------------------------------------------------------------------------------------------------------|
+| Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO         |
+| Must be held active-low when rst or wr_rst_busy or rd_rst_busy is active high.                                      |
++---------------------------------------------------------------------------------------------------------------------+
+| dout           | Output    | READ_DATA_WIDTH                       | rd_clk |             | Required                |
+|---------------------------------------------------------------------------------------------------------------------|
+| Read Data: The output data bus is driven when reading the FIFO.                                                     |
++---------------------------------------------------------------------------------------------------------------------+
+| empty          | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Empty Flag: When asserted, this signal indicates that the FIFO is empty.                                            |
+| Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO.     |
++---------------------------------------------------------------------------------------------------------------------+
+| underflow      | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected                     |
+| because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO.                                   |
++---------------------------------------------------------------------------------------------------------------------+
+| rd_rst_busy    | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state.                     |
++---------------------------------------------------------------------------------------------------------------------+
+| prog_full      | Output    | 1                                     | wr_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal            |
+| to the programmable full threshold value.                                                                           |
+| It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value.          |
++---------------------------------------------------------------------------------------------------------------------+
+| wr_data_count  | Output    | WR_DATA_COUNT_WIDTH                   | wr_clk |             | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Write Data Count: This bus indicates the number of words written into the FIFO.                                     |
++---------------------------------------------------------------------------------------------------------------------+
+| prog_empty     | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal              |
+| to the programmable empty threshold value.                                                                          |
+| It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value.              |
++---------------------------------------------------------------------------------------------------------------------+
+| rd_data_count  | Output    | RD_DATA_COUNT_WIDTH                   | rd_clk |             | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Read Data Count: This bus indicates the number of words read from the FIFO.                                         |
++---------------------------------------------------------------------------------------------------------------------+
+| almost_empty   | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to|
+| empty.                                                                                                              |
++---------------------------------------------------------------------------------------------------------------------+
+| data_valid     | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout).        |
++---------------------------------------------------------------------------------------------------------------------+
+| injectsbiterr  | Intput    | 1                                     | wr_clk | Active-high | Tie to 1'b0             |
+|---------------------------------------------------------------------------------------------------------------------|
+| Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or                  |
+| built-in FIFO macros.                                                                                               |
++---------------------------------------------------------------------------------------------------------------------+
+| injectdbiterr  | Intput    | 1                                     | wr_clk | Active-high | Tie to 1'b0             |
+|---------------------------------------------------------------------------------------------------------------------|
+| Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or                  |
+| built-in FIFO macros.                                                                                               |
++---------------------------------------------------------------------------------------------------------------------+
+| sbiterr        | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.                             |
++---------------------------------------------------------------------------------------------------------------------+
+| dbiterr        | Output    | 1                                     | rd_clk | Active-high | Leave open              |
+|---------------------------------------------------------------------------------------------------------------------|
+| Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.|
++---------------------------------------------------------------------------------------------------------------------+
+*/
+
+//  xpm_fifo_async      : In order to incorporate this function into the design, the following module instantiation
+//       Verilog        : needs to be placed in the body of the design code.  The default values for the parameters
+//        module        : may be changed to meet design requirements.  The instance name (xpm_fifo_async)
+//     instantiation    : and/or the port declarations within the parenthesis may be changed to properly reference and
+//         code         : connect this function to the design.  All inputs and outputs must be connected, unless
+//                      : otherwise specified.
+
+// xpm_fifo_async: Asynchronous FIFO
+// Xilinx Parameterized Macro, Version 2018.1
+xpm_fifo_async # (
+
+  .FIFO_MEMORY_TYPE    ( "distributed"   ) , // string; "auto", "block", or "distributed";
+  .ECC_MODE            ( "no_ecc"        ) , // string; "no_ecc" or "en_ecc";
+  .RELATED_CLOCKS      ( 0               ) , // positive integer; 0 or 1
+  .FIFO_WRITE_DEPTH    ( C_FIFO_DEPTH    ) , // positive integer
+  .WRITE_DATA_WIDTH    ( C_PAYLOAD_WIDTH ) , // positive integer
+  .WR_DATA_COUNT_WIDTH ( LP_COUNT_WIDTH  ) , // positive integer
+  .PROG_FULL_THRESH    ( LP_PROG_FULL    ) , // positive integer
+  .FULL_RESET_VALUE    ( 1               ) , // positive integer; 0 or 1 
+  .USE_ADV_FEATURES    ( "1000"          ) , // string; "0000" to "1F1F"; "1000" = enable data_valid.
+  .READ_MODE           ( "fwft"          ) , // string; "std" or "fwft";
+  .FIFO_READ_LATENCY   ( 1               ) , // positive integer;
+  .READ_DATA_WIDTH     ( C_PAYLOAD_WIDTH ) , // positive integer
+  .RD_DATA_COUNT_WIDTH ( LP_COUNT_WIDTH  ) , // positive integer
+  .PROG_EMPTY_THRESH   ( 10              ) , // positive integer
+  .DOUT_RESET_VALUE    ( "0"             ) , // string
+  .CDC_SYNC_STAGES     ( C_SYNCHRONIZER_STAGE ) , // positive integer
+  .WAKEUP_TIME         ( 0               )   // positive integer; 0 or 2;
+
+) xpm_fifo_async_inst (
+
+  .rst           ( s_and_m_areset_r ) ,
+  .wr_clk        ( s_aclk           ) ,
+  .wr_en         ( s_valid          ) ,
+  .din           ( s_payload        ) ,
+  .full          ( s_full           ) ,
+  .overflow      (                  ) ,
+  .prog_full     (                  ) ,
+  .wr_data_count (                  ) ,
+  .almost_full   (                  ) ,
+  .wr_ack        (                  ) ,
+  .wr_rst_busy   (                  ) ,
+  .rd_clk        ( m_aclk           ) ,
+  .rd_en         ( m_ready          ) ,
+  .dout          ( m_payload        ) ,
+  .empty         (                  ) ,
+  .underflow     (                  ) ,
+  .rd_rst_busy   (                  ) ,
+  .prog_empty    (                  ) ,
+  .rd_data_count (                  ) ,
+  .almost_empty  (                  ) ,
+  .data_valid    ( m_valid          ) ,
+  .sleep         ( 1'b0             ) ,
+  .injectsbiterr ( 1'b0             ) ,
+  .injectdbiterr ( 1'b0             ) ,
+  .sbiterr       (                  ) ,
+  .dbiterr       (                  ) 
+
+);
+
+// End of xpm_fifo_async instance declaration
+
+assign s_ready = ~s_full;
+
+endmodule // axisc_async_clock_converter
+
+`default_nettype wire
+
+
+//  (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+//   Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axic_register_slice
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_clock_converter_v1_1_23_axisc_sample_cycle_ratio # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter C_RATIO = 2 // Must be > 0
+  )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                    SLOW_ACLK,
+  input  wire                    FAST_ACLK,
+
+  output wire                    SAMPLE_CYCLE_EARLY,
+  output wire                    SAMPLE_CYCLE
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; 
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg                slow_aclk_div2 = 0;
+reg                posedge_finder_first;
+reg                posedge_finder_second;
+wire               first_edge;
+wire               second_edge;
+reg  [P_DELAY-1:0] sample_cycle_d;
+(* shreg_extract = "no" *) reg                sample_cycle_r;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+  if (C_RATIO == 1) begin : gen_always_sample
+    assign SAMPLE_CYCLE_EARLY = 1'b1;
+    assign SAMPLE_CYCLE = 1'b1;
+  end
+  else begin : gen_sample_cycle
+    genvar i;
+    always @(posedge SLOW_ACLK) begin 
+      slow_aclk_div2 <= ~slow_aclk_div2;
+    end
+
+    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock
+    always @(posedge FAST_ACLK) begin 
+      posedge_finder_first <= slow_aclk_div2;
+    end
+    always @(posedge FAST_ACLK) begin 
+      posedge_finder_second <= ~slow_aclk_div2;
+    end
+
+    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
+    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
+
+    always @(*) begin 
+      sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
+    end
+   
+    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
+    // the clock one cycle before the posedge.
+    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay
+      always @(posedge FAST_ACLK) begin
+        sample_cycle_d[i-1] <= sample_cycle_d[i];
+      end
+    end
+
+    always @(posedge FAST_ACLK) begin 
+      sample_cycle_r <= sample_cycle_d[0];
+    end
+    assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
+    assign SAMPLE_CYCLE = sample_cycle_r;
+  end
+endgenerate
+
+endmodule // axisc_sample_cycle_ratio
+
+`default_nettype wire
+
+
+//  (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axis_clock_converter
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axis_clock_converter
+//     util_aclken_converter (optional)
+//     fifo_generator
+//       or
+//     axisc_sync_clock_converter
+//     util_aclken_converter (optional)
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_clock_converter_v1_1_23_axis_clock_converter #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter         C_FAMILY           = "virtex6",
+  parameter integer C_AXIS_TDATA_WIDTH = 32,
+  parameter integer C_AXIS_TID_WIDTH   = 1,
+  parameter integer C_AXIS_TDEST_WIDTH = 1,
+  parameter integer C_AXIS_TUSER_WIDTH = 1,
+  parameter [31:0]  C_AXIS_SIGNAL_SET  = 32'hFF,
+  // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+  //   [0] => TREADY present
+  //   [1] => TDATA present
+  //   [2] => TSTRB present, TDATA must be present
+  //   [3] => TKEEP present, TDATA must be present
+  //   [4] => TLAST present
+  //   [5] => TID present
+  //   [6] => TDEST present
+  //   [7] => TUSER present
+  parameter integer C_IS_ACLK_ASYNC     = 1,
+  parameter integer C_SYNCHRONIZER_STAGE = 2,
+  parameter integer C_S_AXIS_ACLK_RATIO = 1,
+  parameter integer C_M_AXIS_ACLK_RATIO = 2,
+  parameter integer C_ACLKEN_CONV_MODE  = 0
+  // C_ACLKEN_CONV_MODE: Determines how to handle the clock enable pins during
+  // clock conversion
+  // 0 -- Clock enables not converted
+  // 1 -- s_axis_aclken can toggle,  m_axis_aclken always high.
+  // 2 -- s_axis_aclken always high, m_axis_aclken can toggle.
+  // 3 -- s_axis_aclken can toggle,  m_axis_aclken can toggle.
+  )
+  (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+   // System Signals
+   input wire                             s_axis_aresetn,
+   input wire                             m_axis_aresetn,
+   input wire                             s_axis_aclken,
+   input wire                             m_axis_aclken,
+
+   // Slave side
+   input  wire                            s_axis_aclk,
+   input  wire                            s_axis_tvalid,
+   output wire                            s_axis_tready,
+   input  wire [C_AXIS_TDATA_WIDTH-1:0]   s_axis_tdata,
+   input  wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
+   input  wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
+   input  wire                            s_axis_tlast,
+   input  wire [C_AXIS_TID_WIDTH-1:0]     s_axis_tid,
+   input  wire [C_AXIS_TDEST_WIDTH-1:0]   s_axis_tdest,
+   input  wire [C_AXIS_TUSER_WIDTH-1:0]   s_axis_tuser,
+
+   // Master side
+   input  wire                            m_axis_aclk,
+   output wire                            m_axis_tvalid,
+   input  wire                            m_axis_tready,
+   output wire [C_AXIS_TDATA_WIDTH-1:0]   m_axis_tdata,
+   output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb,
+   output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
+   output wire                            m_axis_tlast,
+   output wire [C_AXIS_TID_WIDTH-1:0]     m_axis_tid,
+   output wire [C_AXIS_TDEST_WIDTH-1:0]   m_axis_tdest,
+   output wire [C_AXIS_TUSER_WIDTH-1:0]   m_axis_tuser
+
+   );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam integer LP_S_ACLKEN_CAN_TOGGLE = (C_ACLKEN_CONV_MODE == 1) || (C_ACLKEN_CONV_MODE == 3);
+localparam integer LP_M_ACLKEN_CAN_TOGGLE = (C_ACLKEN_CONV_MODE == 2) || (C_ACLKEN_CONV_MODE == 3);
+localparam integer P_FIFO_DEPTH           = 32; // clock converter use of fifo_gen be fixed 
+                                                // at 32 deep fifo.
+                                          
+localparam integer P_S_AXIS_ACLK_RATIO    = f_lcm(C_S_AXIS_ACLK_RATIO, C_M_AXIS_ACLK_RATIO) / C_M_AXIS_ACLK_RATIO;
+localparam integer P_M_AXIS_ACLK_RATIO    = f_lcm(C_S_AXIS_ACLK_RATIO, C_M_AXIS_ACLK_RATIO) / C_S_AXIS_ACLK_RATIO;
+                                          
+localparam integer P_INST_ASYNC_CONV      =  C_IS_ACLK_ASYNC || (P_S_AXIS_ACLK_RATIO != 1 && P_M_AXIS_ACLK_RATIO != 1);
+                                          
+localparam integer P_TPAYLOAD_WIDTH       = f_payload_width(C_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH, 
+                                                 C_AXIS_TDEST_WIDTH, C_AXIS_TUSER_WIDTH, 
+                                                 C_AXIS_SIGNAL_SET);
+localparam integer P_SAMPLE_CYCLE_RATIO   = (C_S_AXIS_ACLK_RATIO > C_M_AXIS_ACLK_RATIO) 
+                                            ? C_S_AXIS_ACLK_RATIO : C_M_AXIS_ACLK_RATIO;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [P_TPAYLOAD_WIDTH-1:0] s_axis_tpayload;
+
+wire [P_TPAYLOAD_WIDTH-1:0] d1_tpayload;
+wire                        d1_tvalid;
+wire                        d1_tready;
+
+wire [P_TPAYLOAD_WIDTH-1:0] d2_tpayload;
+wire                        d2_tvalid;
+wire                        d2_tready;
+
+wire [P_TPAYLOAD_WIDTH-1:0] m_axis_tpayload;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+axis_infrastructure_v1_1_0_util_axis2vector #(
+  .C_TDATA_WIDTH    ( C_AXIS_TDATA_WIDTH ) ,
+  .C_TID_WIDTH      ( C_AXIS_TID_WIDTH   ) ,
+  .C_TDEST_WIDTH    ( C_AXIS_TDEST_WIDTH ) ,
+  .C_TUSER_WIDTH    ( C_AXIS_TUSER_WIDTH ) ,
+  .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH   ) ,
+  .C_SIGNAL_SET     ( C_AXIS_SIGNAL_SET  ) 
+)
+util_axis2vector_0 (
+  .TDATA    ( s_axis_tdata    ) ,
+  .TSTRB    ( s_axis_tstrb    ) ,
+  .TKEEP    ( s_axis_tkeep    ) ,
+  .TLAST    ( s_axis_tlast    ) ,
+  .TID      ( s_axis_tid      ) ,
+  .TDEST    ( s_axis_tdest    ) ,
+  .TUSER    ( s_axis_tuser    ) ,
+  .TPAYLOAD ( s_axis_tpayload )
+);
+
+generate
+  if (LP_S_ACLKEN_CAN_TOGGLE) begin : gen_s_aclken_converter
+    axis_infrastructure_v1_1_0_util_aclken_converter #( 
+      .C_PAYLOAD_WIDTH       ( P_TPAYLOAD_WIDTH       ) ,
+      .C_S_ACLKEN_CAN_TOGGLE ( LP_S_ACLKEN_CAN_TOGGLE ) ,
+      .C_M_ACLKEN_CAN_TOGGLE ( 0                      ) 
+    )
+    s_util_aclken_converter_0 ( 
+      .ACLK      ( s_axis_aclk     ) ,
+      .ARESETN   ( s_axis_aresetn  ) ,
+      .S_ACLKEN  ( s_axis_aclken   ) ,
+      .S_PAYLOAD ( s_axis_tpayload ) ,
+      .S_VALID   ( s_axis_tvalid   ) ,
+      .S_READY   ( s_axis_tready   ) ,
+      .M_ACLKEN  ( 1'b1            ) ,
+      .M_PAYLOAD ( d1_tpayload     ) ,
+      .M_VALID   ( d1_tvalid       ) ,
+      .M_READY   ( d1_tready       )
+    );
+  end
+  else begin : gen_s_aclken_passthru
+    assign d1_tpayload = s_axis_tpayload;
+    assign d1_tvalid   = s_axis_tvalid;
+    assign s_axis_tready = d1_tready;
+  end
+
+  if (P_INST_ASYNC_CONV) begin : gen_async_conv
+    // Use xpm_fifo in 2018.1+ for future part support.
+    axis_clock_converter_v1_1_23_axisc_async_clock_converter #( 
+      .C_PAYLOAD_WIDTH      ( P_TPAYLOAD_WIDTH     ) ,
+      .C_FIFO_DEPTH         ( P_FIFO_DEPTH         ) ,
+      .C_SYNCHRONIZER_STAGE ( C_SYNCHRONIZER_STAGE ) 
+    )
+    axisc_async_clock_converter_0 (
+      .s_aclk    ( s_axis_aclk    ) ,
+      .s_aresetn ( s_axis_aresetn ) ,
+      .s_payload ( d1_tpayload    ) ,
+      .s_valid   ( d1_tvalid      ) ,
+      .s_ready   ( d1_tready      ) ,
+      .m_aclk    ( m_axis_aclk    ) ,
+      .m_aresetn ( m_axis_aresetn ) ,
+      .m_payload ( d2_tpayload    ) ,
+      .m_valid   ( d2_tvalid      ) ,
+      .m_ready   ( d2_tready      ) 
+    );
+
+  end
+  else begin : gen_sync_ck_conv
+
+    wire                        slow_aclk;
+    wire                        fast_aclk;
+    wire                        sample_cycle_early;
+    wire                        sample_cycle;
+
+    // Sample cycle used to determine when to assert a signal on a fast clock
+    // to be flopped onto a slow clock.
+    assign slow_aclk   = (C_S_AXIS_ACLK_RATIO > C_M_AXIS_ACLK_RATIO) ? m_axis_aclk   : s_axis_aclk;
+    assign fast_aclk   = (C_S_AXIS_ACLK_RATIO < C_M_AXIS_ACLK_RATIO) ? m_axis_aclk   : s_axis_aclk;
+
+    axis_clock_converter_v1_1_23_axisc_sample_cycle_ratio #(
+      .C_RATIO ( P_SAMPLE_CYCLE_RATIO )
+    ) 
+    axisc_sample_cycle_ratio_m (
+      .SLOW_ACLK          ( slow_aclk          ) ,
+      .FAST_ACLK          ( fast_aclk          ) ,
+      .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
+      .SAMPLE_CYCLE       ( sample_cycle       ) 
+    );
+
+    axis_clock_converter_v1_1_23_axisc_sync_clock_converter #( 
+      .C_FAMILY        ( C_FAMILY            ) ,
+      .C_PAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH    ) ,
+      .C_S_ACLK_RATIO  ( P_S_AXIS_ACLK_RATIO ) ,
+      .C_M_ACLK_RATIO  ( P_M_AXIS_ACLK_RATIO ) ,
+      .C_MODE          ( 1 )
+    )
+    axisc_sync_clock_converter_0 (
+      .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
+      .SAMPLE_CYCLE       ( sample_cycle       ) ,
+      .S_ACLK             ( s_axis_aclk        ) ,
+      .S_ARESETN          ( s_axis_aresetn     ) ,
+      .S_PAYLOAD          ( d1_tpayload        ) ,
+      .S_VALID            ( d1_tvalid          ) ,
+      .S_READY            ( d1_tready          ) ,
+      .M_ACLK             ( m_axis_aclk        ) ,
+      .M_ARESETN          ( m_axis_aresetn     ) ,
+      .M_PAYLOAD          ( d2_tpayload        ) ,
+      .M_VALID            ( d2_tvalid          ) ,
+      .M_READY            ( d2_tready          ) 
+    );
+  end
+
+  if (LP_M_ACLKEN_CAN_TOGGLE) begin : gen_m_aclken_converter
+    axis_infrastructure_v1_1_0_util_aclken_converter #( 
+      .C_PAYLOAD_WIDTH       ( P_TPAYLOAD_WIDTH       ) ,
+      .C_S_ACLKEN_CAN_TOGGLE ( 0                      ) ,
+      .C_M_ACLKEN_CAN_TOGGLE ( LP_M_ACLKEN_CAN_TOGGLE ) 
+    )
+    m_util_aclken_converter_0 ( 
+      .ACLK      ( m_axis_aclk     ) ,
+      .ARESETN   ( m_axis_aresetn  ) ,
+      .S_ACLKEN  ( 1'b1            ) ,
+      .S_PAYLOAD ( d2_tpayload     ) ,
+      .S_VALID   ( d2_tvalid       ) ,
+      .S_READY   ( d2_tready       ) ,
+      .M_ACLKEN  ( m_axis_aclken   ) ,
+      .M_PAYLOAD ( m_axis_tpayload ) ,
+      .M_VALID   ( m_axis_tvalid   ) ,
+      .M_READY   ( m_axis_tready   ) 
+    );
+  end
+  else begin : gen_m_aclken_passthru
+    assign m_axis_tpayload = d2_tpayload;
+    assign m_axis_tvalid = d2_tvalid;
+    assign d2_tready = m_axis_tready;
+  end
+
+endgenerate
+
+axis_infrastructure_v1_1_0_util_vector2axis #(
+  .C_TDATA_WIDTH    ( C_AXIS_TDATA_WIDTH ) ,
+  .C_TID_WIDTH      ( C_AXIS_TID_WIDTH   ) ,
+  .C_TDEST_WIDTH    ( C_AXIS_TDEST_WIDTH ) ,
+  .C_TUSER_WIDTH    ( C_AXIS_TUSER_WIDTH ) ,
+  .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH   ) ,
+  .C_SIGNAL_SET     ( C_AXIS_SIGNAL_SET  ) 
+)
+util_vector2axis_0 (
+  .TPAYLOAD ( m_axis_tpayload ) ,
+  .TDATA    ( m_axis_tdata    ) ,
+  .TSTRB    ( m_axis_tstrb    ) ,
+  .TKEEP    ( m_axis_tkeep    ) ,
+  .TLAST    ( m_axis_tlast    ) ,
+  .TID      ( m_axis_tid      ) ,
+  .TDEST    ( m_axis_tdest    ) ,
+  .TUSER    ( m_axis_tuser    ) 
+);
+
+endmodule // axis_clock_converter
+
+`default_nettype wire
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_0.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_0.vh
new file mode 100755
index 0000000..14d3524
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_0.vh
@@ -0,0 +1,337 @@
+//  (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+//   f_clogb2
+//   f_gcd
+//   f_lcm
+//   f_get_tdata_indx
+//   f_get_tstrb_indx
+//   f_get_tkeep_indx
+//   f_get_tlast_indx
+//   f_get_tid_indx
+//   f_get_tdest_indx
+//   f_get_tuser_indx
+//   f_payload_width
+// Tasks:
+//   t_display_tdata_error
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+// Define Signal Set indices
+localparam G_INDX_SS_TREADY = 0;
+localparam G_INDX_SS_TDATA  = 1;
+localparam G_INDX_SS_TSTRB  = 2;
+localparam G_INDX_SS_TKEEP  = 3;
+localparam G_INDX_SS_TLAST  = 4;
+localparam G_INDX_SS_TID    = 5;
+localparam G_INDX_SS_TDEST  = 6;
+localparam G_INDX_SS_TUSER  = 7;
+localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
+localparam G_MASK_SS_TDATA  = 32'h1 << G_INDX_SS_TDATA;
+localparam G_MASK_SS_TSTRB  = 32'h1 << G_INDX_SS_TSTRB;
+localparam G_MASK_SS_TKEEP  = 32'h1 << G_INDX_SS_TKEEP;
+localparam G_MASK_SS_TLAST  = 32'h1 << G_INDX_SS_TLAST;
+localparam G_MASK_SS_TID    = 32'h1 << G_INDX_SS_TID  ;
+localparam G_MASK_SS_TDEST  = 32'h1 << G_INDX_SS_TDEST;
+localparam G_MASK_SS_TUSER  = 32'h1 << G_INDX_SS_TUSER;
+
+// Task DRC error levels
+localparam G_TASK_SEVERITY_ERR   = 2;
+localparam G_TASK_SEVERITY_WARNING = 1;
+localparam G_TASK_SEVERITY_INFO    = 0;
+
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Functions
+///////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+  function integer f_clogb2 (input integer size);
+    integer s;
+    begin
+      s = size;
+      s = s - 1;
+      for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+            s = s >> 1;
+    end
+  endfunction // clogb2
+
+  // Calculates the Greatest Common Divisor between two integers using the
+  // euclidean algorithm.
+  function automatic integer f_gcd (
+    input integer a,
+    input integer b
+    );
+    begin : main
+      if (a == 0) begin
+        f_gcd = b;
+      end else if (b == 0) begin
+        f_gcd = a;
+      end else if (a > b) begin
+        f_gcd = f_gcd(a % b, b);
+      end else begin
+        f_gcd = f_gcd(a, b % a);
+      end
+    end
+  endfunction
+
+  // Calculates the Lowest Common Denominator between two integers
+  function integer f_lcm (
+    input integer a,
+    input integer b
+    );
+    begin : main
+      f_lcm = ( a / f_gcd(a, b)) * b; 
+    end
+  endfunction
+
+  // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tdata_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      f_get_tdata_indx = 0;
+    end
+  endfunction
+
+  // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tstrb_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
+      // If TDATA exists, then add its width to its base to get the tstrb index
+      f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tkeep_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tlast_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tid_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tdest_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tuser_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
+    end
+  endfunction
+
+  // Payload is the sum of all the AXIS signals present except for
+  // TREADY/TVALID
+  function integer f_payload_width (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
+      f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
+      // Ensure that the return value is never less than 1
+      f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
+    end
+  endfunction
+
+  task t_check_tdata_width(
+    input  integer    data_width,
+    input  [8*80-1:0] var_name,
+    input  [8*80-1:0] inst_name,
+    input  integer    severity_lvl,
+    output integer    ret_val
+  );
+    // Severity levels:
+    // 0 = INFO
+    // 1 = WARNING
+    // 2 = ERROR
+    begin : t_check_tdata_width
+      if (data_width%8 != 0) begin  
+        //       000       1          2         3         4         5         6         7         8
+        //       012       0          0         0         0         0         0         0         0
+        if (severity_lvl >= 2) begin
+        $display("ERROR: %m::%s", inst_name);
+        end else if (severity_lvl == 1) begin
+        $display("WARNING: %m::%s", inst_name);
+        end else begin
+        $display("INFO: %m::%s", inst_name);
+        end
+        $display("       Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
+        $display("       AXI4-Stream data width is only defined for byte multiples. See the ");
+        $display("       AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
+        $display("       information.");
+        ret_val = 1;
+      end else begin
+        ret_val = 0;
+      end
+    end
+  endtask
+
+  task t_check_tuser_width(
+    input  integer    tuser_width,
+    input  [8*80-1:0] tuser_name,
+    input  integer    tdata_width,
+    input  [8*80-1:0] tdata_name,
+    input  [8*80-1:0] inst_name,
+    input  integer    severity_lvl,
+    output integer    ret_val
+  );
+    // Severity levels:
+    // 0 = INFO
+    // 1 = WARNING
+    // 2 = ERROR
+    begin : t_check_tuser_width
+      integer tdata_bytes; 
+      tdata_bytes = tdata_width/8;
+      if ((tuser_width%tdata_bytes) != 0) begin  
+        //       000       1          2         3         4         5         6         7         8
+        //       012       0          0         0         0         0         0         0         0
+        if (severity_lvl >= 2) begin
+        $display("ERROR: %m::%s", inst_name);
+        end else if (severity_lvl == 1) begin
+        $display("WARNING: %m::%s", inst_name);
+        end else begin
+        $display("INFO: %m::%s", inst_name);
+        end
+        $display("       Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
+        $display("       multiple of the width of the interface (%s == %2d) in bytes.'  AXI4-Stream", tdata_name, tdata_width);
+        $display("       TUSER width in this module is only defined when the TUSER is the");
+        $display("       recommended value.  See the AMBA4 AXI4-Stream Protocol Specification v1.0");
+        $display("       Section 2.1, 2.3.3 and 2.8 for more information.  ");
+        ret_val = 1;
+      end else begin
+        ret_val = 0;
+      end
+    end
+  endtask
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v
new file mode 100755
index 0000000..e44cf42
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v
@@ -0,0 +1,1324 @@
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+////////////////////////////////////////////////////////////
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized Mux using MUXF7/8.
+//  Any mux ratio.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   mux_enc
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
+`define AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_mux_enc #
+  (
+   parameter         C_FAMILY                       = "rtl",
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_RATIO                        = 4,
+                       // Mux select ratio. Can be any binary value (>= 1)
+   parameter integer C_SEL_WIDTH                    = 2,
+                       // Log2-ceiling of C_RATIO (>= 1)
+   parameter integer C_DATA_WIDTH                   = 1
+                       // Data width for comparator (>= 1)
+   )
+  (
+   input  wire [C_SEL_WIDTH-1:0]                    S,
+   input  wire [C_RATIO*C_DATA_WIDTH-1:0]           A,
+   output wire [C_DATA_WIDTH-1:0]                   O,
+   input  wire                                      OE
+   );
+  
+  wire [C_DATA_WIDTH-1:0] o_i;
+  genvar bit_cnt;
+  
+  function [C_DATA_WIDTH-1:0] f_mux
+    (
+     input [C_SEL_WIDTH-1:0] s,
+     input [C_RATIO*C_DATA_WIDTH-1:0] a
+     );
+    integer i;
+    reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
+    begin
+      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
+      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
+        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = 
+          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+      end
+      f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
+    end
+  endfunction
+  
+  function [C_DATA_WIDTH-1:0] f_mux4
+    (
+     input [1:0] s,
+     input [4*C_DATA_WIDTH-1:0] a
+     );
+    integer i;
+    reg [4*C_DATA_WIDTH-1:0] carry;
+    begin
+      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
+      for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
+        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = 
+          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+      end
+      f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
+    end
+  endfunction
+  
+  assign O = o_i & {C_DATA_WIDTH{OE}};  // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
+  
+  generate
+    if ( C_RATIO < 2 ) begin : gen_bypass
+      assign o_i = A;
+    end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
+      assign o_i = f_mux(S, A);
+      
+    end else begin : gen_fpga
+      wire [C_DATA_WIDTH-1:0] l;
+      wire [C_DATA_WIDTH-1:0] h;
+      wire [C_DATA_WIDTH-1:0] ll;
+      wire [C_DATA_WIDTH-1:0] lh;
+      wire [C_DATA_WIDTH-1:0] hl;
+      wire [C_DATA_WIDTH-1:0] hh;
+      
+      case (C_RATIO)
+        1, 5, 9, 13: 
+          assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
+        2, 6, 10, 14:
+          assign hh = S[0] ? 
+            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+            A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
+        3, 7, 11, 15:
+          assign hh = S[1] ? 
+            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+            (S[0] ? 
+              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+        4, 8, 12, 16:
+          assign hh = S[1] ? 
+            (S[0] ? 
+              A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+            (S[0] ? 
+              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+        17:
+          assign hh = S[1] ? 
+            (S[0] ? 
+              A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+            (S[0] ? 
+              A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
+        default:
+          assign hh = 0; 
+      endcase
+
+      case (C_RATIO)
+        5, 6, 7, 8: begin
+          assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
+            MUXF7 mux_s2_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[2]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        9, 10, 11, 12: begin
+          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
+            MUXF7 muxf_s2_low_inst 
+            (
+             .I0  (ll[bit_cnt]),
+             .I1  (lh[bit_cnt]),
+             .S   (S[2]),
+             .O   (l[bit_cnt])
+            ); 
+            MUXF8 muxf_s3_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[3]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        13,14,15,16: begin
+          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
+            MUXF7 muxf_s2_low_inst 
+            (
+             .I0  (ll[bit_cnt]),
+             .I1  (lh[bit_cnt]),
+             .S   (S[2]),
+             .O   (l[bit_cnt])
+            ); 
+            MUXF7 muxf_s2_hi_inst 
+            (
+             .I0  (hl[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[2]),
+             .O   (h[bit_cnt])
+            );
+          
+            MUXF8 muxf_s3_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (h[bit_cnt]),
+             .S   (S[3]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        17: begin
+          assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);  // 5-input mux
+          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
+            MUXF7 muxf_s2_low_inst 
+            (
+             .I0  (ll[bit_cnt]),
+             .I1  (lh[bit_cnt]),
+             .S   (S[2]),
+             .O   (l[bit_cnt])
+            ); 
+            MUXF7 muxf_s2_hi_inst 
+            (
+             .I0  (hl[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[2]),
+             .O   (h[bit_cnt])
+            ); 
+            MUXF8 muxf_s3_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (h[bit_cnt]),
+             .S   (S[3]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        default:  // If RATIO > 17, use RTL
+          assign o_i = f_mux(S, A);
+      endcase
+    end  // gen_fpga
+  endgenerate
+endmodule
+
+`endif
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axis_infrastructure_v1_1_0_util_aclken_converter
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_aclken_converter # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_PAYLOAD_WIDTH       = 32,
+  parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
+  parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
+  )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave side
+  input  wire                        ACLK,
+  input  wire                        ARESETN,
+
+  input  wire                        S_ACLKEN,
+  input  wire [C_PAYLOAD_WIDTH-1:0]  S_PAYLOAD,
+  input  wire                        S_VALID,
+  output wire                        S_READY,
+
+  // Master side
+  input  wire                        M_ACLKEN,
+  output wire [C_PAYLOAD_WIDTH-1:0]  M_PAYLOAD,
+  output wire                        M_VALID,
+  input  wire                        M_READY
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+// State machine states
+localparam SM_NOT_READY    = 3'b000;
+localparam SM_EMPTY        = 3'b001;
+localparam SM_R0_NOT_READY = 3'b010;
+localparam SM_R0           = 3'b011;
+localparam SM_R1           = 3'b100;
+localparam SM_FULL         = 3'b110;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire s_aclken_i;
+wire m_aclken_i;
+reg  areset;
+
+reg [2:0] state = SM_NOT_READY;
+
+// r0 is the output register
+reg [C_PAYLOAD_WIDTH-1:0] r0;
+wire                      load_r0;
+wire                      load_r0_from_r1;
+
+// r1 is the overflow register
+reg [C_PAYLOAD_WIDTH-1:0] r1;
+wire                      load_r1;
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+assign s_aclken_i = C_S_ACLKEN_CAN_TOGGLE ? S_ACLKEN : 1'b1;
+assign m_aclken_i = C_M_ACLKEN_CAN_TOGGLE ? M_ACLKEN : 1'b1;
+
+always @(posedge ACLK) begin 
+  areset <= ~ARESETN;
+end
+
+// Valid/Ready outputs encoded into state machine.
+assign S_READY = (state == SM_NOT_READY ) ? 1'b0 : state[0] ;
+assign M_VALID = (state == SM_NOT_READY ) ? 1'b0 : state[1];
+
+// State machine: Controls outputs and hold register state info
+always @(posedge ACLK) begin 
+  if (areset) begin
+    state <= SM_NOT_READY;
+  end
+  else begin 
+    case (state)
+      // De-assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
+      SM_NOT_READY: begin
+        if (s_aclken_i) begin
+          state <= SM_EMPTY;
+        end
+        else begin
+          state <= state;
+        end
+      end
+
+      // Assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
+      SM_EMPTY: begin
+        if (s_aclken_i & S_VALID & m_aclken_i) begin
+          state <= SM_R0;
+        end
+        else if (s_aclken_i & S_VALID & ~m_aclken_i) begin
+          state <= SM_R1;
+        end
+        else begin 
+          state <= state;
+        end
+      end
+
+      // Assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
+      SM_R0: begin
+        if ((m_aclken_i & M_READY) & ~(s_aclken_i & S_VALID)) begin
+          state <= SM_EMPTY;
+        end
+        else if (~(m_aclken_i & M_READY) & (s_aclken_i & S_VALID)) begin
+          state <= SM_FULL;
+        end
+        else begin 
+          state <= state;
+        end
+      end
+
+      // De-assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
+      SM_R0_NOT_READY: begin
+        if (s_aclken_i & m_aclken_i & M_READY) begin
+          state <= SM_EMPTY;
+        end
+        else if (~s_aclken_i & m_aclken_i & M_READY) begin
+          state <= SM_NOT_READY;
+        end
+        else if (s_aclken_i) begin
+          state <= SM_R0;
+        end
+        else begin 
+          state <= state;
+        end
+      end
+
+      // De-assert s_ready, De-assert m_valid, R0 unoccupied, R1 occupied
+      SM_R1: begin
+        if (~s_aclken_i & m_aclken_i) begin
+          state <= SM_R0_NOT_READY;
+        end
+        else if (s_aclken_i & m_aclken_i) begin 
+          state <= SM_R0;
+        end
+        else begin 
+          state <= state;
+        end
+      end
+
+      // De-assert s_ready, De-assert m_valid, R0 occupied, R1 occupied
+      SM_FULL: begin
+        if (~s_aclken_i & m_aclken_i & M_READY) begin
+          state <= SM_R0_NOT_READY;
+        end
+        else if (s_aclken_i & m_aclken_i & M_READY) begin 
+          state <= SM_R0;
+        end
+        else begin 
+          state <= state;
+        end
+      end
+
+      default: begin
+        state <= SM_NOT_READY;
+      end
+    endcase
+  end
+end
+
+assign M_PAYLOAD = r0;
+
+always @(posedge ACLK) begin
+  if (m_aclken_i) begin 
+    r0 <= ~load_r0 ? r0 :
+          load_r0_from_r1 ? r1 :
+          S_PAYLOAD ;
+  end
+end
+
+assign load_r0 = (state == SM_EMPTY) 
+                 | (state == SM_R1) 
+                 | ((state == SM_R0) & M_READY)
+                 | ((state == SM_FULL) & M_READY);
+
+assign load_r0_from_r1 = (state == SM_R1) | (state == SM_FULL);
+
+always @(posedge ACLK) begin
+  r1 <= ~load_r1 ? r1 : S_PAYLOAD;
+end
+
+assign load_r1 = (state == SM_EMPTY) | (state == SM_R0);
+
+
+endmodule // axis_infrastructure_v1_1_0_util_aclken_converter
+
+`default_nettype wire
+`endif
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard:  Verilog 2001
+////////////////////////////////////////////////////////////
+//
+// Structure:
+//   axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
+//     axis_infrastructure_v1_1_0_util_axis2_vector
+//     axis_infrastructure_v1_1_0_util_aclken_converter
+//     axis_infrastructure_v1_1_0_util_vector2axis 
+//
+////////////////////////////////////////////////////////////
+`ifndef axis_infrastructure_v1_1_0_UTIL_ACLKEN_CONVERTER_WRAPPER_V
+`define axis_infrastructure_v1_1_0_UTIL_ACLKEN_CONVERTER_WRAPPER_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_aclken_converter_wrapper # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_TDATA_WIDTH = 32,
+  parameter integer C_TID_WIDTH   = 1,
+  parameter integer C_TDEST_WIDTH = 1,
+  parameter integer C_TUSER_WIDTH = 1,
+  parameter [31:0]  C_SIGNAL_SET  = 32'hFF,
+  // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+  //   [0] => TREADY present
+  //   [1] => TDATA present
+  //   [2] => TSTRB present, TDATA must be present
+  //   [3] => TKEEP present, TDATA must be present
+  //   [4] => TLAST present
+  //   [5] => TID present
+  //   [6] => TDEST present
+  //   [7] => TUSER present
+  parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
+  parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
+  )
+ (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave side
+  input  wire                       ACLK,
+  input  wire                       ARESETN,
+  input  wire                       S_ACLKEN,
+  input  wire                       S_VALID,
+  output wire                       S_READY,
+  input  wire [C_TDATA_WIDTH-1:0]   S_TDATA,
+  input  wire [C_TDATA_WIDTH/8-1:0] S_TSTRB,
+  input  wire [C_TDATA_WIDTH/8-1:0] S_TKEEP,
+  input  wire                       S_TLAST,
+  input  wire [C_TID_WIDTH-1:0]     S_TID,
+  input  wire [C_TDEST_WIDTH-1:0]   S_TDEST,
+  input  wire [C_TUSER_WIDTH-1:0]   S_TUSER,
+                                    
+  input  wire                       M_ACLKEN,
+  output wire                       M_VALID,
+  input  wire                       M_READY,
+  output wire [C_TDATA_WIDTH-1:0]   M_TDATA,
+  output wire [C_TDATA_WIDTH/8-1:0] M_TSTRB,
+  output wire [C_TDATA_WIDTH/8-1:0] M_TKEEP,
+  output wire                       M_TLAST,
+  output wire [C_TID_WIDTH-1:0]     M_TID,
+  output wire [C_TDEST_WIDTH-1:0]   M_TDEST,
+  output wire [C_TUSER_WIDTH-1:0]   M_TUSER
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+localparam integer P_TPAYLOAD_WIDTH       = f_payload_width(C_TDATA_WIDTH, C_TID_WIDTH, 
+                                                 C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                                 C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [P_TPAYLOAD_WIDTH-1:0] s_tpayload;
+wire [P_TPAYLOAD_WIDTH-1:0] m_tpayload;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+axis_infrastructure_v1_1_0_util_axis2vector #(
+  .C_TDATA_WIDTH    ( C_TDATA_WIDTH ) ,
+  .C_TID_WIDTH      ( C_TID_WIDTH   ) ,
+  .C_TDEST_WIDTH    ( C_TDEST_WIDTH ) ,
+  .C_TUSER_WIDTH    ( C_TUSER_WIDTH ) ,
+  .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH   ) ,
+  .C_SIGNAL_SET     ( C_SIGNAL_SET  ) 
+)
+util_axis2vector_0 (
+  .TDATA    ( S_TDATA    ) ,
+  .TSTRB    ( S_TSTRB    ) ,
+  .TKEEP    ( S_TKEEP    ) ,
+  .TLAST    ( S_TLAST    ) ,
+  .TID      ( S_TID      ) ,
+  .TDEST    ( S_TDEST    ) ,
+  .TUSER    ( S_TUSER    ) ,
+  .TPAYLOAD ( s_tpayload )
+);
+
+generate
+if (C_S_ACLKEN_CAN_TOGGLE | C_M_ACLKEN_CAN_TOGGLE) begin : gen_aclken_converter
+  axis_infrastructure_v1_1_0_util_aclken_converter #( 
+    .C_PAYLOAD_WIDTH       ( P_TPAYLOAD_WIDTH       ) ,
+    .C_S_ACLKEN_CAN_TOGGLE ( C_S_ACLKEN_CAN_TOGGLE ) ,
+    .C_M_ACLKEN_CAN_TOGGLE ( C_M_ACLKEN_CAN_TOGGLE ) 
+  )
+  s_util_aclken_converter_0 ( 
+    .ACLK      ( ACLK       ) ,
+    .ARESETN   ( ARESETN    ) ,
+    .S_ACLKEN  ( S_ACLKEN   ) ,
+    .S_PAYLOAD ( s_tpayload ) ,
+    .S_VALID   ( S_VALID   ) ,
+    .S_READY   ( S_READY   ) ,
+    .M_ACLKEN  ( M_ACLKEN   ) ,
+    .M_PAYLOAD ( m_tpayload ) ,
+    .M_VALID   ( M_VALID   ) ,
+    .M_READY   ( M_READY   ) 
+  );
+end
+else begin : gen_aclken_passthru
+  assign m_tpayload = s_tpayload;
+  assign M_VALID   = S_VALID;
+  assign S_READY = M_READY;
+end
+endgenerate
+
+axis_infrastructure_v1_1_0_util_vector2axis #(
+  .C_TDATA_WIDTH    ( C_TDATA_WIDTH ) ,
+  .C_TID_WIDTH      ( C_TID_WIDTH   ) ,
+  .C_TDEST_WIDTH    ( C_TDEST_WIDTH ) ,
+  .C_TUSER_WIDTH    ( C_TUSER_WIDTH ) ,
+  .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH   ) ,
+  .C_SIGNAL_SET     ( C_SIGNAL_SET  ) 
+)
+util_vector2axis_0 (
+  .TPAYLOAD ( m_tpayload ) ,
+  .TDATA    ( M_TDATA    ) ,
+  .TSTRB    ( M_TSTRB    ) ,
+  .TKEEP    ( M_TKEEP    ) ,
+  .TLAST    ( M_TLAST    ) ,
+  .TID      ( M_TID      ) ,
+  .TDEST    ( M_TDEST    ) ,
+  .TUSER    ( M_TUSER    ) 
+);
+
+endmodule // axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
+
+`default_nettype wire
+`endif
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+////////////////////////////////////////////////////////////
+//
+// axis to vector
+//   A generic module to merge all axis 'data' signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axis_infrastructure_v1_1_0_util_axis2vector
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_axis2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+   parameter integer C_TDATA_WIDTH = 32,
+   parameter integer C_TID_WIDTH   = 1,
+   parameter integer C_TDEST_WIDTH = 1,
+   parameter integer C_TUSER_WIDTH = 1,
+   parameter integer C_TPAYLOAD_WIDTH = 44,
+   parameter [31:0]  C_SIGNAL_SET  = 32'hFF
+   // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+   //   [0] => TREADY present
+   //   [1] => TDATA present
+   //   [2] => TSTRB present, TDATA must be present
+   //   [3] => TKEEP present, TDATA must be present
+   //   [4] => TLAST present
+   //   [5] => TID present
+   //   [6] => TDEST present
+   //   [7] => TUSER present
+   )
+  (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+   // inputs
+   input  wire [C_TDATA_WIDTH-1:0]   TDATA,
+   input  wire [C_TDATA_WIDTH/8-1:0] TSTRB,
+   input  wire [C_TDATA_WIDTH/8-1:0] TKEEP,
+   input  wire                       TLAST,
+   input  wire [C_TID_WIDTH-1:0]     TID,
+   input  wire [C_TDEST_WIDTH-1:0]   TDEST,
+   input  wire [C_TUSER_WIDTH-1:0]   TUSER,
+
+   // outputs
+   output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD
+   );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TID_INDX   = f_get_tid_indx  (C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+  if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
+    assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH]   = TDATA;
+  end else begin : no_gen_tdata
+    // Do nothing
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
+    assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB;
+  end else begin : no_gen_tstrb
+    // Do nothing
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
+    assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP;
+  end else begin : no_gen_tkeep
+    // Do nothing
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
+    assign TPAYLOAD[P_TLAST_INDX+:1]               = TLAST;
+  end else begin : no_gen_tlast
+    // Do nothing
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
+    assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH]       = TID;
+  end else begin : no_gen_tid
+    // Do nothing
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
+    assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH]   = TDEST;
+  end else begin : no_gen_tdest
+    // Do nothing
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
+    assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH]   = TUSER;
+  end else begin : no_gen_tuser
+    // Do nothing
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+`endif
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+////////////////////////////////////////////////////////////
+//
+// axis to vector
+//   A generic module to unmerge all axis 'data' signals from payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axis_infrastructure_v1_1_0_util_vector2axis
+//
+//--------------------------------------------------------------------------
+`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
+`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_util_vector2axis #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+   parameter integer C_TDATA_WIDTH = 32,
+   parameter integer C_TID_WIDTH   = 1,
+   parameter integer C_TDEST_WIDTH = 1,
+   parameter integer C_TUSER_WIDTH = 1,
+   parameter integer C_TPAYLOAD_WIDTH = 44,
+   parameter [31:0]  C_SIGNAL_SET  = 32'hFF
+   // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+   //   [0] => TREADY present
+   //   [1] => TDATA present
+   //   [2] => TSTRB present, TDATA must be present
+   //   [3] => TKEEP present, TDATA must be present
+   //   [4] => TLAST present
+   //   [5] => TID present
+   //   [6] => TDEST present
+   //   [7] => TUSER present
+   )
+  (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+   // outputs
+   input  wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
+
+   // inputs
+   output wire [C_TDATA_WIDTH-1:0]   TDATA,
+   output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
+   output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
+   output wire                       TLAST,
+   output wire [C_TID_WIDTH-1:0]     TID,
+   output wire [C_TDEST_WIDTH-1:0]   TDEST,
+   output wire [C_TUSER_WIDTH-1:0]   TUSER
+   );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TID_INDX   = f_get_tid_indx  (C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
+                                           C_TDEST_WIDTH, C_TUSER_WIDTH, 
+                                           C_SIGNAL_SET);
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+  if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
+    assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH]  ;
+  end
+  else begin : no_gen_tdata
+    assign TDATA = {C_TDATA_WIDTH{1'b0}};
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
+    assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
+  end 
+  else begin : no_gen_tstrb
+    assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}};
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
+    assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
+  end 
+  else begin : no_gen_tkeep
+    assign TKEEP = {(C_TDATA_WIDTH/8){1'b1}};
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
+    assign TLAST = TPAYLOAD[P_TLAST_INDX+:1]              ;
+  end 
+  else begin : no_gen_tlast
+    assign TLAST = 1'b0;
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
+    assign TID   = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH]      ;
+  end 
+  else begin : no_gen_tid
+    assign TID   = {C_TID_WIDTH{1'b0}};
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
+    assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH]  ;
+  end 
+  else begin : no_gen_tdest
+    assign TDEST   = {C_TDEST_WIDTH{1'b0}};
+  end
+  if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
+    assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH]  ;
+  end 
+  else begin : no_gen_tuser
+    assign TUSER   = {C_TUSER_WIDTH{1'b0}};
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+`endif
+
+
+//*****************************************************************************
+//  (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//
+//*****************************************************************************
+// Description
+//   This module instantiates the clock synchronization logic.  It passes the 
+//   incoming signal through two flops to ensure metastability. 
+//              
+//*****************************************************************************
+`timescale 1ps / 1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module axis_infrastructure_v1_1_0_clock_synchronizer # (
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_NUM_STAGES              = 4
+)     
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations     
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                               clk,
+  input  wire                               synch_in ,
+  output wire                               synch_out
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local Parameters           
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+xpm_cdc_single #(
+	.DEST_SYNC_FF   ( C_NUM_STAGES ) ,
+	.SRC_INPUT_REG  ( 0            ) ,
+	.SIM_ASSERT_CHK ( 0            ) 
+)
+inst_xpm_cdc_single   (
+  .src_clk  ( 1'b0      ) ,
+  .src_in   ( synch_in  ) ,
+  .dest_out ( synch_out ) ,
+  .dest_clk ( clk       ) 
+);
+
+endmodule
+
+`default_nettype wire
+
+
+// (c) Copyright 2014 Xilinx, Inc. All rights reserved. 
+//                                                             
+// This file contains confidential and proprietary information 
+// of Xilinx, Inc. and is protected under U.S. and             
+// international copyright and other intellectual property     
+// laws.                                                       
+//                                                             
+// DISCLAIMER                                                  
+// This disclaimer is not a license and does not grant any     
+// rights to the materials distributed herewith. Except as     
+// otherwise provided in a valid license issued to you by      
+// Xilinx, and to the maximum extent permitted by applicable   
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND     
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING   
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-      
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and    
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of          
+// liability) for any loss or damage of any kind or nature     
+// related to, arising under or in connection with these       
+// materials, including for any direct, or any indirect,       
+// special, incidental, or consequential loss or damage        
+// (including loss of data, profits, goodwill, or any type of  
+// loss or damage suffered as a result of any action brought   
+// by a third party) even if such damage or loss was           
+// reasonably foreseeable or Xilinx had been advised of the    
+// possibility of the same.                                    
+//                                                             
+// CRITICAL APPLICATIONS                                       
+// Xilinx products are not designed or intended to be fail-    
+// safe, or for use in any application requiring fail-safe     
+// performance, such as life-support or safety devices or      
+// systems, Class III medical devices, nuclear facilities,     
+// applications related to the deployment of airbags, or any   
+// other applications that could lead to death, personal       
+// injury, or severe property or environmental damage          
+// (individually and collectively, "Critical                   
+// Applications"). Customer assumes the sole risk and          
+// liability of any use of Xilinx products in Critical         
+// Applications, subject only to applicable laws and           
+// regulations governing limitations on product liability.     
+//                                                             
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS    
+// PART OF THIS FILE AT ALL TIMES.                             
+//  
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axis_infrastructure_v1_1_0_cdc_handshake
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+module axis_infrastructure_v1_1_0_cdc_handshake #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_WIDTH                   = 32,
+  parameter integer C_NUM_SYNCHRONIZER_STAGES = 2
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations     
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                               from_clk,
+  input  wire                               req, 
+  output wire                               ack,
+  input  wire [C_WIDTH-1:0]                 data_in,
+
+  input  wire                               to_clk,
+  output wire                               data_valid,
+  output wire [C_WIDTH-1:0]                 data_out
+);
+
+/////////////////////////////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+///////////////////////////////////////////////////////////////////////////////
+xpm_cdc_handshake #(
+  .WIDTH          ( C_WIDTH                   ) ,
+  .DEST_SYNC_FF   ( C_NUM_SYNCHRONIZER_STAGES ) ,
+  .SRC_SYNC_FF    ( C_NUM_SYNCHRONIZER_STAGES ) ,
+  .DEST_EXT_HSK   ( 0                         ) ,
+  .SIM_ASSERT_CHK ( 0                         ) 
+)
+inst_xpm_cdc_handshake (
+  .src_in   ( data_in    ) ,
+  .src_send ( req        ) ,
+  .src_rcv  ( ack        ) ,
+  .src_clk  ( from_clk ) ,
+  .dest_out ( data_out   ) ,
+  .dest_req ( data_valid ) ,
+  .dest_ack ( 1'b0       ) ,
+  .dest_clk ( to_clk     ) 
+);
+
+endmodule // axis_infrastructure_v1_1_0_cdc_handshake
+
+`default_nettype wire
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v
new file mode 100755
index 0000000..8b0ba48
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v
@@ -0,0 +1,7777 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
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+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
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+agXy7/8mSKVHJJWUwzY=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2020_08", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 438576)
+`pragma protect data_block
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+`pragma protect end_protected
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd
new file mode 100755
index 0000000..69171e9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd
@@ -0,0 +1,18837 @@
+`protect begin_protected
+`protect version = 1
+`protect encrypt_agent = "XILINX"
+`protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
+`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`protect key_block
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+FZV1B91GDQ==
+
+`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`protect key_block
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+ZuZUz/Pqg8Lu63Xwe+0=
+
+`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`protect key_block
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+
+`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`protect key_block
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+
+`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`protect key_block
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+
+`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`protect key_block
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+
+`protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`protect key_block
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+
+`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2020_08", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`protect key_block
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+
+`protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`protect key_block
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+
+`protect data_method = "AES128-CBC"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1069024)
+`protect data_block
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+`protect end_protected
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v
new file mode 100755
index 0000000..37a3b4c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v
@@ -0,0 +1,88 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_bit_synchronizer # (
+
+  parameter INITIALIZE = 5'b00000,
+  parameter FREQUENCY  = 512
+
+)(
+
+  input  wire clk_in,
+  input  wire i_in,
+  output wire o_out
+
+);
+
+  // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
+  // enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
+
+  (* ASYNC_REG = "TRUE" *) reg i_in_meta  = INITIALIZE[0];
+  (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
+  (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
+  (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
+                           reg i_in_out   = INITIALIZE[4];
+
+  always @(posedge clk_in) begin
+    i_in_meta  <= i_in;
+    i_in_sync1 <= i_in_meta;
+    i_in_sync2 <= i_in_sync1;
+    i_in_sync3 <= i_in_sync2;
+    i_in_out   <= i_in_sync3;
+  end
+
+  assign o_out = i_in_out;
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v
new file mode 100755
index 0000000..6cd28fd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v
@@ -0,0 +1,608 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gte4_drp_arb 
+
+#(
+  parameter [9:0]  ADDR_TX_PROGCLK_SEL = 10'h00C,
+  parameter [9:0]  ADDR_TX_PROGDIV_CFG = 10'h03E, //GTY /GTH addresses are different  (003E in GTH; 0057 in GTY)
+  parameter [9:0]  ADDR_RX_PROGDIV_CFG = 10'h0C6,
+  parameter [9:0]  ADDR_X0E1 = 10'h0E1,
+  parameter [9:0]  ADDR_X079 = 10'h079,
+  parameter [9:0]  ADDR_X114 = 10'h114,
+  parameter C_NUM_CLIENTS = 2,
+  parameter C_ADDR_WIDTH = 9,
+  parameter C_DATA_WIDTH = 16
+)
+(
+
+  input  wire                                     DCLK_I,
+
+  input  wire                                     RESET_I,
+  
+  input wire                                      TX_CAL_DONE_I, 
+  input wire                                      RX_CAL_DONE_I,
+
+  input  wire [C_NUM_CLIENTS-1:0]                 DEN_USR_I,
+
+  input  wire [C_NUM_CLIENTS-1:0]                 DWE_USR_I,
+
+  input  wire [(C_ADDR_WIDTH*C_NUM_CLIENTS)-1:0]  DADDR_USR_I,
+
+  input  wire [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0]  DI_USR_I,
+
+  output reg  [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0]  DO_USR_O = 'h0,
+
+  output reg  [C_NUM_CLIENTS-1:0]                 DRDY_USR_O = 'h0,
+
+
+
+  output reg                                      DEN_O = 1'b0,
+
+  output reg                                      DWE_O = 1'b0,
+
+  output reg  [C_ADDR_WIDTH-1:0]                  DADDR_O = 1'b0,
+
+  output reg  [C_DATA_WIDTH-1:0]                  DI_O = 'h0,
+
+  input  wire [C_DATA_WIDTH-1:0]                  DO_I,
+
+  input  wire                                     DRDY_I
+
+);
+
+  //
+
+  //  log base 2
+
+  //
+
+  function integer clogb2;
+
+    input integer depth;
+
+    integer d;
+
+    begin
+
+      if (depth == 0)
+
+        clogb2 = 1;
+
+      else
+
+      begin
+
+        d = depth;
+
+        for (clogb2=0; d > 0; clogb2 = clogb2+1)
+
+          d = d >> 1;
+
+      end
+
+    end
+
+  endfunction
+
+
+
+  
+
+  reg [clogb2(C_NUM_CLIENTS)-1:0]         idx = 'b0;
+
+  reg                                     done = 1'b0;
+
+  
+
+  reg                                     rd = 1'b0;
+
+  reg                                     wr = 1'b0;
+
+  
+
+  reg [C_NUM_CLIENTS-1:0]                 en = 'h0;
+
+  reg [C_NUM_CLIENTS-1:0]                 we = 'h0;
+
+  reg [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0]  data_i = 'h0;
+
+  reg [(C_ADDR_WIDTH*C_NUM_CLIENTS)-1:0]  addr_i = 'h0;
+
+  
+
+  
+
+  reg [C_DATA_WIDTH-1:0]                  di = 'h0;
+
+  reg [C_ADDR_WIDTH-1:0]                  daddr = 'h0;
+
+  reg [C_DATA_WIDTH-1:0]                  do_r = 'h0;
+
+  
+
+  //
+
+  // Arbitration state machine encodings
+
+  //
+
+  localparam [3:0] ARB_START    = 4'd1;
+
+  localparam [3:0] ARB_WAIT     = 4'd2;
+
+  localparam [3:0] ARB_REPORT   = 4'd4;
+
+  localparam [3:0] ARB_INC      = 4'd8;
+
+  
+
+  reg [3:0] arb_state = ARB_START;
+
+  
+
+  //
+
+  // DRP state machine encodings
+
+  //
+
+  localparam [6:0] DRP_WAIT      = 7'd1;
+
+  localparam [6:0] DRP_READ      = 7'd2;
+
+  localparam [6:0] DRP_READ_ACK  = 7'd4;
+
+  localparam [6:0] DRP_MODIFY    = 7'd8;
+
+  localparam [6:0] DRP_WRITE     = 7'd16;
+
+  localparam [6:0] DRP_WRITE_ACK = 7'd32;
+
+  localparam [6:0] DRP_DONE      = 7'd64;
+
+  
+
+  reg [6:0] drp_state = DRP_WAIT;
+
+  
+
+  reg [7:0] timeout_cntr = 0;
+
+  
+
+  integer i;
+
+  
+
+  //
+
+  // Register incoming transactions: grab data, address, write enable when DEN is high
+
+  // Clear internal enable when transaction is (eventually) finished
+
+  //
+
+  always @(posedge DCLK_I)
+
+  begin
+
+    if (RESET_I)
+
+    begin
+
+      en <= 'b0;
+
+      we <= 'b0;
+
+      data_i <= 'b0;
+
+      addr_i <= 'b0;
+
+    end
+
+    else
+
+    begin
+
+      if (DEN_USR_I[0]) begin 
+      
+        en[0] <= 1'b1;  // this means this client wants to do a transaction
+
+        we[0] <= DWE_USR_I[0];
+
+        //data_i[(i*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(i*C_DATA_WIDTH) +: C_DATA_WIDTH];
+        //addr_i[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH];      
+        
+        // if cpll cal not done (mask) from cpll cal, if user tries to write, always save progdiv to temp holding place. 
+        if (!TX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_TX_PROGDIV_CFG && DWE_USR_I[0]) begin  
+            addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X079;
+            data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
+        end
+        else if (!TX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_TX_PROGCLK_SEL && DWE_USR_I[0]) begin 
+            addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X0E1;
+            data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
+        end
+        else if (!RX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_RX_PROGDIV_CFG && DWE_USR_I[0]) begin 
+            addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X114;
+            data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
+        end
+        else begin
+            //behave normal
+            addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
+            data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH];
+        end
+        
+      end
+
+      for (i = 1; i < C_NUM_CLIENTS; i= i+1) 
+
+      begin
+
+        if (DEN_USR_I[i])
+
+        begin
+
+          en[i] <= 1'b1;  // this means this client wants to do a transaction
+
+          we[i] <= DWE_USR_I[i];
+
+          data_i[(i*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(i*C_DATA_WIDTH) +: C_DATA_WIDTH];
+
+          addr_i[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
+
+        end
+
+      end
+
+      if (done)
+
+      begin
+
+        en[idx] <= 1'b0;
+
+        we[idx] <= 1'b0;
+
+      end  
+
+    end     
+
+  end
+
+           
+
+  
+
+  //
+
+  // Arbitration FSM - does a round-robin arbritration scheme
+
+  //
+
+  always @(posedge DCLK_I)
+
+  begin
+
+    if (RESET_I) 
+
+    begin
+
+      idx <= 'b0;
+
+      di <= 'b0;
+
+      daddr <= 'b0;
+
+      rd <= 1'b0;
+
+      wr <= 1'b0;
+
+      arb_state <= ARB_START;
+
+      DRDY_USR_O <= 'b0;
+
+      DO_USR_O <= 'b0;
+
+    end
+
+    else
+
+    begin
+
+      case (arb_state)
+
+        ARB_START: begin
+
+          if (en[idx] == 1'b1) 
+
+          begin
+
+            di    <= data_i[idx*C_DATA_WIDTH +: C_DATA_WIDTH];
+
+            daddr <= addr_i[idx*C_ADDR_WIDTH +: C_ADDR_WIDTH];
+
+            rd    <= !we[idx];
+
+            wr    <= we[idx];
+
+            arb_state <= ARB_WAIT;
+
+          end
+
+          else
+
+          begin 
+
+            rd    <= 1'b0;
+
+            wr    <= 1'b0;
+
+            arb_state <= ARB_INC;
+
+          end 
+
+        end
+
+        ARB_WAIT: begin
+
+          rd <= 1'b0;
+
+          wr <= 1'b0;
+
+          if (done == 1'b1)  
+
+            arb_state <= ARB_REPORT;
+
+          else
+
+            arb_state <= ARB_WAIT;
+
+        end
+
+        ARB_REPORT: begin
+
+          DRDY_USR_O[idx] <= 1'b1;
+
+          DO_USR_O[idx*C_DATA_WIDTH +: C_DATA_WIDTH] <= do_r;
+
+          arb_state <= ARB_INC;
+
+        end
+
+        ARB_INC : begin
+
+          DRDY_USR_O[idx] <= 1'b0;
+
+          if (idx == C_NUM_CLIENTS-1)
+
+            idx <= 1'b0;
+
+          else
+
+            idx <= idx + 1;
+
+          arb_state <= ARB_START;
+
+        end
+
+        default: arb_state <= ARB_START;
+
+        
+
+      endcase
+
+    end
+
+  end  
+
+  
+
+  
+
+  //
+
+  // DRP FSM - does the actual DRP read or write
+
+  //
+
+  always @(posedge DCLK_I) 
+
+  begin
+
+    if (RESET_I) 
+
+    begin
+
+      DEN_O <=  1'b0;
+
+      DWE_O <=  1'b0;
+
+      DI_O <=  16'h0000;
+
+      DADDR_O <= 'b0;
+
+      do_r <= 'b0;
+
+      drp_state <=  DRP_WAIT;
+
+      done <=  1'b0;
+
+    end
+
+    else 
+
+    begin
+
+      case (drp_state)
+
+        DRP_WAIT: begin
+
+          timeout_cntr <= 8'h0;
+
+          if (rd) drp_state <=  DRP_READ;
+
+          else if (wr) drp_state <=  DRP_WRITE;
+
+          else         drp_state <=  DRP_WAIT;
+
+        end
+
+        DRP_READ: begin
+
+          DEN_O <=  1'b1;
+
+          DWE_O <=  1'b0;
+
+          DADDR_O <= daddr;
+
+          timeout_cntr <= 8'h0;
+
+          done <= 1'b0;
+
+          drp_state <=  DRP_READ_ACK;
+
+        end
+
+        DRP_READ_ACK: begin
+
+          DEN_O <=  1'b0;
+
+          DWE_O <=  1'b0;
+
+          timeout_cntr <= timeout_cntr + 1;
+
+          if (DRDY_I == 1'b1 || timeout_cntr == 8'hFF) 
+
+          begin
+
+            do_r <= DO_I;
+
+            done <= 1'b1;
+
+            drp_state <=  DRP_DONE;
+
+          end  
+
+          else      
+
+            drp_state <=  DRP_READ_ACK; 
+
+        end
+
+        DRP_WRITE: begin
+
+          DEN_O <=  1'b1;
+
+          DWE_O <=  1'b1;
+
+          DADDR_O <=  daddr;
+
+          DI_O <=  di;
+
+          timeout_cntr <= 8'h0;
+
+          done <= 1'b0;
+
+          drp_state <=  DRP_WRITE_ACK;
+
+        end
+
+        DRP_WRITE_ACK: begin
+
+          DEN_O <=  1'b0;
+
+          DWE_O <=  1'b0;
+
+          timeout_cntr <= timeout_cntr + 1;
+
+          if (DRDY_I == 1'b1 || timeout_cntr == 8'hFF) 
+
+          begin
+          
+            do_r <= DO_I;
+
+            done <= 1'b1;
+
+            drp_state <=  DRP_DONE;
+
+          end  
+
+          else              
+
+            drp_state <=  DRP_WRITE_ACK;
+
+        end
+
+        DRP_DONE: begin
+
+          timeout_cntr <= 8'h0;
+
+          done <= 1'b0; // done was asserted in the previous state
+
+          drp_state <=  DRP_WAIT;
+
+        end
+
+          default: drp_state <=  DRP_WAIT;
+
+      endcase
+
+    end
+
+  end
+
+  
+
+endmodule  
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v
new file mode 100755
index 0000000..c243d64
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v
@@ -0,0 +1,224 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe3_cpll_cal_freq_counter # (
+  parameter REVISION = 1
+)(
+  output reg  [17:0] freq_cnt_o = 18'd0,
+  output reg  done_o,
+  input  wire rst_i,
+  input  wire [15:0] test_term_cnt_i,
+  input  wire ref_clk_i,
+  input  wire test_clk_i
+);
+  //****************************************************************************
+  //  Local Parameters
+  //****************************************************************************
+  localparam RESET_STATE = 0;
+  localparam MEASURE_STATE = 1;
+  localparam HOLD_STATE = 2;
+  localparam UPDATE_STATE = 3;
+  localparam DONE_STATE = 4;
+
+  //****************************************************************************
+  //  Local Signals
+  //****************************************************************************
+  reg [17:0] testclk_cnt = 18'h00000;
+  reg [15:0] refclk_cnt = 16'h0000;
+  reg [3:0] testclk_div4 = 4'h1;
+  wire testclk_rst;
+  wire testclk_en;
+  reg [5:0] hold_clk = 6'd0;
+  reg [4:0] state = 5'd1;
+
+  (* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
+  (* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
+
+  //
+  // need to get testclk_rst into TESTCLK_I domain
+  //
+  always @(posedge test_clk_i)
+  begin
+    tstclk_rst_dly1 <= testclk_rst;
+    tstclk_rst_dly2 <= tstclk_rst_dly1;
+  end
+
+  //
+  // need to get testclk_en into TESTCLK_I domain
+  //
+  always @(posedge test_clk_i)
+  begin
+    testclk_en_dly1 <= testclk_en;
+    testclk_en_dly2 <= testclk_en_dly1;
+  end
+
+  always @(posedge test_clk_i)
+  begin
+    if (tstclk_rst_dly2 == 1'b1)
+    begin
+      testclk_div4 <= 4'h1;
+    end
+    else
+    begin
+      testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
+    end
+  end
+
+  wire testclk_rst_sync;
+
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_testclk_rst_inst (
+    .clk_in (test_clk_i),
+    .rst_in   (testclk_rst),
+    .rst_out  (testclk_rst_sync)
+  );
+
+  always @(posedge test_clk_i or posedge testclk_rst_sync)
+  begin
+    if (testclk_rst_sync == 1'b1)
+    begin
+      testclk_cnt <= 0;
+    end
+    else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
+    begin
+      testclk_cnt <= testclk_cnt + 1;
+    end
+  end
+
+/*   always @(posedge test_clk_i or posedge testclk_rst)
+  begin
+    if (testclk_rst == 1'b1)
+    begin
+      testclk_cnt <= 0;
+    end
+    else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
+    begin
+      testclk_cnt <= testclk_cnt + 1;
+    end
+  end */
+
+  always @(posedge ref_clk_i or posedge rst_i)
+  begin
+    if (rst_i)
+      done_o <= 1'b0;
+    else
+      done_o <= state[DONE_STATE];
+  end
+
+  always @(posedge ref_clk_i or posedge rst_i)
+  begin
+    if (rst_i) begin
+      state <= 0;
+      state[RESET_STATE] <= 1'b1;
+    end
+    else begin
+      state <= 0;
+      case (1'b1) // synthesis parallel_case full_case
+        state[RESET_STATE]:
+          begin
+            if (hold_clk == 6'h3F)
+              state[MEASURE_STATE] <= 1'b1;
+            else
+              state[RESET_STATE] <= 1'b1;
+          end
+        state[MEASURE_STATE]:
+          begin
+            if (refclk_cnt == test_term_cnt_i)
+              state[HOLD_STATE] <= 1'b1;
+            else
+              state[MEASURE_STATE] <= 1'b1;
+          end
+        state[HOLD_STATE]:
+          begin
+            if (hold_clk == 6'hF)
+              state[UPDATE_STATE] <= 1'b1;
+            else
+              state[HOLD_STATE] <= 1'b1;
+          end
+        state[UPDATE_STATE]:
+          begin
+            freq_cnt_o <= testclk_cnt;
+            state[DONE_STATE] <= 1'b1;
+          end
+        state[DONE_STATE]:
+          begin
+            state[DONE_STATE] <= 1'b1;
+          end
+      endcase
+    end
+  end
+
+  assign testclk_rst = state[RESET_STATE];
+  assign testclk_en = state[MEASURE_STATE];
+
+
+  always @(posedge ref_clk_i)
+  begin
+    if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
+      hold_clk <= hold_clk + 1;
+    else
+      hold_clk <= 0;
+  end
+
+  always @(posedge ref_clk_i)
+  begin
+    if (state[MEASURE_STATE] == 1'b1)
+      refclk_cnt <= refclk_cnt + 1;
+    else
+      refclk_cnt <= 0;
+  end
+
+
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v
new file mode 100755
index 0000000..c89dfd7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v
@@ -0,0 +1,748 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe3_cpll_cal # (
+        parameter REVISION = 2
+)(
+        // control signals
+        input wire  [17:0] TXOUTCLK_PERIOD_IN,
+        input wire  [15:0] WAIT_DEASSERT_CPLLPD_IN,
+        input wire  [17:0] CNT_TOL_IN,
+        input wire  [15:0] FREQ_COUNT_WINDOW_IN,
+        // User Interface
+        input wire         RESET_IN,
+        input wire         CLK_IN,
+        input wire         USER_TXPROGDIVRESET_IN,
+        output reg         USER_TXPRGDIVRESETDONE_OUT,
+        input wire  [2:0]  USER_TXOUTCLKSEL_IN,
+        input wire         USER_TXOUTCLK_BUFG_CE_IN,
+        input wire         USER_TXOUTCLK_BUFG_CLR_IN,
+        output reg         USER_CPLLLOCK_OUT,
+        input wire  [8:0]  USER_CHANNEL_DRPADDR_IN,
+        input wire  [15:0] USER_CHANNEL_DRPDI_IN,
+        input wire         USER_CHANNEL_DRPEN_IN,
+        input wire         USER_CHANNEL_DRPWE_IN,
+        output reg         USER_CHANNEL_DRPRDY_OUT,
+        output reg [15:0]  USER_CHANNEL_DRPDO_OUT,
+        // Debug Interface
+        output wire        CPLL_CAL_FAIL,
+        output wire        CPLL_CAL_DONE,
+        output wire [15:0] DEBUG_OUT,
+        // GT Interface
+        input wire         GTHE3_TXOUTCLK_IN,
+        input wire         GTHE3_CPLLLOCK_IN,
+        output wire        GTHE3_CPLLRESET_OUT,
+        output wire        GTHE3_CPLLPD_OUT,
+        output reg         GTHE3_TXPROGDIVRESET_OUT,
+        output reg  [2:0]  GTHE3_TXOUTCLKSEL_OUT,
+        input wire         GTHE3_TXPRGDIVRESETDONE_IN,
+        output reg [8:0]   GTHE3_CHANNEL_DRPADDR_OUT,
+        output reg [15:0]  GTHE3_CHANNEL_DRPDI_OUT,
+        output reg         GTHE3_CHANNEL_DRPEN_OUT,
+        output reg         GTHE3_CHANNEL_DRPWE_OUT,
+        input wire         GTHE3_CHANNEL_DRPRDY_IN,
+        input wire  [15:0] GTHE3_CHANNEL_DRPDO_IN
+);
+
+
+  //DRP FSM
+  localparam DRP_WAIT      = 0;
+  localparam DRP_READ      = 1;
+  localparam DRP_READ_ACK  = 2;
+  localparam DRP_MODIFY    = 3;
+  localparam DRP_WRITE     = 4;
+  localparam DRP_WRITE_ACK = 5;
+  localparam DRP_DONE      = 6;
+
+  //CPLL CAL FSM
+  localparam RESET                = 0;
+  localparam READ_PROGCLK_SEL     = 1;
+  localparam MODIFY_PROGCLK_SEL   = 2;
+  localparam READ_PROGDIV         = 3;
+  localparam MODIFY_PROGDIV       = 4;
+  localparam MODIFY_TXOUTCLK_SEL  = 5;
+  localparam ASSERT_CPLLRESET1    = 6;
+  localparam READ_FBOOST          = 7;
+  localparam MODIFY_FBOOST        = 8;
+  localparam ASSERT_CPLLRESET     = 9;
+  localparam ASSERT_CPLLPD        = 10;
+  localparam DEASSERT_CPLLPD      = 11;
+  localparam DEASSERT_CPLLRESET   = 12;
+  localparam RESTORE_FBOOST       = 13;
+  localparam WAIT_GTCPLLLOCK      = 14;
+  localparam ASSERT_PROGDIVRESET  = 15;
+  localparam WAIT_PRGDIVRESETDONE = 16;
+  localparam CHECK_FREQ           = 17;
+  localparam RESTORE_PROGDIV      = 18;
+  localparam RESTORE_PROGCLK_SEL  = 19;
+  localparam ASSERT_CPLLRESET2    = 20;
+  localparam WAIT_GTCPLLLOCK2     = 21;
+  localparam ASSERT_PROGDIVRESET2 = 22;
+  localparam WAIT_PRGDIVRESETDONE2= 23;
+  localparam CAL_FAIL             = 24;
+  localparam CAL_DONE             = 25;
+
+  reg [25:0] cpll_cal_state = 26'd0;
+  wire [4:0] cpll_cal_state_bin;
+  reg [6:0] drp_state = 7'd1;
+  wire drp_done;
+  reg [8:0] daddr = 9'd0;
+  //reg [8:0] daddr = 9'd0;
+  reg [15:0] di = 16'd0;
+  wire drdy;
+  wire [15:0] dout;
+  reg den = 1'b0;
+  reg dwe = 1'b0;
+  reg wr = 1'b0;
+  reg rd = 1'b0;
+  reg [15:0] di_msk;
+  reg [15:0] mask;
+  //reg [15:0] mask;
+  reg [15:0] wait_ctr;
+  reg [3:0] repeat_ctr;
+  reg [1:0] progclk_sel_store = 2'b00;
+  reg [15:0] progdiv_cfg_store = 16'd0;
+  reg fboost_store = 1'b0;
+  reg mask_user_in = 1'b0;
+  reg cpllreset_int = 1'b0;
+  reg cpllpd_int = 1'b0;
+  reg txprogdivreset_int = 1'b0;
+  reg [2:0] txoutclksel_int = 3'b000;
+  reg cal_fail_store = 1'b0;
+
+  localparam [4:0]  WAIT_WIDTH_PROGDIVRESET = 5'd31;
+  localparam [4:0]  WAIT_ASSERT_CPLLRESET   = 5'd31;
+  localparam [4:0]  WAIT_ASSERT_CPLLPD      = 5'd31;
+  localparam [4:0]  WAIT_DEASSERT_CPLLRESET = 5'd31;
+  localparam [15:0] WAIT_CPLLLOCK = 16'h4000;
+  localparam [3:0]  REPEAT_RESET_LIMIT = 4'd15;
+
+  localparam [1:0]  MOD_PROGCLK_SEL = 2'b10;
+  localparam [15:0] MOD_PROGDIV_CFG = 16'hA1A2; //divider 20
+  localparam [2:0]  MOD_TXOUTCLK_SEL = 3'b101;
+  localparam        MOD_FBOOST = 1'b1;
+  localparam [8:0]  ADDR_TX_PROGCLK_SEL = 9'h00C;
+  localparam [8:0]  ADDR_TX_PROGDIV_CFG = 9'h03E;
+  localparam [8:0]  ADDR_FBOOST = 9'h0CB;
+
+  // Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
+  wire txoutclkmon;
+  BUFG_GT bufg_gt_txoutclkmon_inst (
+    .CE      (USER_TXOUTCLK_BUFG_CE_IN),
+    .CEMASK  (1'b1),
+    .CLR     (USER_TXOUTCLK_BUFG_CLR_IN),
+    .CLRMASK (1'b1),
+    .DIV     (3'b000),
+    .I       (GTHE3_TXOUTCLK_IN),
+    .O       (txoutclkmon)
+  );
+
+  wire reset_in_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_resetin_inst (
+    .clk_in (CLK_IN),
+    .rst_in   (RESET_IN),
+    .rst_out  (reset_in_sync)
+  );
+
+  wire gthe3_cplllock_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_cplllock_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE3_CPLLLOCK_IN),
+    .o_out  (gthe3_cplllock_sync)
+  );
+
+  wire user_txprogdivreset_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXPROGDIVRESET_IN),
+    .o_out  (user_txprogdivreset_sync)
+  );
+
+  wire gthe3_txprgdivresetdone_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE3_TXPRGDIVRESETDONE_IN),
+    .o_out  (gthe3_txprgdivresetdone_sync)
+  );
+
+  wire [2:0] user_txoutclksel_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[0]),
+    .o_out  (user_txoutclksel_sync[0])
+  );
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[1]),
+    .o_out  (user_txoutclksel_sync[1])
+  );
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[2]),
+    .o_out  (user_txoutclksel_sync[2])
+  );
+
+  assign GTHE3_CPLLRESET_OUT = cpllreset_int;
+  assign GTHE3_CPLLPD_OUT = cpllpd_int;
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | reset_in_sync)
+      USER_CPLLLOCK_OUT <= 1'b0;
+    else
+      USER_CPLLLOCK_OUT <= gthe3_cplllock_sync;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in)
+      GTHE3_TXPROGDIVRESET_OUT <= txprogdivreset_int;
+    else
+      GTHE3_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in)
+      GTHE3_TXOUTCLKSEL_OUT <= txoutclksel_int;
+    else
+      GTHE3_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in)
+      USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
+    else
+      USER_TXPRGDIVRESETDONE_OUT <= gthe3_txprgdivresetdone_sync;
+  end
+
+  // frequency counter for txoutclk
+  wire [17:0] txoutclk_freq_cnt;
+  reg freq_counter_rst = 1'b1;
+  wire freq_cnt_done;
+  gtwizard_ultrascale_v1_7_9_gthe3_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
+    (
+      .freq_cnt_o(txoutclk_freq_cnt),
+      .done_o(freq_cnt_done),
+      .rst_i(freq_counter_rst),
+      .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
+      .ref_clk_i(CLK_IN),
+      .test_clk_i(txoutclkmon)
+    );
+
+  //Debug signals
+  assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gthe3_cplllock_sync,fboost_store,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
+  assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
+  assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
+
+  //CPLL CAL FSM
+  always @(posedge CLK_IN) begin
+      if (reset_in_sync) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        txprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+      end
+      else begin
+         cpll_cal_state <= 0;
+         case(1'b1) // synthesis parallel_case full_case
+             cpll_cal_state[RESET]:
+             begin
+               wait_ctr <= 16'd0;
+               repeat_ctr <= 4'd0;
+               mask_user_in <= 1'b1;
+               di_msk <= 16'b0000_0000_0000_0000;
+               cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
+             end
+
+             cpll_cal_state[READ_PROGCLK_SEL]:
+             begin
+               rd <= 1'b1;
+               if (drp_done) begin
+                 rd <= 1'b0;
+                 progclk_sel_store <= dout[11:10];
+                 cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+               end
+               else begin
+                 cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
+               end
+             end
+
+             cpll_cal_state[MODIFY_PROGCLK_SEL]:
+             begin
+               if (!drp_done) begin
+                 wr <= 1'b1;
+                 cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+               end
+               else begin
+                 wr <= 1'b0;
+                 cpll_cal_state[READ_PROGDIV] <= 1'b1;
+               end
+               di_msk<= {4'd0,MOD_PROGCLK_SEL,10'd0};
+             end
+
+             cpll_cal_state[READ_PROGDIV]:
+             begin
+               rd <= 1'b1;
+               if (drp_done) begin
+                 rd <= 1'b0;
+                 progdiv_cfg_store <= dout;
+                 cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+               end
+               else begin
+                 cpll_cal_state[READ_PROGDIV] <= 1'b1;
+               end
+             end
+
+             cpll_cal_state[MODIFY_PROGDIV]:
+             begin
+               if (!drp_done) begin
+                 wr <= 1'b1;
+                 cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+               end
+               else begin
+                 wr <= 1'b0;
+                 cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+               di_msk<= MOD_PROGDIV_CFG;
+             end
+
+             cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
+             begin
+               cpll_cal_state[ASSERT_CPLLRESET1] <= 1'b1;
+             end
+
+             cpll_cal_state[ASSERT_CPLLRESET1]:
+             begin
+               if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 cpll_cal_state[ASSERT_CPLLRESET1] <= 1'b1;
+                 cpllreset_int <= 1'b1;
+               end
+               else begin
+                 cpllreset_int <= 1'b0;
+                 freq_counter_rst <= 1'b1;
+                 cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+               repeat_ctr <= 4'd0;
+             end
+
+             cpll_cal_state[READ_FBOOST]:
+             begin
+               rd <= 1'b1;
+               if (drp_done) begin
+                 rd <= 1'b0;
+                 fboost_store <= dout[2];
+                 cpll_cal_state[MODIFY_FBOOST] <= 1'b1;
+               end
+               else begin
+                 cpll_cal_state[READ_FBOOST] <= 1'b1;
+               end
+             end
+
+             cpll_cal_state[MODIFY_FBOOST]:
+             begin
+               if (!drp_done) begin
+                 wr <= 1'b1;
+                 cpll_cal_state[MODIFY_FBOOST] <= 1'b1;
+               end
+               else begin
+                 wr <= 1'b0;
+                 cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+               di_msk<= {13'd0,MOD_FBOOST,2'b00};
+             end
+
+             cpll_cal_state[ASSERT_CPLLRESET]:
+             begin
+               if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+               end
+               else begin
+                 cpllreset_int <= 1'b1;
+                 freq_counter_rst <= 1'b1;
+                 cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[ASSERT_CPLLPD]:
+             begin
+               if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+               end
+               else begin
+                 cpllpd_int <= 1'b1;
+                 cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[DEASSERT_CPLLPD]:
+             begin
+               if (wait_ctr < WAIT_DEASSERT_CPLLPD_IN) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+               end
+               else begin
+                 cpllpd_int <= 1'b0;
+                 cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[DEASSERT_CPLLRESET]:
+             begin
+               if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+               end
+               else begin
+                 cpllreset_int <= 1'b0;
+                 cpll_cal_state[RESTORE_FBOOST] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[RESTORE_FBOOST]:
+             begin
+               if (!drp_done) begin
+                 wr <= 1'b1;
+                 cpll_cal_state[RESTORE_FBOOST] <= 1'b1;
+               end
+               else begin
+                 wr <= 1'b0;
+                 cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+               end
+               di_msk<= {13'd0,fboost_store,2'b00};
+             end
+
+             cpll_cal_state[WAIT_GTCPLLLOCK]:
+             begin
+               if(wait_ctr < WAIT_CPLLLOCK) begin
+                 cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+                 wait_ctr <= wait_ctr + 1'b1;
+               end
+               else begin
+                 cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[ASSERT_PROGDIVRESET]:
+             begin
+               if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 txprogdivreset_int <= 1'b1;
+                 cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+               end
+               else begin
+                 txprogdivreset_int <= 1'b0;
+                 cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+             begin
+               if (gthe3_txprgdivresetdone_sync) begin
+                 cpll_cal_state[CHECK_FREQ] <= 1'b1;
+                 freq_counter_rst <= 1'b0;
+               end
+               else begin
+                 cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+               end
+             end
+
+             cpll_cal_state[CHECK_FREQ]:
+             begin
+               if(freq_cnt_done) begin
+                 if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                   cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+                   cal_fail_store <= 1'b0;
+                 end
+                 else begin
+                   if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                     cpll_cal_state[READ_FBOOST] <= 1'b1;
+                     repeat_ctr <= repeat_ctr + 1'b1;
+                   end
+                   else begin
+                     cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+                     cal_fail_store <= 1'b1;
+                   end
+                 end
+               end
+               else
+                 cpll_cal_state[CHECK_FREQ] <= 1'b1;
+             end
+
+             cpll_cal_state[RESTORE_PROGDIV]:
+             begin
+               if (!drp_done) begin
+                 wr <= 1'b1;
+                 cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+               end
+               else begin
+                 wr <= 1'b0;
+                 cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+               end
+               di_msk<= progdiv_cfg_store;
+             end
+
+             cpll_cal_state[RESTORE_PROGCLK_SEL]:
+             begin
+               if (!drp_done) begin
+                 wr <= 1'b1;
+                 cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+               end
+               else begin
+                 wr <= 1'b0;
+                 cpll_cal_state[ASSERT_CPLLRESET2] <= 1'b1;
+               end
+               di_msk<= {4'd0,progclk_sel_store,10'd0};
+             end
+
+             cpll_cal_state[ASSERT_CPLLRESET2]:
+             begin
+               if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 cpll_cal_state[ASSERT_CPLLRESET2] <= 1'b1;
+                 cpllreset_int <= 1'b1;
+               end
+               else begin
+                 cpllreset_int <= 1'b0;
+                 cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[WAIT_GTCPLLLOCK2]:
+             begin
+               if(gthe3_cplllock_sync)
+                 cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+               else
+                 cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
+             end
+
+             cpll_cal_state[ASSERT_PROGDIVRESET2]:
+             begin
+               if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+                 wait_ctr <= wait_ctr + 1'b1;
+                 txprogdivreset_int <= 1'b1;
+                 cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+               end
+               else begin
+                 txprogdivreset_int <= 1'b0;
+                 cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+                 wait_ctr <= 16'd0;
+               end
+             end
+
+             cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+             begin
+               if (gthe3_txprgdivresetdone_sync) begin
+                 if (cal_fail_store)
+                   cpll_cal_state[CAL_FAIL] <= 1'b1;
+                 else
+                   cpll_cal_state[CAL_DONE] <= 1'b1;
+               end
+               else begin
+                 cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+               end
+             end
+
+             cpll_cal_state[CAL_FAIL]:
+             begin
+               cpll_cal_state[CAL_FAIL] <= 1'b1;
+               mask_user_in <= 1'b0;
+             end
+
+             cpll_cal_state[CAL_DONE]:
+             begin
+               cpll_cal_state[CAL_DONE] <= 1'b1;
+               mask_user_in <= 1'b0;
+             end
+         endcase
+       end
+   end // always block
+
+   always @(posedge CLK_IN) begin
+     if (cpll_cal_state[RESET])
+       txoutclksel_int <= 3'b0;
+     else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
+       txoutclksel_int <= MOD_TXOUTCLK_SEL;
+   end
+
+   always @(posedge CLK_IN) begin
+     if      (cpll_cal_state[RESET]) begin
+       daddr <= 9'h000;
+       mask  <= 16'b1111_1111_1111_1111;
+     end
+     else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
+       daddr <= ADDR_TX_PROGCLK_SEL;
+       mask  <= 16'b1111_0011_1111_1111;
+     end
+     else if (cpll_cal_state[READ_PROGDIV] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
+       daddr <= ADDR_TX_PROGDIV_CFG;
+       mask  <= 16'b0000_0000_0000_0000;
+     end
+     else if (cpll_cal_state[READ_FBOOST] | cpll_cal_state[MODIFY_FBOOST] | cpll_cal_state[RESTORE_FBOOST]) begin
+       daddr <= ADDR_FBOOST;
+       mask  <= 16'b1111_1111_1111_1011;
+     end
+   end
+
+
+  // DRP FSM
+  always @(posedge CLK_IN) begin
+    if (mask_user_in) begin
+      GTHE3_CHANNEL_DRPADDR_OUT <= daddr;
+      GTHE3_CHANNEL_DRPDI_OUT   <= di;
+      GTHE3_CHANNEL_DRPEN_OUT   <= den;
+      GTHE3_CHANNEL_DRPWE_OUT   <= dwe;
+      USER_CHANNEL_DRPRDY_OUT   <= 1'b0;
+      USER_CHANNEL_DRPDO_OUT    <= 16'd0;
+    end
+    else begin
+      GTHE3_CHANNEL_DRPADDR_OUT <= USER_CHANNEL_DRPADDR_IN;
+      GTHE3_CHANNEL_DRPDI_OUT   <= USER_CHANNEL_DRPDI_IN;
+      GTHE3_CHANNEL_DRPEN_OUT   <= USER_CHANNEL_DRPEN_IN;
+      GTHE3_CHANNEL_DRPWE_OUT   <= USER_CHANNEL_DRPWE_IN;
+      USER_CHANNEL_DRPRDY_OUT   <= GTHE3_CHANNEL_DRPRDY_IN;
+      USER_CHANNEL_DRPDO_OUT    <= GTHE3_CHANNEL_DRPDO_IN;
+    end
+  end
+  assign drdy = GTHE3_CHANNEL_DRPRDY_IN;
+  assign dout = GTHE3_CHANNEL_DRPDO_IN;
+
+  always @(posedge CLK_IN or posedge reset_in_sync) begin
+  if (reset_in_sync) begin
+    den <= 1'b0;
+    dwe <= 1'b0;
+    di <= 16'h0000;
+    drp_state <= 0;
+    drp_state[DRP_WAIT] <= 1'b1;
+  end
+  else begin
+    drp_state <= 0;
+    case (1'b1) // synthesis parallel_case full_case
+        drp_state[DRP_WAIT]:
+        begin
+          if (wr | rd) drp_state[DRP_READ] <= 1'b1;
+          else         drp_state[DRP_WAIT] <= 1'b1;
+        end
+        drp_state[DRP_READ]:
+        begin
+          den <= 1'b1;
+          drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_READ_ACK]:
+        begin
+          den <= 1'b0;
+          if (drdy == 1'b1) begin
+            if (rd) drp_state[DRP_DONE] <= 1'b1;
+            else    drp_state[DRP_MODIFY] <= 1'b1;
+          end
+          else      drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_MODIFY]:
+        begin
+          di <= di_msk | (dout & mask);
+          drp_state[DRP_WRITE] <= 1'b1;
+        end
+        drp_state[DRP_WRITE]:
+        begin
+          den <= 1'b1;
+          dwe <= 1'b1;
+          drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_WRITE_ACK]:
+        begin
+          den <= 1'b0;
+          dwe <= 1'b0;
+          if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
+          else              drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_DONE]:
+        begin
+          drp_state[DRP_WAIT] <= 1'b1;
+        end
+    endcase
+  end
+  end
+
+  assign drp_done = drp_state[DRP_DONE];
+
+
+  //debug logic - convert one hot state to binary
+  genvar i,j;
+  generate
+    for (j=0; j<5; j=j+1)
+    begin : jl
+      wire [26-1:0] tmp_mask;
+      for (i=0; i<26; i=i+1)
+      begin : il
+        assign tmp_mask[i] = i[j];
+      end
+      assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
+    end
+  endgenerate
+
+endmodule //CPLL_CAL
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v
new file mode 100755
index 0000000..9b54bae
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v
@@ -0,0 +1,224 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_freq_counter # (
+  parameter REVISION = 1
+)(
+  output reg  [17:0] freq_cnt_o = 18'd0,
+  output reg  done_o,
+  input  wire rst_i,
+  input  wire [15:0] test_term_cnt_i,
+  input  wire ref_clk_i,
+  input  wire test_clk_i
+);
+  //****************************************************************************
+  //  Local Parameters
+  //****************************************************************************
+  localparam RESET_STATE = 0;
+  localparam MEASURE_STATE = 1;
+  localparam HOLD_STATE = 2;
+  localparam UPDATE_STATE = 3;
+  localparam DONE_STATE = 4;
+
+  //****************************************************************************
+  //  Local Signals
+  //****************************************************************************
+  reg [17:0] testclk_cnt = 18'h00000;
+  reg [15:0] refclk_cnt = 16'h0000;
+  reg [3:0] testclk_div4 = 4'h1;
+  wire testclk_rst;
+  wire testclk_en;
+  reg [5:0] hold_clk = 6'd0;
+  reg [4:0] state = 5'd1;
+
+  (* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
+  (* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
+
+  //
+  // need to get testclk_rst into TESTCLK_I domain
+  //
+  always @(posedge test_clk_i)
+  begin
+    tstclk_rst_dly1 <= testclk_rst;
+    tstclk_rst_dly2 <= tstclk_rst_dly1;
+  end
+
+  //
+  // need to get testclk_en into TESTCLK_I domain
+  //
+  always @(posedge test_clk_i)
+  begin
+    testclk_en_dly1 <= testclk_en;
+    testclk_en_dly2 <= testclk_en_dly1;
+  end
+
+  always @(posedge test_clk_i)
+  begin
+    if (tstclk_rst_dly2 == 1'b1)
+    begin
+      testclk_div4 <= 4'h1;
+    end
+    else
+    begin
+      testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
+    end
+  end
+
+  wire testclk_rst_sync;
+
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_testclk_rst_inst (
+    .clk_in (test_clk_i),
+    .rst_in   (testclk_rst),
+    .rst_out  (testclk_rst_sync)
+  );
+
+  always @(posedge test_clk_i or posedge testclk_rst_sync)
+  begin
+    if (testclk_rst_sync == 1'b1)
+    begin
+      testclk_cnt <= 0;
+    end
+    else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
+    begin
+      testclk_cnt <= testclk_cnt + 1;
+    end
+  end
+
+/*   always @(posedge test_clk_i or posedge testclk_rst)
+  begin
+    if (testclk_rst == 1'b1)
+    begin
+      testclk_cnt <= 0;
+    end
+    else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
+    begin
+      testclk_cnt <= testclk_cnt + 1;
+    end
+  end */
+
+  always @(posedge ref_clk_i or posedge rst_i)
+  begin
+    if (rst_i)
+      done_o <= 1'b0;
+    else
+      done_o <= state[DONE_STATE];
+  end
+
+  always @(posedge ref_clk_i or posedge rst_i)
+  begin
+    if (rst_i) begin
+      state <= 0;
+      state[RESET_STATE] <= 1'b1;
+    end
+    else begin
+      state <= 0;
+      case (1'b1) // synthesis parallel_case full_case
+        state[RESET_STATE]:
+          begin
+            if (hold_clk == 6'h3F)
+              state[MEASURE_STATE] <= 1'b1;
+            else
+              state[RESET_STATE] <= 1'b1;
+          end
+        state[MEASURE_STATE]:
+          begin
+            if (refclk_cnt == test_term_cnt_i)
+              state[HOLD_STATE] <= 1'b1;
+            else
+              state[MEASURE_STATE] <= 1'b1;
+          end
+        state[HOLD_STATE]:
+          begin
+            if (hold_clk == 6'hF)
+              state[UPDATE_STATE] <= 1'b1;
+            else
+              state[HOLD_STATE] <= 1'b1;
+          end
+        state[UPDATE_STATE]:
+          begin
+            freq_cnt_o <= testclk_cnt;
+            state[DONE_STATE] <= 1'b1;
+          end
+        state[DONE_STATE]:
+          begin
+            state[DONE_STATE] <= 1'b1;
+          end
+      endcase
+    end
+  end
+
+  assign testclk_rst = state[RESET_STATE];
+  assign testclk_en = state[MEASURE_STATE];
+
+
+  always @(posedge ref_clk_i)
+  begin
+    if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
+      hold_clk <= hold_clk + 1;
+    else
+      hold_clk <= 0;
+  end
+
+  always @(posedge ref_clk_i)
+  begin
+    if (state[MEASURE_STATE] == 1'b1)
+      refclk_cnt <= refclk_cnt + 1;
+    else
+      refclk_cnt <= 0;
+  end
+
+
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v
new file mode 100755
index 0000000..69bc7d2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v
@@ -0,0 +1,346 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal # (
+  parameter integer C_RX_PLL_TYPE = 0,
+  parameter integer C_TX_PLL_TYPE = 0,
+  parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
+  parameter SIM_RESET_SPEEDUP     = "TRUE",
+  parameter C_FREERUN_FREQUENCY   = 100, 
+  parameter REVISION              = 2,
+  parameter C_PCIE_ENABLE         = "FALSE",
+  parameter C_PCIE_CORECLK_FREQ   = 250
+)(
+  // control signals
+  input   wire  [17:0]  TXOUTCLK_PERIOD_IN,
+  input   wire  [17:0]  CNT_TOL_IN,
+  input   wire  [15:0]  FREQ_COUNT_WINDOW_IN,
+  // User Interface
+  input   wire          RESET_IN,
+  input   wire          CLK_IN,
+  input   wire          DRPRST_IN,
+  input   wire  [1:0]   USER_TXPLLCLKSEL,
+  input   wire  [1:0]   USER_RXPLLCLKSEL,
+  input   wire          USER_RXPROGDIVRESET_IN,
+  output  wire          USER_RXPRGDIVRESETDONE_OUT,
+  output  wire          USER_RXPMARESETDONE_OUT,
+  input   wire  [2:0]   USER_RXOUTCLKSEL_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CLR_IN,
+  input   wire          USER_GTRXRESET_IN,
+  input   wire          USER_RXCDRHOLD_IN,
+  input   wire          USER_RXPMARESET_IN,
+  input   wire          USER_TXPROGDIVRESET_IN,
+  output  wire          USER_TXPRGDIVRESETDONE_OUT,
+  input   wire  [2:0]   USER_TXOUTCLKSEL_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CLR_IN,
+  output  wire          USER_CPLLLOCK_OUT,
+  input   wire  [9:0]   USER_CHANNEL_DRPADDR_IN,
+  input   wire  [15:0]  USER_CHANNEL_DRPDI_IN,
+  input   wire          USER_CHANNEL_DRPEN_IN,
+  input   wire          USER_CHANNEL_DRPWE_IN,
+  output  wire          USER_CHANNEL_DRPRDY_OUT,
+  output  wire  [15:0]  USER_CHANNEL_DRPDO_OUT,
+  // Debug Interface
+  output  wire          CPLL_CAL_FAIL,
+  output  wire          CPLL_CAL_DONE,
+  output  wire  [15:0]  DEBUG_OUT,
+  output  wire  [17:0]  CAL_FREQ_CNT,
+  input         [3:0]   REPEAT_RESET_LIMIT,
+  // GT Interface
+  input   wire          GTHE4_TXOUTCLK_IN,
+  input   wire          GTHE4_RXOUTCLK_IN,
+  input   wire          GTHE4_CPLLLOCK_IN,
+  output  wire          GTHE4_CPLLRESET_OUT,
+  output  wire          GTHE4_RXCDRHOLD_OUT,
+  output  wire          GTHE4_GTRXRESET_OUT,
+  output  wire          GTHE4_RXPMARESET_OUT,
+  output  wire          GTHE4_RXPROGDIVRESET_OUT,
+  output  wire  [2:0]   GTHE4_RXOUTCLKSEL_OUT,
+  input   wire          GTHE4_RXPRGDIVRESETDONE_IN,
+  input   wire          GTHE4_RXPMARESETDONE_IN,
+  output  wire          GTHE4_CPLLPD_OUT,
+  output  wire          GTHE4_TXPROGDIVRESET_OUT,
+  output  wire  [2:0]   GTHE4_TXOUTCLKSEL_OUT,
+  input   wire          GTHE4_TXPRGDIVRESETDONE_IN,
+  output  wire  [9:0]   GTHE4_CHANNEL_DRPADDR_OUT,
+  output  wire  [15:0]  GTHE4_CHANNEL_DRPDI_OUT,
+  output  wire          GTHE4_CHANNEL_DRPEN_OUT,
+  output  wire          GTHE4_CHANNEL_DRPWE_OUT,
+  input   wire          GTHE4_CHANNEL_DRPRDY_IN,
+  input   wire  [15:0]  GTHE4_CHANNEL_DRPDO_IN
+);
+
+  wire rx_done;
+  wire tx_done; 
+  
+  wire cal_on_rx_cal_fail;
+  wire cal_on_rx_cal_done; 
+  wire [15:0] cal_on_rx_debug_out; 
+  wire [17:0] cal_on_rx_cal_freq_cnt;
+  wire cal_on_rx_cpllreset_out;
+  wire cal_on_rx_cpllpd_out;
+  wire cal_on_rx_cplllock_out;
+  
+  wire cal_on_rx_drpen_out;
+  wire cal_on_rx_drpwe_out;
+  wire [9:0] cal_on_rx_drpaddr_out;
+  wire [15:0] cal_on_rx_drpdi_out;
+  wire [15:0] cal_on_rx_dout;
+  wire cal_on_rx_drdy;
+
+  wire cal_on_tx_cal_fail;
+  wire cal_on_tx_cal_done; 
+  wire [15:0] cal_on_tx_debug_out; 
+  wire [17:0] cal_on_tx_cal_freq_cnt;
+  wire cal_on_tx_cpllreset_out;
+  wire cal_on_tx_cpllpd_out;
+  wire cal_on_tx_cplllock_out;
+  
+  wire cal_on_tx_drpen_out;
+  wire cal_on_tx_drpwe_out;
+  wire [9:0] cal_on_tx_drpaddr_out;
+  wire [15:0] cal_on_tx_drpdi_out;
+  wire [15:0] cal_on_tx_dout;
+  wire cal_on_tx_drdy;  
+  
+  localparam [9:0]  ADDR_TX_PROGCLK_SEL = 10'h00C;
+  localparam [9:0]  ADDR_TX_PROGDIV_CFG = 10'h03E;  // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
+  localparam [9:0]  ADDR_RX_PROGDIV_CFG = 10'h0C6;
+  localparam [9:0]  ADDR_X0E1 = 10'h0E1;
+  localparam [9:0]  ADDR_X079 = 10'h079;
+  localparam [9:0]  ADDR_X114 = 10'h114; 
+  localparam CPLL_CAL_ONLY_TX = (C_RX_PLL_TYPE == C_TX_PLL_TYPE); // If top level configuration of TX and RX PLL TYPE are same, don't use RX Cal block
+
+  wire cpll_cal_on_tx_or_rx;  //1: RX cal block, 0: TX cal block;
+  assign cpll_cal_on_tx_or_rx = CPLL_CAL_ONLY_TX ? 1'b0 : ((USER_TXPLLCLKSEL != 2'b00 && USER_RXPLLCLKSEL == 2'b00) ? 1'b1 : 1'b0); 
+  
+  // TX reset version
+  wire cal_on_tx_reset_in; 
+  assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx;
+  
+  wire cal_on_tx_reset_in_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_resetin_tx_inst (
+    .clk_in   (CLK_IN),
+    .rst_in   (cal_on_tx_reset_in),
+    .rst_out  (cal_on_tx_reset_in_sync)
+  );
+  
+  // RX reset version
+  wire cal_on_rx_reset_in; 
+  assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx;  
+  
+  wire cal_on_rx_reset_in_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_resetin_rx_inst (
+    .clk_in   (CLK_IN),
+    .rst_in   (cal_on_rx_reset_in),
+    .rst_out  (cal_on_rx_reset_in_sync)
+  );
+
+  wire drprst_in_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_drprst_inst (
+    .clk_in (CLK_IN),
+    .i_in   (DRPRST_IN),
+    .o_out  (drprst_in_sync)
+  );
+
+  gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_tx #
+  (
+    .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
+    .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
+    .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
+    .C_PCIE_ENABLE(C_PCIE_ENABLE),
+    .C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ)
+  ) gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_tx_i
+  (
+    // control signals
+    .TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
+    .CNT_TOL_IN(CNT_TOL_IN),
+    .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
+    // User Interface
+    .RESET_IN(cal_on_tx_reset_in_sync),
+    .CLK_IN(CLK_IN),
+    .USER_TXPLLCLKSEL(USER_TXPLLCLKSEL),
+    .USER_TXPROGDIVRESET_IN(USER_TXPROGDIVRESET_IN),
+    .USER_TXPRGDIVRESETDONE_OUT(USER_TXPRGDIVRESETDONE_OUT),
+    .USER_TXOUTCLKSEL_IN(USER_TXOUTCLKSEL_IN),
+    .USER_TXOUTCLK_BUFG_CE_IN(USER_TXOUTCLK_BUFG_CE_IN),
+    .USER_TXOUTCLK_BUFG_CLR_IN(USER_TXOUTCLK_BUFG_CLR_IN),
+    .USER_CPLLLOCK_OUT(cal_on_tx_cplllock_out),
+    // Debug Interface
+    .CPLL_CAL_FAIL(cal_on_tx_cal_fail),
+    .CPLL_CAL_DONE(cal_on_tx_cal_done),
+    .DEBUG_OUT(cal_on_tx_debug_out),
+    .CAL_FREQ_CNT(cal_on_tx_cal_freq_cnt),
+    .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
+    // GT Interface
+    .GTHE4_TXOUTCLK_IN(GTHE4_TXOUTCLK_IN),
+    .GTHE4_CPLLLOCK_IN(GTHE4_CPLLLOCK_IN),
+    .GTHE4_CPLLRESET_OUT(cal_on_tx_cpllreset_out),
+    .GTHE4_CPLLPD_OUT(cal_on_tx_cpllpd_out),
+    .GTHE4_TXPROGDIVRESET_OUT(GTHE4_TXPROGDIVRESET_OUT),
+    .GTHE4_TXOUTCLKSEL_OUT(GTHE4_TXOUTCLKSEL_OUT),
+    .GTHE4_TXPRGDIVRESETDONE_IN(GTHE4_TXPRGDIVRESETDONE_IN),
+    .GTHE4_CHANNEL_DRPADDR_OUT(cal_on_tx_drpaddr_out),
+    .GTHE4_CHANNEL_DRPDI_OUT(cal_on_tx_drpdi_out),
+    .GTHE4_CHANNEL_DRPEN_OUT(cal_on_tx_drpen_out),
+    .GTHE4_CHANNEL_DRPWE_OUT(cal_on_tx_drpwe_out),
+    .GTHE4_CHANNEL_DRPRDY_IN(cal_on_tx_drdy),
+    .GTHE4_CHANNEL_DRPDO_IN(cal_on_tx_dout),
+    .DONE(tx_done)
+  );  
+  
+  gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_rx #
+  (
+    .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
+    .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
+    .CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX),
+    .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY)
+  ) gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_rx_i
+  (
+    // control signals
+    .RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
+    .CNT_TOL_IN(CNT_TOL_IN),
+    .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
+    // User Interface
+    .RESET_IN(cal_on_rx_reset_in_sync),
+    .CLK_IN(CLK_IN),
+    .USER_RXPROGDIVRESET_IN(USER_RXPROGDIVRESET_IN),
+    .USER_RXPRGDIVRESETDONE_OUT(USER_RXPRGDIVRESETDONE_OUT),
+    .USER_RXPMARESETDONE_OUT(USER_RXPMARESETDONE_OUT),
+    .USER_RXOUTCLKSEL_IN(USER_RXOUTCLKSEL_IN),
+    .USER_RXOUTCLK_BUFG_CE_IN(USER_RXOUTCLK_BUFG_CE_IN),
+    .USER_RXOUTCLK_BUFG_CLR_IN(USER_RXOUTCLK_BUFG_CLR_IN),
+    .USER_CPLLLOCK_OUT(cal_on_rx_cplllock_out),
+    .USER_RXCDRHOLD_IN(USER_RXCDRHOLD_IN),
+    .USER_GTRXRESET_IN(USER_GTRXRESET_IN),
+    .USER_RXPMARESET_IN(USER_RXPMARESET_IN),
+    // Debug Interface
+    .CPLL_CAL_FAIL(cal_on_rx_cal_fail),
+    .CPLL_CAL_DONE(cal_on_rx_cal_done),
+    .DEBUG_OUT(cal_on_rx_debug_out),
+    .CAL_FREQ_CNT(cal_on_rx_cal_freq_cnt),
+    .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
+    // GT Interface
+    .GTHE4_RXOUTCLK_IN(GTHE4_RXOUTCLK_IN),
+    .GTHE4_CPLLLOCK_IN(GTHE4_CPLLLOCK_IN),
+    .GTHE4_CPLLRESET_OUT(cal_on_rx_cpllreset_out),
+    .GTHE4_CPLLPD_OUT(cal_on_rx_cpllpd_out),
+    .GTHE4_RXPROGDIVRESET_OUT(GTHE4_RXPROGDIVRESET_OUT),
+    .GTHE4_RXOUTCLKSEL_OUT(GTHE4_RXOUTCLKSEL_OUT),
+    .GTHE4_RXPRGDIVRESETDONE_IN(GTHE4_RXPRGDIVRESETDONE_IN),
+    .GTHE4_CHANNEL_DRPADDR_OUT(cal_on_rx_drpaddr_out),
+    .GTHE4_CHANNEL_DRPDI_OUT(cal_on_rx_drpdi_out),
+    .GTHE4_CHANNEL_DRPEN_OUT(cal_on_rx_drpen_out),
+    .GTHE4_CHANNEL_DRPWE_OUT(cal_on_rx_drpwe_out),
+    .GTHE4_CHANNEL_DRPRDY_IN(cal_on_rx_drdy),
+    .GTHE4_CHANNEL_DRPDO_IN(cal_on_rx_dout),
+    .GTHE4_GTRXRESET_OUT(GTHE4_GTRXRESET_OUT),
+    .GTHE4_RXPMARESET_OUT(GTHE4_RXPMARESET_OUT),
+    .GTHE4_RXCDRHOLD_OUT(GTHE4_RXCDRHOLD_OUT),
+    .GTHE4_RXPMARESETDONE_IN(GTHE4_RXPMARESETDONE_IN),
+    .DONE(rx_done)
+  );
+  
+  //OR with TX versions
+  assign GTHE4_CPLLRESET_OUT = cal_on_rx_cpllreset_out | cal_on_tx_cpllreset_out; 
+  assign GTHE4_CPLLPD_OUT = cal_on_rx_cpllpd_out | cal_on_tx_cpllpd_out;
+  assign USER_CPLLLOCK_OUT = cal_on_rx_cplllock_out | cal_on_tx_cplllock_out;
+
+  //Mux the debug signals out
+  assign CPLL_CAL_DONE = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_done : cal_on_tx_cal_done;
+  assign CPLL_CAL_FAIL = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_fail : cal_on_tx_cal_fail;
+  assign DEBUG_OUT = cpll_cal_on_tx_or_rx ? cal_on_rx_debug_out : cal_on_tx_debug_out;
+  assign CAL_FREQ_CNT = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_freq_cnt : cal_on_tx_cal_freq_cnt;
+  
+  //----------------------------------------------------------------------------------------------
+  // DRP ARBITER
+  //----------------------------------------------------------------------------------------------
+  
+  gtwizard_ultrascale_v1_7_9_gte4_drp_arb #
+  (
+    .ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL),
+    .ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG),
+    .ADDR_RX_PROGDIV_CFG(ADDR_RX_PROGDIV_CFG),
+    .ADDR_X0E1(ADDR_X0E1),
+    .ADDR_X079(ADDR_X079),
+    .ADDR_X114(ADDR_X114),
+    .C_NUM_CLIENTS(3),
+    .C_ADDR_WIDTH(10),
+    .C_DATA_WIDTH(16)
+  ) gtwizard_ultrascale_v1_7_9_gte4_drp_arb_i
+  (
+    .DCLK_I         (CLK_IN),
+    .RESET_I        (drprst_in_sync),
+    .DEN_USR_I      ({cal_on_tx_drpen_out, cal_on_rx_drpen_out, USER_CHANNEL_DRPEN_IN}),
+    .DWE_USR_I      ({cal_on_tx_drpwe_out, cal_on_rx_drpwe_out, USER_CHANNEL_DRPWE_IN}),
+    .DADDR_USR_I    ({cal_on_tx_drpaddr_out, cal_on_rx_drpaddr_out, USER_CHANNEL_DRPADDR_IN}),
+    .DI_USR_I       ({cal_on_tx_drpdi_out, cal_on_rx_drpdi_out, USER_CHANNEL_DRPDI_IN}),
+    .DO_USR_O       ({cal_on_tx_dout, cal_on_rx_dout, USER_CHANNEL_DRPDO_OUT}),
+    .DRDY_USR_O     ({cal_on_tx_drdy, cal_on_rx_drdy, USER_CHANNEL_DRPRDY_OUT}),
+    // arbitrated port
+    .DEN_O          (GTHE4_CHANNEL_DRPEN_OUT),
+    .DWE_O          (GTHE4_CHANNEL_DRPWE_OUT),
+    .DADDR_O        (GTHE4_CHANNEL_DRPADDR_OUT),
+    .DI_O           (GTHE4_CHANNEL_DRPDI_OUT),
+    .DO_I           (GTHE4_CHANNEL_DRPDO_IN),
+    .DRDY_I         (GTHE4_CHANNEL_DRPRDY_IN),
+    .TX_CAL_DONE_I  (tx_done),
+    .RX_CAL_DONE_I  (rx_done)
+  );
+
+endmodule //CPLL_CAL
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v
new file mode 100755
index 0000000..a3e3da3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v
@@ -0,0 +1,1091 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_rx # (
+  parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
+  parameter SIM_RESET_SPEEDUP     = "TRUE",
+  parameter CPLL_CAL_ONLY_TX      = 1,
+  parameter C_FREERUN_FREQUENCY   = 100
+)(
+  // control signals
+  input   wire  [17:0]  RXOUTCLK_PERIOD_IN,
+  input   wire  [17:0]  CNT_TOL_IN,
+  input   wire  [15:0]  FREQ_COUNT_WINDOW_IN,
+  // User Interface
+  input   wire          RESET_IN,
+  input   wire          CLK_IN,
+  
+  input   wire          USER_RXPROGDIVRESET_IN,
+  output  wire          USER_RXPRGDIVRESETDONE_OUT,
+  output  wire          USER_RXPMARESETDONE_OUT,
+  input   wire  [2:0]   USER_RXOUTCLKSEL_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CLR_IN,
+  output  reg           USER_CPLLLOCK_OUT,
+  input   wire          USER_GTRXRESET_IN, 
+  input   wire          USER_RXCDRHOLD_IN,
+  input   wire          USER_RXPMARESET_IN,
+  // Debug Interface
+  output  wire          CPLL_CAL_FAIL,
+  output  wire          CPLL_CAL_DONE,
+  output  wire  [15:0]  DEBUG_OUT,
+  output  wire  [17:0]  CAL_FREQ_CNT,
+  input         [3:0]   REPEAT_RESET_LIMIT,
+  // GT Interface
+  input   wire          GTHE4_RXOUTCLK_IN,
+  input   wire          GTHE4_CPLLLOCK_IN,
+  output  wire          GTHE4_CPLLRESET_OUT,
+  output  wire          GTHE4_CPLLPD_OUT,
+  output  wire          GTHE4_RXPROGDIVRESET_OUT,
+  output  wire   [2:0]  GTHE4_RXOUTCLKSEL_OUT,
+  input   wire          GTHE4_RXPRGDIVRESETDONE_IN,
+  output  wire  [9:0]   GTHE4_CHANNEL_DRPADDR_OUT,
+  output  wire  [15:0]  GTHE4_CHANNEL_DRPDI_OUT,
+  output  wire          GTHE4_CHANNEL_DRPEN_OUT,
+  output  wire          GTHE4_CHANNEL_DRPWE_OUT,
+  input   wire          GTHE4_CHANNEL_DRPRDY_IN,
+  input   wire  [15:0]  GTHE4_CHANNEL_DRPDO_IN, 
+  output  wire          GTHE4_GTRXRESET_OUT,
+  output  wire          GTHE4_RXPMARESET_OUT,
+  output  wire          GTHE4_RXCDRHOLD_OUT,
+  input   wire          GTHE4_RXPMARESETDONE_IN,
+  output  wire          DONE
+);
+
+generate if (CPLL_CAL_ONLY_TX == 1)
+begin: gen_cal_rx_dis
+  assign GTHE4_RXPROGDIVRESET_OUT   =   USER_RXPROGDIVRESET_IN;
+  assign GTHE4_GTRXRESET_OUT        =   USER_GTRXRESET_IN; 
+  assign GTHE4_RXOUTCLKSEL_OUT      =   USER_RXOUTCLKSEL_IN;
+  assign GTHE4_RXCDRHOLD_OUT        =   USER_RXCDRHOLD_IN;
+  assign GTHE4_RXPMARESET_OUT       =   USER_RXPMARESET_IN; 
+  assign USER_RXPRGDIVRESETDONE_OUT =   GTHE4_RXPRGDIVRESETDONE_IN;
+  assign USER_RXPMARESETDONE_OUT    =   GTHE4_RXPMARESETDONE_IN; 
+  assign  CPLL_CAL_DONE              =  1'd0;
+  assign  CPLL_CAL_FAIL              =  1'd0;
+  assign  DONE                       =  1'd1;
+  assign  GTHE4_CHANNEL_DRPEN_OUT    =  1'd0;
+  assign  GTHE4_CHANNEL_DRPWE_OUT    =  1'd0;
+  assign  GTHE4_CPLLPD_OUT           =  1'd0;
+  assign  GTHE4_CPLLRESET_OUT        =  1'd0;
+  assign  DEBUG_OUT                  = 16'd0;
+  assign  GTHE4_CHANNEL_DRPDI_OUT    = 16'd0;
+  assign  CAL_FREQ_CNT               = 18'd0;
+  assign  GTHE4_CHANNEL_DRPADDR_OUT  = 10'd0;
+
+  always @(posedge CLK_IN) begin
+    if(RESET_IN)
+    	USER_CPLLLOCK_OUT <= 1'b0;
+    else
+    	USER_CPLLLOCK_OUT <= 1'b0;
+  end
+
+end
+else
+begin: gen_cal_rx_en
+
+  //DRP FSM
+  localparam DRP_WAIT      = 0;
+  localparam DRP_READ      = 1;
+  localparam DRP_READ_ACK  = 2;
+  localparam DRP_MODIFY    = 3;
+  localparam DRP_WRITE     = 4;
+  localparam DRP_WRITE_ACK = 5;
+  localparam DRP_DONE      = 6;
+
+  localparam RESET                = 0;
+  localparam READ_X114            = 1;
+  localparam CHECK_X114_STATUS    = 2;
+  localparam READ_PROGDIV_CFG     = 3;
+  localparam SAVE_PROGDIV_CFG     = 4;
+  localparam MODIFY_PROGDIV       = 5; 
+  localparam MODIFY_RXOUTCLK_SEL  = 6;
+  localparam ASSERT_RXCDRHOLD     = 7;
+  localparam ASSERT_CPLLPD        = 8;
+  localparam DEASSERT_CPLLPD      = 9;
+  localparam ASSERT_CPLLRESET     = 10;
+  localparam DEASSERT_CPLLRESET   = 11;
+  localparam WAIT_GTCPLLLOCK      = 12;
+  localparam ASSERT_GTRXRESET     = 13;
+  localparam WAIT_RXPMARESETDONE  = 14;
+  localparam WAIT_RXPMARESETDONE_DEASSERT = 15; 
+  localparam WAIT_RXPMARESETDONE_2        = 16;
+  localparam ASSERT_PROGDIVRESET  = 17;
+  localparam WAIT_PRGDIVRESETDONE = 18;
+  localparam CHECK_FREQ           = 19;
+  localparam RESTORE_READ_X114    = 20; 
+  localparam RESTORE_PROGDIV      = 21;
+  localparam CLEAR_FLAG_x114      = 22;
+  localparam WAIT_GTCPLLLOCK2     = 23;
+  localparam ASSERT_PROGDIVRESET2 = 24;
+  localparam WAIT_PRGDIVRESETDONE2= 25;
+  localparam CAL_FAIL             = 26;
+  localparam CAL_DONE             = 27;
+  
+  reg [31:0] cpll_cal_state = 31'd0;
+  wire [4:0] cpll_cal_state_bin;
+  reg [6:0] drp_state = 7'd1;
+  wire drp_done;
+  reg [9:0] daddr = 10'd0;
+  reg [15:0] di = 16'd0;
+  wire drdy;
+  wire [15:0] dout;
+  reg den = 1'b0;
+  reg dwe = 1'b0;
+  reg wr = 1'b0;
+  reg rd = 1'b0;
+  reg [15:0] di_msk;
+  reg [15:0] mask;
+  reg [24:0] wait_ctr;
+  reg [3:0] repeat_ctr;
+  reg [15:0] progdiv_cfg_store = 16'd0;
+  reg mask_user_in = 1'b0;
+  reg cpllreset_int = 1'b0;
+  reg cpllpd_int = 1'b0;
+  reg rxprogdivreset_int = 1'b0;
+  reg rxcdrhold_int = 1'b0; 
+  reg gtrxreset_int = 1'b0;
+  reg [2:0] rxoutclksel_int = 3'b000;
+  reg cal_fail_store = 1'b0;
+  reg status_store = 1'b0;
+  wire den_i; 
+  wire dwe_i;
+  
+  //All these need to be based on CLK_IN frequency (free_run) 
+  localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY );  // 1 ms
+  localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY );         // 1 ms 
+  localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY );   // 100 us 
+  localparam [24:0] SYNTH_WAIT_ASSERT_PROGDIVRESET = C_FREERUN_FREQUENCY ;   // 1 us 
+
+  localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10; 
+  localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
+  localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;  
+  localparam [24:0] SIM_WAIT_ASSERT_PROGDIVRESET = SYNTH_WAIT_ASSERT_PROGDIVRESET/10;
+  
+  localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
+  localparam [4:0]  WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
+  localparam [24:0] WAIT_ASSERT_CPLLRESET =
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_ASSERT_CPLLRESET;
+  localparam [4:0]  WAIT_ASSERT_CPLLPD = 5'd25;  // >= 100 ns
+  localparam [24:0] WAIT_DEASSERT_CPLLRESET =  
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_DEASSERT_CPLLRESET;
+  localparam [24:0] WAIT_CPLLLOCK = 
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
+    //pragma translate_on
+                                        SYNTH_WAIT_CPLLLOCK;
+  
+  localparam [24:0] WAIT_ASSERT_PROGDIVRESET = 
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_PROGDIVRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_ASSERT_PROGDIVRESET;  
+
+
+  localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
+  localparam [2:0]  MOD_RXOUTCLK_SEL = 3'b101;
+  localparam [9:0]  ADDR_RX_PROGDIV_CFG = 10'h0C6; 
+  localparam [9:0]  ADDR_X114 = 10'h114;
+
+  // Drive RXOUTCLK with BUFG_GT-buffered source clock, divider = 1
+  wire rxoutclkmon;
+  //assign rxoutclkmon = GTHE4_RXOUTCLK_IN;
+  BUFG_GT bufg_gt_rxoutclkmon_inst (
+    .CE      (USER_RXOUTCLK_BUFG_CE_IN),
+    .CEMASK  (1'b1),
+    .CLR     (USER_RXOUTCLK_BUFG_CLR_IN),
+    .CLRMASK (1'b1),
+    .DIV     (3'b000),
+    .I       (GTHE4_RXOUTCLK_IN),
+    .O       (rxoutclkmon)
+  );
+
+  wire gthe4_cplllock_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_cplllock_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE4_CPLLLOCK_IN),
+    .o_out  (gthe4_cplllock_sync)
+  );
+
+  wire gthe4_rxpmaresetdone_sync; 
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_rxpmaresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE4_RXPMARESETDONE_IN),
+    .o_out  (gthe4_rxpmaresetdone_sync)
+  );
+  
+  wire gthe4_rxprgdivresetdone_sync; 
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_rxprgdivresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE4_RXPRGDIVRESETDONE_IN),
+    .o_out  (gthe4_rxprgdivresetdone_sync)
+  );  
+
+  assign GTHE4_CPLLRESET_OUT = cpllreset_int;
+  assign GTHE4_CPLLPD_OUT = cpllpd_int;
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
+      USER_CPLLLOCK_OUT <= 1'b0;
+    else
+      USER_CPLLLOCK_OUT <= gthe4_cplllock_sync;
+  end
+
+  assign GTHE4_RXPROGDIVRESET_OUT = mask_user_in ? rxprogdivreset_int : USER_RXPROGDIVRESET_IN;
+  assign GTHE4_GTRXRESET_OUT = mask_user_in ? gtrxreset_int : USER_GTRXRESET_IN; 
+  assign GTHE4_RXOUTCLKSEL_OUT = mask_user_in ? rxoutclksel_int : USER_RXOUTCLKSEL_IN;
+  assign GTHE4_RXCDRHOLD_OUT = mask_user_in ? rxcdrhold_int : USER_RXCDRHOLD_IN;
+  assign GTHE4_RXPMARESET_OUT = mask_user_in ? 1'b0 : USER_RXPMARESET_IN; 
+  assign USER_RXPRGDIVRESETDONE_OUT = mask_user_in ? 1'b0 : GTHE4_RXPRGDIVRESETDONE_IN;
+  assign USER_RXPMARESETDONE_OUT = mask_user_in ? 1'b0 : GTHE4_RXPMARESETDONE_IN; 
+
+  // frequency counter for rxoutclk
+  wire [17:0] rxoutclk_freq_cnt;
+  reg freq_counter_rst = 1'b1;
+  wire freq_cnt_done;
+  gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_freq_counter U_RXOUTCLK_FREQ_COUNTER
+  (
+    .freq_cnt_o(rxoutclk_freq_cnt),
+    .done_o(freq_cnt_done),
+    .rst_i(freq_counter_rst),
+    .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
+    .ref_clk_i(CLK_IN),
+    .test_clk_i(rxoutclkmon)
+  );
+
+  //Debug signals
+  assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gthe4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
+  assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
+  assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
+  assign CAL_FREQ_CNT = rxoutclk_freq_cnt;
+  assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
+
+  //pragma translate_off
+  if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
+  begin: gen_sim_cpll_cal_bypass_gthe4
+    //CPLL CAL FSM for simulation
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        rxprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+        rxcdrhold_int <= 1'b0;
+        gtrxreset_int <= 1'b0;
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]: 
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X114]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X114_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X114_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end          
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_RXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_RXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_RXCDRHOLD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_RXCDRHOLD]:
+          begin
+            rxcdrhold_int <= 1'b1;
+            cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            cpllreset_int <= 1'b1;
+            freq_counter_rst <= 1'b1;
+            cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            wait_ctr <= 25'd0;
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(!gthe4_cplllock_sync) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[ASSERT_GTRXRESET]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              gtrxreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+            end
+            else begin
+              gtrxreset_int <= 1'b0;
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+
+          cpll_cal_state[WAIT_RXPMARESETDONE]:
+          begin
+            if (gthe4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+            end 
+          end  
+
+          cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT]:
+          begin
+            if (!gthe4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end 
+          end  
+          
+          cpll_cal_state[WAIT_RXPMARESETDONE_2]:
+          begin
+            if (gthe4_rxpmaresetdone_sync) begin
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end 
+          end    
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+          begin
+            if (gthe4_rxprgdivresetdone_sync) begin
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+              freq_counter_rst <= 1'b0;
+            end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_FREQ]:
+          begin
+            if(freq_cnt_done) begin
+              if ((rxoutclk_freq_cnt >= (RXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (rxoutclk_freq_cnt <= (RXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                cal_fail_store <= 1'b0;
+              end
+              else begin
+                if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                  cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+                  repeat_ctr <= repeat_ctr + 1'b1;
+                end
+                else begin
+                  cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                  cal_fail_store <= 1'b1;
+                end
+              end
+            end
+            else
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+          end
+          
+          cpll_cal_state[RESTORE_READ_X114]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X114] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x114]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+         
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gthe4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gthe4_rxprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+
+  end
+  else
+  begin: gen_cpll_cal_gthe4_rx
+  //pragma translate_on
+    //CPLL CAL FSM
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        rxprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+        rxcdrhold_int <= 1'b0;
+        gtrxreset_int <= 1'b0;        
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]: 
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X114]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X114_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X114_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end          
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_RXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_RXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_RXCDRHOLD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_RXCDRHOLD]:
+          begin
+            rxcdrhold_int <= 1'b1;
+            cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;                 
+            end
+            else begin
+              cpllpd_int <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+            end
+            else begin
+              cpllpd_int <= 1'b0;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+              freq_counter_rst <= 1'b1;
+            end
+          end 
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b1;
+              freq_counter_rst <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(wait_ctr < WAIT_CPLLLOCK) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= wait_ctr + 1'b1;
+            end
+            else begin
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[ASSERT_GTRXRESET]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              gtrxreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+            end
+            else begin
+              gtrxreset_int <= 1'b0;
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+
+          cpll_cal_state[WAIT_RXPMARESETDONE]:
+          begin
+            if (gthe4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+            end 
+          end  
+          
+          cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT]:
+          begin
+            if (!gthe4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end 
+          end  
+          
+          cpll_cal_state[WAIT_RXPMARESETDONE_2]:
+          begin
+            if (gthe4_rxpmaresetdone_sync) begin
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end 
+          end    
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+          begin
+            if (gthe4_rxprgdivresetdone_sync) begin
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+              freq_counter_rst <= 1'b0;
+            end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_FREQ]:
+          begin
+            if(freq_cnt_done) begin
+              if ((rxoutclk_freq_cnt >= (RXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (rxoutclk_freq_cnt <= (RXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                cal_fail_store <= 1'b0;
+              end
+              else begin
+                if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                  cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+                  repeat_ctr <= repeat_ctr + 1'b1;
+                end
+                else begin
+                  cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                  cal_fail_store <= 1'b1;
+                end
+              end
+            end
+            else
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+          end
+          
+          cpll_cal_state[RESTORE_READ_X114]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X114] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x114]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gthe4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gthe4_rxprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            rxcdrhold_int <= 1'b0;
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            rxcdrhold_int <= 1'b0;          
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+  
+  //pragma translate_off
+  end
+  //pragma translate_on
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET])
+      rxoutclksel_int <= 3'b0;
+    else if (cpll_cal_state[MODIFY_RXOUTCLK_SEL])
+      rxoutclksel_int <= MOD_RXOUTCLK_SEL;
+    else 
+      rxoutclksel_int <= rxoutclksel_int;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET]) begin
+      daddr <= 10'h000;
+      mask  <= 16'b1111_1111_1111_1111;
+    end
+    else if (cpll_cal_state[READ_X114] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X114] | cpll_cal_state[CLEAR_FLAG_x114]) begin 
+      daddr <= ADDR_X114;
+    end
+    else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
+      daddr <= ADDR_RX_PROGDIV_CFG;
+    end
+  end
+
+  assign drp_done = drp_state[DRP_DONE];
+  assign GTHE4_CHANNEL_DRPEN_OUT = den;
+  assign GTHE4_CHANNEL_DRPWE_OUT = dwe;
+  assign GTHE4_CHANNEL_DRPADDR_OUT = daddr;
+  assign GTHE4_CHANNEL_DRPDI_OUT = di;
+  assign drdy = GTHE4_CHANNEL_DRPRDY_IN; 
+  assign dout = GTHE4_CHANNEL_DRPDO_IN; 
+  
+  always @(posedge CLK_IN) begin
+  if (RESET_IN) begin
+    den <= 1'b0;
+    dwe <= 1'b0;
+    di <= 16'h0000;
+    drp_state <= 0;
+    drp_state[DRP_WAIT] <= 1'b1;
+  end
+  else begin
+    drp_state <= 0;
+    case (1'b1) // synthesis parallel_case full_case
+        drp_state[DRP_WAIT]:
+        begin
+          if (rd) drp_state[DRP_READ] <= 1'b1;
+          else if (wr) drp_state[DRP_WRITE] <= 1'b1;
+          else         drp_state[DRP_WAIT] <= 1'b1;
+        end
+        drp_state[DRP_READ]:
+        begin
+          den <= 1'b1;
+          drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_READ_ACK]:
+        begin
+          den <= 1'b0;
+          if (drdy == 1'b1) begin
+            if (rd) drp_state[DRP_DONE] <= 1'b1;
+            else    drp_state[DRP_MODIFY] <= 1'b1;
+          end
+          else      drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_MODIFY]:
+        begin
+          drp_state[DRP_WRITE] <= 1'b1;
+        end
+        drp_state[DRP_WRITE]:
+        begin
+          den <= 1'b1;
+          dwe <= 1'b1;
+          di <= di_msk;
+          drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_WRITE_ACK]:
+        begin
+          den <= 1'b0;
+          dwe <= 1'b0;
+          if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
+          else              drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_DONE]:
+        begin
+          drp_state[DRP_WAIT] <= 1'b1;
+        end
+    endcase
+  end
+  end 
+
+    //debug logic - convert one hot state to binary
+  genvar i,j;
+    for (j=0; j<5; j=j+1)
+    begin : jl
+      wire [32-1:0] tmp_mask;
+      for (i=0; i<32; i=i+1)
+      begin : il
+        assign tmp_mask[i] = i[j];
+      end
+      assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
+    end
+  
+end
+endgenerate
+endmodule //CPLL_CAL  
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v
new file mode 100755
index 0000000..63bedf6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v
@@ -0,0 +1,1175 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_tx # (
+  parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
+  parameter SIM_RESET_SPEEDUP     = "TRUE",
+  parameter C_FREERUN_FREQUENCY   = 100, 
+  parameter REVISION              = 2,
+  parameter C_PCIE_ENABLE         = "FALSE",
+  parameter C_PCIE_CORECLK_FREQ   = 250
+)(
+  // control signals
+  input   wire  [17:0]  TXOUTCLK_PERIOD_IN,
+  input   wire  [17:0]  CNT_TOL_IN,
+  input   wire  [15:0]  FREQ_COUNT_WINDOW_IN,
+  // User Interface
+  input   wire          RESET_IN,
+  input   wire          CLK_IN,
+  
+  input   wire  [1:0]   USER_TXPLLCLKSEL,
+  input   wire          USER_TXPROGDIVRESET_IN,
+  output  reg           USER_TXPRGDIVRESETDONE_OUT,
+  input   wire  [2:0]   USER_TXOUTCLKSEL_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CLR_IN,
+  output  reg           USER_CPLLLOCK_OUT,
+  // Debug Interface
+  output  wire          CPLL_CAL_FAIL,
+  output  wire          CPLL_CAL_DONE,
+  output  wire  [15:0]  DEBUG_OUT,
+  output  wire  [17:0]  CAL_FREQ_CNT,
+  input         [3:0]   REPEAT_RESET_LIMIT,
+  // GT Interface
+  input   wire          GTHE4_TXOUTCLK_IN,
+  input   wire          GTHE4_CPLLLOCK_IN,
+  output  wire          GTHE4_CPLLRESET_OUT,
+  output  wire          GTHE4_CPLLPD_OUT,
+  output  reg           GTHE4_TXPROGDIVRESET_OUT,
+  output  reg   [2:0]   GTHE4_TXOUTCLKSEL_OUT,
+  input   wire          GTHE4_TXPRGDIVRESETDONE_IN,
+  output  wire  [9:0]   GTHE4_CHANNEL_DRPADDR_OUT,
+  output  wire  [15:0]  GTHE4_CHANNEL_DRPDI_OUT,
+  output  wire          GTHE4_CHANNEL_DRPEN_OUT,
+  output  wire          GTHE4_CHANNEL_DRPWE_OUT,
+  input   wire          GTHE4_CHANNEL_DRPRDY_IN,
+  input   wire  [15:0]  GTHE4_CHANNEL_DRPDO_IN,
+  output  wire          DONE
+);
+
+  //DRP FSM
+  localparam DRP_WAIT      = 0;
+  localparam DRP_READ      = 1;
+  localparam DRP_READ_ACK  = 2;
+  localparam DRP_MODIFY    = 3;
+  localparam DRP_WRITE     = 4;
+  localparam DRP_WRITE_ACK = 5;
+  localparam DRP_DONE      = 6;
+
+  localparam RESET                = 0;
+  localparam READ_X0E1            = 1;
+  localparam CHECK_X0E1_STATUS    = 2;
+  localparam READ_PROGCLK_SEL     = 3;
+  localparam SAVE_PROGCLK_SEL     = 4;
+  localparam READ_X079            = 5;
+  localparam CHECK_X079_STATUS    = 6; 
+  localparam READ_PROGDIV_CFG     = 7;
+  localparam SAVE_PROGDIV_CFG     = 8;
+  localparam READ_X0E1_BEFORE_PROGCLK_SEL_MOD = 9;
+  localparam MODIFY_PROGCLK_SEL   = 10;
+  localparam MODIFY_PROGDIV       = 11; 
+  localparam MODIFY_TXOUTCLK_SEL  = 12;
+  localparam ASSERT_CPLLPD        = 13;
+  localparam DEASSERT_CPLLPD      = 14;
+  localparam ASSERT_CPLLRESET     = 15;
+  localparam DEASSERT_CPLLRESET   = 16;
+  localparam WAIT_GTCPLLLOCK      = 17;
+  localparam ASSERT_PROGDIVRESET  = 18;
+  localparam WAIT_PRGDIVRESETDONE = 19;
+  localparam CHECK_FREQ           = 20;
+  localparam RESTORE_READ_X0E1    = 21; 
+  localparam RESTORE_READ_X079    = 22;
+  localparam RESTORE_PROGDIV      = 23;
+  localparam RESTORE_PROGCLK_SEL  = 24;
+  localparam CLEAR_FLAG_x0E1      = 25; 
+  localparam CLEAR_FLAG_x079      = 26; 
+  localparam WAIT_GTCPLLLOCK2     = 27;
+  localparam ASSERT_PROGDIVRESET2 = 28;
+  localparam WAIT_PRGDIVRESETDONE2= 29;
+  localparam CAL_FAIL             = 30;
+  localparam CAL_DONE             = 31;
+  
+  reg [31:0] cpll_cal_state = 31'd0;
+  wire [4:0] cpll_cal_state_bin;
+  reg [6:0] drp_state = 7'd1;
+  wire drp_done;
+  reg [9:0] daddr = 10'd0;
+  reg [15:0] di = 16'd0;
+  wire drdy;
+  wire [15:0] dout;
+  reg den = 1'b0;
+  reg dwe = 1'b0;
+  reg wr = 1'b0;
+  reg rd = 1'b0;
+  reg [15:0] di_msk;
+  reg [15:0] mask;
+  reg [24:0] wait_ctr;
+  reg [3:0] repeat_ctr;
+  reg [15:0] progclk_sel_store = 16'd0;
+  reg [15:0] progdiv_cfg_store = 16'd0;
+  reg fboost_store = 1'b0;
+  reg mask_user_in = 1'b0;
+  reg cpllreset_int = 1'b0;
+  reg cpllpd_int = 1'b0;
+  reg txprogdivreset_int = 1'b0;
+  reg [2:0] txoutclksel_int = 3'b000;
+  reg cal_fail_store = 1'b0;
+  reg [15:0] x0e1_store = 16'd0;
+  
+  reg status_store = 1'b0;
+  wire den_i; 
+  wire dwe_i;
+  
+  //All these need to be based on CLK_IN frequency (free_run) 
+  localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY );  // 1 ms
+  localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY );         // 1 ms 
+  localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY );   // 100 us 
+
+  localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10; 
+  localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
+  localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;  
+  
+  localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
+  localparam [4:0]  WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
+  localparam [24:0] WAIT_ASSERT_CPLLRESET =
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_ASSERT_CPLLRESET;
+  localparam [4:0]  WAIT_ASSERT_CPLLPD = 5'd25;  // >= 100 ns
+  localparam [24:0] WAIT_DEASSERT_CPLLRESET =  
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_DEASSERT_CPLLRESET;
+  localparam [24:0] WAIT_CPLLLOCK = 
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
+    //pragma translate_on
+                                        SYNTH_WAIT_CPLLLOCK;
+
+
+  localparam [1:0]  MOD_PROGCLK_SEL = 2'b10;
+  localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
+  localparam [2:0]  MOD_TXOUTCLK_SEL = 3'b101;
+  localparam [9:0]  ADDR_TX_PROGCLK_SEL = 10'h00C;
+  localparam [9:0]  ADDR_TX_PROGDIV_CFG = 10'h03E;  // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
+  localparam [9:0]  ADDR_X0E1 = 10'h0E1;
+  localparam [9:0]  ADDR_X079 = 10'h079;
+
+  // Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
+  wire txoutclkmon;
+  //assign txoutclkmon = GTHE4_TXOUTCLK_IN;
+  BUFG_GT bufg_gt_txoutclkmon_inst (
+    .CE      (USER_TXOUTCLK_BUFG_CE_IN),
+    .CEMASK  (1'b1),
+    .CLR     (USER_TXOUTCLK_BUFG_CLR_IN),
+    .CLRMASK (1'b1),
+    .DIV     (3'b000),
+    .I       (GTHE4_TXOUTCLK_IN),
+    .O       (txoutclkmon)
+  );
+
+  wire gthe4_cplllock_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_cplllock_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE4_CPLLLOCK_IN),
+    .o_out  (gthe4_cplllock_sync)
+  );
+
+  wire user_txprogdivreset_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXPROGDIVRESET_IN),
+    .o_out  (user_txprogdivreset_sync)
+  );
+
+  wire gthe4_txprgdivresetdone_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTHE4_TXPRGDIVRESETDONE_IN),
+    .o_out  (gthe4_txprgdivresetdone_sync)
+  );
+  
+  wire [2:0] user_txoutclksel_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[0]),
+    .o_out  (user_txoutclksel_sync[0])
+  );
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[1]),
+    .o_out  (user_txoutclksel_sync[1])
+  );
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[2]),
+    .o_out  (user_txoutclksel_sync[2])
+  );
+
+
+  assign GTHE4_CPLLRESET_OUT = cpllreset_int;
+  assign GTHE4_CPLLPD_OUT = cpllpd_int;
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
+      USER_CPLLLOCK_OUT <= 1'b0;
+    else
+      USER_CPLLLOCK_OUT <= gthe4_cplllock_sync;
+  end
+
+  generate if (C_PCIE_ENABLE) 
+  begin : pcie_txoutclksel 
+    always @(*) begin 
+      GTHE4_TXOUTCLKSEL_OUT <= mask_user_in ? txoutclksel_int : USER_TXOUTCLKSEL_IN; 
+      GTHE4_TXPROGDIVRESET_OUT <= mask_user_in ? txprogdivreset_int : USER_TXPROGDIVRESET_IN;
+    end 
+  end 
+  else begin : non_pcie_txoutclksel
+  	always @(posedge CLK_IN) begin
+      if (mask_user_in)
+      	GTHE4_TXPROGDIVRESET_OUT <= txprogdivreset_int;
+      else
+      	GTHE4_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
+    end
+    
+    always @(posedge CLK_IN) begin
+      if (mask_user_in)
+      	GTHE4_TXOUTCLKSEL_OUT <= txoutclksel_int;
+      else
+      	GTHE4_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
+    end
+  end 
+  endgenerate
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in)
+      USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
+    else
+      USER_TXPRGDIVRESETDONE_OUT <= gthe4_txprgdivresetdone_sync;
+  end
+
+  // frequency counter for txoutclk
+  wire [17:0] txoutclk_freq_cnt;
+  reg freq_counter_rst = 1'b1;
+  wire freq_cnt_done;
+  gtwizard_ultrascale_v1_7_9_gthe4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
+  (
+    .freq_cnt_o(txoutclk_freq_cnt),
+    .done_o(freq_cnt_done),
+    .rst_i(freq_counter_rst),
+    .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
+    .ref_clk_i(CLK_IN),
+    .test_clk_i(txoutclkmon)
+  );
+
+  //Debug signals
+  assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gthe4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
+  assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
+  assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
+  assign CAL_FREQ_CNT = txoutclk_freq_cnt;
+  assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
+
+  //pragma translate_off
+  generate if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
+  begin: gen_sim_cpll_cal_bypass_gthe4
+    //CPLL CAL FSM for simulation
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        txprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]:
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X0E1]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X0E1_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X079] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGCLK_SEL]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGCLK_SEL]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[READ_X079] <= 1'b1; 
+            end 
+            else begin
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= {1'b1,progclk_sel_store[14:0]};
+          end
+          
+          cpll_cal_state[READ_X079]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_X079] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_X079_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]: 
+          begin 
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0;
+              x0e1_store <= dout;
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end 
+            else begin 
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[MODIFY_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
+          end             
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            cpllreset_int <= 1'b1;
+            freq_counter_rst <= 1'b1;
+            cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            wait_ctr <= 25'd0;
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(!gthe4_cplllock_sync) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[RESTORE_READ_X0E1]: 
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin 
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end else begin 
+              cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_READ_X079]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end 
+          end            
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[RESTORE_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]}; 
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x0E1]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000; 
+          end 
+          
+          cpll_cal_state[CLEAR_FLAG_x079]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gthe4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              txprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              txprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gthe4_txprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+
+  end
+  else
+  begin: gen_cpll_cal_gthe4
+  //pragma translate_on
+    //CPLL CAL FSM
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        txprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]:
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X0E1]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X0E1_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X079] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGCLK_SEL]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGCLK_SEL]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[READ_X079] <= 1'b1; 
+            end 
+            else begin
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= {1'b1,progclk_sel_store[14:0]};
+          end
+          
+          cpll_cal_state[READ_X079]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_X079] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_X079_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]: 
+          begin 
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0;
+              x0e1_store <= dout;
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end 
+            else begin 
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[MODIFY_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
+          end             
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;                 
+            end
+            else begin
+              cpllpd_int <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+            end
+            else begin
+              cpllpd_int <= 1'b0;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+              freq_counter_rst <= 1'b1;
+            end
+          end 
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b1;
+              freq_counter_rst <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(wait_ctr < WAIT_CPLLLOCK) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= wait_ctr + 1'b1;
+            end
+            else begin
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              txprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin
+              txprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+          begin
+            if (gthe4_txprgdivresetdone_sync) begin
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+              freq_counter_rst <= 1'b0;
+            end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_FREQ]:
+          begin
+            if(freq_cnt_done) begin
+              if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
+                cal_fail_store <= 1'b0;
+              end
+              else begin
+                if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                  cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+                  repeat_ctr <= repeat_ctr + 1'b1;
+                end
+                else begin
+                  cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
+                  cal_fail_store <= 1'b1;
+                end
+              end
+            end
+            else
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+          end
+          
+          cpll_cal_state[RESTORE_READ_X0E1]: 
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin 
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end else begin 
+              cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_READ_X079]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end 
+          end            
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[RESTORE_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]}; 
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x0E1]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000; 
+          end 
+          
+          cpll_cal_state[CLEAR_FLAG_x079]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gthe4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              txprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              txprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gthe4_txprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+  
+  //pragma translate_off
+  end
+  endgenerate
+  //pragma translate_on
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET])
+      txoutclksel_int <= 3'b0;
+    else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
+      txoutclksel_int <= MOD_TXOUTCLK_SEL;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET]) begin
+      daddr <= 10'h000;
+      mask  <= 16'b1111_1111_1111_1111;
+    end
+    else if (cpll_cal_state[READ_X0E1] | cpll_cal_state[SAVE_PROGCLK_SEL] | cpll_cal_state[RESTORE_READ_X0E1] | cpll_cal_state[CLEAR_FLAG_x0E1] | cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]) begin 
+      daddr <= ADDR_X0E1;
+    end 
+    else if (cpll_cal_state[READ_X079] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X079] | cpll_cal_state[CLEAR_FLAG_x079]) begin 
+      daddr <= ADDR_X079;
+    end 
+    else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
+      daddr <= ADDR_TX_PROGCLK_SEL;
+    end
+    else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
+      daddr <= ADDR_TX_PROGDIV_CFG;
+    end
+  
+  end
+  
+  assign drp_done = drp_state[DRP_DONE];
+  assign GTHE4_CHANNEL_DRPEN_OUT = den;
+  assign GTHE4_CHANNEL_DRPWE_OUT = dwe;
+  assign GTHE4_CHANNEL_DRPADDR_OUT = daddr;
+  assign GTHE4_CHANNEL_DRPDI_OUT = di;
+  assign drdy = GTHE4_CHANNEL_DRPRDY_IN; 
+  assign dout = GTHE4_CHANNEL_DRPDO_IN;   
+  
+  always @(posedge CLK_IN or posedge RESET_IN) begin
+  if (RESET_IN) begin
+    den <= 1'b0;
+    dwe <= 1'b0;
+    di <= 16'h0000;
+    drp_state <= 0;
+    drp_state[DRP_WAIT] <= 1'b1;
+  end
+  else begin
+    drp_state <= 0;
+    case (1'b1) // synthesis parallel_case full_case
+        drp_state[DRP_WAIT]:
+        begin
+          if (rd) drp_state[DRP_READ] <= 1'b1;
+          else if (wr) drp_state[DRP_WRITE] <= 1'b1;
+          else         drp_state[DRP_WAIT] <= 1'b1;
+        end
+        drp_state[DRP_READ]:
+        begin
+          den <= 1'b1;
+          drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_READ_ACK]:
+        begin
+          den <= 1'b0;
+          if (drdy == 1'b1) begin
+            if (rd) drp_state[DRP_DONE] <= 1'b1;
+            else    drp_state[DRP_MODIFY] <= 1'b1;
+          end
+          else      drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_MODIFY]:
+        begin
+          drp_state[DRP_WRITE] <= 1'b1;
+        end
+        drp_state[DRP_WRITE]:
+        begin
+          den <= 1'b1;
+          dwe <= 1'b1;
+          di <= di_msk;
+          drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_WRITE_ACK]:
+        begin
+          den <= 1'b0;
+          dwe <= 1'b0;
+          if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
+          else              drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_DONE]:
+        begin
+          drp_state[DRP_WAIT] <= 1'b1;
+        end
+    endcase
+  end
+  end
+  
+  //debug logic - convert one hot state to binary
+  genvar i,j;
+  generate
+    for (j=0; j<5; j=j+1)
+    begin : jl
+      wire [32-1:0] tmp_mask;
+      for (i=0; i<32; i=i+1)
+      begin : il
+        assign tmp_mask[i] = i[j];
+      end
+      assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
+    end
+  endgenerate
+  
+endmodule //CPLL_CAL  
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v
new file mode 100755
index 0000000..7276607
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v
@@ -0,0 +1,170 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_delay_powergood # (
+  parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
+  parameter C_PCIE_ENABLE = "FALSE"
+)(
+  input wire GT_RXOUTCLKPCS,
+
+  input wire GT_GTPOWERGOOD,
+  input wire [2:0] USER_RXRATE,
+  input wire USER_RXRATEMODE,
+  input wire USER_GTRXRESET,
+  input wire USER_RXPMARESET,
+  input wire [1:0] USER_RXPD,
+
+  output wire USER_GTPOWERGOOD,
+  output wire [2:0] GT_RXRATE,
+  output wire GT_RXRATEMODE,
+  output wire GT_GTRXRESET,
+  output wire GT_RXPMARESET,
+  output wire [1:0] GT_RXPD
+);
+
+generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
+begin : gen_powergood_nodelay
+  assign GT_RXPD          = USER_RXPD;
+  assign GT_GTRXRESET     = USER_GTRXRESET;
+  assign GT_RXPMARESET    = USER_RXPMARESET;
+  assign GT_RXRATE        = USER_RXRATE;
+  assign GT_RXRATEMODE    = USER_RXRATEMODE;
+  assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
+end
+else
+begin: gen_powergood_delay
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [8:0] wait_cnt;
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
+  wire intclk_rrst_n;
+  
+  //--------------------------------------------------------------------------
+  //  POWER ON FSM Encoding
+  //-------------------------------------------------------------------------- 
+  localparam PWR_ON_WAIT_CNT           = 4'd0;
+  localparam PWR_ON_DONE               = 4'd1; 
+  
+  //--------------------------------------------------------------------------------------------------
+  //  Reset Synchronizer
+  //--------------------------------------------------------------------------------------------------
+  always @ (posedge GT_RXOUTCLKPCS or negedge GT_GTPOWERGOOD)
+  begin
+      if (!GT_GTPOWERGOOD)
+          intclk_rrst_n_r <= 5'd0;
+      else if(!int_pwr_on_fsm)
+          intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1}; 
+  end
+
+  assign intclk_rrst_n = intclk_rrst_n_r[4];
+
+  //--------------------------------------------------------------------------------------------------
+  //  Wait counter 
+  //--------------------------------------------------------------------------------------------------
+  always @ (posedge GT_RXOUTCLKPCS)
+  begin
+    if (!intclk_rrst_n)
+    	wait_cnt <= 9'd0;
+    else begin
+    	if (int_pwr_on_fsm == PWR_ON_WAIT_CNT)
+    		wait_cnt <= {wait_cnt[7:0],1'b1};
+    	else
+    		wait_cnt <= wait_cnt;
+    end
+  end
+
+  //--------------------------------------------------------------------------------------------------
+  // Power On FSM
+  //--------------------------------------------------------------------------------------------------
+
+  always @ (posedge GT_RXOUTCLKPCS or negedge GT_GTPOWERGOOD)
+  begin
+    if (!GT_GTPOWERGOOD)
+    begin
+      int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
+    end
+    else begin
+      case (int_pwr_on_fsm)
+        PWR_ON_WAIT_CNT :
+          begin
+            int_pwr_on_fsm <= (wait_cnt[7] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
+          end 
+
+        PWR_ON_DONE :
+          begin
+            int_pwr_on_fsm <= PWR_ON_DONE;
+          end
+
+        default :
+        begin
+          int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
+        end
+      endcase
+    end
+  end
+
+  always @(posedge GT_RXOUTCLKPCS)
+    pwr_on_fsm <= int_pwr_on_fsm;
+
+  assign GT_RXPD          = pwr_on_fsm ? USER_RXPD : 2'b11;
+  assign GT_GTRXRESET     = pwr_on_fsm ? USER_GTRXRESET : !GT_GTPOWERGOOD;
+  assign GT_RXPMARESET    = pwr_on_fsm ? USER_RXPMARESET : 1'b0;
+  assign GT_RXRATE        = pwr_on_fsm ? USER_RXRATE : 3'b001;
+  assign GT_RXRATEMODE    = pwr_on_fsm ? USER_RXRATEMODE : 1'b1;
+  assign USER_GTPOWERGOOD = pwr_on_fsm; 
+
+end
+endgenerate
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v
new file mode 100755
index 0000000..55c3e05
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v
@@ -0,0 +1,245 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_buffbypass_rx #(
+
+  parameter integer P_BUFFER_BYPASS_MODE       = 0,
+  parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
+  parameter integer P_MASTER_CHANNEL_POINTER   = 0
+
+)(
+
+  // User interface ports
+  input  wire gtwiz_buffbypass_rx_clk_in,
+  input  wire gtwiz_buffbypass_rx_reset_in,
+  input  wire gtwiz_buffbypass_rx_start_user_in,
+  input  wire gtwiz_buffbypass_rx_resetdone_in,
+  output reg  gtwiz_buffbypass_rx_done_out  = 1'b0,
+  output reg  gtwiz_buffbypass_rx_error_out = 1'b0,
+
+  // Transceiver interface ports
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphaligndone_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlysresetdone_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncout_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncdone_in,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphdlyreset_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphalign_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphalignen_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphdlypd_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphovrden_out,
+  output reg  [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}},
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlybypass_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlyen_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlyovrden_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncmode_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncallin_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncin_out
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Receiver buffer bypass conditional generation, based on parameter values in module instantiation
+  // -------------------------------------------------------------------------------------------------------------------
+  localparam [1:0] ST_BUFFBYPASS_RX_IDLE                 = 2'd0;
+  localparam [1:0] ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET = 2'd1;
+  localparam [1:0] ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE      = 2'd2;
+  localparam [1:0] ST_BUFFBYPASS_RX_DONE                 = 2'd3;
+
+  generate if (1) begin: gen_gtwiz_buffbypass_rx_main
+
+    // Use auto mode buffer bypass
+    if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode
+
+      // For single-lane auto mode buffer bypass, perform specified input port tie-offs
+      if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan
+        assign rxphdlyreset_out = 1'b0;
+        assign rxphalign_out    = 1'b0;
+        assign rxphalignen_out  = 1'b0;
+        assign rxphdlypd_out    = 1'b0;
+        assign rxphovrden_out   = 1'b0;
+        assign rxdlybypass_out  = 1'b0;
+        assign rxdlyen_out      = 1'b0;
+        assign rxdlyovrden_out  = 1'b0;
+        assign rxsyncmode_out   = 1'b1;
+        assign rxsyncallin_out  = rxphaligndone_in;
+        assign rxsyncin_out     = 1'b0;
+      end
+
+      // For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs
+      else begin : gen_assign_multi_chan
+        assign rxphdlyreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxphalign_out    = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxphalignen_out  = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxphdlypd_out    = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxphovrden_out   = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxdlybypass_out  = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxdlyen_out      = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign rxdlyovrden_out  = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+
+        genvar gi;
+        for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_rxsyncmode
+          if (gi == P_MASTER_CHANNEL_POINTER)
+            assign rxsyncmode_out[gi] = 1'b1;
+          else
+            assign rxsyncmode_out[gi] = 1'b0;
+        end
+
+        assign rxsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&rxphaligndone_in}};
+        assign rxsyncin_out    = {P_TOTAL_NUMBER_OF_CHANNELS{rxsyncout_in[P_MASTER_CHANNEL_POINTER]}};
+      end
+
+      // Detect the rising edge of the receiver reset done re-synchronized input. Assign an internal buffer bypass
+      // start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
+      wire gtwiz_buffbypass_rx_resetdone_sync_int;
+
+      gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
+        .clk_in  (gtwiz_buffbypass_rx_clk_in),
+        .rst_in  (gtwiz_buffbypass_rx_resetdone_in),
+        .rst_out (gtwiz_buffbypass_rx_resetdone_sync_int)
+      );
+
+      reg  gtwiz_buffbypass_rx_resetdone_reg = 1'b0;
+      wire gtwiz_buffbypass_rx_start_int;
+
+      always @(posedge gtwiz_buffbypass_rx_clk_in) begin
+        if (gtwiz_buffbypass_rx_reset_in)
+          gtwiz_buffbypass_rx_resetdone_reg <= 1'b0;
+        else
+          gtwiz_buffbypass_rx_resetdone_reg <= gtwiz_buffbypass_rx_resetdone_sync_int;
+      end
+
+      assign gtwiz_buffbypass_rx_start_int = (gtwiz_buffbypass_rx_resetdone_sync_int &&
+                                             ~gtwiz_buffbypass_rx_resetdone_reg) || gtwiz_buffbypass_rx_start_user_in;
+
+      // Synchronize the master channel's buffer bypass completion output (RXSYNCDONE) into the local clock domain
+      // and detect its rising edge for purposes of safe state machine transitions
+      reg  gtwiz_buffbypass_rx_master_syncdone_sync_reg = 1'b0;
+      wire gtwiz_buffbypass_rx_master_syncdone_sync_int;
+      wire gtwiz_buffbypass_rx_master_syncdone_sync_re;
+
+      gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_mastersyncdone_inst (
+        .clk_in (gtwiz_buffbypass_rx_clk_in),
+        .i_in   (rxsyncdone_in[P_MASTER_CHANNEL_POINTER]),
+        .o_out  (gtwiz_buffbypass_rx_master_syncdone_sync_int)
+      );
+
+      always @(posedge gtwiz_buffbypass_rx_clk_in)
+        gtwiz_buffbypass_rx_master_syncdone_sync_reg <= gtwiz_buffbypass_rx_master_syncdone_sync_int;
+
+      assign gtwiz_buffbypass_rx_master_syncdone_sync_re = gtwiz_buffbypass_rx_master_syncdone_sync_int &&
+                                                          ~gtwiz_buffbypass_rx_master_syncdone_sync_reg;
+
+      // Synchronize the master channel's phase alignment completion output (RXPHALIGNDONE) into the local clock domain
+      wire gtwiz_buffbypass_rx_master_phaligndone_sync_int;
+
+      gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_masterphaligndone_inst (
+        .clk_in (gtwiz_buffbypass_rx_clk_in),
+        .i_in   (rxphaligndone_in[P_MASTER_CHANNEL_POINTER]),
+        .o_out  (gtwiz_buffbypass_rx_master_phaligndone_sync_int)
+      );
+
+      // Implement a simple state machine to perform the receiver auto mode buffer bypass procedure
+      reg [1:0] sm_buffbypass_rx = ST_BUFFBYPASS_RX_IDLE;
+
+      always @(posedge gtwiz_buffbypass_rx_clk_in) begin
+        if (gtwiz_buffbypass_rx_reset_in) begin
+          gtwiz_buffbypass_rx_done_out  <= 1'b0;
+          gtwiz_buffbypass_rx_error_out <= 1'b0;
+          rxdlysreset_out               <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+          sm_buffbypass_rx              <= ST_BUFFBYPASS_RX_IDLE;
+        end
+        else begin
+          case (sm_buffbypass_rx)
+
+            // Upon assertion of the internal buffer bypass start signal, assert RXDLYSRESET output(s)
+            default: begin
+              if (gtwiz_buffbypass_rx_start_int) begin
+                gtwiz_buffbypass_rx_done_out  <= 1'b0;
+                gtwiz_buffbypass_rx_error_out <= 1'b0;
+                rxdlysreset_out               <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}};
+                sm_buffbypass_rx              <= ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET;
+              end
+            end
+
+            // De-assert the RXDLYSRESET output(s)
+            ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET: begin
+              rxdlysreset_out  <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+              sm_buffbypass_rx <= ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE;
+            end
+
+            // Upon assertion of the synchronized RXSYNCDONE indicator, transition to the final state
+            ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE: begin
+              if (gtwiz_buffbypass_rx_master_syncdone_sync_re)
+                sm_buffbypass_rx <= ST_BUFFBYPASS_RX_DONE;
+            end
+
+            // Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the
+            // synchronized RXPHALIGNDONE indicator is not high
+            ST_BUFFBYPASS_RX_DONE: begin
+              gtwiz_buffbypass_rx_done_out  <= 1'b1;
+              gtwiz_buffbypass_rx_error_out <= ~gtwiz_buffbypass_rx_master_phaligndone_sync_int;
+              sm_buffbypass_rx              <= ST_BUFFBYPASS_RX_IDLE;
+            end
+
+          endcase
+        end
+      end
+
+    end
+  end
+  endgenerate
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v
new file mode 100755
index 0000000..474e639
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v
@@ -0,0 +1,258 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_buffbypass_tx #(
+
+  parameter integer P_BUFFER_BYPASS_MODE       = 0,
+  parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
+  parameter integer P_MASTER_CHANNEL_POINTER   = 0
+
+)(
+
+  // User interface ports
+  input  wire gtwiz_buffbypass_tx_clk_in,
+  input  wire gtwiz_buffbypass_tx_reset_in,
+  input  wire gtwiz_buffbypass_tx_start_user_in,
+  input  wire gtwiz_buffbypass_tx_resetdone_in,
+  output reg  gtwiz_buffbypass_tx_done_out  = 1'b0,
+  output reg  gtwiz_buffbypass_tx_error_out = 1'b0,
+
+  // Transceiver interface ports
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphaligndone_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinitdone_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysresetdone_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncout_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncdone_in,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlyreset_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalign_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalignen_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlypd_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinit_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphovrden_out,
+  output reg  [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}},
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlybypass_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyen_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyovrden_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlytstclk_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyhold_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyupdown_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncmode_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncallin_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncin_out
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Transmitter buffer bypass conditional generation, based on parameter values in module instantiation
+  // -------------------------------------------------------------------------------------------------------------------
+  localparam [1:0] ST_BUFFBYPASS_TX_IDLE                 = 2'd0;
+  localparam [1:0] ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET = 2'd1;
+  localparam [1:0] ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE      = 2'd2;
+  localparam [1:0] ST_BUFFBYPASS_TX_DONE                 = 2'd3;
+
+  generate if (1) begin: gen_gtwiz_buffbypass_tx_main
+
+    // Use auto mode buffer bypass
+    if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode
+
+      // For single-lane auto mode buffer bypass, perform specified input port tie-offs
+      if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan
+        assign txphdlyreset_out  = 1'b0;
+        assign txphalign_out     = 1'b0;
+        assign txphalignen_out   = 1'b0;
+        assign txphdlypd_out     = 1'b0;
+        assign txphinit_out      = 1'b0;
+        assign txphovrden_out    = 1'b0;
+        assign txdlybypass_out   = 1'b0;
+        assign txdlyen_out       = 1'b0;
+        assign txdlyovrden_out   = 1'b0;
+        assign txphdlytstclk_out = 1'b0;
+        assign txdlyhold_out     = 1'b0;
+        assign txdlyupdown_out   = 1'b0;
+        assign txsyncmode_out    = 1'b1;
+        assign txsyncallin_out   = txphaligndone_in;
+        assign txsyncin_out      = 1'b0;
+      end
+
+      // For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs
+      else begin : gen_assign_multi_chan
+        assign txphdlyreset_out  = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txphalign_out     = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txphalignen_out   = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txphdlypd_out     = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txphinit_out      = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txphovrden_out    = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txdlybypass_out   = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txdlyen_out       = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txdlyovrden_out   = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txphdlytstclk_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txdlyhold_out     = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+        assign txdlyupdown_out   = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+
+        genvar gi;
+        for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_txsyncmode
+          if (gi == P_MASTER_CHANNEL_POINTER)
+            assign txsyncmode_out[gi] = 1'b1;
+          else
+            assign txsyncmode_out[gi] = 1'b0;
+        end
+
+        assign txsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&txphaligndone_in}};
+        assign txsyncin_out    = {P_TOTAL_NUMBER_OF_CHANNELS{txsyncout_in[P_MASTER_CHANNEL_POINTER]}};
+      end
+
+      // Detect the rising edge of the transmitter reset done re-synchronized input. Assign an internal buffer bypass
+      // start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
+      wire gtwiz_buffbypass_tx_resetdone_sync_int;
+
+      gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
+        .clk_in  (gtwiz_buffbypass_tx_clk_in),
+        .rst_in  (gtwiz_buffbypass_tx_resetdone_in),
+        .rst_out (gtwiz_buffbypass_tx_resetdone_sync_int)
+      );
+
+      reg  gtwiz_buffbypass_tx_resetdone_reg = 1'b0;
+      wire gtwiz_buffbypass_tx_start_int;
+
+      always @(posedge gtwiz_buffbypass_tx_clk_in) begin
+        if (gtwiz_buffbypass_tx_reset_in)
+          gtwiz_buffbypass_tx_resetdone_reg <= 1'b0;
+        else
+          gtwiz_buffbypass_tx_resetdone_reg <= gtwiz_buffbypass_tx_resetdone_sync_int;
+      end
+
+      assign gtwiz_buffbypass_tx_start_int = (gtwiz_buffbypass_tx_resetdone_sync_int &&
+                                             ~gtwiz_buffbypass_tx_resetdone_reg) || gtwiz_buffbypass_tx_start_user_in;
+
+      // Synchronize the master channel's buffer bypass completion output (TXSYNCDONE) into the local clock domain
+      // and detect its rising edge for purposes of safe state machine transitions
+      reg  gtwiz_buffbypass_tx_master_syncdone_sync_reg = 1'b0;
+      wire gtwiz_buffbypass_tx_master_syncdone_sync_int;
+      wire gtwiz_buffbypass_tx_master_syncdone_sync_re;
+
+      gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_master_syncdone_inst (
+        .clk_in (gtwiz_buffbypass_tx_clk_in),
+        .i_in   (txsyncdone_in[P_MASTER_CHANNEL_POINTER]),
+        .o_out  (gtwiz_buffbypass_tx_master_syncdone_sync_int)
+      );
+
+      always @(posedge gtwiz_buffbypass_tx_clk_in)
+        gtwiz_buffbypass_tx_master_syncdone_sync_reg <= gtwiz_buffbypass_tx_master_syncdone_sync_int;
+
+      assign gtwiz_buffbypass_tx_master_syncdone_sync_re = gtwiz_buffbypass_tx_master_syncdone_sync_int &&
+                                                          ~gtwiz_buffbypass_tx_master_syncdone_sync_reg;
+
+      // Synchronize the master channel's phase alignment completion output (TXPHALIGNDONE) into the local clock domain
+      wire gtwiz_buffbypass_tx_master_phaligndone_sync_int;
+
+      gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_master_phaligndone_inst (
+        .clk_in (gtwiz_buffbypass_tx_clk_in),
+        .i_in   (txphaligndone_in[P_MASTER_CHANNEL_POINTER]),
+        .o_out  (gtwiz_buffbypass_tx_master_phaligndone_sync_int)
+      );
+
+      // Implement a simple state machine to perform the transmitter auto mode buffer bypass procedure
+      reg [1:0] sm_buffbypass_tx = ST_BUFFBYPASS_TX_IDLE;
+
+      always @(posedge gtwiz_buffbypass_tx_clk_in) begin
+        if (gtwiz_buffbypass_tx_reset_in) begin
+          gtwiz_buffbypass_tx_done_out  <= 1'b0;
+          gtwiz_buffbypass_tx_error_out <= 1'b0;
+          txdlysreset_out               <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+          sm_buffbypass_tx              <= ST_BUFFBYPASS_TX_IDLE;
+        end
+        else begin
+          case (sm_buffbypass_tx)
+
+            // Upon assertion of the internal buffer bypass start signal, assert TXDLYSRESET output(s)
+            default: begin
+              if (gtwiz_buffbypass_tx_start_int) begin
+                gtwiz_buffbypass_tx_done_out  <= 1'b0;
+                gtwiz_buffbypass_tx_error_out <= 1'b0;
+                txdlysreset_out               <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}};
+                sm_buffbypass_tx              <= ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET;
+              end
+            end
+
+            // De-assert the TXDLYSRESET output(s)
+            ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET: begin
+              txdlysreset_out  <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
+              sm_buffbypass_tx <= ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE;
+            end
+
+            // Upon assertion of the synchronized TXSYNCDONE indicator, transition to the final state
+            ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE: begin
+              if (gtwiz_buffbypass_tx_master_syncdone_sync_re)
+                sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DONE;
+            end
+
+            // Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the
+            // synchronized TXPHALIGNDONE indicator is not high
+            ST_BUFFBYPASS_TX_DONE: begin
+              gtwiz_buffbypass_tx_done_out  <= 1'b1;
+              gtwiz_buffbypass_tx_error_out <= ~gtwiz_buffbypass_tx_master_phaligndone_sync_int;
+              sm_buffbypass_tx              <= ST_BUFFBYPASS_TX_IDLE;
+            end
+
+          endcase
+        end
+      end
+
+    end
+  end
+  endgenerate
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v
new file mode 100755
index 0000000..14f9243
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v
@@ -0,0 +1,766 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_reset # (
+
+  parameter real    P_FREERUN_FREQUENCY       = 200,
+  parameter integer P_USE_CPLL_CAL            = 0,
+  parameter integer P_TX_PLL_TYPE             = 0,
+  parameter integer P_RX_PLL_TYPE             = 0,
+  parameter real    P_RX_LINE_RATE            = 10.3125,
+  parameter [25:0]  P_CDR_TIMEOUT_FREERUN_CYC = (37000 * P_FREERUN_FREQUENCY) / P_RX_LINE_RATE
+
+)(
+
+  // User interface ports
+  input  wire gtwiz_reset_clk_freerun_in,
+  input  wire gtwiz_reset_all_in,
+  input  wire gtwiz_reset_tx_pll_and_datapath_in,
+  input  wire gtwiz_reset_tx_datapath_in,
+  input  wire gtwiz_reset_rx_pll_and_datapath_in,
+  input  wire gtwiz_reset_rx_datapath_in,
+  output wire gtwiz_reset_rx_cdr_stable_out,
+  output wire gtwiz_reset_tx_done_out,
+  output wire gtwiz_reset_rx_done_out,
+  input  wire gtwiz_reset_userclk_tx_active_in,
+  input  wire gtwiz_reset_userclk_rx_active_in,
+
+  // Transceiver interface ports
+  input  wire gtpowergood_in,
+  input  wire txusrclk2_in,
+  input  wire plllock_tx_in,
+  input  wire txresetdone_in,
+  input  wire rxusrclk2_in,
+  input  wire plllock_rx_in,
+  input  wire rxcdrlock_in,
+  input  wire rxresetdone_in,
+  output reg  pllreset_tx_out    = 1'b1,
+  output wire txprogdivreset_out,
+  output reg  gttxreset_out      = 1'b1,
+  output reg  txuserrdy_out      = 1'b0,
+  output reg  pllreset_rx_out,
+  output reg  rxprogdivreset_out = 1'b1,
+  output reg  gtrxreset_out      = 1'b1,
+  output reg  rxuserrdy_out      = 1'b0,
+
+  // Tie-offs based on core configuration
+  input  wire tx_enabled_tie_in,
+  input  wire rx_enabled_tie_in,
+  input  wire shared_pll_tie_in
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // "Reset all" state machine
+  // -------------------------------------------------------------------------------------------------------------------
+
+  // The "reset all" state machine responds to the synchronized gtwiz_reset_all_in input by resetting the enabled PLLs
+  // and data paths of those transceiver resources to which the reset helper block is connected. It does so by guiding
+  // the independent transmitter and receiver reset state machines, which are also user-accessible. The path through the
+  // "reset all" state machine is a function of module input tie-offs, which depend on the core configuration.
+
+  // Synchronize the "reset all" input signal into the free-running clock domain
+  wire gtwiz_reset_all_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_all_in),
+    .rst_out (gtwiz_reset_all_sync)
+  );
+
+  // Synchronize the transceiver power good indicator
+  wire gtpowergood_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtpowergood_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtpowergood_in),
+    .o_out  (gtpowergood_sync)
+  );
+
+  // Declare the "reset all" state machine reset timer registers
+  reg       sm_reset_all_timer_clr = 1'b1;
+  reg [2:0] sm_reset_all_timer_ctr = 3'd0;
+  reg       sm_reset_all_timer_sat = 1'b0;
+
+  // Declare local parameters used to represent both static and variable state machine state values
+  localparam [2:0] ST_RESET_ALL_INIT        = 3'd0;
+  localparam [2:0] ST_RESET_ALL_BRANCH      = 3'd1;
+  localparam [2:0] ST_RESET_ALL_TX_PLL      = 3'd2;
+  localparam [2:0] ST_RESET_ALL_TX_PLL_WAIT = 3'd3;
+  localparam [2:0] ST_RESET_ALL_RX_DP       = 3'd4;
+  localparam [2:0] ST_RESET_ALL_RX_PLL      = 3'd5;
+  localparam [2:0] ST_RESET_ALL_RX_WAIT     = 3'd6;
+  localparam [2:0] ST_RESET_ALL_DONE        = 3'd7;
+  reg        [2:0] sm_reset_all             = ST_RESET_ALL_INIT;
+
+  // Declare relevant internal control and status registers of this and other state machines
+  reg gtwiz_reset_tx_pll_and_datapath_int = 1'b0;
+  reg gtwiz_reset_tx_done_int             = 1'b0;
+  reg gtwiz_reset_rx_pll_and_datapath_int = 1'b0;
+  reg gtwiz_reset_rx_datapath_int         = 1'b0;
+  reg gtwiz_reset_rx_done_int             = 1'b0;
+
+  // Implement the "reset all" state machine control and its outputs as a single sequential process. The state machine
+  // is reset by the synchronized gtwiz_reset_all_sync input.
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (gtwiz_reset_all_sync) begin
+      gtwiz_reset_tx_pll_and_datapath_int <= 1'b0;
+      gtwiz_reset_rx_pll_and_datapath_int <= 1'b0;
+      gtwiz_reset_rx_datapath_int         <= 1'b0;
+      sm_reset_all_timer_clr              <= 1'b1;
+      sm_reset_all                        <= ST_RESET_ALL_BRANCH;
+    end
+    else begin
+      case (sm_reset_all)
+
+        // Upon initial configuration, check or wait for the transceiver power good indicator to be asserted before
+        // proceeding with the sequence automatically
+        ST_RESET_ALL_INIT: begin
+          if (gtpowergood_sync)
+            sm_reset_all <= ST_RESET_ALL_BRANCH;
+        end
+
+        // If the transmitter is enabled, begin by resetting the TX PLL. If the transmitter is disabled, begin by
+        // resetting the RX PLL.
+        ST_RESET_ALL_BRANCH: begin
+          if (tx_enabled_tie_in)
+            sm_reset_all <= ST_RESET_ALL_TX_PLL;
+          else
+            sm_reset_all <= ST_RESET_ALL_RX_PLL;
+          sm_reset_all_timer_clr <= 1'b1;
+        end
+
+        // Force the transmitter reset state machine to reset the TX PLL and data path
+        ST_RESET_ALL_TX_PLL: begin
+          gtwiz_reset_tx_pll_and_datapath_int <= 1'b1;
+          sm_reset_all                        <= ST_RESET_ALL_TX_PLL_WAIT;
+        end
+
+        // Await completion of the TX PLL and data path reset sequence. Then, if the receiver is enabled, continue by
+        // either resetting just the RX data path (if the receiver and transmitter share a PLL) or the RX PLL (if the
+        // receiver and transmitter PLLs are indepdendent). If the receiver is disabled, complete the sequence.
+        ST_RESET_ALL_TX_PLL_WAIT: begin
+          gtwiz_reset_tx_pll_and_datapath_int <= 1'b0;
+          sm_reset_all_timer_clr              <= 1'b0;
+          if (gtwiz_reset_tx_done_int && (~sm_reset_all_timer_clr) && sm_reset_all_timer_sat) begin
+            if (rx_enabled_tie_in) begin
+              if (shared_pll_tie_in)
+                sm_reset_all <= ST_RESET_ALL_RX_DP;
+              else
+                sm_reset_all <= ST_RESET_ALL_RX_PLL;
+            end
+            else
+              sm_reset_all <= ST_RESET_ALL_DONE;
+            sm_reset_all_timer_clr <= 1'b1;
+          end
+        end
+
+        // Force the receiver reset state machine to reset the RX data path
+        ST_RESET_ALL_RX_DP: begin
+          gtwiz_reset_rx_datapath_int <= 1'b1;
+          sm_reset_all                <= ST_RESET_ALL_RX_WAIT;
+        end
+
+        // Force the receiver reset state machine to reset the RX PLL and data path
+        ST_RESET_ALL_RX_PLL: begin
+          gtwiz_reset_rx_pll_and_datapath_int <= 1'b1;
+          sm_reset_all                        <= ST_RESET_ALL_RX_WAIT;
+        end
+
+        // Await completion of whichever RX reset sequence was performed
+        ST_RESET_ALL_RX_WAIT: begin
+          gtwiz_reset_rx_datapath_int         <= 1'b0;
+          sm_reset_all_timer_clr              <= 1'b0;
+          gtwiz_reset_rx_pll_and_datapath_int <= 1'b0;
+          if (gtwiz_reset_rx_done_int && (~sm_reset_all_timer_clr) && sm_reset_all_timer_sat) begin
+            sm_reset_all           <= ST_RESET_ALL_DONE;
+            sm_reset_all_timer_clr <= 1'b1;
+          end
+        end
+
+      endcase
+    end
+  end
+
+  // Generate a small "reset all" state machine reset timer, used to stall certain states to guarantee that their
+  // synchronized input values are being used at the appropriate time
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (sm_reset_all_timer_clr) begin
+      sm_reset_all_timer_ctr <= 3'd0;
+      sm_reset_all_timer_sat <= 1'b0;
+    end
+    else begin
+      if (sm_reset_all_timer_ctr != 3'd7)
+        sm_reset_all_timer_ctr <= sm_reset_all_timer_ctr + 3'd1;
+      else
+        sm_reset_all_timer_sat <= 1'b1;
+    end
+  end
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Transmitter reset state machine
+  // -------------------------------------------------------------------------------------------------------------------
+
+  // The transmitter reset state machine responds to various synchronized inputs by resetting enabled transmitter-
+  // related transceiver resources to which the reset helper block is connected. Various entry points to the sequential
+  // reset sequence are available.
+
+  // Synchronize the OR of all user input and internal TX reset signals for use in resetting the TX reset state machine
+  wire gtwiz_reset_tx_any;
+  wire gtwiz_reset_tx_any_sync;
+  assign gtwiz_reset_tx_any = gtwiz_reset_tx_pll_and_datapath_in  ||
+                              gtwiz_reset_tx_pll_and_datapath_int ||
+                              gtwiz_reset_tx_datapath_in;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_any_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_tx_any),
+    .rst_out (gtwiz_reset_tx_any_sync)
+  );
+
+  // Synchronize the OR of the user input and internal TX PLL and data path reset signals
+  wire gtwiz_reset_tx_pll_and_datapath_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_tx_pll_and_datapath_in || gtwiz_reset_tx_pll_and_datapath_int),
+    .rst_out (gtwiz_reset_tx_pll_and_datapath_sync)
+  );
+
+  // Use another synchronizer to delay the above signal for purposes of its detection following reset
+  wire gtwiz_reset_tx_pll_and_datapath_dly;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtwiz_reset_tx_pll_and_datapath_sync),
+    .o_out  (gtwiz_reset_tx_pll_and_datapath_dly)
+  );
+
+  // Synchronize the TX data path reset user input
+  wire gtwiz_reset_tx_datapath_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_datapath_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_tx_datapath_in),
+    .rst_out (gtwiz_reset_tx_datapath_sync)
+  );
+
+  // Use another synchronizer to delay the above signal for purposes of its detection following reset
+  wire gtwiz_reset_tx_datapath_dly;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtwiz_reset_tx_datapath_sync),
+    .o_out  (gtwiz_reset_tx_datapath_dly)
+  );
+
+  // Synchronize the TX user clock active indicator
+  wire gtwiz_reset_userclk_tx_active_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtwiz_reset_userclk_tx_active_in),
+    .o_out  (gtwiz_reset_userclk_tx_active_sync)
+  );
+
+  // Synchronize the TX PLL lock indicator
+  wire plllock_tx_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_plllock_tx_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (plllock_tx_in),
+    .o_out  (plllock_tx_sync)
+  );
+
+  // Declare the TX state machine reset timer registers
+  reg       sm_reset_tx_timer_clr = 1'b1;
+  reg [2:0] sm_reset_tx_timer_ctr = 3'd0;
+  reg       sm_reset_tx_timer_sat = 1'b0;
+
+  // Declare the TX state machine PLL reset timer registers
+  localparam [9:0] P_TX_PLL_RESET_FREERUN_CYC = (P_TX_PLL_TYPE == 2) ?
+                                                (2 * P_FREERUN_FREQUENCY) + 2 : 7;
+  reg        sm_reset_tx_pll_timer_clr = 1'b1;
+  reg  [9:0] sm_reset_tx_pll_timer_ctr = 10'd0;
+  reg        sm_reset_tx_pll_timer_sat = 1'b0;
+  wire [9:0] p_tx_pll_reset_freerun_cyc_int = P_TX_PLL_RESET_FREERUN_CYC;
+
+  // Declare local parameters for TX reset state machine state values
+  localparam [2:0] ST_RESET_TX_BRANCH         = 3'd0;
+  localparam [2:0] ST_RESET_TX_PLL            = 3'd1;
+  localparam [2:0] ST_RESET_TX_DATAPATH       = 3'd2;
+  localparam [2:0] ST_RESET_TX_WAIT_LOCK      = 3'd3;
+  localparam [2:0] ST_RESET_TX_WAIT_USERRDY   = 3'd4;
+  localparam [2:0] ST_RESET_TX_WAIT_RESETDONE = 3'd5;
+  localparam [2:0] ST_RESET_TX_IDLE           = 3'd6;
+  reg        [2:0] sm_reset_tx                = ST_RESET_TX_BRANCH;
+
+  // Implementation of transmitter reset state machine synchronous process
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+
+    // The state machine is synchronously reset by the synchronized OR of all user input and internal TX reset signals
+    if (gtwiz_reset_tx_any_sync) begin
+      gtwiz_reset_tx_done_int   <= 1'b0;
+      sm_reset_tx_timer_clr     <= 1'b1;
+      sm_reset_tx_pll_timer_clr <= 1'b1;
+      sm_reset_tx               <= ST_RESET_TX_BRANCH;
+    end
+    else begin
+      case (sm_reset_tx)
+
+        // Once released from reset, branch to the reset control state indicated by the highest-priority synchronized
+        // signal (which remains asserted due to its long synchronizer chain)
+        ST_RESET_TX_BRANCH: begin
+          if (gtwiz_reset_tx_pll_and_datapath_dly)
+            sm_reset_tx <= ST_RESET_TX_PLL;
+          else if (gtwiz_reset_tx_datapath_dly)
+            sm_reset_tx <= ST_RESET_TX_DATAPATH;
+          sm_reset_tx_timer_clr     <= 1'b1;
+          sm_reset_tx_pll_timer_clr <= 1'b1;
+        end
+
+        // Assert the TX PLL and TX data path reset outputs
+        ST_RESET_TX_PLL: begin
+          pllreset_tx_out           <= 1'b1;
+          gttxreset_out             <= 1'b1;
+          txuserrdy_out             <= 1'b0;
+          sm_reset_tx_pll_timer_clr <= 1'b0;
+          if ((~sm_reset_tx_pll_timer_clr) && sm_reset_tx_pll_timer_sat) begin
+            sm_reset_tx_pll_timer_clr <= 1'b1;
+            sm_reset_tx               <= ST_RESET_TX_WAIT_LOCK;
+          end
+        end
+
+        // Assert the TX data path reset output
+        ST_RESET_TX_DATAPATH: begin
+          gttxreset_out         <= 1'b1;
+          txuserrdy_out         <= 1'b0;
+          sm_reset_tx_timer_clr <= 1'b0;
+          if ((~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
+            sm_reset_tx_timer_clr <= 1'b1;
+            sm_reset_tx           <= ST_RESET_TX_WAIT_LOCK;
+          end
+        end
+
+        // De-assert the TX PLL reset output, and await the TX PLL lock indicator before de-asserting the TX data path
+        // reset output
+        ST_RESET_TX_WAIT_LOCK: begin
+          pllreset_tx_out       <= 1'b0;
+          sm_reset_tx_timer_clr <= 1'b0;
+          if (plllock_tx_sync && (~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
+            gttxreset_out         <= 1'b0;
+            sm_reset_tx_timer_clr <= 1'b1;
+            sm_reset_tx           <= ST_RESET_TX_WAIT_USERRDY;
+          end
+        end
+
+        // Await the TX user clock active indicator from the TX user clocking helper block before asserting the TX user
+        // ready output
+        ST_RESET_TX_WAIT_USERRDY: begin
+          sm_reset_tx_timer_clr <= 1'b0;
+          if (gtwiz_reset_userclk_tx_active_sync && (~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
+            txuserrdy_out         <= 1'b1;
+            sm_reset_tx_timer_clr <= 1'b1;
+            sm_reset_tx           <= ST_RESET_TX_WAIT_RESETDONE;
+          end
+        end
+
+        // Await the TX reset done indicator before asserting the reset helper block TX reset done user output
+        ST_RESET_TX_WAIT_RESETDONE: begin
+          sm_reset_tx_timer_clr <= 1'b0;
+          if (txresetdone_in && (~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
+            gtwiz_reset_tx_done_int <= 1'b1;
+            sm_reset_tx_timer_clr   <= 1'b1;
+            sm_reset_tx             <= ST_RESET_TX_IDLE;
+          end
+        end
+
+        // While idle, de-assert the reset helper block TX reset done user output if PLL lock is lost, signaling the
+        // need for user intervention
+        ST_RESET_TX_IDLE: begin
+          if (!plllock_tx_sync)
+            gtwiz_reset_tx_done_int <= 1'b0;
+        end
+
+        // Encountering the default case indicates a state register error, so de-assert the reset helper block TX
+        // reset done user output, signaling the need for user intervention
+        default: begin
+          gtwiz_reset_tx_done_int <= 1'b0;
+        end
+
+      endcase
+    end
+  end
+
+  // Generate a small TX state machine reset timer, used to stall certain states to guarantee that their synchronized
+  // input values are being used at the appropriate time
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (sm_reset_tx_timer_clr) begin
+      sm_reset_tx_timer_ctr <= 3'd0;
+      sm_reset_tx_timer_sat <= 1'b0;
+    end
+    else begin
+      if (sm_reset_tx_timer_ctr != 3'd7)
+        sm_reset_tx_timer_ctr <= sm_reset_tx_timer_ctr + 3'd1;
+      else
+        sm_reset_tx_timer_sat <= 1'b1;
+    end
+  end
+
+  // Generate an TX PLL reset timer, used to indicate when the specified minimum TX PLL reset duration has expired. This
+  // is used by the TX state machine to proceed beyond the ST_RESET_TX_PLL wait state.
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (sm_reset_tx_pll_timer_clr) begin
+      sm_reset_tx_pll_timer_ctr <= 10'd0;
+      sm_reset_tx_pll_timer_sat <= 1'b0;
+    end
+    else begin
+      if (sm_reset_tx_pll_timer_ctr != p_tx_pll_reset_freerun_cyc_int)
+        sm_reset_tx_pll_timer_ctr <= sm_reset_tx_pll_timer_ctr + 10'd1;
+      else
+        sm_reset_tx_pll_timer_sat <= 1'b1;
+    end
+  end
+
+  // Hold the TX programmable divider in reset until the TX PLL has locked
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_txprogdivreset_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (~plllock_tx_in),
+    .rst_out (txprogdivreset_out)
+  );
+
+  // Synchronize the reset helper block TX reset done user output into the TXUSRCLK2 domain for user consumption
+  gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_tx_done_inst (
+    .clk_in  (txusrclk2_in),
+    .rst_in  (gtwiz_reset_tx_done_int),
+    .rst_out (gtwiz_reset_tx_done_out)
+  );
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Receiver reset state machine
+  // -------------------------------------------------------------------------------------------------------------------
+
+  // The receiver reset state machine responds to various synchronized inputs by resetting enabled receiver-
+  // related transceiver resources to which the reset helper block is connected. Various entry points to the sequential
+  // reset sequence are available.
+
+  // Initialize (for both synthesis and simulation) the RX PLL reset output flip-flop to 0 if the TX and RX PLLs are
+  // shared upon device configuration, so as to not block TX PLL reset; or to 1 if the PLLs are independent, for
+  // consistency with TX PLL initialization
+  initial begin
+    if (P_TX_PLL_TYPE == P_RX_PLL_TYPE)
+      pllreset_rx_out = 1'b0;
+    else
+      pllreset_rx_out = 1'b1;
+  end
+
+  // Synchronize the OR of all user input and internal RX reset signals for use in resetting the RX reset state machine
+  wire gtwiz_reset_rx_any;
+  wire gtwiz_reset_rx_any_sync;
+  assign gtwiz_reset_rx_any = gtwiz_reset_rx_pll_and_datapath_in  ||
+                              gtwiz_reset_rx_pll_and_datapath_int ||
+                              gtwiz_reset_rx_datapath_in          ||
+                              gtwiz_reset_rx_datapath_int;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_any_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_rx_any),
+    .rst_out (gtwiz_reset_rx_any_sync)
+  );
+
+  // Synchronize the OR of the user input and internal RX PLL and data path reset signals
+  wire gtwiz_reset_rx_pll_and_datapath_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_rx_pll_and_datapath_in || gtwiz_reset_rx_pll_and_datapath_int),
+    .rst_out (gtwiz_reset_rx_pll_and_datapath_sync)
+  );
+
+  // Use another synchronizer to delay the above signal for purposes of its detection following reset
+  wire gtwiz_reset_rx_pll_and_datapath_dly;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtwiz_reset_rx_pll_and_datapath_sync),
+    .o_out  (gtwiz_reset_rx_pll_and_datapath_dly)
+  );
+
+  // Synchronize the RX data path reset user input
+  wire gtwiz_reset_rx_datapath_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_datapath_inst (
+    .clk_in  (gtwiz_reset_clk_freerun_in),
+    .rst_in  (gtwiz_reset_rx_datapath_in || gtwiz_reset_rx_datapath_int),
+    .rst_out (gtwiz_reset_rx_datapath_sync)
+  );
+
+  // Use another synchronizer to delay the above signal for purposes of its detection following reset
+  wire gtwiz_reset_rx_datapath_dly;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtwiz_reset_rx_datapath_sync),
+    .o_out  (gtwiz_reset_rx_datapath_dly)
+  );
+
+  // Synchronize the RX user clock active indicator
+  wire gtwiz_reset_userclk_rx_active_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (gtwiz_reset_userclk_rx_active_in),
+    .o_out  (gtwiz_reset_userclk_rx_active_sync)
+  );
+
+  // Synchronize the RX PLL lock indicator
+  wire plllock_rx_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_plllock_rx_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (plllock_rx_in),
+    .o_out  (plllock_rx_sync)
+  );
+
+  // Synchronize the RX CDR lock indicator
+  wire rxcdrlock_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_rxcdrlock_inst (
+    .clk_in (gtwiz_reset_clk_freerun_in),
+    .i_in   (rxcdrlock_in),
+    .o_out  (rxcdrlock_sync)
+  );
+
+  // Declare the RX state machine reset timer registers
+  reg       sm_reset_rx_timer_clr = 1'b1;
+  reg [2:0] sm_reset_rx_timer_ctr = 3'd0;
+  reg       sm_reset_rx_timer_sat = 1'b0;
+
+  // Declare the RX state machine PLL reset timer registers
+  localparam [9:0] P_RX_PLL_RESET_FREERUN_CYC = (P_RX_PLL_TYPE == 2) ?
+                                                (2 * P_FREERUN_FREQUENCY) + 2 : 7;
+  reg        sm_reset_rx_pll_timer_clr = 1'b1;
+  reg  [9:0] sm_reset_rx_pll_timer_ctr = 10'd0;
+  reg        sm_reset_rx_pll_timer_sat = 1'b0;
+  wire [9:0] p_rx_pll_reset_freerun_cyc_int = P_RX_PLL_RESET_FREERUN_CYC;
+
+  // Declare the RX state machine CDR lock timeout counter
+  reg         sm_reset_rx_cdr_to_clr = 1'b1;
+  reg  [25:0] sm_reset_rx_cdr_to_ctr = 26'd0;
+  reg         sm_reset_rx_cdr_to_sat = 1'b0;
+  wire [25:0] p_cdr_timeout_freerun_cyc_int = P_CDR_TIMEOUT_FREERUN_CYC;
+
+  // Declare local parameters for RX reset state machine state values
+  localparam [2:0] ST_RESET_RX_BRANCH         = 3'd0;
+  localparam [2:0] ST_RESET_RX_PLL            = 3'd1;
+  localparam [2:0] ST_RESET_RX_DATAPATH       = 3'd2;
+  localparam [2:0] ST_RESET_RX_WAIT_LOCK      = 3'd3;
+  localparam [2:0] ST_RESET_RX_WAIT_CDR       = 3'd4;
+  localparam [2:0] ST_RESET_RX_WAIT_USERRDY   = 3'd5;
+  localparam [2:0] ST_RESET_RX_WAIT_RESETDONE = 3'd6;
+  localparam [2:0] ST_RESET_RX_IDLE           = 3'd7;
+  reg        [2:0] sm_reset_rx                = ST_RESET_RX_BRANCH;
+
+  // Implementation of receiver reset state machine synchronous process
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+
+    // The state machine is synchronously reset by the synchronized OR of all user input and internal RX reset signals
+    if (gtwiz_reset_rx_any_sync) begin
+      gtwiz_reset_rx_done_int   <= 1'b0;
+      sm_reset_rx_timer_clr     <= 1'b1;
+      sm_reset_rx_pll_timer_clr <= 1'b1;
+      sm_reset_rx_cdr_to_clr    <= 1'b1;
+      sm_reset_rx               <= ST_RESET_RX_BRANCH;
+    end
+    else begin
+      case (sm_reset_rx)
+
+        // Once released from reset, branch to the reset control state indicated by the highest-priority synchronized
+        // signal (which remains asserted due to its long synchronizer chain)
+        ST_RESET_RX_BRANCH: begin
+          if (gtwiz_reset_rx_pll_and_datapath_dly)
+            sm_reset_rx <= ST_RESET_RX_PLL;
+          else if (gtwiz_reset_rx_datapath_dly)
+            sm_reset_rx <= ST_RESET_RX_DATAPATH;
+          sm_reset_rx_timer_clr     <= 1'b1;
+          sm_reset_rx_pll_timer_clr <= 1'b1;
+          sm_reset_rx_cdr_to_clr    <= 1'b1;
+        end
+
+        // Assert the RX PLL, RX programmable divider, and RX data path reset outputs
+        ST_RESET_RX_PLL: begin
+          pllreset_rx_out           <= 1'b1;
+          rxprogdivreset_out        <= 1'b1;
+          gtrxreset_out             <= 1'b1;
+          rxuserrdy_out             <= 1'b0;
+          sm_reset_rx_pll_timer_clr <= 1'b0;
+          if ((~sm_reset_rx_pll_timer_clr) && sm_reset_rx_pll_timer_sat) begin
+            sm_reset_rx_pll_timer_clr <= 1'b1;
+            sm_reset_rx               <= ST_RESET_RX_WAIT_LOCK;
+          end
+        end
+
+        // Assert the RX data path and RX programmable divider reset outputs
+        ST_RESET_RX_DATAPATH: begin
+          rxprogdivreset_out    <= 1'b1;
+          gtrxreset_out         <= 1'b1;
+          rxuserrdy_out         <= 1'b0;
+          sm_reset_rx_timer_clr <= 1'b0;
+          if ((~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat) begin
+            sm_reset_rx_timer_clr <= 1'b1;
+            sm_reset_rx           <= ST_RESET_RX_WAIT_LOCK;
+          end
+        end
+
+        // De-assert the RX PLL reset output, and await the RX PLL lock indicator before de-asserting the RX data path
+        // reset output
+        ST_RESET_RX_WAIT_LOCK: begin
+          pllreset_rx_out       <= 1'b0;
+          sm_reset_rx_timer_clr <= 1'b0;
+          if (plllock_rx_sync && (~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat) begin
+            gtrxreset_out          <= 1'b0;
+            sm_reset_rx_timer_clr  <= 1'b1;
+            sm_reset_rx_cdr_to_clr <= 1'b0;
+            sm_reset_rx            <= ST_RESET_RX_WAIT_CDR;
+          end
+        end
+
+        // Await an indication of CDR stability (either the direct transceiver RXCDRLOCK output, or expiration of the
+        // specified maximum CDR locking time, whichever occurs first) before removing the RX programmable divider reset
+        // and proceeding
+        ST_RESET_RX_WAIT_CDR: begin
+          if (rxcdrlock_sync || sm_reset_rx_cdr_to_sat) begin
+            rxprogdivreset_out     <= 1'b0;
+            sm_reset_rx_cdr_to_clr <= 1'b1;
+            sm_reset_rx            <= ST_RESET_RX_WAIT_USERRDY;
+          end
+        end
+
+        // Await the RX user clock active indicator from the RX user clocking helper block before asserting the RX user
+        // ready output
+        ST_RESET_RX_WAIT_USERRDY: begin
+          sm_reset_rx_timer_clr <= 1'b0;
+          if (gtwiz_reset_userclk_rx_active_sync && (~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat) begin
+            rxuserrdy_out         <= 1'b1;
+            sm_reset_rx_timer_clr <= 1'b1;
+            sm_reset_rx           <= ST_RESET_RX_WAIT_RESETDONE;
+          end
+        end
+
+        // Await the RX reset done indicator before asserting the reset helper block RX reset done user output
+        ST_RESET_RX_WAIT_RESETDONE: begin
+          sm_reset_rx_timer_clr <= 1'b0;
+          if (rxresetdone_in && (~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat)
+          begin
+            gtwiz_reset_rx_done_int <= 1'b1;
+            sm_reset_rx_timer_clr   <= 1'b1;
+            sm_reset_rx             <= ST_RESET_RX_IDLE;
+          end
+        end
+
+        // While idle, de-assert the reset helper block RX reset done user output if PLL lock is lost, signaling the
+        // need for user intervention
+        ST_RESET_RX_IDLE: begin
+          if (!plllock_rx_sync)
+            gtwiz_reset_rx_done_int <= 1'b0;
+        end
+
+      endcase
+    end
+  end
+
+  // Generate a small RX state machine reset timer, used to stall certain states to guarantee that their synchronized
+  // input values are being used at the appropriate time
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (sm_reset_rx_timer_clr) begin
+      sm_reset_rx_timer_ctr <= 3'd0;
+      sm_reset_rx_timer_sat <= 1'b0;
+    end
+    else begin
+      if (sm_reset_rx_timer_ctr != 3'd7)
+        sm_reset_rx_timer_ctr <= sm_reset_rx_timer_ctr + 3'd1;
+      else
+        sm_reset_rx_timer_sat <= 1'b1;
+    end
+  end
+
+  // Generate an RX PLL reset timer, used to indicate when the specified minimum RX PLL reset duration has expired. This
+  // is used by the RX state machine to proceed beyond the ST_RESET_RX_PLL wait state.
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (sm_reset_rx_pll_timer_clr) begin
+      sm_reset_rx_pll_timer_ctr <= 10'd0;
+      sm_reset_rx_pll_timer_sat <= 1'b0;
+    end
+    else begin
+      if (sm_reset_rx_pll_timer_ctr != p_rx_pll_reset_freerun_cyc_int)
+        sm_reset_rx_pll_timer_ctr <= sm_reset_rx_pll_timer_ctr + 10'd1;
+      else
+        sm_reset_rx_pll_timer_sat <= 1'b1;
+    end
+  end
+
+  // Generate a CDR lock timeout timer, used to indicate when the specified maximum CDR locking time has expired. This
+  // is used by the RX state machine to proceed beyond the ST_RESET_RX_WAIT_CDR wait state in the event that the
+  // transceiver RXCDRLOCK output does not assert within that time period.
+  always @(posedge gtwiz_reset_clk_freerun_in) begin
+    if (sm_reset_rx_cdr_to_clr) begin
+      sm_reset_rx_cdr_to_ctr <= 26'd0;
+      sm_reset_rx_cdr_to_sat <= 1'b0;
+    end
+    else begin
+      if (sm_reset_rx_cdr_to_ctr != p_cdr_timeout_freerun_cyc_int)
+        sm_reset_rx_cdr_to_ctr <= sm_reset_rx_cdr_to_ctr + 26'd1;
+      else
+        sm_reset_rx_cdr_to_sat <= 1'b1;
+    end
+  end
+
+  // Assign the RX CDR stable user indicator to the transceiver RXCDRLOCK output
+  assign gtwiz_reset_rx_cdr_stable_out = rxcdrlock_sync;
+
+  // Synchronize the reset helper block RX reset done user output into the RXUSRCLK2 domain for user consumption
+  gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_rx_done_inst (
+    .clk_in  (rxusrclk2_in),
+    .rst_in  (gtwiz_reset_rx_done_int),
+    .rst_out (gtwiz_reset_rx_done_out)
+  );
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v
new file mode 100755
index 0000000..5faa3dd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v
@@ -0,0 +1,140 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_userclk_rx #(
+
+  parameter integer P_CONTENTS                     = 0,
+  parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK  = 1,
+  parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
+
+)(
+
+  input  wire gtwiz_userclk_rx_srcclk_in,
+  input  wire gtwiz_userclk_rx_reset_in,
+  output wire gtwiz_userclk_rx_usrclk_out,
+  output wire gtwiz_userclk_rx_usrclk2_out,
+  output wire gtwiz_userclk_rx_active_out
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Local parameters
+  // -------------------------------------------------------------------------------------------------------------------
+
+  // Convert integer parameters with known, limited legal range to a 3-bit local parameter values
+  localparam integer P_USRCLK_INT_DIV  = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
+  localparam   [2:0] P_USRCLK_DIV      = P_USRCLK_INT_DIV[2:0];
+  localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
+  localparam   [2:0] P_USRCLK2_DIV     = P_USRCLK2_INT_DIV[2:0];
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Receiver user clocking network conditional generation, based on parameter values in module instantiation
+  // -------------------------------------------------------------------------------------------------------------------
+  generate if (1) begin: gen_gtwiz_userclk_rx_main
+
+    // Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
+    if (P_CONTENTS == 0) begin
+
+      // Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
+      // frequency ratio
+      BUFG_GT bufg_gt_usrclk_inst (
+        .CE      (1'b1),
+        .CEMASK  (1'b0),
+        .CLR     (gtwiz_userclk_rx_reset_in),
+        .CLRMASK (1'b0),
+        .DIV     (P_USRCLK_DIV),
+        .I       (gtwiz_userclk_rx_srcclk_in),
+        .O       (gtwiz_userclk_rx_usrclk_out)
+      );
+
+      // If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
+      // RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
+      if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
+        assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
+      else begin
+        BUFG_GT bufg_gt_usrclk2_inst (
+          .CE      (1'b1),
+          .CEMASK  (1'b0),
+          .CLR     (gtwiz_userclk_rx_reset_in),
+          .CLRMASK (1'b0),
+          .DIV     (P_USRCLK2_DIV),
+          .I       (gtwiz_userclk_rx_srcclk_in),
+          .O       (gtwiz_userclk_rx_usrclk2_out)
+        );
+      end
+
+      // Indicate active helper block functionality when the BUFG_GT divider is not held in reset
+      (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0;
+      (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0;
+      always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin
+        if (gtwiz_userclk_rx_reset_in) begin
+          gtwiz_userclk_rx_active_meta <= 1'b0;
+          gtwiz_userclk_rx_active_sync <= 1'b0;
+        end
+        else begin
+          gtwiz_userclk_rx_active_meta <= 1'b1;
+          gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta;
+        end
+      end
+      assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync;
+
+    end
+
+  end
+  endgenerate
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v
new file mode 100755
index 0000000..edc0db5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v
@@ -0,0 +1,140 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_userclk_tx #(
+
+  parameter integer P_CONTENTS                     = 0,
+  parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK  = 1,
+  parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
+
+)(
+
+  input  wire gtwiz_userclk_tx_srcclk_in,
+  input  wire gtwiz_userclk_tx_reset_in,
+  output wire gtwiz_userclk_tx_usrclk_out,
+  output wire gtwiz_userclk_tx_usrclk2_out,
+  output wire gtwiz_userclk_tx_active_out
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Local parameters
+  // -------------------------------------------------------------------------------------------------------------------
+
+  // Convert integer parameters with known, limited legal range to a 3-bit local parameter values
+  localparam integer P_USRCLK_INT_DIV  = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
+  localparam   [2:0] P_USRCLK_DIV      = P_USRCLK_INT_DIV[2:0];
+  localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
+  localparam   [2:0] P_USRCLK2_DIV     = P_USRCLK2_INT_DIV[2:0];
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Transmitter user clocking network conditional generation, based on parameter values in module instantiation
+  // -------------------------------------------------------------------------------------------------------------------
+  generate if (1) begin: gen_gtwiz_userclk_tx_main
+
+    // Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
+    if (P_CONTENTS == 0) begin
+
+      // Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
+      // frequency ratio
+      BUFG_GT bufg_gt_usrclk_inst (
+        .CE      (1'b1),
+        .CEMASK  (1'b0),
+        .CLR     (gtwiz_userclk_tx_reset_in),
+        .CLRMASK (1'b0),
+        .DIV     (P_USRCLK_DIV),
+        .I       (gtwiz_userclk_tx_srcclk_in),
+        .O       (gtwiz_userclk_tx_usrclk_out)
+      );
+
+      // If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
+      // TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
+      if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
+        assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
+      else begin
+        BUFG_GT bufg_gt_usrclk2_inst (
+          .CE      (1'b1),
+          .CEMASK  (1'b0),
+          .CLR     (gtwiz_userclk_tx_reset_in),
+          .CLRMASK (1'b0),
+          .DIV     (P_USRCLK2_DIV),
+          .I       (gtwiz_userclk_tx_srcclk_in),
+          .O       (gtwiz_userclk_tx_usrclk2_out)
+        );
+      end
+
+      // Indicate active helper block functionality when the BUFG_GT divider is not held in reset
+      (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0;
+      (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0;
+      always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
+        if (gtwiz_userclk_tx_reset_in) begin
+          gtwiz_userclk_tx_active_meta <= 1'b0;
+          gtwiz_userclk_tx_active_sync <= 1'b0;
+        end
+        else begin
+          gtwiz_userclk_tx_active_meta <= 1'b1;
+          gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta;
+        end
+      end
+      assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync;
+
+    end
+
+  end
+  endgenerate
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v
new file mode 100755
index 0000000..79352ad
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v
@@ -0,0 +1,219 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_userdata_rx #(
+
+  parameter integer P_RX_USER_DATA_WIDTH       = 32,
+  parameter integer P_RX_DATA_DECODING         = 0,
+  parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1
+
+)(
+
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS*128)-1:0]                  rxdata_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0]                  rxctrl0_in,
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0]                  rxctrl1_in,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS*P_RX_USER_DATA_WIDTH)-1:0] gtwiz_userdata_rx_out
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Receiver user data width sizing conditional generation, based on parameter values in module instantiation
+  // -------------------------------------------------------------------------------------------------------------------
+  generate if (1) begin : gen_gtwiz_userdata_rx_main
+    genvar ch_idx;
+
+    // If receiver data decoding is either not raw mode, or is raw mode but user data width is not modulus 10, then
+    // simply assign the user-facing data vector with the active data bits from the transceiver-facing RXDATA vector.
+    if ((P_RX_DATA_DECODING != 0) ||
+       ((P_RX_DATA_DECODING == 0) && (P_RX_USER_DATA_WIDTH % 10 != 0))) begin : gen_rxdata
+
+      for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_assign
+        assign gtwiz_userdata_rx_out[(P_RX_USER_DATA_WIDTH*ch_idx)+P_RX_USER_DATA_WIDTH-1:
+                                     (P_RX_USER_DATA_WIDTH*ch_idx)] =
+          rxdata_in[(128*ch_idx)+P_RX_USER_DATA_WIDTH-1:(128*ch_idx)];
+      end
+
+    end
+
+    // If receiver data decoding is raw mode and user data width is modulus 10, then assign the user-facing data vector
+    // with the specified combination of transceiver-facing RXDATA, RXCTRL0, and RXCTRL1 vectors. The interleaving of
+    // these vectors is always in a repeating 8-1-1 bit pattern, scaling with the user data width size.
+    else begin : gen_rxdata_rxctrl
+
+      case (P_RX_USER_DATA_WIDTH)
+        20:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width20
+            assign gtwiz_userdata_rx_out [(ch_idx*20)+19:(ch_idx*20)] =
+              {rxctrl1_in[(ch_idx* 16)+1],
+               rxctrl0_in[(ch_idx* 16)+1],
+               rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
+               rxctrl1_in[(ch_idx* 16)],
+               rxctrl0_in[(ch_idx* 16)],
+               rxdata_in [(ch_idx*128)+7:ch_idx*128]};
+          end
+
+        40:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width40
+            assign gtwiz_userdata_rx_out [(ch_idx*40)+39:(ch_idx*40)] =
+              {rxctrl1_in[(ch_idx* 16)+3],
+               rxctrl0_in[(ch_idx* 16)+3],
+               rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
+               rxctrl1_in[(ch_idx* 16)+2],
+               rxctrl0_in[(ch_idx* 16)+2],
+               rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
+               rxctrl1_in[(ch_idx* 16)+1],
+               rxctrl0_in[(ch_idx* 16)+1],
+               rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
+               rxctrl1_in[(ch_idx* 16)],
+               rxctrl0_in[(ch_idx* 16)],
+               rxdata_in [(ch_idx*128)+7:ch_idx*128]};
+          end
+
+        80:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width80
+            assign gtwiz_userdata_rx_out [(ch_idx*80)+79:(ch_idx*80)] =
+              {rxctrl1_in[(ch_idx* 16)+7],
+               rxctrl0_in[(ch_idx* 16)+7],
+               rxdata_in [(ch_idx*128)+63:(ch_idx*128)+56],
+               rxctrl1_in[(ch_idx* 16)+6],
+               rxctrl0_in[(ch_idx* 16)+6],
+               rxdata_in [(ch_idx*128)+55:(ch_idx*128)+48],
+               rxctrl1_in[(ch_idx* 16)+5],
+               rxctrl0_in[(ch_idx* 16)+5],
+               rxdata_in [(ch_idx*128)+47:(ch_idx*128)+40],
+               rxctrl1_in[(ch_idx* 16)+4],
+               rxctrl0_in[(ch_idx* 16)+4],
+               rxdata_in [(ch_idx*128)+39:(ch_idx*128)+32],
+               rxctrl1_in[(ch_idx* 16)+3],
+               rxctrl0_in[(ch_idx* 16)+3],
+               rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
+               rxctrl1_in[(ch_idx* 16)+2],
+               rxctrl0_in[(ch_idx* 16)+2],
+               rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
+               rxctrl1_in[(ch_idx* 16)+1],
+               rxctrl0_in[(ch_idx* 16)+1],
+               rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
+               rxctrl1_in[(ch_idx* 16)],
+               rxctrl0_in[(ch_idx* 16)],
+               rxdata_in [(ch_idx*128)+7:ch_idx*128]};
+          end
+
+        160:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width160
+            assign gtwiz_userdata_rx_out [(ch_idx*160)+159:(ch_idx*160)] =
+              {rxctrl1_in[(ch_idx* 16)+15],
+               rxctrl0_in[(ch_idx* 16)+15],
+               rxdata_in [(ch_idx*128)+127:(ch_idx*128)+120],
+               rxctrl1_in[(ch_idx* 16)+14],
+               rxctrl0_in[(ch_idx* 16)+14],
+               rxdata_in [(ch_idx*128)+119:(ch_idx*128)+112],
+               rxctrl1_in[(ch_idx* 16)+13],
+               rxctrl0_in[(ch_idx* 16)+13],
+               rxdata_in [(ch_idx*128)+111:(ch_idx*128)+104],
+               rxctrl1_in[(ch_idx* 16)+12],
+               rxctrl0_in[(ch_idx* 16)+12],
+               rxdata_in [(ch_idx*128)+103:(ch_idx*128)+96],
+               rxctrl1_in[(ch_idx* 16)+11],
+               rxctrl0_in[(ch_idx* 16)+11],
+               rxdata_in [(ch_idx*128)+95:(ch_idx*128)+88],
+               rxctrl1_in[(ch_idx* 16)+10],
+               rxctrl0_in[(ch_idx* 16)+10],
+               rxdata_in [(ch_idx*128)+87:(ch_idx*128)+80],
+               rxctrl1_in[(ch_idx* 16)+9],
+               rxctrl0_in[(ch_idx* 16)+9],
+               rxdata_in [(ch_idx*128)+79:(ch_idx*128)+72],
+               rxctrl1_in[(ch_idx* 16)+8],
+               rxctrl0_in[(ch_idx* 16)+8],
+               rxdata_in [(ch_idx*128)+71:(ch_idx*128)+64],
+               rxctrl1_in[(ch_idx* 16)+7],
+               rxctrl0_in[(ch_idx* 16)+7],
+               rxdata_in [(ch_idx*128)+63:(ch_idx*128)+56],
+               rxctrl1_in[(ch_idx* 16)+6],
+               rxctrl0_in[(ch_idx* 16)+6],
+               rxdata_in [(ch_idx*128)+55:(ch_idx*128)+48],
+               rxctrl1_in[(ch_idx* 16)+5],
+               rxctrl0_in[(ch_idx* 16)+5],
+               rxdata_in [(ch_idx*128)+47:(ch_idx*128)+40],
+               rxctrl1_in[(ch_idx* 16)+4],
+               rxctrl0_in[(ch_idx* 16)+4],
+               rxdata_in [(ch_idx*128)+39:(ch_idx*128)+32],
+               rxctrl1_in[(ch_idx* 16)+3],
+               rxctrl0_in[(ch_idx* 16)+3],
+               rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
+               rxctrl1_in[(ch_idx* 16)+2],
+               rxctrl0_in[(ch_idx* 16)+2],
+               rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
+               rxctrl1_in[(ch_idx* 16)+1],
+               rxctrl0_in[(ch_idx* 16)+1],
+               rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
+               rxctrl1_in[(ch_idx* 16)],
+               rxctrl0_in[(ch_idx* 16)],
+               rxdata_in [(ch_idx*128)+7:ch_idx*128]};
+          end
+
+        default:
+          begin : gen_default
+            // The default case is a configuration error scenario should never be exercised
+            assign gtwiz_userdata_rx_out = {P_TOTAL_NUMBER_OF_CHANNELS*P_RX_USER_DATA_WIDTH{1'b1}};
+          end
+      endcase
+
+    end
+
+  end
+  endgenerate
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v
new file mode 100755
index 0000000..cfaea9c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v
@@ -0,0 +1,249 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtwiz_userdata_tx #(
+
+  parameter integer P_TX_USER_DATA_WIDTH       = 32,
+  parameter integer P_TX_DATA_ENCODING         = 0,
+  parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1
+
+)(
+
+  input  wire [(P_TOTAL_NUMBER_OF_CHANNELS*P_TX_USER_DATA_WIDTH)-1:0] gtwiz_userdata_tx_in,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS*128)-1:0]                  txdata_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0]                  txctrl0_out,
+  output wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0]                  txctrl1_out
+
+);
+
+
+  // -------------------------------------------------------------------------------------------------------------------
+  // Transmitter user data width sizing conditional generation, based on parameter values in module instantiation
+  // -------------------------------------------------------------------------------------------------------------------
+  generate if (1) begin : gen_gtwiz_userdata_tx_main
+    genvar ch_idx;
+
+    // If transmitter data encoding is either not raw mode, or is raw mode but user data width is not modulus 10, then
+    // simply assign the transceiver-facing TXDATA vector with data bits from the user-facing data vector, plus padding.
+    if ((P_TX_DATA_ENCODING != 0) ||
+       ((P_TX_DATA_ENCODING == 0) && (P_TX_USER_DATA_WIDTH % 10 != 0))) begin : gen_txdata
+
+      for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_assign
+        if (P_TX_USER_DATA_WIDTH < 128) begin : gen_less_128
+          assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
+            {{128-P_TX_USER_DATA_WIDTH{1'b0}},
+             gtwiz_userdata_tx_in[(P_TX_USER_DATA_WIDTH*ch_idx)+P_TX_USER_DATA_WIDTH-1:
+                                  (P_TX_USER_DATA_WIDTH*ch_idx)]};
+        end
+        else begin : gen_128
+          assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
+             gtwiz_userdata_tx_in[(P_TX_USER_DATA_WIDTH*ch_idx)+P_TX_USER_DATA_WIDTH-1:
+                                  (P_TX_USER_DATA_WIDTH*ch_idx)];
+        end
+      end
+
+      // Transceiver-facing TXCTRL0 and TXCTRL1 vectors are not driven by this helper block in this configuration
+      assign txctrl0_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b0}};
+      assign txctrl1_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b0}};
+    end
+
+    // If transmitter data encoding is raw mode and user data width is modulus 10, then assign the specified combination
+    // of transceiver-facing TXDATA, TXCTRL0, and TXCTRL1 vectors with the user-facing data vector. The interleaving of
+    // these vectors is always in a repeating 8-1-1 bit pattern, scaling with the user data width size.
+    else begin : gen_txdata_txctrl
+
+      case (P_TX_USER_DATA_WIDTH)
+        20:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width20
+            assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {14'b0,
+               gtwiz_userdata_tx_in[(ch_idx*20)+19],
+               gtwiz_userdata_tx_in[(ch_idx*20)+9]};
+            assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {14'b0,
+               gtwiz_userdata_tx_in[(ch_idx*20)+18],
+               gtwiz_userdata_tx_in[(ch_idx*20)+8]};
+            assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
+              {112'b0,
+               gtwiz_userdata_tx_in[(ch_idx*20)+17:(ch_idx*20)+10],
+               gtwiz_userdata_tx_in[(ch_idx*20)+7:ch_idx*20]};
+          end
+
+        40:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width40
+            assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {12'b0,
+               gtwiz_userdata_tx_in[(ch_idx*40)+39],
+               gtwiz_userdata_tx_in[(ch_idx*40)+29],
+               gtwiz_userdata_tx_in[(ch_idx*40)+19],
+               gtwiz_userdata_tx_in[(ch_idx*40)+9]};
+            assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {12'b0,
+               gtwiz_userdata_tx_in[(ch_idx*40)+38],
+               gtwiz_userdata_tx_in[(ch_idx*40)+28],
+               gtwiz_userdata_tx_in[(ch_idx*40)+18],
+               gtwiz_userdata_tx_in[(ch_idx*40)+8]};
+            assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
+              {96'b0,
+               gtwiz_userdata_tx_in[(ch_idx*40)+37:(ch_idx*40)+30],
+               gtwiz_userdata_tx_in[(ch_idx*40)+27:(ch_idx*40)+20],
+               gtwiz_userdata_tx_in[(ch_idx*40)+17:(ch_idx*40)+10],
+               gtwiz_userdata_tx_in[(ch_idx*40)+7:ch_idx*40]};
+          end
+
+        80:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width80
+            assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {8'b0,
+               gtwiz_userdata_tx_in[(ch_idx*80)+79],
+               gtwiz_userdata_tx_in[(ch_idx*80)+69],
+               gtwiz_userdata_tx_in[(ch_idx*80)+59],
+               gtwiz_userdata_tx_in[(ch_idx*80)+49],
+               gtwiz_userdata_tx_in[(ch_idx*80)+39],
+               gtwiz_userdata_tx_in[(ch_idx*80)+29],
+               gtwiz_userdata_tx_in[(ch_idx*80)+19],
+               gtwiz_userdata_tx_in[(ch_idx*80)+9]};
+            assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {8'b0,
+               gtwiz_userdata_tx_in[(ch_idx*80)+78],
+               gtwiz_userdata_tx_in[(ch_idx*80)+68],
+               gtwiz_userdata_tx_in[(ch_idx*80)+58],
+               gtwiz_userdata_tx_in[(ch_idx*80)+48],
+               gtwiz_userdata_tx_in[(ch_idx*80)+38],
+               gtwiz_userdata_tx_in[(ch_idx*80)+28],
+               gtwiz_userdata_tx_in[(ch_idx*80)+18],
+               gtwiz_userdata_tx_in[(ch_idx*80)+8]};
+            assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
+              {64'b0,
+               gtwiz_userdata_tx_in[(ch_idx*80)+77:(ch_idx*80)+70],
+               gtwiz_userdata_tx_in[(ch_idx*80)+67:(ch_idx*80)+60],
+               gtwiz_userdata_tx_in[(ch_idx*80)+57:(ch_idx*80)+50],
+               gtwiz_userdata_tx_in[(ch_idx*80)+47:(ch_idx*80)+40],
+               gtwiz_userdata_tx_in[(ch_idx*80)+37:(ch_idx*80)+30],
+               gtwiz_userdata_tx_in[(ch_idx*80)+27:(ch_idx*80)+20],
+               gtwiz_userdata_tx_in[(ch_idx*80)+17:(ch_idx*80)+10],
+               gtwiz_userdata_tx_in[(ch_idx*80)+7:ch_idx*80]};
+          end
+
+        160:
+          for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width160
+            assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {gtwiz_userdata_tx_in[(ch_idx*160)+159],
+               gtwiz_userdata_tx_in[(ch_idx*160)+149],
+               gtwiz_userdata_tx_in[(ch_idx*160)+139],
+               gtwiz_userdata_tx_in[(ch_idx*160)+129],
+               gtwiz_userdata_tx_in[(ch_idx*160)+119],
+               gtwiz_userdata_tx_in[(ch_idx*160)+109],
+               gtwiz_userdata_tx_in[(ch_idx*160)+99],
+               gtwiz_userdata_tx_in[(ch_idx*160)+89],
+               gtwiz_userdata_tx_in[(ch_idx*160)+79],
+               gtwiz_userdata_tx_in[(ch_idx*160)+69],
+               gtwiz_userdata_tx_in[(ch_idx*160)+59],
+               gtwiz_userdata_tx_in[(ch_idx*160)+49],
+               gtwiz_userdata_tx_in[(ch_idx*160)+39],
+               gtwiz_userdata_tx_in[(ch_idx*160)+29],
+               gtwiz_userdata_tx_in[(ch_idx*160)+19],
+               gtwiz_userdata_tx_in[(ch_idx*160)+9]};
+            assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
+              {gtwiz_userdata_tx_in[(ch_idx*160)+158],
+               gtwiz_userdata_tx_in[(ch_idx*160)+148],
+               gtwiz_userdata_tx_in[(ch_idx*160)+138],
+               gtwiz_userdata_tx_in[(ch_idx*160)+128],
+               gtwiz_userdata_tx_in[(ch_idx*160)+118],
+               gtwiz_userdata_tx_in[(ch_idx*160)+108],
+               gtwiz_userdata_tx_in[(ch_idx*160)+98],
+               gtwiz_userdata_tx_in[(ch_idx*160)+88],
+               gtwiz_userdata_tx_in[(ch_idx*160)+78],
+               gtwiz_userdata_tx_in[(ch_idx*160)+68],
+               gtwiz_userdata_tx_in[(ch_idx*160)+58],
+               gtwiz_userdata_tx_in[(ch_idx*160)+48],
+               gtwiz_userdata_tx_in[(ch_idx*160)+38],
+               gtwiz_userdata_tx_in[(ch_idx*160)+28],
+               gtwiz_userdata_tx_in[(ch_idx*160)+18],
+               gtwiz_userdata_tx_in[(ch_idx*160)+8]};
+            assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
+              {gtwiz_userdata_tx_in[(ch_idx*160)+157:(ch_idx*160)+150],
+               gtwiz_userdata_tx_in[(ch_idx*160)+147:(ch_idx*160)+140],
+               gtwiz_userdata_tx_in[(ch_idx*160)+137:(ch_idx*160)+130],
+               gtwiz_userdata_tx_in[(ch_idx*160)+127:(ch_idx*160)+120],
+               gtwiz_userdata_tx_in[(ch_idx*160)+117:(ch_idx*160)+110],
+               gtwiz_userdata_tx_in[(ch_idx*160)+107:(ch_idx*160)+100],
+               gtwiz_userdata_tx_in[(ch_idx*160)+97:(ch_idx*160)+90],
+               gtwiz_userdata_tx_in[(ch_idx*160)+87:(ch_idx*160)+80],
+               gtwiz_userdata_tx_in[(ch_idx*160)+77:(ch_idx*160)+70],
+               gtwiz_userdata_tx_in[(ch_idx*160)+67:(ch_idx*160)+60],
+               gtwiz_userdata_tx_in[(ch_idx*160)+57:(ch_idx*160)+50],
+               gtwiz_userdata_tx_in[(ch_idx*160)+47:(ch_idx*160)+40],
+               gtwiz_userdata_tx_in[(ch_idx*160)+37:(ch_idx*160)+30],
+               gtwiz_userdata_tx_in[(ch_idx*160)+27:(ch_idx*160)+20],
+               gtwiz_userdata_tx_in[(ch_idx*160)+17:(ch_idx*160)+10],
+               gtwiz_userdata_tx_in[(ch_idx*160)+7:ch_idx*160]};
+          end
+
+        default:
+          begin : gen_default
+            // The default case is a configuration error scenario should never be exercised
+            assign txdata_out  = {P_TOTAL_NUMBER_OF_CHANNELS*128{1'b1}};
+            assign txctrl0_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b1}};
+            assign txctrl1_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b1}};
+          end
+      endcase
+
+    end
+
+  end
+  endgenerate
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v
new file mode 100755
index 0000000..6ea0c72
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v
@@ -0,0 +1,224 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_freq_counter # (
+  parameter REVISION = 1
+)(
+  output reg  [17:0] freq_cnt_o = 18'd0,
+  output reg  done_o,
+  input  wire rst_i,
+  input  wire [15:0] test_term_cnt_i,
+  input  wire ref_clk_i,
+  input  wire test_clk_i
+);
+  //****************************************************************************
+  //  Local Parameters
+  //****************************************************************************
+  localparam RESET_STATE = 0;
+  localparam MEASURE_STATE = 1;
+  localparam HOLD_STATE = 2;
+  localparam UPDATE_STATE = 3;
+  localparam DONE_STATE = 4;
+
+  //****************************************************************************
+  //  Local Signals
+  //****************************************************************************
+  reg [17:0] testclk_cnt = 18'h00000;
+  reg [15:0] refclk_cnt = 16'h0000;
+  reg [3:0] testclk_div4 = 4'h1;
+  wire testclk_rst;
+  wire testclk_en;
+  reg [5:0] hold_clk = 6'd0;
+  reg [4:0] state = 5'd1;
+
+  (* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
+  (* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
+
+  //
+  // need to get testclk_rst into TESTCLK_I domain
+  //
+  always @(posedge test_clk_i)
+  begin
+    tstclk_rst_dly1 <= testclk_rst;
+    tstclk_rst_dly2 <= tstclk_rst_dly1;
+  end
+
+  //
+  // need to get testclk_en into TESTCLK_I domain
+  //
+  always @(posedge test_clk_i)
+  begin
+    testclk_en_dly1 <= testclk_en;
+    testclk_en_dly2 <= testclk_en_dly1;
+  end
+
+  always @(posedge test_clk_i)
+  begin
+    if (tstclk_rst_dly2 == 1'b1)
+    begin
+      testclk_div4 <= 4'h1;
+    end
+    else
+    begin
+      testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
+    end
+  end
+
+  wire testclk_rst_sync;
+
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_testclk_rst_inst (
+    .clk_in (test_clk_i),
+    .rst_in   (testclk_rst),
+    .rst_out  (testclk_rst_sync)
+  );
+
+  always @(posedge test_clk_i or posedge testclk_rst_sync)
+  begin
+    if (testclk_rst_sync == 1'b1)
+    begin
+      testclk_cnt <= 0;
+    end
+    else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
+    begin
+      testclk_cnt <= testclk_cnt + 1;
+    end
+  end
+
+/*   always @(posedge test_clk_i or posedge testclk_rst)
+  begin
+    if (testclk_rst == 1'b1)
+    begin
+      testclk_cnt <= 0;
+    end
+    else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
+    begin
+      testclk_cnt <= testclk_cnt + 1;
+    end
+  end */
+
+  always @(posedge ref_clk_i or posedge rst_i)
+  begin
+    if (rst_i)
+      done_o <= 1'b0;
+    else
+      done_o <= state[DONE_STATE];
+  end
+
+  always @(posedge ref_clk_i or posedge rst_i)
+  begin
+    if (rst_i) begin
+      state <= 0;
+      state[RESET_STATE] <= 1'b1;
+    end
+    else begin
+      state <= 0;
+      case (1'b1) // synthesis parallel_case full_case
+        state[RESET_STATE]:
+          begin
+            if (hold_clk == 6'h3F)
+              state[MEASURE_STATE] <= 1'b1;
+            else
+              state[RESET_STATE] <= 1'b1;
+          end
+        state[MEASURE_STATE]:
+          begin
+            if (refclk_cnt == test_term_cnt_i)
+              state[HOLD_STATE] <= 1'b1;
+            else
+              state[MEASURE_STATE] <= 1'b1;
+          end
+        state[HOLD_STATE]:
+          begin
+            if (hold_clk == 6'hF)
+              state[UPDATE_STATE] <= 1'b1;
+            else
+              state[HOLD_STATE] <= 1'b1;
+          end
+        state[UPDATE_STATE]:
+          begin
+            freq_cnt_o <= testclk_cnt;
+            state[DONE_STATE] <= 1'b1;
+          end
+        state[DONE_STATE]:
+          begin
+            state[DONE_STATE] <= 1'b1;
+          end
+      endcase
+    end
+  end
+
+  assign testclk_rst = state[RESET_STATE];
+  assign testclk_en = state[MEASURE_STATE];
+
+
+  always @(posedge ref_clk_i)
+  begin
+    if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
+      hold_clk <= hold_clk + 1;
+    else
+      hold_clk <= 0;
+  end
+
+  always @(posedge ref_clk_i)
+  begin
+    if (state[MEASURE_STATE] == 1'b1)
+      refclk_cnt <= refclk_cnt + 1;
+    else
+      refclk_cnt <= 0;
+  end
+
+
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v
new file mode 100755
index 0000000..63729c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v
@@ -0,0 +1,346 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal # (
+  parameter integer C_RX_PLL_TYPE = 0,
+  parameter integer C_TX_PLL_TYPE = 0,
+  parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
+  parameter SIM_RESET_SPEEDUP     = "TRUE",
+  parameter C_FREERUN_FREQUENCY   = 100, 
+  parameter REVISION              = 2,
+  parameter C_PCIE_ENABLE         = "FALSE",
+  parameter C_PCIE_CORECLK_FREQ   = 250
+)(
+  // control signals
+  input   wire  [17:0]  TXOUTCLK_PERIOD_IN,
+  input   wire  [17:0]  CNT_TOL_IN,
+  input   wire  [15:0]  FREQ_COUNT_WINDOW_IN,
+  // User Interface
+  input   wire          RESET_IN,
+  input   wire          CLK_IN,
+  input   wire          DRPRST_IN,
+  input   wire  [1:0]   USER_TXPLLCLKSEL,
+  input   wire  [1:0]   USER_RXPLLCLKSEL,
+  input   wire          USER_RXPROGDIVRESET_IN,
+  output  wire          USER_RXPRGDIVRESETDONE_OUT,
+  output  wire          USER_RXPMARESETDONE_OUT,
+  input   wire  [2:0]   USER_RXOUTCLKSEL_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CLR_IN,
+  input   wire          USER_GTRXRESET_IN,
+  input   wire          USER_RXCDRHOLD_IN,
+  input   wire          USER_RXPMARESET_IN,
+  input   wire          USER_TXPROGDIVRESET_IN,
+  output  wire          USER_TXPRGDIVRESETDONE_OUT,
+  input   wire  [2:0]   USER_TXOUTCLKSEL_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CLR_IN,
+  output  wire          USER_CPLLLOCK_OUT,
+  input   wire  [9:0]   USER_CHANNEL_DRPADDR_IN,
+  input   wire  [15:0]  USER_CHANNEL_DRPDI_IN,
+  input   wire          USER_CHANNEL_DRPEN_IN,
+  input   wire          USER_CHANNEL_DRPWE_IN,
+  output  wire          USER_CHANNEL_DRPRDY_OUT,
+  output  wire  [15:0]  USER_CHANNEL_DRPDO_OUT,
+  // Debug Interface
+  output  wire          CPLL_CAL_FAIL,
+  output  wire          CPLL_CAL_DONE,
+  output  wire  [15:0]  DEBUG_OUT,
+  output  wire  [17:0]  CAL_FREQ_CNT,
+  input         [3:0]   REPEAT_RESET_LIMIT,
+  // GT Interface
+  input   wire          GTYE4_TXOUTCLK_IN,
+  input   wire          GTYE4_RXOUTCLK_IN,
+  input   wire          GTYE4_CPLLLOCK_IN,
+  output  wire          GTYE4_CPLLRESET_OUT,
+  output  wire          GTYE4_RXCDRHOLD_OUT,
+  output  wire          GTYE4_GTRXRESET_OUT,
+  output  wire          GTYE4_RXPMARESET_OUT,
+  output  wire          GTYE4_RXPROGDIVRESET_OUT,
+  output  wire  [2:0]   GTYE4_RXOUTCLKSEL_OUT,
+  input   wire          GTYE4_RXPRGDIVRESETDONE_IN,
+  input   wire          GTYE4_RXPMARESETDONE_IN,
+  output  wire          GTYE4_CPLLPD_OUT,
+  output  wire          GTYE4_TXPROGDIVRESET_OUT,
+  output  wire  [2:0]   GTYE4_TXOUTCLKSEL_OUT,
+  input   wire          GTYE4_TXPRGDIVRESETDONE_IN,
+  output  wire  [9:0]   GTYE4_CHANNEL_DRPADDR_OUT,
+  output  wire  [15:0]  GTYE4_CHANNEL_DRPDI_OUT,
+  output  wire          GTYE4_CHANNEL_DRPEN_OUT,
+  output  wire          GTYE4_CHANNEL_DRPWE_OUT,
+  input   wire          GTYE4_CHANNEL_DRPRDY_IN,
+  input   wire  [15:0]  GTYE4_CHANNEL_DRPDO_IN
+);
+
+  wire rx_done;
+  wire tx_done; 
+  
+  wire cal_on_rx_cal_fail;
+  wire cal_on_rx_cal_done; 
+  wire [15:0] cal_on_rx_debug_out; 
+  wire [17:0] cal_on_rx_cal_freq_cnt;
+  wire cal_on_rx_cpllreset_out;
+  wire cal_on_rx_cpllpd_out;
+  wire cal_on_rx_cplllock_out;
+  
+  wire cal_on_rx_drpen_out;
+  wire cal_on_rx_drpwe_out;
+  wire [9:0] cal_on_rx_drpaddr_out;
+  wire [15:0] cal_on_rx_drpdi_out;
+  wire [15:0] cal_on_rx_dout;
+  wire cal_on_rx_drdy;
+
+  wire cal_on_tx_cal_fail;
+  wire cal_on_tx_cal_done; 
+  wire [15:0] cal_on_tx_debug_out; 
+  wire [17:0] cal_on_tx_cal_freq_cnt;
+  wire cal_on_tx_cpllreset_out;
+  wire cal_on_tx_cpllpd_out;
+  wire cal_on_tx_cplllock_out;
+  
+  wire cal_on_tx_drpen_out;
+  wire cal_on_tx_drpwe_out;
+  wire [9:0] cal_on_tx_drpaddr_out;
+  wire [15:0] cal_on_tx_drpdi_out;
+  wire [15:0] cal_on_tx_dout;
+  wire cal_on_tx_drdy;  
+  
+  localparam [9:0]  ADDR_TX_PROGCLK_SEL = 10'h00C;
+  localparam [9:0]  ADDR_TX_PROGDIV_CFG = 10'h057;  // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
+  localparam [9:0]  ADDR_RX_PROGDIV_CFG = 10'h0C6;
+  localparam [9:0]  ADDR_X0E1 = 10'h0E1;
+  localparam [9:0]  ADDR_X079 = 10'h079;
+  localparam [9:0]  ADDR_X114 = 10'h114; 
+  localparam CPLL_CAL_ONLY_TX = (C_RX_PLL_TYPE == C_TX_PLL_TYPE); // If top level configuration of TX and RX PLL TYPE are same, don't use RX Cal block
+
+  wire cpll_cal_on_tx_or_rx;  //1: RX cal block, 0: TX cal block;
+  assign cpll_cal_on_tx_or_rx = CPLL_CAL_ONLY_TX ? 1'b0 : ((USER_TXPLLCLKSEL != 2'b00 && USER_RXPLLCLKSEL == 2'b00) ? 1'b1 : 1'b0); 
+  
+  // TX reset version
+  wire cal_on_tx_reset_in; 
+  assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx;
+  
+  wire cal_on_tx_reset_in_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_resetin_tx_inst (
+    .clk_in   (CLK_IN),
+    .rst_in   (cal_on_tx_reset_in),
+    .rst_out  (cal_on_tx_reset_in_sync)
+  );
+  
+  // RX reset version
+  wire cal_on_rx_reset_in; 
+  assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx;  
+  
+  wire cal_on_rx_reset_in_sync;
+  gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_resetin_rx_inst (
+    .clk_in   (CLK_IN),
+    .rst_in   (cal_on_rx_reset_in),
+    .rst_out  (cal_on_rx_reset_in_sync)
+  );
+
+  wire drprst_in_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_drprst_inst (
+    .clk_in (CLK_IN),
+    .i_in   (DRPRST_IN),
+    .o_out  (drprst_in_sync)
+  );
+
+  gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx #
+  (
+    .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
+    .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
+    .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
+    .C_PCIE_ENABLE(C_PCIE_ENABLE),
+    .C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ)
+  ) gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i
+  (
+    // control signals
+    .TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
+    .CNT_TOL_IN(CNT_TOL_IN),
+    .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
+    // User Interface
+    .RESET_IN(cal_on_tx_reset_in_sync),
+    .CLK_IN(CLK_IN),
+    .USER_TXPLLCLKSEL(USER_TXPLLCLKSEL),
+    .USER_TXPROGDIVRESET_IN(USER_TXPROGDIVRESET_IN),
+    .USER_TXPRGDIVRESETDONE_OUT(USER_TXPRGDIVRESETDONE_OUT),
+    .USER_TXOUTCLKSEL_IN(USER_TXOUTCLKSEL_IN),
+    .USER_TXOUTCLK_BUFG_CE_IN(USER_TXOUTCLK_BUFG_CE_IN),
+    .USER_TXOUTCLK_BUFG_CLR_IN(USER_TXOUTCLK_BUFG_CLR_IN),
+    .USER_CPLLLOCK_OUT(cal_on_tx_cplllock_out),
+    // Debug Interface
+    .CPLL_CAL_FAIL(cal_on_tx_cal_fail),
+    .CPLL_CAL_DONE(cal_on_tx_cal_done),
+    .DEBUG_OUT(cal_on_tx_debug_out),
+    .CAL_FREQ_CNT(cal_on_tx_cal_freq_cnt),
+    .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
+    // GT Interface
+    .GTYE4_TXOUTCLK_IN(GTYE4_TXOUTCLK_IN),
+    .GTYE4_CPLLLOCK_IN(GTYE4_CPLLLOCK_IN),
+    .GTYE4_CPLLRESET_OUT(cal_on_tx_cpllreset_out),
+    .GTYE4_CPLLPD_OUT(cal_on_tx_cpllpd_out),
+    .GTYE4_TXPROGDIVRESET_OUT(GTYE4_TXPROGDIVRESET_OUT),
+    .GTYE4_TXOUTCLKSEL_OUT(GTYE4_TXOUTCLKSEL_OUT),
+    .GTYE4_TXPRGDIVRESETDONE_IN(GTYE4_TXPRGDIVRESETDONE_IN),
+    .GTYE4_CHANNEL_DRPADDR_OUT(cal_on_tx_drpaddr_out),
+    .GTYE4_CHANNEL_DRPDI_OUT(cal_on_tx_drpdi_out),
+    .GTYE4_CHANNEL_DRPEN_OUT(cal_on_tx_drpen_out),
+    .GTYE4_CHANNEL_DRPWE_OUT(cal_on_tx_drpwe_out),
+    .GTYE4_CHANNEL_DRPRDY_IN(cal_on_tx_drdy),
+    .GTYE4_CHANNEL_DRPDO_IN(cal_on_tx_dout),
+    .DONE(tx_done)
+  );  
+  
+  gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_rx #
+  (
+    .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
+    .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
+    .CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX),
+    .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY)
+  ) gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_rx_i
+  (
+    // control signals
+    .RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
+    .CNT_TOL_IN(CNT_TOL_IN),
+    .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
+    // User Interface
+    .RESET_IN(cal_on_rx_reset_in_sync),
+    .CLK_IN(CLK_IN),
+    .USER_RXPROGDIVRESET_IN(USER_RXPROGDIVRESET_IN),
+    .USER_RXPRGDIVRESETDONE_OUT(USER_RXPRGDIVRESETDONE_OUT),
+    .USER_RXPMARESETDONE_OUT(USER_RXPMARESETDONE_OUT),
+    .USER_RXOUTCLKSEL_IN(USER_RXOUTCLKSEL_IN),
+    .USER_RXOUTCLK_BUFG_CE_IN(USER_RXOUTCLK_BUFG_CE_IN),
+    .USER_RXOUTCLK_BUFG_CLR_IN(USER_RXOUTCLK_BUFG_CLR_IN),
+    .USER_CPLLLOCK_OUT(cal_on_rx_cplllock_out),
+    .USER_RXCDRHOLD_IN(USER_RXCDRHOLD_IN),
+    .USER_GTRXRESET_IN(USER_GTRXRESET_IN),
+    .USER_RXPMARESET_IN(USER_RXPMARESET_IN),
+    // Debug Interface
+    .CPLL_CAL_FAIL(cal_on_rx_cal_fail),
+    .CPLL_CAL_DONE(cal_on_rx_cal_done),
+    .DEBUG_OUT(cal_on_rx_debug_out),
+    .CAL_FREQ_CNT(cal_on_rx_cal_freq_cnt),
+    .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
+    // GT Interface
+    .GTYE4_RXOUTCLK_IN(GTYE4_RXOUTCLK_IN),
+    .GTYE4_CPLLLOCK_IN(GTYE4_CPLLLOCK_IN),
+    .GTYE4_CPLLRESET_OUT(cal_on_rx_cpllreset_out),
+    .GTYE4_CPLLPD_OUT(cal_on_rx_cpllpd_out),
+    .GTYE4_RXPROGDIVRESET_OUT(GTYE4_RXPROGDIVRESET_OUT),
+    .GTYE4_RXOUTCLKSEL_OUT(GTYE4_RXOUTCLKSEL_OUT),
+    .GTYE4_RXPRGDIVRESETDONE_IN(GTYE4_RXPRGDIVRESETDONE_IN),
+    .GTYE4_CHANNEL_DRPADDR_OUT(cal_on_rx_drpaddr_out),
+    .GTYE4_CHANNEL_DRPDI_OUT(cal_on_rx_drpdi_out),
+    .GTYE4_CHANNEL_DRPEN_OUT(cal_on_rx_drpen_out),
+    .GTYE4_CHANNEL_DRPWE_OUT(cal_on_rx_drpwe_out),
+    .GTYE4_CHANNEL_DRPRDY_IN(cal_on_rx_drdy),
+    .GTYE4_CHANNEL_DRPDO_IN(cal_on_rx_dout),
+    .GTYE4_GTRXRESET_OUT(GTYE4_GTRXRESET_OUT),
+    .GTYE4_RXPMARESET_OUT(GTYE4_RXPMARESET_OUT),
+    .GTYE4_RXCDRHOLD_OUT(GTYE4_RXCDRHOLD_OUT),
+    .GTYE4_RXPMARESETDONE_IN(GTYE4_RXPMARESETDONE_IN),
+    .DONE(rx_done)
+  );
+  
+  //OR with TX versions
+  assign GTYE4_CPLLRESET_OUT = cal_on_rx_cpllreset_out | cal_on_tx_cpllreset_out; 
+  assign GTYE4_CPLLPD_OUT = cal_on_rx_cpllpd_out | cal_on_tx_cpllpd_out;
+  assign USER_CPLLLOCK_OUT = cal_on_rx_cplllock_out | cal_on_tx_cplllock_out;
+
+  //Mux the debug signals out
+  assign CPLL_CAL_DONE = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_done : cal_on_tx_cal_done;
+  assign CPLL_CAL_FAIL = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_fail : cal_on_tx_cal_fail;
+  assign DEBUG_OUT = cpll_cal_on_tx_or_rx ? cal_on_rx_debug_out : cal_on_tx_debug_out;
+  assign CAL_FREQ_CNT = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_freq_cnt : cal_on_tx_cal_freq_cnt;
+  
+  //----------------------------------------------------------------------------------------------
+  // DRP ARBITER
+  //----------------------------------------------------------------------------------------------
+  
+  gtwizard_ultrascale_v1_7_9_gte4_drp_arb #
+  (
+    .ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL),
+    .ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG),
+    .ADDR_RX_PROGDIV_CFG(ADDR_RX_PROGDIV_CFG),
+    .ADDR_X0E1(ADDR_X0E1),
+    .ADDR_X079(ADDR_X079),
+    .ADDR_X114(ADDR_X114),
+    .C_NUM_CLIENTS(3),
+    .C_ADDR_WIDTH(10),
+    .C_DATA_WIDTH(16)
+  ) gtwizard_ultrascale_v1_7_9_gte4_drp_arb_i
+  (
+    .DCLK_I         (CLK_IN),
+    .RESET_I        (drprst_in_sync),
+    .DEN_USR_I      ({cal_on_tx_drpen_out, cal_on_rx_drpen_out, USER_CHANNEL_DRPEN_IN}),
+    .DWE_USR_I      ({cal_on_tx_drpwe_out, cal_on_rx_drpwe_out, USER_CHANNEL_DRPWE_IN}),
+    .DADDR_USR_I    ({cal_on_tx_drpaddr_out, cal_on_rx_drpaddr_out, USER_CHANNEL_DRPADDR_IN}),
+    .DI_USR_I       ({cal_on_tx_drpdi_out, cal_on_rx_drpdi_out, USER_CHANNEL_DRPDI_IN}),
+    .DO_USR_O       ({cal_on_tx_dout, cal_on_rx_dout, USER_CHANNEL_DRPDO_OUT}),
+    .DRDY_USR_O     ({cal_on_tx_drdy, cal_on_rx_drdy, USER_CHANNEL_DRPRDY_OUT}),
+    // arbitrated port
+    .DEN_O          (GTYE4_CHANNEL_DRPEN_OUT),
+    .DWE_O          (GTYE4_CHANNEL_DRPWE_OUT),
+    .DADDR_O        (GTYE4_CHANNEL_DRPADDR_OUT),
+    .DI_O           (GTYE4_CHANNEL_DRPDI_OUT),
+    .DO_I           (GTYE4_CHANNEL_DRPDO_IN),
+    .DRDY_I         (GTYE4_CHANNEL_DRPRDY_IN),
+    .TX_CAL_DONE_I  (tx_done),
+    .RX_CAL_DONE_I  (rx_done)
+  );
+
+endmodule //CPLL_CAL
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v
new file mode 100755
index 0000000..b2f12c2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v
@@ -0,0 +1,1091 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_rx # (
+  parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
+  parameter SIM_RESET_SPEEDUP     = "TRUE",
+  parameter CPLL_CAL_ONLY_TX      = 1,
+  parameter C_FREERUN_FREQUENCY   = 100
+)(
+  // control signals
+  input   wire  [17:0]  RXOUTCLK_PERIOD_IN,
+  input   wire  [17:0]  CNT_TOL_IN,
+  input   wire  [15:0]  FREQ_COUNT_WINDOW_IN,
+  // User Interface
+  input   wire          RESET_IN,
+  input   wire          CLK_IN,
+  
+  input   wire          USER_RXPROGDIVRESET_IN,
+  output  wire          USER_RXPRGDIVRESETDONE_OUT,
+  output  wire          USER_RXPMARESETDONE_OUT,
+  input   wire  [2:0]   USER_RXOUTCLKSEL_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_RXOUTCLK_BUFG_CLR_IN,
+  output  reg           USER_CPLLLOCK_OUT,
+  input   wire          USER_GTRXRESET_IN, 
+  input   wire          USER_RXCDRHOLD_IN,
+  input   wire          USER_RXPMARESET_IN,
+  // Debug Interface
+  output  wire          CPLL_CAL_FAIL,
+  output  wire          CPLL_CAL_DONE,
+  output  wire  [15:0]  DEBUG_OUT,
+  output  wire  [17:0]  CAL_FREQ_CNT,
+  input         [3:0]   REPEAT_RESET_LIMIT,
+  // GT Interface
+  input   wire          GTYE4_RXOUTCLK_IN,
+  input   wire          GTYE4_CPLLLOCK_IN,
+  output  wire          GTYE4_CPLLRESET_OUT,
+  output  wire          GTYE4_CPLLPD_OUT,
+  output  wire          GTYE4_RXPROGDIVRESET_OUT,
+  output  wire   [2:0]  GTYE4_RXOUTCLKSEL_OUT,
+  input   wire          GTYE4_RXPRGDIVRESETDONE_IN,
+  output  wire  [9:0]   GTYE4_CHANNEL_DRPADDR_OUT,
+  output  wire  [15:0]  GTYE4_CHANNEL_DRPDI_OUT,
+  output  wire          GTYE4_CHANNEL_DRPEN_OUT,
+  output  wire          GTYE4_CHANNEL_DRPWE_OUT,
+  input   wire          GTYE4_CHANNEL_DRPRDY_IN,
+  input   wire  [15:0]  GTYE4_CHANNEL_DRPDO_IN, 
+  output  wire          GTYE4_GTRXRESET_OUT,
+  output  wire          GTYE4_RXPMARESET_OUT,
+  output  wire          GTYE4_RXCDRHOLD_OUT,
+  input   wire          GTYE4_RXPMARESETDONE_IN,
+  output  wire          DONE
+);
+
+generate if (CPLL_CAL_ONLY_TX == 1)
+begin: gen_cal_rx_dis
+  assign GTYE4_RXPROGDIVRESET_OUT   =   USER_RXPROGDIVRESET_IN;
+  assign GTYE4_GTRXRESET_OUT        =   USER_GTRXRESET_IN; 
+  assign GTYE4_RXOUTCLKSEL_OUT      =   USER_RXOUTCLKSEL_IN;
+  assign GTYE4_RXCDRHOLD_OUT        =   USER_RXCDRHOLD_IN;
+  assign GTYE4_RXPMARESET_OUT       =   USER_RXPMARESET_IN; 
+  assign USER_RXPRGDIVRESETDONE_OUT =   GTYE4_RXPRGDIVRESETDONE_IN;
+  assign USER_RXPMARESETDONE_OUT    =   GTYE4_RXPMARESETDONE_IN; 
+  assign  CPLL_CAL_DONE              =  1'd0;
+  assign  CPLL_CAL_FAIL              =  1'd0;
+  assign  DONE                       =  1'd1;
+  assign  GTYE4_CHANNEL_DRPEN_OUT    =  1'd0;
+  assign  GTYE4_CHANNEL_DRPWE_OUT    =  1'd0;
+  assign  GTYE4_CPLLPD_OUT           =  1'd0;
+  assign  GTYE4_CPLLRESET_OUT        =  1'd0;
+  assign  DEBUG_OUT                  = 16'd0;
+  assign  GTYE4_CHANNEL_DRPDI_OUT    = 16'd0;
+  assign  CAL_FREQ_CNT               = 18'd0;
+  assign  GTYE4_CHANNEL_DRPADDR_OUT  = 10'd0;
+
+  always @(posedge CLK_IN) begin
+    if(RESET_IN)
+    	USER_CPLLLOCK_OUT <= 1'b0;
+    else
+    	USER_CPLLLOCK_OUT <= 1'b0;
+  end
+
+end
+else
+begin: gen_cal_rx_en
+
+  //DRP FSM
+  localparam DRP_WAIT      = 0;
+  localparam DRP_READ      = 1;
+  localparam DRP_READ_ACK  = 2;
+  localparam DRP_MODIFY    = 3;
+  localparam DRP_WRITE     = 4;
+  localparam DRP_WRITE_ACK = 5;
+  localparam DRP_DONE      = 6;
+
+  localparam RESET                = 0;
+  localparam READ_X114            = 1;
+  localparam CHECK_X114_STATUS    = 2;
+  localparam READ_PROGDIV_CFG     = 3;
+  localparam SAVE_PROGDIV_CFG     = 4;
+  localparam MODIFY_PROGDIV       = 5; 
+  localparam MODIFY_RXOUTCLK_SEL  = 6;
+  localparam ASSERT_RXCDRHOLD     = 7;
+  localparam ASSERT_CPLLPD        = 8;
+  localparam DEASSERT_CPLLPD      = 9;
+  localparam ASSERT_CPLLRESET     = 10;
+  localparam DEASSERT_CPLLRESET   = 11;
+  localparam WAIT_GTCPLLLOCK      = 12;
+  localparam ASSERT_GTRXRESET     = 13;
+  localparam WAIT_RXPMARESETDONE  = 14;
+  localparam WAIT_RXPMARESETDONE_DEASSERT = 15; 
+  localparam WAIT_RXPMARESETDONE_2        = 16;
+  localparam ASSERT_PROGDIVRESET  = 17;
+  localparam WAIT_PRGDIVRESETDONE = 18;
+  localparam CHECK_FREQ           = 19;
+  localparam RESTORE_READ_X114    = 20; 
+  localparam RESTORE_PROGDIV      = 21;
+  localparam CLEAR_FLAG_x114      = 22;
+  localparam WAIT_GTCPLLLOCK2     = 23;
+  localparam ASSERT_PROGDIVRESET2 = 24;
+  localparam WAIT_PRGDIVRESETDONE2= 25;
+  localparam CAL_FAIL             = 26;
+  localparam CAL_DONE             = 27;
+  
+  reg [31:0] cpll_cal_state = 31'd0;
+  wire [4:0] cpll_cal_state_bin;
+  reg [6:0] drp_state = 7'd1;
+  wire drp_done;
+  reg [9:0] daddr = 10'd0;
+  reg [15:0] di = 16'd0;
+  wire drdy;
+  wire [15:0] dout;
+  reg den = 1'b0;
+  reg dwe = 1'b0;
+  reg wr = 1'b0;
+  reg rd = 1'b0;
+  reg [15:0] di_msk;
+  reg [15:0] mask;
+  reg [24:0] wait_ctr;
+  reg [3:0] repeat_ctr;
+  reg [15:0] progdiv_cfg_store = 16'd0;
+  reg mask_user_in = 1'b0;
+  reg cpllreset_int = 1'b0;
+  reg cpllpd_int = 1'b0;
+  reg rxprogdivreset_int = 1'b0;
+  reg rxcdrhold_int = 1'b0; 
+  reg gtrxreset_int = 1'b0;
+  reg [2:0] rxoutclksel_int = 3'b000;
+  reg cal_fail_store = 1'b0;
+  reg status_store = 1'b0;
+  wire den_i; 
+  wire dwe_i;
+  
+  //All these need to be based on CLK_IN frequency (free_run) 
+  localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY );  // 1 ms
+  localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY );         // 1 ms 
+  localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY );   // 100 us 
+  localparam [24:0] SYNTH_WAIT_ASSERT_PROGDIVRESET = C_FREERUN_FREQUENCY ;   // 1 us 
+
+  localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10; 
+  localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
+  localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;  
+  localparam [24:0] SIM_WAIT_ASSERT_PROGDIVRESET = SYNTH_WAIT_ASSERT_PROGDIVRESET/10;
+  
+  localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
+  localparam [4:0]  WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
+  localparam [24:0] WAIT_ASSERT_CPLLRESET =
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_ASSERT_CPLLRESET;
+  localparam [4:0]  WAIT_ASSERT_CPLLPD = 5'd25;  // >= 100 ns
+  localparam [24:0] WAIT_DEASSERT_CPLLRESET =  
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_DEASSERT_CPLLRESET;
+  localparam [24:0] WAIT_CPLLLOCK = 
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
+    //pragma translate_on
+                                        SYNTH_WAIT_CPLLLOCK;
+  
+  localparam [24:0] WAIT_ASSERT_PROGDIVRESET = 
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_PROGDIVRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_ASSERT_PROGDIVRESET;  
+
+
+  localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
+  localparam [2:0]  MOD_RXOUTCLK_SEL = 3'b101;
+  localparam [9:0]  ADDR_RX_PROGDIV_CFG = 10'h0C6; 
+  localparam [9:0]  ADDR_X114 = 10'h114;
+
+  // Drive RXOUTCLK with BUFG_GT-buffered source clock, divider = 1
+  wire rxoutclkmon;
+  //assign rxoutclkmon = GTYE4_RXOUTCLK_IN;
+  BUFG_GT bufg_gt_rxoutclkmon_inst (
+    .CE      (USER_RXOUTCLK_BUFG_CE_IN),
+    .CEMASK  (1'b1),
+    .CLR     (USER_RXOUTCLK_BUFG_CLR_IN),
+    .CLRMASK (1'b1),
+    .DIV     (3'b000),
+    .I       (GTYE4_RXOUTCLK_IN),
+    .O       (rxoutclkmon)
+  );
+
+  wire gtye4_cplllock_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_cplllock_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTYE4_CPLLLOCK_IN),
+    .o_out  (gtye4_cplllock_sync)
+  );
+
+  wire gtye4_rxpmaresetdone_sync; 
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_rxpmaresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTYE4_RXPMARESETDONE_IN),
+    .o_out  (gtye4_rxpmaresetdone_sync)
+  );
+  
+  wire gtye4_rxprgdivresetdone_sync; 
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_rxprgdivresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTYE4_RXPRGDIVRESETDONE_IN),
+    .o_out  (gtye4_rxprgdivresetdone_sync)
+  );  
+
+  assign GTYE4_CPLLRESET_OUT = cpllreset_int;
+  assign GTYE4_CPLLPD_OUT = cpllpd_int;
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
+      USER_CPLLLOCK_OUT <= 1'b0;
+    else
+      USER_CPLLLOCK_OUT <= gtye4_cplllock_sync;
+  end
+
+  assign GTYE4_RXPROGDIVRESET_OUT = mask_user_in ? rxprogdivreset_int : USER_RXPROGDIVRESET_IN;
+  assign GTYE4_GTRXRESET_OUT = mask_user_in ? gtrxreset_int : USER_GTRXRESET_IN; 
+  assign GTYE4_RXOUTCLKSEL_OUT = mask_user_in ? rxoutclksel_int : USER_RXOUTCLKSEL_IN;
+  assign GTYE4_RXCDRHOLD_OUT = mask_user_in ? rxcdrhold_int : USER_RXCDRHOLD_IN;
+  assign GTYE4_RXPMARESET_OUT = mask_user_in ? 1'b0 : USER_RXPMARESET_IN; 
+  assign USER_RXPRGDIVRESETDONE_OUT = mask_user_in ? 1'b0 : GTYE4_RXPRGDIVRESETDONE_IN;
+  assign USER_RXPMARESETDONE_OUT = mask_user_in ? 1'b0 : GTYE4_RXPMARESETDONE_IN; 
+
+  // frequency counter for rxoutclk
+  wire [17:0] rxoutclk_freq_cnt;
+  reg freq_counter_rst = 1'b1;
+  wire freq_cnt_done;
+  gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_freq_counter U_RXOUTCLK_FREQ_COUNTER
+  (
+    .freq_cnt_o(rxoutclk_freq_cnt),
+    .done_o(freq_cnt_done),
+    .rst_i(freq_counter_rst),
+    .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
+    .ref_clk_i(CLK_IN),
+    .test_clk_i(rxoutclkmon)
+  );
+
+  //Debug signals
+  assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gtye4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
+  assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
+  assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
+  assign CAL_FREQ_CNT = rxoutclk_freq_cnt;
+  assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
+
+  //pragma translate_off
+  if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
+  begin: gen_sim_cpll_cal_bypass_gtye4
+    //CPLL CAL FSM for simulation
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        rxprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+        rxcdrhold_int <= 1'b0;
+        gtrxreset_int <= 1'b0;
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]: 
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X114]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X114_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X114_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end          
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_RXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_RXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_RXCDRHOLD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_RXCDRHOLD]:
+          begin
+            rxcdrhold_int <= 1'b1;
+            cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            cpllreset_int <= 1'b1;
+            freq_counter_rst <= 1'b1;
+            cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            wait_ctr <= 25'd0;
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(!gtye4_cplllock_sync) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[ASSERT_GTRXRESET]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              gtrxreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+            end
+            else begin
+              gtrxreset_int <= 1'b0;
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+
+          cpll_cal_state[WAIT_RXPMARESETDONE]:
+          begin
+            if (gtye4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+            end 
+          end  
+
+          cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT]:
+          begin
+            if (!gtye4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end 
+          end  
+          
+          cpll_cal_state[WAIT_RXPMARESETDONE_2]:
+          begin
+            if (gtye4_rxpmaresetdone_sync) begin
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end 
+          end    
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+          begin
+            if (gtye4_rxprgdivresetdone_sync) begin
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+              freq_counter_rst <= 1'b0;
+            end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_FREQ]:
+          begin
+            if(freq_cnt_done) begin
+              if ((rxoutclk_freq_cnt >= (RXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (rxoutclk_freq_cnt <= (RXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                cal_fail_store <= 1'b0;
+              end
+              else begin
+                if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                  cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+                  repeat_ctr <= repeat_ctr + 1'b1;
+                end
+                else begin
+                  cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                  cal_fail_store <= 1'b1;
+                end
+              end
+            end
+            else
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+          end
+          
+          cpll_cal_state[RESTORE_READ_X114]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X114] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x114]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+         
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gtye4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gtye4_rxprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+
+  end
+  else
+  begin: gen_cpll_cal_gtye4_rx
+  //pragma translate_on
+    //CPLL CAL FSM
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        rxprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+        rxcdrhold_int <= 1'b0;
+        gtrxreset_int <= 1'b0;        
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]: 
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X114]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X114_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X114] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X114_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end          
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_RXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_RXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_RXCDRHOLD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_RXCDRHOLD]:
+          begin
+            rxcdrhold_int <= 1'b1;
+            cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;                 
+            end
+            else begin
+              cpllpd_int <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+            end
+            else begin
+              cpllpd_int <= 1'b0;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+              freq_counter_rst <= 1'b1;
+            end
+          end 
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b1;
+              freq_counter_rst <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(wait_ctr < WAIT_CPLLLOCK) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= wait_ctr + 1'b1;
+            end
+            else begin
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[ASSERT_GTRXRESET]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              gtrxreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_GTRXRESET] <= 1'b1;
+            end
+            else begin
+              gtrxreset_int <= 1'b0;
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+
+          cpll_cal_state[WAIT_RXPMARESETDONE]:
+          begin
+            if (gtye4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE] <= 1'b1;
+            end 
+          end  
+          
+          cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT]:
+          begin
+            if (!gtye4_rxpmaresetdone_sync) begin
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_DEASSERT] <= 1'b1;
+            end 
+          end  
+          
+          cpll_cal_state[WAIT_RXPMARESETDONE_2]:
+          begin
+            if (gtye4_rxpmaresetdone_sync) begin
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin 
+              cpll_cal_state[WAIT_RXPMARESETDONE_2] <= 1'b1;
+            end 
+          end    
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+          begin
+            if (gtye4_rxprgdivresetdone_sync) begin
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+              freq_counter_rst <= 1'b0;
+            end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_FREQ]:
+          begin
+            if(freq_cnt_done) begin
+              if ((rxoutclk_freq_cnt >= (RXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (rxoutclk_freq_cnt <= (RXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                cal_fail_store <= 1'b0;
+              end
+              else begin
+                if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                  cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+                  repeat_ctr <= repeat_ctr + 1'b1;
+                end
+                else begin
+                  cpll_cal_state[RESTORE_READ_X114] <= 1'b1;
+                  cal_fail_store <= 1'b1;
+                end
+              end
+            end
+            else
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+          end
+          
+          cpll_cal_state[RESTORE_READ_X114]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X114] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x114]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x114] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gtye4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              rxprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              rxprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gtye4_rxprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            rxcdrhold_int <= 1'b0;
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            rxcdrhold_int <= 1'b0;          
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+  
+  //pragma translate_off
+  end
+  //pragma translate_on
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET])
+      rxoutclksel_int <= 3'b0;
+    else if (cpll_cal_state[MODIFY_RXOUTCLK_SEL])
+      rxoutclksel_int <= MOD_RXOUTCLK_SEL;
+    else 
+      rxoutclksel_int <= rxoutclksel_int;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET]) begin
+      daddr <= 10'h000;
+      mask  <= 16'b1111_1111_1111_1111;
+    end
+    else if (cpll_cal_state[READ_X114] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X114] | cpll_cal_state[CLEAR_FLAG_x114]) begin 
+      daddr <= ADDR_X114;
+    end
+    else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
+      daddr <= ADDR_RX_PROGDIV_CFG;
+    end
+  end
+
+  assign drp_done = drp_state[DRP_DONE];
+  assign GTYE4_CHANNEL_DRPEN_OUT = den;
+  assign GTYE4_CHANNEL_DRPWE_OUT = dwe;
+  assign GTYE4_CHANNEL_DRPADDR_OUT = daddr;
+  assign GTYE4_CHANNEL_DRPDI_OUT = di;
+  assign drdy = GTYE4_CHANNEL_DRPRDY_IN; 
+  assign dout = GTYE4_CHANNEL_DRPDO_IN; 
+  
+  always @(posedge CLK_IN) begin
+  if (RESET_IN) begin
+    den <= 1'b0;
+    dwe <= 1'b0;
+    di <= 16'h0000;
+    drp_state <= 0;
+    drp_state[DRP_WAIT] <= 1'b1;
+  end
+  else begin
+    drp_state <= 0;
+    case (1'b1) // synthesis parallel_case full_case
+        drp_state[DRP_WAIT]:
+        begin
+          if (rd) drp_state[DRP_READ] <= 1'b1;
+          else if (wr) drp_state[DRP_WRITE] <= 1'b1;
+          else         drp_state[DRP_WAIT] <= 1'b1;
+        end
+        drp_state[DRP_READ]:
+        begin
+          den <= 1'b1;
+          drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_READ_ACK]:
+        begin
+          den <= 1'b0;
+          if (drdy == 1'b1) begin
+            if (rd) drp_state[DRP_DONE] <= 1'b1;
+            else    drp_state[DRP_MODIFY] <= 1'b1;
+          end
+          else      drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_MODIFY]:
+        begin
+          drp_state[DRP_WRITE] <= 1'b1;
+        end
+        drp_state[DRP_WRITE]:
+        begin
+          den <= 1'b1;
+          dwe <= 1'b1;
+          di <= di_msk;
+          drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_WRITE_ACK]:
+        begin
+          den <= 1'b0;
+          dwe <= 1'b0;
+          if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
+          else              drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_DONE]:
+        begin
+          drp_state[DRP_WAIT] <= 1'b1;
+        end
+    endcase
+  end
+  end 
+
+    //debug logic - convert one hot state to binary
+  genvar i,j;
+    for (j=0; j<5; j=j+1)
+    begin : jl
+      wire [32-1:0] tmp_mask;
+      for (i=0; i<32; i=i+1)
+      begin : il
+        assign tmp_mask[i] = i[j];
+      end
+      assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
+    end
+  
+end
+endgenerate
+endmodule //CPLL_CAL  
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v
new file mode 100755
index 0000000..363f439
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v
@@ -0,0 +1,1175 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx # (
+  parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
+  parameter SIM_RESET_SPEEDUP     = "TRUE",
+  parameter C_FREERUN_FREQUENCY   = 100, 
+  parameter REVISION              = 2,
+  parameter C_PCIE_ENABLE         = "FALSE",
+  parameter C_PCIE_CORECLK_FREQ   = 250
+)(
+  // control signals
+  input   wire  [17:0]  TXOUTCLK_PERIOD_IN,
+  input   wire  [17:0]  CNT_TOL_IN,
+  input   wire  [15:0]  FREQ_COUNT_WINDOW_IN,
+  // User Interface
+  input   wire          RESET_IN,
+  input   wire          CLK_IN,
+  
+  input   wire  [1:0]   USER_TXPLLCLKSEL,
+  input   wire          USER_TXPROGDIVRESET_IN,
+  output  reg           USER_TXPRGDIVRESETDONE_OUT,
+  input   wire  [2:0]   USER_TXOUTCLKSEL_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CE_IN,
+  input   wire          USER_TXOUTCLK_BUFG_CLR_IN,
+  output  reg           USER_CPLLLOCK_OUT,
+  // Debug Interface
+  output  wire          CPLL_CAL_FAIL,
+  output  wire          CPLL_CAL_DONE,
+  output  wire  [15:0]  DEBUG_OUT,
+  output  wire  [17:0]  CAL_FREQ_CNT,
+  input         [3:0]   REPEAT_RESET_LIMIT,
+  // GT Interface
+  input   wire          GTYE4_TXOUTCLK_IN,
+  input   wire          GTYE4_CPLLLOCK_IN,
+  output  wire          GTYE4_CPLLRESET_OUT,
+  output  wire          GTYE4_CPLLPD_OUT,
+  output  reg           GTYE4_TXPROGDIVRESET_OUT,
+  output  reg   [2:0]   GTYE4_TXOUTCLKSEL_OUT,
+  input   wire          GTYE4_TXPRGDIVRESETDONE_IN,
+  output  wire  [9:0]   GTYE4_CHANNEL_DRPADDR_OUT,
+  output  wire  [15:0]  GTYE4_CHANNEL_DRPDI_OUT,
+  output  wire          GTYE4_CHANNEL_DRPEN_OUT,
+  output  wire          GTYE4_CHANNEL_DRPWE_OUT,
+  input   wire          GTYE4_CHANNEL_DRPRDY_IN,
+  input   wire  [15:0]  GTYE4_CHANNEL_DRPDO_IN,
+  output  wire          DONE
+);
+
+  //DRP FSM
+  localparam DRP_WAIT      = 0;
+  localparam DRP_READ      = 1;
+  localparam DRP_READ_ACK  = 2;
+  localparam DRP_MODIFY    = 3;
+  localparam DRP_WRITE     = 4;
+  localparam DRP_WRITE_ACK = 5;
+  localparam DRP_DONE      = 6;
+
+  localparam RESET                = 0;
+  localparam READ_X0E1            = 1;
+  localparam CHECK_X0E1_STATUS    = 2;
+  localparam READ_PROGCLK_SEL     = 3;
+  localparam SAVE_PROGCLK_SEL     = 4;
+  localparam READ_X079            = 5;
+  localparam CHECK_X079_STATUS    = 6; 
+  localparam READ_PROGDIV_CFG     = 7;
+  localparam SAVE_PROGDIV_CFG     = 8;
+  localparam READ_X0E1_BEFORE_PROGCLK_SEL_MOD = 9;
+  localparam MODIFY_PROGCLK_SEL   = 10;
+  localparam MODIFY_PROGDIV       = 11; 
+  localparam MODIFY_TXOUTCLK_SEL  = 12;
+  localparam ASSERT_CPLLPD        = 13;
+  localparam DEASSERT_CPLLPD      = 14;
+  localparam ASSERT_CPLLRESET     = 15;
+  localparam DEASSERT_CPLLRESET   = 16;
+  localparam WAIT_GTCPLLLOCK      = 17;
+  localparam ASSERT_PROGDIVRESET  = 18;
+  localparam WAIT_PRGDIVRESETDONE = 19;
+  localparam CHECK_FREQ           = 20;
+  localparam RESTORE_READ_X0E1    = 21; 
+  localparam RESTORE_READ_X079    = 22;
+  localparam RESTORE_PROGDIV      = 23;
+  localparam RESTORE_PROGCLK_SEL  = 24;
+  localparam CLEAR_FLAG_x0E1      = 25; 
+  localparam CLEAR_FLAG_x079      = 26; 
+  localparam WAIT_GTCPLLLOCK2     = 27;
+  localparam ASSERT_PROGDIVRESET2 = 28;
+  localparam WAIT_PRGDIVRESETDONE2= 29;
+  localparam CAL_FAIL             = 30;
+  localparam CAL_DONE             = 31;
+  
+  reg [31:0] cpll_cal_state = 31'd0;
+  wire [4:0] cpll_cal_state_bin;
+  reg [6:0] drp_state = 7'd1;
+  wire drp_done;
+  reg [9:0] daddr = 10'd0;
+  reg [15:0] di = 16'd0;
+  wire drdy;
+  wire [15:0] dout;
+  reg den = 1'b0;
+  reg dwe = 1'b0;
+  reg wr = 1'b0;
+  reg rd = 1'b0;
+  reg [15:0] di_msk;
+  reg [15:0] mask;
+  reg [24:0] wait_ctr;
+  reg [3:0] repeat_ctr;
+  reg [15:0] progclk_sel_store = 16'd0;
+  reg [15:0] progdiv_cfg_store = 16'd0;
+  reg fboost_store = 1'b0;
+  reg mask_user_in = 1'b0;
+  reg cpllreset_int = 1'b0;
+  reg cpllpd_int = 1'b0;
+  reg txprogdivreset_int = 1'b0;
+  reg [2:0] txoutclksel_int = 3'b000;
+  reg cal_fail_store = 1'b0;
+  reg [15:0] x0e1_store = 16'd0;
+  
+  reg status_store = 1'b0;
+  wire den_i; 
+  wire dwe_i;
+  
+  //All these need to be based on CLK_IN frequency (free_run) 
+  localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY);  // 1 ms
+  localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY);         // 1 ms 
+  localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY);   // 100 us 
+
+  localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10; 
+  localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
+  localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;  
+  
+  localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
+  localparam [4:0]  WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
+  localparam [24:0] WAIT_ASSERT_CPLLRESET =
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_ASSERT_CPLLRESET;
+  localparam [4:0]  WAIT_ASSERT_CPLLPD = 5'd25;  // >= 100 ns
+  localparam [24:0] WAIT_DEASSERT_CPLLRESET =  
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
+    //pragma translate_on
+                                        SYNTH_WAIT_DEASSERT_CPLLRESET;
+  localparam [24:0] WAIT_CPLLLOCK = 
+    //pragma translate_off
+    (SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
+    //pragma translate_on
+                                        SYNTH_WAIT_CPLLLOCK;
+
+
+  localparam [1:0]  MOD_PROGCLK_SEL = 2'b10;
+  localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
+  localparam [2:0]  MOD_TXOUTCLK_SEL = 3'b101;
+  localparam [9:0]  ADDR_TX_PROGCLK_SEL = 10'h00C;
+  localparam [9:0]  ADDR_TX_PROGDIV_CFG = 10'h057; //GTY /GTH addresses are different  (003E in GTH; 0057 in GTY)
+  localparam [9:0]  ADDR_X0E1 = 10'h0E1;
+  localparam [9:0]  ADDR_X079 = 10'h079;
+
+  // Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
+  wire txoutclkmon;
+  //assign txoutclkmon = GTYE4_TXOUTCLK_IN;
+  BUFG_GT bufg_gt_txoutclkmon_inst (
+    .CE      (USER_TXOUTCLK_BUFG_CE_IN),
+    .CEMASK  (1'b1),
+    .CLR     (USER_TXOUTCLK_BUFG_CLR_IN),
+    .CLRMASK (1'b1),
+    .DIV     (3'b000),
+    .I       (GTYE4_TXOUTCLK_IN),
+    .O       (txoutclkmon)
+  );
+
+  wire gtye4_cplllock_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_cplllock_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTYE4_CPLLLOCK_IN),
+    .o_out  (gtye4_cplllock_sync)
+  );
+
+  wire user_txprogdivreset_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXPROGDIVRESET_IN),
+    .o_out  (user_txprogdivreset_sync)
+  );
+
+  wire gtye4_txprgdivresetdone_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
+    .clk_in (CLK_IN),
+    .i_in   (GTYE4_TXPRGDIVRESETDONE_IN),
+    .o_out  (gtye4_txprgdivresetdone_sync)
+  );
+  
+  wire [2:0] user_txoutclksel_sync;
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[0]),
+    .o_out  (user_txoutclksel_sync[0])
+  );
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[1]),
+    .o_out  (user_txoutclksel_sync[1])
+  );
+  gtwizard_ultrascale_v1_7_9_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
+    .clk_in (CLK_IN),
+    .i_in   (USER_TXOUTCLKSEL_IN[2]),
+    .o_out  (user_txoutclksel_sync[2])
+  );
+
+
+  assign GTYE4_CPLLRESET_OUT = cpllreset_int;
+  assign GTYE4_CPLLPD_OUT = cpllpd_int;
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
+      USER_CPLLLOCK_OUT <= 1'b0;
+    else
+      USER_CPLLLOCK_OUT <= gtye4_cplllock_sync;
+  end
+
+  generate if (C_PCIE_ENABLE) 
+  begin : pcie_txoutclksel 
+    always @(*) begin 
+      GTYE4_TXOUTCLKSEL_OUT <= mask_user_in ? txoutclksel_int : USER_TXOUTCLKSEL_IN; 
+      GTYE4_TXPROGDIVRESET_OUT <= mask_user_in ? txprogdivreset_int : USER_TXPROGDIVRESET_IN;
+    end 
+  end 
+  else begin : non_pcie_txoutclksel
+  	always @(posedge CLK_IN) begin
+      if (mask_user_in)
+      	GTYE4_TXPROGDIVRESET_OUT <= txprogdivreset_int;
+      else
+      	GTYE4_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
+    end
+    
+    always @(posedge CLK_IN) begin
+      if (mask_user_in)
+      	GTYE4_TXOUTCLKSEL_OUT <= txoutclksel_int;
+      else
+      	GTYE4_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
+    end
+  end 
+  endgenerate
+
+  always @(posedge CLK_IN) begin
+    if (mask_user_in)
+      USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
+    else
+      USER_TXPRGDIVRESETDONE_OUT <= gtye4_txprgdivresetdone_sync;
+  end
+
+  // frequency counter for txoutclk
+  wire [17:0] txoutclk_freq_cnt;
+  reg freq_counter_rst = 1'b1;
+  wire freq_cnt_done;
+  gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
+  (
+    .freq_cnt_o(txoutclk_freq_cnt),
+    .done_o(freq_cnt_done),
+    .rst_i(freq_counter_rst),
+    .test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
+    .ref_clk_i(CLK_IN),
+    .test_clk_i(txoutclkmon)
+  );
+
+  //Debug signals
+  assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gtye4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
+  assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
+  assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
+  assign CAL_FREQ_CNT = txoutclk_freq_cnt;
+  assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
+
+  //pragma translate_off
+  generate if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
+  begin: gen_sim_cpll_cal_bypass_gtye4
+    //CPLL CAL FSM for simulation
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        txprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]:
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X0E1]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X0E1_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X079] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGCLK_SEL]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGCLK_SEL]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[READ_X079] <= 1'b1; 
+            end 
+            else begin
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= {1'b1,progclk_sel_store[14:0]};
+          end
+          
+          cpll_cal_state[READ_X079]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_X079] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_X079_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]: 
+          begin 
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0;
+              x0e1_store <= dout;
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end 
+            else begin 
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[MODIFY_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
+          end             
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            cpllreset_int <= 1'b1;
+            freq_counter_rst <= 1'b1;
+            cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            wait_ctr <= 25'd0;
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(!gtye4_cplllock_sync) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[RESTORE_READ_X0E1]: 
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin 
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end else begin 
+              cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_READ_X079]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end 
+          end            
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[RESTORE_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]}; 
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x0E1]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000; 
+          end 
+          
+          cpll_cal_state[CLEAR_FLAG_x079]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gtye4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              txprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              txprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gtye4_txprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+
+  end
+  else
+  begin: gen_cpll_cal_gtye4
+  //pragma translate_on
+    //CPLL CAL FSM
+    always @(posedge CLK_IN) begin
+      if (RESET_IN) begin
+        cpll_cal_state <= 0;
+        cpll_cal_state[RESET] <= 1'b1;
+        cpllreset_int <= 1'b0;
+        cpllpd_int <= 1'b0;
+        txprogdivreset_int <= 1'b0;
+        mask_user_in <= 1'b0;
+        wr <= 1'b0;
+        rd <= 1'b0;
+      end
+      else begin
+        cpll_cal_state <= 0;
+        case(1'b1) // synthesis parallel_case full_case
+          cpll_cal_state[RESET]:
+          begin
+            wait_ctr <= 25'd0;
+            repeat_ctr <= 4'd0;
+            mask_user_in <= 1'b1;
+            di_msk <= 16'b0000_0000_0000_0000;
+            cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[READ_X0E1]:
+          begin
+            mask_user_in <= 1'b1;
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
+            end
+            else
+              cpll_cal_state[READ_X0E1] <= 1'b1;
+          end
+          
+          cpll_cal_state[CHECK_X0E1_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X079] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGCLK_SEL]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGCLK_SEL]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[READ_X079] <= 1'b1; 
+            end 
+            else begin
+              cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= {1'b1,progclk_sel_store[14:0]};
+          end
+          
+          cpll_cal_state[READ_X079]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              status_store <= dout[15];
+              cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_X079] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_X079_STATUS]:
+          begin 
+            if (status_store)
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
+            else 
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;  
+          end
+          
+          cpll_cal_state[READ_PROGDIV_CFG]:
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin
+              rd <= 1'b0;
+              progdiv_cfg_store <= {1'b1,dout[14:0]};
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[SAVE_PROGDIV_CFG]:
+          begin 
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end
+            else begin
+              cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
+            end
+            di_msk <= progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]: 
+          begin 
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0;
+              x0e1_store <= dout;
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end 
+            else begin 
+              cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[MODIFY_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
+          end             
+          
+          cpll_cal_state[MODIFY_PROGDIV]:
+          begin
+            wr <= 1'b1;
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+            di_msk<= MOD_PROGDIV_CFG;
+          end
+          
+          cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
+          begin
+            cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+          end
+          
+          cpll_cal_state[ASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;                 
+            end
+            else begin
+              cpllpd_int <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLPD]:
+          begin
+            if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
+            end
+            else begin
+              cpllpd_int <= 1'b0;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+              freq_counter_rst <= 1'b1;
+            end
+          end 
+          
+          cpll_cal_state[ASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b1;
+              freq_counter_rst <= 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[DEASSERT_CPLLRESET]:
+          begin
+            if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
+            end
+            else begin
+              cpllreset_int <= 1'b0;
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK]:
+          begin
+            if(wait_ctr < WAIT_CPLLLOCK) begin
+              cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
+              wait_ctr <= wait_ctr + 1'b1;
+            end
+            else begin
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+              wait_ctr <= 16'd0;
+            end
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              txprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
+            end
+            else begin
+              txprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE]:
+          begin
+            if (gtye4_txprgdivresetdone_sync) begin
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+              freq_counter_rst <= 1'b0;
+            end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CHECK_FREQ]:
+          begin
+            if(freq_cnt_done) begin
+              if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
+                cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
+                cal_fail_store <= 1'b0;
+              end
+              else begin
+                if (repeat_ctr < REPEAT_RESET_LIMIT) begin
+                  cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
+                  repeat_ctr <= repeat_ctr + 1'b1;
+                end
+                else begin
+                  cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
+                  cal_fail_store <= 1'b1;
+                end
+              end
+            end
+            else
+              cpll_cal_state[CHECK_FREQ] <= 1'b1;
+          end
+          
+          cpll_cal_state[RESTORE_READ_X0E1]: 
+          begin
+            rd <= 1'b1;
+            if (drp_done) begin 
+              rd <= 1'b0;
+              progclk_sel_store <= dout;
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end else begin 
+              cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1; 
+            end 
+          end
+          
+          cpll_cal_state[RESTORE_READ_X079]: 
+          begin
+            rd <= 1'b1; 
+            if (drp_done) begin
+              rd <= 1'b0; 
+              progdiv_cfg_store <= dout; 
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1; 
+            end else begin
+              cpll_cal_state[RESTORE_READ_X079] <= 1'b1; 
+            end 
+          end            
+          
+          cpll_cal_state[RESTORE_PROGDIV]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0; 
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
+          end
+          
+          cpll_cal_state[RESTORE_PROGCLK_SEL]:
+          begin
+            wr <= 1'b1; 
+            if (drp_done) begin
+              wr <= 1'b0;
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
+            end
+            else begin
+              cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
+            end
+            di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]}; 
+          end
+          
+          cpll_cal_state[CLEAR_FLAG_x0E1]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000; 
+          end 
+          
+          cpll_cal_state[CLEAR_FLAG_x079]: 
+          begin
+            //set [15] to 0
+            wr <= 1'b1; 
+            if (drp_done) begin 
+              wr <= 1'b0; 
+              cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1; 
+            end 
+            else begin 
+              cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1; 
+            end
+            // clear
+            di_msk <= 16'h0000;
+          end 
+          
+          cpll_cal_state[WAIT_GTCPLLLOCK2]:
+          begin
+            cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            if(!gtye4_cplllock_sync)
+              cal_fail_store <= 1'b1;
+            else
+              cal_fail_store <= cal_fail_store;
+          end
+          
+          cpll_cal_state[ASSERT_PROGDIVRESET2]:
+          begin
+            if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
+              wait_ctr <= wait_ctr + 1'b1;
+              txprogdivreset_int <= 1'b1;
+              cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
+            end
+            else begin
+              txprogdivreset_int <= 1'b0;
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+              wait_ctr <= 25'd0;
+            end
+          end
+          
+          cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
+          begin
+            if (gtye4_txprgdivresetdone_sync) begin
+              if (cal_fail_store)
+                cpll_cal_state[CAL_FAIL] <= 1'b1;
+              else
+                cpll_cal_state[CAL_DONE] <= 1'b1;
+              end
+            else begin
+              cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
+            end
+          end
+          
+          cpll_cal_state[CAL_FAIL]:
+          begin
+            cpll_cal_state[CAL_FAIL] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+          
+          cpll_cal_state[CAL_DONE]:
+          begin
+            cpll_cal_state[CAL_DONE] <= 1'b1;
+            mask_user_in <= 1'b0;
+          end
+        endcase
+      end
+    end // always block
+  
+  //pragma translate_off
+  end
+  endgenerate
+  //pragma translate_on
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET])
+      txoutclksel_int <= 3'b0;
+    else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
+      txoutclksel_int <= MOD_TXOUTCLK_SEL;
+  end
+
+  always @(posedge CLK_IN) begin
+    if (cpll_cal_state[RESET]) begin
+      daddr <= 10'h000;
+      mask  <= 16'b1111_1111_1111_1111;
+    end
+    else if (cpll_cal_state[READ_X0E1] | cpll_cal_state[SAVE_PROGCLK_SEL] | cpll_cal_state[RESTORE_READ_X0E1] | cpll_cal_state[CLEAR_FLAG_x0E1] | cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]) begin 
+      daddr <= ADDR_X0E1;
+    end 
+    else if (cpll_cal_state[READ_X079] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X079] | cpll_cal_state[CLEAR_FLAG_x079]) begin 
+      daddr <= ADDR_X079;
+    end 
+    else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
+      daddr <= ADDR_TX_PROGCLK_SEL;
+    end
+    else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
+      daddr <= ADDR_TX_PROGDIV_CFG;
+    end
+  
+  end
+  
+  assign drp_done = drp_state[DRP_DONE];
+  assign GTYE4_CHANNEL_DRPEN_OUT = den;
+  assign GTYE4_CHANNEL_DRPWE_OUT = dwe;
+  assign GTYE4_CHANNEL_DRPADDR_OUT = daddr;
+  assign GTYE4_CHANNEL_DRPDI_OUT = di;
+  assign drdy = GTYE4_CHANNEL_DRPRDY_IN; 
+  assign dout = GTYE4_CHANNEL_DRPDO_IN;   
+  
+  always @(posedge CLK_IN or posedge RESET_IN) begin
+  if (RESET_IN) begin
+    den <= 1'b0;
+    dwe <= 1'b0;
+    di <= 16'h0000;
+    drp_state <= 0;
+    drp_state[DRP_WAIT] <= 1'b1;
+  end
+  else begin
+    drp_state <= 0;
+    case (1'b1) // synthesis parallel_case full_case
+        drp_state[DRP_WAIT]:
+        begin
+          if (rd) drp_state[DRP_READ] <= 1'b1;
+          else if (wr) drp_state[DRP_WRITE] <= 1'b1;
+          else         drp_state[DRP_WAIT] <= 1'b1;
+        end
+        drp_state[DRP_READ]:
+        begin
+          den <= 1'b1;
+          drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_READ_ACK]:
+        begin
+          den <= 1'b0;
+          if (drdy == 1'b1) begin
+            if (rd) drp_state[DRP_DONE] <= 1'b1;
+            else    drp_state[DRP_MODIFY] <= 1'b1;
+          end
+          else      drp_state[DRP_READ_ACK] <= 1'b1;
+        end
+        drp_state[DRP_MODIFY]:
+        begin
+          drp_state[DRP_WRITE] <= 1'b1;
+        end
+        drp_state[DRP_WRITE]:
+        begin
+          den <= 1'b1;
+          dwe <= 1'b1;
+          di <= di_msk;
+          drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_WRITE_ACK]:
+        begin
+          den <= 1'b0;
+          dwe <= 1'b0;
+          if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
+          else              drp_state[DRP_WRITE_ACK] <= 1'b1;
+        end
+        drp_state[DRP_DONE]:
+        begin
+          drp_state[DRP_WAIT] <= 1'b1;
+        end
+    endcase
+  end
+  end
+  
+  //debug logic - convert one hot state to binary
+  genvar i,j;
+  generate
+    for (j=0; j<5; j=j+1)
+    begin : jl
+      wire [32-1:0] tmp_mask;
+      for (i=0; i<32; i=i+1)
+      begin : il
+        assign tmp_mask[i] = i[j];
+      end
+      assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
+    end
+  endgenerate
+  
+endmodule //CPLL_CAL  
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v
new file mode 100755
index 0000000..a335853
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v
@@ -0,0 +1,170 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gtye4_delay_powergood # (
+  parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
+  parameter C_PCIE_ENABLE = "FALSE"
+)(
+  input wire GT_TXOUTCLKPCS,
+
+  input wire GT_GTPOWERGOOD,
+  input wire [2:0] USER_TXRATE,
+  input wire USER_TXRATEMODE,
+  input wire USER_GTTXRESET,
+  input wire USER_TXPMARESET,
+  input wire USER_TXPISOPD,
+
+  output wire USER_GTPOWERGOOD,
+  output wire [2:0] GT_TXRATE,
+  output wire GT_TXRATEMODE,
+  output wire GT_GTTXRESET,
+  output wire GT_TXPMARESET,
+  output wire GT_TXPISOPD
+);
+
+generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
+begin : gen_powergood_nodelay
+  assign GT_TXPISOPD      = USER_TXPISOPD;
+  assign GT_GTTXRESET     = USER_GTTXRESET;
+  assign GT_TXPMARESET    = USER_TXPMARESET;
+  assign GT_TXRATE        = USER_TXRATE;
+  assign GT_TXRATEMODE    = USER_TXRATEMODE;
+  assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
+end
+else
+begin: gen_powergood_delay
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [8:0] wait_cnt;
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
+  (*  ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
+  wire intclk_rrst_n;
+  
+  //--------------------------------------------------------------------------
+  //  POWER ON FSM Encoding
+  //-------------------------------------------------------------------------- 
+  localparam PWR_ON_WAIT_CNT           = 4'd0;
+  localparam PWR_ON_DONE               = 4'd1; 
+  
+  //--------------------------------------------------------------------------------------------------
+  //  Reset Synchronizer
+  //--------------------------------------------------------------------------------------------------
+  always @ (posedge GT_TXOUTCLKPCS or negedge GT_GTPOWERGOOD)
+  begin
+      if (!GT_GTPOWERGOOD)
+          intclk_rrst_n_r <= 5'd0;
+      else if(!int_pwr_on_fsm)
+          intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1}; 
+  end
+
+  assign intclk_rrst_n = intclk_rrst_n_r[4];
+
+  //--------------------------------------------------------------------------------------------------
+  //  Wait counter 
+  //--------------------------------------------------------------------------------------------------
+  always @ (posedge GT_TXOUTCLKPCS)
+  begin
+    if (!intclk_rrst_n)
+    	wait_cnt <= 9'd0;
+    else begin
+    	if (int_pwr_on_fsm == PWR_ON_WAIT_CNT)
+    		wait_cnt <= {wait_cnt[7:0],1'b1};
+    	else
+    		wait_cnt <= wait_cnt;
+    end
+  end
+
+  //--------------------------------------------------------------------------------------------------
+  // Power On FSM
+  //--------------------------------------------------------------------------------------------------
+
+  always @ (posedge GT_TXOUTCLKPCS or negedge GT_GTPOWERGOOD)
+  begin
+    if (!GT_GTPOWERGOOD)
+    begin
+      int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
+    end
+    else begin
+      case (int_pwr_on_fsm)
+        PWR_ON_WAIT_CNT :
+          begin
+            int_pwr_on_fsm <= (wait_cnt[7] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
+          end 
+
+        PWR_ON_DONE :
+          begin
+            int_pwr_on_fsm <= PWR_ON_DONE;
+          end
+
+        default :
+        begin
+          int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
+        end
+      endcase
+    end
+  end
+
+  always @(posedge GT_TXOUTCLKPCS)
+    pwr_on_fsm <= int_pwr_on_fsm;
+
+  assign GT_TXPISOPD      = pwr_on_fsm ? USER_TXPISOPD : 1'b1;
+  assign GT_GTTXRESET     = pwr_on_fsm ? USER_GTTXRESET : !GT_GTPOWERGOOD;
+  assign GT_TXPMARESET    = pwr_on_fsm ? USER_TXPMARESET : 1'b0;
+  assign GT_TXRATE        = pwr_on_fsm ? USER_TXRATE : 3'b001;
+  assign GT_TXRATEMODE    = pwr_on_fsm ? USER_TXRATEMODE : 1'b1;
+  assign USER_GTPOWERGOOD = pwr_on_fsm; 
+
+end
+endgenerate
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v
new file mode 100755
index 0000000..41110b9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v
@@ -0,0 +1,98 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer # (
+
+  parameter FREQUENCY = 512
+
+)(
+
+  input  wire clk_in,
+  input  wire rst_in,
+  output wire rst_out
+
+);
+
+  // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
+  // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
+  // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
+  // downstream logic is also removed from reset synchronously. This module is designed for active-low reset use.
+
+  (* ASYNC_REG = "TRUE" *) reg rst_in_meta  = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
+                           reg rst_in_out   = 1'b0;
+
+  always @(posedge clk_in, negedge rst_in) begin
+    if (!rst_in) begin
+      rst_in_meta  <= 1'b0;
+      rst_in_sync1 <= 1'b0;
+      rst_in_sync2 <= 1'b0;
+      rst_in_sync3 <= 1'b0;
+      rst_in_out   <= 1'b0;
+    end
+    else begin
+      rst_in_meta  <= 1'b1;
+      rst_in_sync1 <= rst_in_meta;
+      rst_in_sync2 <= rst_in_sync1;
+      rst_in_sync3 <= rst_in_sync2;
+      rst_in_out   <= rst_in_sync3;
+    end
+  end
+
+  assign rst_out = rst_in_out;
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v
new file mode 100755
index 0000000..a3129d3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v
@@ -0,0 +1,98 @@
+//------------------------------------------------------------------------------
+//  (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_reset_synchronizer # (
+
+  parameter FREQUENCY = 512
+
+)(
+
+  input  wire clk_in,
+  input  wire rst_in,
+  output wire rst_out
+
+);
+
+  // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
+  // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
+  // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
+  // downstream logic is also removed from reset synchronously. This module is designed for active-high reset use.
+
+  (* ASYNC_REG = "TRUE" *) reg rst_in_meta  = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
+                           reg rst_in_out   = 1'b0;
+
+  always @(posedge clk_in, posedge rst_in) begin
+    if (rst_in) begin
+      rst_in_meta  <= 1'b1;
+      rst_in_sync1 <= 1'b1;
+      rst_in_sync2 <= 1'b1;
+      rst_in_sync3 <= 1'b1;
+      rst_in_out   <= 1'b1;
+    end
+    else begin
+      rst_in_meta  <= 1'b0;
+      rst_in_sync1 <= rst_in_meta;
+      rst_in_sync2 <= rst_in_sync1;
+      rst_in_sync3 <= rst_in_sync2;
+      rst_in_out   <= rst_in_sync3;
+    end
+  end
+
+  assign rst_out = rst_in_out;
+
+
+endmodule
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd
new file mode 100755
index 0000000..9a0ed7e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd
@@ -0,0 +1,10899 @@
+-------------------------------------------------------------------------------
+-- iomodule_vote_pkg.vhd - Package specification
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2015-2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        iomodule_vote_pkg.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              iomodule_vote_pkg
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+--
+-- History:
+--   rolandp 2015-09-14    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package IOModule_Vote_Pkg is
+
+  function vote (vote1, vote2, vote3 : std_logic_vector; tmr_disable : boolean) return std_logic_vector;
+  function vote (vote1, vote2, vote3 : std_logic_vector; tmr_disable : boolean; tmr : integer) return std_logic_vector;
+
+  function vote (vote1, vote2, vote3 : std_logic; tmr_disable : boolean) return std_logic;
+  function vote (vote1, vote2, vote3 : std_logic; tmr_disable : boolean; tmr : integer) return std_logic;
+
+  function vote (vote1 : boolean; vote2, vote3 : std_logic; tmr_disable : boolean) return boolean;
+  function vote (vote1 : boolean; vote2, vote3 : std_logic; tmr_disable : boolean; tmr : integer) return boolean;
+
+  constant C_MAX_FIT_SIZE       : natural := 32;
+  constant C_MAX_PIT_SIZE       : natural := 32;
+  constant C_MAX_GPO_SIZE       : natural := 32;
+  constant C_UART_PROG_CNT_SIZE : natural := 20;
+
+  -- FIT
+  subtype  FIT_COUNT_Pos    is natural range C_MAX_FIT_SIZE - 1 downto 0;
+  constant FIT_INTERRUPT_Pos : natural :=    FIT_COUNT_Pos'high + 1;
+  constant FIT_TOGGLE_Pos    : natural :=    FIT_INTERRUPT_Pos + 1;
+
+  constant C_FIT_VOTE_SIZE   : natural := FIT_TOGGLE_Pos  + 1;
+  subtype  FIT1_Pos         is natural range C_FIT_VOTE_SIZE - 1 downto 0;
+  subtype  FIT2_Pos         is natural range FIT1_Pos'high + C_FIT_VOTE_SIZE downto FIT1_Pos'high + 1;
+  subtype  FIT3_Pos         is natural range FIT2_Pos'high + C_FIT_VOTE_SIZE downto FIT2_Pos'high + 1;
+  subtype  FIT4_Pos         is natural range FIT3_Pos'high + C_FIT_VOTE_SIZE downto FIT3_Pos'high + 1;
+
+  -- UART Baudrate Counter
+  subtype  UART_BAUD_FIT_Pos  is natural range C_MAX_FIT_SIZE + 2 downto 0;
+  subtype  UART_BAUD_REG_Pos  is natural range UART_BAUD_FIT_Pos'high + C_UART_PROG_CNT_SIZE downto
+                                               UART_BAUD_FIT_Pos'high + 1;
+  subtype  UART_BAUD_CNT_Pos  is natural range UART_BAUD_REG_Pos'high + C_UART_PROG_CNT_SIZE downto
+                                               UART_BAUD_REG_Pos'high + 1;
+  constant UART_BAUD_EN16_Pos  : natural :=    UART_BAUD_CNT_Pos'high + 1;
+
+  -- UART Control
+  constant PARITY_ERROR_Pos    : natural :=    0;
+  constant FRAME_ERROR_Pos     : natural :=    PARITY_ERROR_Pos + 1;
+  constant OVERRUN_ERROR_Pos   : natural :=    FRAME_ERROR_Pos + 1;
+  constant ERROR_INTERRUPT_Pos : natural :=    OVERRUN_ERROR_Pos + 1;
+
+  subtype  UART_CONTROL_Pos   is natural range UART_BAUD_EN16_Pos + 1 + ERROR_INTERRUPT_Pos downto
+                                               UART_BAUD_EN16_Pos + 1;
+
+  -- UART Transmit
+  constant UART_TX_DIV16_Pos         : natural :=    0;
+  constant UART_TX_DATA_ENABLE_Pos   : natural :=    UART_TX_DIV16_Pos + 1;
+  constant UART_TX_START_Pos         : natural :=    UART_TX_DATA_ENABLE_Pos + 1;
+  constant UART_TX_DATABITS_Pos      : natural :=    UART_TX_START_Pos + 1;
+  subtype  UART_TX_MUX_SEL_Pos      is natural range UART_TX_DATABITS_Pos + 3 downto UART_TX_DATABITS_Pos + 1;
+  constant UART_TX_DATA_IS_SENT_Pos  : natural :=    UART_TX_MUX_SEL_Pos'high + 1;
+  constant UART_TX_SERIAL_DATA_Pos   : natural :=    UART_TX_DATA_IS_SENT_Pos + 1;
+  constant UART_TX_Pos               : natural :=    UART_TX_SERIAL_DATA_Pos + 1;
+  constant UART_TX_CALC_PARITY_Pos   : natural :=    UART_TX_Pos + 1;
+  constant UART_TX_RUN_Pos           : natural :=    UART_TX_CALC_PARITY_Pos + 1;
+  constant UART_TX_SEL_PARITY_Pos    : natural :=    UART_TX_RUN_Pos + 1;
+  subtype  UART_TX_FIFO_DOUT_Pos    is natural range UART_TX_SEL_PARITY_Pos + 8 downto UART_TX_SEL_PARITY_Pos + 1;
+  constant UART_TX_BUFFER_EMPTY_Pos  : natural :=    UART_TX_FIFO_DOUT_Pos'high + 1;
+
+  subtype  UART_TRANSMIT_Pos        is natural range UART_CONTROL_Pos'high + 1 + UART_TX_BUFFER_EMPTY_Pos downto
+                                                     UART_CONTROL_Pos'high + 1;
+
+  -- UART Receive
+  constant UART_RX_PREVIOUS_RX_Pos         : natural :=    0;
+  constant UART_RX_START_EDGE_DETECTED_Pos : natural :=    UART_RX_PREVIOUS_RX_Pos + 1;
+  constant UART_RX_RUNNING_Pos             : natural :=    UART_RX_START_EDGE_DETECTED_Pos + 1;
+  constant UART_RX_RECYCLE_Pos             : natural :=    UART_RX_RUNNING_Pos + 1;
+  constant UART_RX_STOP_BIT_POSITION_Pos   : natural :=    UART_RX_RECYCLE_Pos + 1;
+  constant UART_RX_CALC_PARITY_Pos         : natural :=    UART_RX_STOP_BIT_POSITION_Pos + 1;
+  constant UART_RX_MID_START_BIT_Pos       : natural :=    UART_RX_CALC_PARITY_Pos + 1;
+  subtype  UART_RX_SERIAL_TO_PARALLEL_Pos is natural range UART_RX_MID_START_BIT_Pos + 9 downto
+                                                           UART_RX_MID_START_BIT_Pos + 1;
+  constant UART_RX_NEW_RX_DATA_WRITE_Pos   : natural :=    UART_RX_SERIAL_TO_PARALLEL_Pos'high + 1;
+  constant UART_RX_DATA_EXISTS_Pos         : natural :=    UART_RX_NEW_RX_DATA_WRITE_Pos + 1;
+  subtype  UART_RX_DATA_I_Pos             is natural range UART_RX_DATA_EXISTS_Pos + 8 downto
+                                                           UART_RX_DATA_EXISTS_Pos + 1;
+  subtype  UART_RX_DATA_Pos               is natural range UART_RX_DATA_I_Pos'high + 8 downto
+                                                           UART_RX_DATA_I_Pos'high + 1;
+
+  subtype  UART_RECEIVE_Pos               is natural range UART_TRANSMIT_Pos'high + 1 + UART_RX_DATA_Pos'high downto
+                                                           UART_TRANSMIT_Pos'high + 1;
+  -- UART Core at UART level 
+  constant UART_CORE_low   : natural := 0;
+  constant UART_CORE_high  : natural := UART_RECEIVE_Pos'high;
+  subtype UART_CORE_Pos   is natural range UART_CORE_high downto UART_CORE_low;
+
+  -- Pulse Sync
+  constant PULSE_SYNC           : natural := 2;
+  constant PULSE_SYNC_KEEP_Pos  : natural := 0;
+  constant PULSE_SYNC_PULSE_Pos : natural := 1;
+  subtype PULSE_SYNC_Pos       is natural range PULSE_SYNC_PULSE_Pos downto PULSE_SYNC_KEEP_Pos;
+
+  -- UART Async fields
+  constant TMR_DISABLE_UART_CLK_Pos   : natural := UART_CORE_high+1;
+  subtype  WRITE_TX_DATA_Pos         is natural range TMR_DISABLE_UART_CLK_Pos+PULSE_SYNC downto TMR_DISABLE_UART_CLK_Pos+1;
+  subtype  WRITE_DATA_Pos            is natural range WRITE_TX_DATA_Pos'high+8 downto WRITE_TX_DATA_Pos'high+1;
+  subtype  WRITE_BAUD_Pos            is natural range WRITE_DATA_Pos'high+PULSE_SYNC downto WRITE_DATA_Pos'high+1;
+  subtype  BAUD_DATA_Pos             is natural range WRITE_BAUD_Pos'high+C_UART_PROG_CNT_SIZE downto WRITE_BAUD_Pos'high+1;
+  subtype  RX_DATA_RECEIVED_Pos      is natural range BAUD_DATA_Pos'high+PULSE_SYNC downto BAUD_DATA_Pos'high+1;
+  subtype  RX_DATA_Pos               is natural range RX_DATA_RECEIVED_Pos'high+8 downto RX_DATA_RECEIVED_Pos'high+1;
+  subtype  READ_RX_DATA_Pos          is natural range RX_DATA_Pos'high+PULSE_SYNC downto RX_DATA_Pos'high+1;
+  constant READ_RX_PULSE_Pos          : natural := READ_RX_DATA_Pos'high+1;
+  subtype  UART_STATUS_READ_Pos      is natural range READ_RX_PULSE_Pos+PULSE_SYNC downto READ_RX_PULSE_Pos+1;
+  subtype  UART_STATUS_Pos           is natural range UART_STATUS_READ_Pos'high+8 downto UART_STATUS_READ_Pos'high+1;
+  constant UART_STATUS_READ_PULSE_Pos : natural := UART_STATUS_Pos'high+1;
+  subtype  UART_RX_INTERRUPT_Pos     is natural range UART_STATUS_READ_PULSE_Pos+PULSE_SYNC downto UART_STATUS_READ_PULSE_Pos+1;
+  subtype  UART_TX_INTERRUPT_Pos     is natural range UART_RX_INTERRUPT_Pos'high+PULSE_SYNC downto UART_RX_INTERRUPT_Pos'high+1;
+  subtype  UART_ERROR_INTERRUPT_Pos  is natural range UART_TX_INTERRUPT_Pos'high+PULSE_SYNC downto UART_TX_INTERRUPT_Pos'high+1;
+
+  -- Async UART at UART level
+  constant UART_ASYNC_low   : natural := UART_CORE_high+1;
+  constant UART_ASYNC_high  : natural := UART_ERROR_INTERRUPT_Pos'high;
+  subtype  UART_ASYNC_Pos   is natural range UART_ASYNC_high downto UART_ASYNC_low;
+                                                
+  -- All UART fields at iomodule level
+  constant UART_low   : natural := FIT4_Pos'high + 1;
+  constant UART_high  : natural := UART_ASYNC_high + FIT4_Pos'high + 1;
+  subtype UART_Pos   is natural range UART_high downto UART_low;
+  
+  -- GPO
+  subtype  GPO1_Pos                       is natural range UART_high+ C_MAX_GPO_SIZE downto
+                                                           UART_high + 1;
+  subtype  GPO2_Pos                       is natural range GPO1_Pos'high + C_MAX_GPO_SIZE downto GPO1_Pos'high + 1;
+  subtype  GPO3_Pos                       is natural range GPO2_Pos'high + C_MAX_GPO_SIZE downto GPO2_Pos'high + 1;
+  subtype  GPO4_Pos                       is natural range GPO3_Pos'high + C_MAX_GPO_SIZE downto GPO3_Pos'high + 1;
+
+  -- PIT
+  subtype  PIT_PRELOAD_VALUE_Pos          is natural range C_MAX_PIT_SIZE-1 downto 0;
+  constant PIT_RELOAD_Pos                  : natural :=    PIT_PRELOAD_VALUE_Pos'high + 1;
+  constant PIT_COUNT_EN_Pos                : natural :=    PIT_RELOAD_Pos + 1;
+  constant PIT_COUNT_LOAD_N_Pos            : natural :=    PIT_COUNT_EN_Pos + 1;
+  constant PIT_PRELOAD_WRITTEN_Pos         : natural :=    PIT_COUNT_LOAD_N_Pos + 1;
+  subtype  PIT_COUNT_Pos                  is natural range PIT_PRELOAD_WRITTEN_Pos + C_MAX_PIT_SIZE downto
+                                                           PIT_PRELOAD_WRITTEN_Pos + 1;
+  constant PIT_INTERRUPT_I_Pos             : natural :=    PIT_COUNT_Pos'high + 1;
+  constant PIT_TOGGLE_I_Pos                : natural :=    PIT_INTERRUPT_I_Pos + 1;
+  constant PIT_VOTE_SIZE                   : natural :=    PIT_TOGGLE_I_Pos + 1;
+
+  subtype  PIT1_Pos                       is natural range GPO4_Pos'high + PIT_VOTE_SIZE downto GPO4_Pos'high + 1;
+  subtype  PIT2_Pos                       is natural range PIT1_Pos'high + PIT_VOTE_SIZE downto PIT1_Pos'high + 1;
+  subtype  PIT3_Pos                       is natural range PIT2_Pos'high + PIT_VOTE_SIZE downto PIT2_Pos'high + 1;
+  subtype  PIT4_Pos                       is natural range PIT3_Pos'high + PIT_VOTE_SIZE downto PIT3_Pos'high + 1;
+
+  -- Interrupt
+  subtype  IRQ_INTERRUPT_Pos              is natural range 31 downto 0;
+  subtype  IRQ_INTR_PRESENT_Pos           is natural range IRQ_INTERRUPT_Pos'high + 32 downto
+                                                           IRQ_INTERRUPT_Pos'high + 1;
+  subtype  IRQ_CISR_Pos                   is natural range IRQ_INTR_PRESENT_Pos'high + 32 downto
+                                                           IRQ_INTR_PRESENT_Pos'high + 1;
+  subtype  IRQ_CIER_Pos                   is natural range IRQ_CISR_Pos'high + 32 downto IRQ_CISR_Pos'high + 1;
+  subtype  IRQ_CIMR_Pos                   is natural range IRQ_CIER_Pos'high + 32 downto IRQ_CIER_Pos'high + 1;
+  subtype  IRQ_CIVR_Pos                   is natural range IRQ_CIMR_Pos'high + 5 downto IRQ_CIMR_Pos'high + 1;
+  subtype  IRQ_FAST_STATE_Pos             is natural range IRQ_CIVR_Pos'high + 2 downto IRQ_CIVR_Pos'high + 1;
+  constant IRQ_INTC_IRQ_Pos                : natural :=    IRQ_FAST_STATE_Pos'high + 1;
+  constant IRQ_DO_FAST_ACK_Pos             : natural :=    IRQ_INTC_IRQ_Pos + 1;
+  constant IRQ_RST_CIPR_RD_Pos             : natural :=    IRQ_DO_FAST_ACK_Pos + 1;
+  constant IRQ_VOTE_SIZE                   : natural :=    IRQ_RST_CIPR_RD_Pos + 1;
+
+
+  subtype  IRQ_Pos                        is natural range PIT4_Pos'high + IRQ_VOTE_SIZE downto PIT4_Pos'high + 1;
+
+  constant VOTE_SIZE : natural := IRQ_Pos'high + 1;
+
+end package IOModule_Vote_Pkg;
+
+
+-------------------------------------------------------------------------------
+-- iomodule_vote_pkg_body.vhd - Package body
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2015-2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        iomodule_vote_pkg_body.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              iomodule_vote_pkg
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+--
+-- History:
+--   rolandp 2015-09-14    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package body IOModule_Vote_Pkg is
+
+  function vote(vote1, vote2, vote3 : std_logic_vector) return std_logic_vector is
+    variable I     : integer := 0;
+    variable voted : std_logic_vector(1023 downto 0);
+    variable vote1_l, vote2_l, vote3_l : std_logic_vector(1023 downto 0);
+  begin
+    vote1_l(vote1'length - 1 downto 0) := vote1;
+    vote2_l(vote2'length - 1 downto 0) := vote2;
+    vote3_l(vote3'length - 1 downto 0) := vote3;
+    for I in vote1_l'range loop
+      voted(I) := (vote1_l(I) and vote2_l(I)) or
+                  (vote1_l(I) and vote3_l(I)) or
+                  (vote2_l(I) and vote3_l(I));
+    end loop;
+    return voted(vote1'length - 1 downto 0);
+  end function vote;
+
+  function vote(vote1, vote2, vote3 : std_logic_vector; tmr_disable : boolean) return std_logic_vector is
+  begin
+    if tmr_disable then
+      return vote1;
+    else
+      return vote(vote1, vote2, vote3);
+    end if;
+  end function vote;
+
+  function vote(vote1, vote2, vote3 : std_logic_vector;
+                tmr_disable         : boolean;
+                tmr                 : integer) return std_logic_vector is
+  begin
+    if (tmr = 0 or tmr_disable) then
+      return vote1;
+    else
+      return vote(vote1, vote2, vote3);
+    end if;
+  end function vote;
+
+  function vote(vote1, vote2, vote3 : std_logic) return std_logic is
+    variable voted : std_logic;
+  begin
+    voted := (vote1 and vote2) or
+             (vote1 and vote3) or
+             (vote2 and vote3);
+    return voted;
+  end function vote;
+
+  function vote(vote1, vote2, vote3 : std_logic; tmr_disable : boolean) return std_logic is
+  begin
+    if tmr_disable then
+      return vote1;
+    else
+      return vote(vote1, vote2, vote3);
+    end if;
+  end function vote;
+
+  function vote (vote1, vote2, vote3 : std_logic; tmr_disable : boolean; tmr : integer) return std_logic is
+  begin
+    if (tmr = 0 or tmr_disable) then
+       return vote1;
+    else
+      return vote(vote1, vote2, vote3);
+    end if;
+  end function vote;
+
+  function vote(vote1 : boolean; vote2, vote3 : std_logic) return boolean is
+    variable voted, vote2_b, vote3_b : boolean;
+  begin
+    if (vote2 = '1') then
+      vote2_b := true;
+    else
+      vote2_b := false;
+    end if;
+    if (vote3 = '1') then
+      vote3_b := true;
+    else
+      vote3_b := false;
+    end if;
+    voted := (vote1   and vote2_b) or
+             (vote1   and vote3_b) or
+             (vote2_b and vote3_b);
+    return voted;
+  end function vote;
+
+  function vote(vote1 : boolean; vote2, vote3 : std_logic; tmr_disable : boolean) return boolean is
+  begin
+    if tmr_disable then
+      return vote1;
+    else
+      return vote(vote1, vote2, vote3);
+    end if;
+  end function vote;
+
+  function vote(vote1 : boolean; vote2, vote3 : std_logic; tmr_disable : boolean; tmr : integer) return boolean is
+  begin
+    if (tmr = 0 or tmr_disable) then
+      return vote1;
+    else
+      return vote(vote1, vote2, vote3);
+    end if;
+  end function vote;
+
+end package body IOModule_Vote_Pkg;
+
+
+-------------------------------------------------------------------------------
+-- iomodule_funcs.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2001-2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        iomodule_funcs.vhd
+--
+-- Description:     Support functions for iomodule
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--                  iomodule_funcs.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package iomodule_funcs is
+
+  type TARGET_FAMILY_TYPE is (
+                              -- pragma xilinx_rtl_off
+                              non_RTL,
+                              -- pragma xilinx_rtl_on
+                              RTL
+                             );
+
+  function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
+
+end package iomodule_funcs;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package body iomodule_funcs is
+
+  function LowerCase_Char(char : character) return character is
+  begin
+    -- If char is not an upper case letter then return char
+    if char < 'A' or char > 'Z' then
+      return char;
+    end if;
+    -- Otherwise map char to its corresponding lower case character and
+    -- return that
+    case char is
+      when 'A'    => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
+      when 'E'    => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
+      when 'I'    => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
+      when 'M'    => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
+      when 'Q'    => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
+      when 'U'    => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
+      when 'Y'    => return 'y'; when 'Z' => return 'z';
+      when others => return char;
+    end case;
+  end LowerCase_Char;
+
+  function LowerCase_String (s : string) return string is
+    variable res : string(s'range);
+  begin  -- function LoweerCase_String
+    for I in s'range loop
+      res(I) := LowerCase_Char(s(I));
+    end loop;  -- I
+    return res;
+  end function LowerCase_String;
+
+  -- Returns true if case insensitive string comparison determines that
+  -- str1 and str2 are equal
+  function Equal_String( str1, str2 : string ) return boolean is
+    constant len1 : integer := str1'length;
+    constant len2 : integer := str2'length;
+    variable equal : boolean := true;
+  begin
+    if not (len1=len2) then
+      equal := false;
+    else
+      for i in str1'range loop
+        if not (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) then
+          equal := false;
+        end if;
+      end loop;
+    end if;
+
+    return equal;
+  end Equal_String;
+
+  function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
+  begin  -- function String_To_Family
+    if ((Select_RTL) or Equal_String(S, "rtl")) then
+      return RTL;
+    else
+      return non_RTL;
+    end if;
+  end function String_To_Family;
+
+end package body iomodule_funcs;
+
+
+-------------------------------------------------------------------------------
+-- xilinx_primitives.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        xilinx_primitives.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--                  xilinx_primitives.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+--
+-- History:
+--   rolandp 2016-05-21    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+-- XIL_Scan_Reset_Control
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity xil_scan_reset_control is
+  port (
+    Scan_En          : in  std_logic;
+    Scan_Reset_Sel   : in  std_logic;
+    Scan_Reset       : in  std_logic;
+    Functional_Reset : in  std_logic;
+    Reset            : out std_logic);
+end entity xil_scan_reset_control;
+
+architecture IMP of xil_scan_reset_control is
+
+begin
+  Reset <= '0'               when Scan_En = '1' else
+            Functional_Reset when Scan_Reset_Sel = '0' else
+            Scan_Reset;
+end architecture IMP;
+
+----- entity XIL_SRL16E -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity XIL_SRL16E is
+  generic(
+    C_TARGET    : TARGET_FAMILY_TYPE;
+    C_USE_SRL16 : string;
+    C_STATIC    : boolean    := false;
+    INIT        : bit_vector := X"0000");
+  port(
+    Config_Reset : in  std_logic;
+    Q            : out std_logic;
+    A0           : in  std_logic;
+    A1           : in  std_logic;
+    A2           : in  std_logic;
+    A3           : in  std_logic;
+    CE           : in  std_logic;
+    CLK          : in  std_logic;
+    D            : in  std_logic);
+end entity XIL_SRL16E;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture IMP of XIL_SRL16E is
+
+begin  -- architecture IMP
+
+  Use_unisim: if (C_USE_SRL16 /= "no" and C_TARGET /= RTL) generate
+    XIL_SRL16E_I1: SRL16E
+      generic map (
+        INIT  => INIT)  -- [bit_vector]
+      port map (
+        Q   => Q,       -- [out std_logic]
+        A0  => A0,      -- [in  std_logic]
+        A1  => A1,      -- [in  std_logic]
+        A2  => A2,      -- [in  std_logic]
+        A3  => A3,      -- [in  std_logic]
+        CE  => CE,      -- [in  std_logic]
+        CLK => CLK,     -- [in  std_logic]
+        D   => D);      -- [in std_logic]
+  end generate Use_unisim;
+
+  Use_RTL : if (C_USE_SRL16 = "no" or C_TARGET = RTL) generate
+    signal shift_reg         : std_logic_vector(15 downto 0) := to_stdLogicVector(INIT);
+    constant shift_reg_const : std_logic_vector(15 downto 0) := to_stdLogicVector(INIT);
+    attribute shreg_extract : string;
+    attribute shreg_extract of SHIFT_REG : signal is C_USE_SRL16;
+  begin
+
+    Static_Values: if (C_STATIC) generate
+    begin
+      Q <= shift_reg_const(to_integer(unsigned(to_stdLogicVector(A3 & A2 & A1 & A0))));
+    end generate Static_Values;
+
+    Dynamic_Values: if (not C_STATIC) generate
+    begin
+      Q <= shift_reg(to_integer(unsigned(to_stdLogicVector(A3 & A2 & A1 & A0))));
+
+      process(CLK)
+      begin
+        if (rising_edge(CLK)) then
+          if (Config_Reset = '1') then
+            shift_reg <= shift_reg_const;
+          else
+            if CE = '1' then
+              shift_reg <= shift_reg(14 downto 0) & D;
+            end if;
+          end if;
+        end if;
+      end process;
+      
+    end generate Dynamic_Values;
+
+  end generate Use_RTL;
+
+end architecture IMP;
+
+----- entity XIL_SRLC16E -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity XIL_SRLC16E is
+  generic(
+    C_TARGET    : TARGET_FAMILY_TYPE;
+    C_USE_SRL16 : string;
+    INIT        : bit_vector := X"0000");
+  port(
+    Config_Reset : in  std_logic;
+    Q            : out std_logic;
+    Q15          : out std_logic;
+    A0           : in  std_logic;
+    A1           : in  std_logic;
+    A2           : in  std_logic;
+    A3           : in  std_logic;
+    CE           : in  std_logic;
+    CLK          : in  std_logic;
+    D            : in  std_logic);
+end entity XIL_SRLC16E;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture IMP of XIL_SRLC16E is
+
+begin  -- architecture IMP
+
+  Use_unisim: if (C_USE_SRL16 /= "no" and C_TARGET /= RTL) generate
+    XIL_SRL16CE_I1: SRLC16E
+      generic map (
+        INIT  => INIT)  -- [bit_vector]
+      port map (
+        Q15 => Q15,       -- [out std_logic]
+        Q   => Q,       -- [out std_logic]
+        A0  => A0,      -- [in  std_logic]
+        A1  => A1,      -- [in  std_logic]
+        A2  => A2,      -- [in  std_logic]
+        A3  => A3,      -- [in  std_logic]
+        CE  => CE,      -- [in  std_logic]
+        CLK => CLK,     -- [in  std_logic]
+        D   => D);      -- [in std_logic]
+  end generate Use_unisim;
+
+  Use_RTL : if (C_USE_SRL16 = "no" or C_TARGET = RTL) generate
+    signal shift_reg        : std_logic_vector(15 downto 0) := to_stdLogicVector(INIT);
+    attribute shreg_extract : string;
+    attribute shreg_extract of SHIFT_REG : signal is C_USE_SRL16;
+  begin
+
+    Q   <= shift_reg(to_integer(unsigned(to_stdLogicVector(A3 & A2 & A1 & A0))));
+    Q15 <= shift_reg(15);
+
+    process(CLK)
+    begin
+      if (rising_edge(CLK)) then
+        if (Config_Reset = '1') then
+          shift_reg <= (others => '0');
+        else
+          if CE = '1' then
+            shift_reg <= shift_reg(14 downto 0) & D;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  end generate Use_RTL;
+
+end architecture IMP;
+
+----- entity MUXCY -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_MUXCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    LO : out std_logic;
+    CI : in  std_logic;
+    DI : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXCY;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXCY is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    LO <= DI when S = '0' else CI;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MUXCY_L
+      port map(
+        LO => LO,
+        CI => CI,
+        DI => DI,
+        S  => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity XORCY -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_XORCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    CI : in  std_logic;
+    LI : in  std_logic
+  );
+end entity MB_XORCY;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_XORCY is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= (CI xor LI);
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: XORCY
+      port map(
+        O  => O,
+        CI => CI,
+        LI => LI
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MUXCY with XORCY -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_MUXCY_XORCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    LO : out std_logic;
+    CI : in  std_logic;
+    DI : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXCY_XORCY;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXCY_XORCY is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= (CI xor S);
+    LO <= DI when S = '0' else CI;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native_I1: MUXCY_L
+      port map(
+        LO => LO,
+        CI => CI,
+        DI => DI,
+        S  => S
+      );
+    Native_I2: XORCY
+      port map(
+        O  => O,
+        CI => CI,
+        LI => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity FDR -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_FDR is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0'
+  );
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    D  : in  std_logic;
+    R  : in  std_logic
+  );
+end entity MB_FDR;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_FDR is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+    function To_StdLogic(A : in bit ) return std_logic is
+    begin
+      if( A = '1' ) then
+        return '1';
+      end if;
+      return '0';
+    end;
+
+    signal q_o : std_logic := To_StdLogic(INIT);
+  begin
+    Q <=  q_o;
+    process(C)
+    begin
+      if (rising_edge(C)) then
+        if (R = '1') then
+          q_o <= '0';
+        else
+          q_o <= D;
+        end if;
+      end if;
+    end process;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: FDR
+      generic map(
+        INIT => INIT
+      )
+      port map(
+        Q   => Q,
+        C   => C,
+        D   => D,
+        R   => R
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity FDRE -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_FDRE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0'
+  );
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    R  : in  std_logic
+  );
+end entity MB_FDRE;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_FDRE is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+    function To_StdLogic(A : in bit ) return std_logic is
+    begin
+      if( A = '1' ) then
+        return '1';
+      end if;
+      return '0';
+    end;
+
+    signal q_o : std_logic := To_StdLogic(INIT);
+  begin
+    Q <=  q_o;
+    process(C)
+    begin
+      if (rising_edge(C)) then
+        if (R = '1') then
+          q_o <= '0';
+        elsif (CE = '1') then
+          q_o <= D;
+        end if;
+      end if;
+    end process;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: FDRE
+      generic map(
+        INIT => INIT
+      )
+      port map(
+        Q   => Q,
+        C   => C,
+        CE  => CE,
+        D   => D,
+        R   => R
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity FDSE -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_FDSE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '1'
+  );
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_FDSE;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_FDSE is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+    function To_StdLogic(A : in bit ) return std_logic is
+    begin
+      if( A = '1' ) then
+        return '1';
+      end if;
+      return '0';
+    end;
+
+    signal q_o : std_logic := To_StdLogic(INIT);
+  begin
+    Q <=  q_o;
+    process(C)
+    begin
+      if (rising_edge(C)) then
+        if (S = '1') then
+          q_o <= '1';
+        elsif (CE = '1') then
+          q_o <= D;
+        end if;
+      end if;
+    end process;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: FDSE
+      generic map(
+        INIT => INIT
+      )
+      port map(
+        Q   => Q,
+        C   => C,
+        CE  => CE,
+        D   => D,
+        S   => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MULT_AND -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_MULT_AND is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0'
+  );
+  port(
+    LO : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic
+  );
+end entity MB_MULT_AND;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MULT_AND is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    LO <= I0 and I1;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MULT_AND
+      port map(
+        LO => LO,
+        I0 => I0,
+        I1 => I1
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity LUT3 -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_LUT3 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT     : bit_vector := X"00"
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    I2 : in  std_logic
+  );
+end entity MB_LUT3;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_LUT3 is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+    constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT);
+  begin
+    process (I0, I1, I2)
+      variable I_reg    : std_logic_vector(2 downto 0);
+      variable I0_v, I1_v, I2_v : std_logic;
+    begin
+      -- Filter unknowns
+      if I0 = '0' then I0_v := '0'; else I0_v := '1'; end if;
+      if I1 = '0' then I1_v := '0'; else I1_v := '1'; end if;
+      if I2 = '0' then I2_v := '0'; else I2_v := '1'; end if;
+      I_reg := TO_STDLOGICVECTOR( I2_v & I1_v & I0_v);
+      O     <= INIT_reg(TO_INTEGER(unsigned(I_reg)));
+    end process;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: LUT3
+      generic map(
+        INIT    => INIT
+      )
+      port map(
+        O       => O,
+        I0      => I0,
+        I1      => I1,
+        I2      => I2
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MUXF5 -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_MUXF5 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXF5;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXF5 is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= I0 when S = '0' else I1;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MUXF5
+      port map(
+        O  => O,
+        I0 => I0,
+        I1 => I1,
+        S  => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MUXF6 -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity MB_MUXF6 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXF6;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXF6 is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= I0 when S = '0' else I1;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MUXF6
+      port map(
+        O  => O,
+        I0 => I0,
+        I1 => I1,
+        S  => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+
+
+
+------------------------------------------------------------------------------
+-- synchronizers.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2014,2017 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        synchronizers.vhd
+--
+-- Description:     
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:   
+--              mb_sync_bit
+--              mb_sync_vec
+--                mb_sync_bit
+--              mb_sync_reset
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+--
+-- History:
+--   rolandp 2014-09-01    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mb_sync_bit is
+  generic(
+    C_LEVELS            : natural   := 2;
+    C_RESET_VALUE       : std_logic := '0';
+    C_RESET_SYNCHRONOUS : boolean   := true;
+    C_RESET_ACTIVE_HIGH : boolean   := true);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic;
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic;
+    Scan_Reset     : in  std_logic;
+    Raw            : in  std_logic;
+    Synced         : out std_logic);
+end mb_sync_bit;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.xil_scan_reset_control;
+
+architecture IMP of mb_sync_bit is
+
+  component xil_scan_reset_control is
+  port (
+    Scan_En          : in  std_logic;
+    Scan_Reset_Sel   : in  std_logic;
+    Scan_Reset       : in  std_logic;
+    Functional_Reset : in  std_logic;
+    Reset            : out std_logic);
+  end component xil_scan_reset_control;
+  
+  -- Downgrade Synth 8-3332 warnings
+  attribute DowngradeIPIdentifiedWarnings: string;
+  attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
+
+begin
+
+  -- Generate synchronizer DFFs
+  Synchronize : if C_LEVELS > 1 generate
+    signal reset : std_logic; 
+    signal sync  : std_logic_vector(1 to C_LEVELS) := (others => C_RESET_VALUE);
+    attribute ASYNC_REG : string;
+    attribute ASYNC_REG of sync : signal is "TRUE";
+  begin
+    
+    -- Internal reset always has active high polarity 
+    reset <= Rst when C_RESET_ACTIVE_HIGH else
+             not Rst;
+
+    -- Synchronous reset
+    use_sync_reset: if C_RESET_SYNCHRONOUS generate
+    begin
+      
+      Sync_Rst_DFFs : process(Clk)
+      begin
+        if Clk'event and Clk = '1' then
+          if reset = '1' then
+            sync <= (sync'range  => C_RESET_VALUE); 
+          else
+            for I in C_LEVELS downto 2 loop
+              sync(I) <= sync(I-1);
+            end loop;
+            sync(1) <= Raw;
+          end if;
+        end if;
+      end process;
+
+    end generate use_sync_reset;
+
+    -- Asychronous reset
+    use_async_reset: if not C_RESET_SYNCHRONOUS generate
+      signal async_reset : std_logic;
+    begin
+
+      -- Make sure asynchronous reset can be controlled during scan test
+      scan_reset_control_i: xil_scan_reset_control
+        port map (
+          Scan_En          => Scan_En,
+          Scan_Reset_Sel   => Scan_Reset_Sel,
+          Scan_Reset       => Scan_Reset,
+          Functional_Reset => reset,
+          Reset            => async_reset);
+      
+      Async_Rst_DFFs : process(Clk, async_reset)
+      begin
+        if async_reset = '1' then
+          sync <= (sync'range => C_RESET_VALUE); 
+        elsif Clk'event and Clk = '1' then
+          for I in C_LEVELS downto 2 loop
+            sync(I) <= sync(I-1);
+          end loop;
+          sync(1) <= Raw;
+        end if;
+      end process;
+
+    end generate use_async_reset;
+
+    Synced <= sync(C_LEVELS);
+
+  end generate Synchronize;
+
+  -- 1 synchronizer DFF
+  Single_Synchronize : if C_LEVELS = 1 generate
+    signal reset : std_logic;
+    signal sync  : std_logic := C_RESET_VALUE;
+  begin
+    
+    -- Internal reset always has active high polarity 
+    reset <= Rst when C_RESET_ACTIVE_HIGH else
+             not Rst;
+
+    -- Synchronous reset
+    use_sync_reset: if C_RESET_SYNCHRONOUS generate
+    begin
+      
+      Sync_Rst_DFFs : process(Clk)
+      begin
+        if Clk'event and Clk = '1' then
+          if reset = '1' then
+            sync <= C_RESET_VALUE; 
+          else
+            sync <= Raw;
+          end if;
+        end if;
+      end process;
+
+    end generate use_sync_reset;
+
+    -- Asychronous reset
+    use_async_reset: if not C_RESET_SYNCHRONOUS generate
+      signal async_reset : std_logic;
+    begin
+
+      -- Make sure asynchronous reset can be controlled from during scan test
+      scan_reset_control_i: xil_scan_reset_control
+      port map (
+        Scan_En          => Scan_En,
+        Scan_Reset_Sel   => Scan_Reset_Sel,
+        Scan_Reset       => Scan_Reset,
+        Functional_Reset => reset,
+        Reset            => async_reset);
+      
+      Async_Rst_DFFs : process(Clk, async_reset)
+      begin
+        if async_reset = '1' then
+          sync <= C_RESET_VALUE; 
+        elsif Clk'event and Clk = '1' then
+          sync <= Raw;
+        end if;
+      end process;
+
+    end generate use_async_reset;
+
+    Synced <= sync;
+    
+  end generate Single_Synchronize;
+
+  -- No synchronizer DFFs, connect input to output directly
+  No_Synchronize : if C_LEVELS = 0 generate
+  begin
+    Synced <= Raw;
+  end generate No_Synchronize;
+      
+end architecture IMP;  -- mb_sync_bit
+
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.mb_sync_bit;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mb_sync_vec is
+  generic(
+    C_LEVELS            : natural   := 2;
+    C_RESET_VALUE       : std_logic := '0';
+    C_RESET_SYNCHRONOUS : boolean   := true;
+    C_RESET_ACTIVE_HIGH : boolean   := true;
+    C_WIDTH             : natural);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic := '0';
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic := '0';
+    Scan_Reset     : in  std_logic := '0';
+    Raw            : in  std_logic_vector(0 to C_WIDTH-1);
+    Synced         : out std_logic_vector(0 to C_WIDTH-1));
+end mb_sync_vec;
+
+architecture IMP of mb_sync_vec is
+
+  component mb_sync_bit
+  generic(
+    C_LEVELS            : natural;
+    C_RESET_VALUE       : std_logic;
+    C_RESET_SYNCHRONOUS : boolean;
+    C_RESET_ACTIVE_HIGH : boolean);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic;
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic;
+    Scan_Reset     : in  std_logic;
+    Raw            : in  std_logic;
+    Synced         : out std_logic);
+  end component;
+  
+begin
+
+  sync_bits: for I in 0 to C_WIDTH-1 generate
+  begin
+    
+    sync_bit : mb_sync_bit
+      generic map(
+        C_LEVELS             => C_LEVELS,
+        C_RESET_VALUE        => C_RESET_VALUE,
+        C_RESET_SYNCHRONOUS  => C_RESET_SYNCHRONOUS,
+        C_RESET_ACTIVE_HIGH  => C_RESET_ACTIVE_HIGH)
+      port map (
+        Clk            => Clk,
+        Rst            => Rst,
+        Scan_En        => Scan_En,
+        Scan_Reset_Sel => Scan_Reset_Sel,
+        Scan_Reset     => Scan_Reset,
+        Raw            => Raw(I),
+        Synced         => Synced(I));
+    
+  end generate sync_bits;  
+
+end architecture IMP;   -- mb_sync_vec
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mb_sync_reset is
+  generic(
+    C_LEVELS            : natural := 2;
+    C_RESET_VALUE       : std_logic := '1';
+    C_RESET_ACTIVE_HIGH : boolean := true);
+  port(
+    Clk            : in  std_logic;
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic;
+    Scan_Reset     : in  std_logic;
+    Raw            : in  std_logic;
+    Synced         : out std_logic);
+end mb_sync_reset;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.xil_scan_reset_control;
+
+architecture IMP of mb_sync_reset is
+
+  component xil_scan_reset_control is
+  port (
+    Scan_En          : in  std_logic;
+    Scan_Reset_Sel   : in  std_logic;
+    Scan_Reset       : in  std_logic;
+    Functional_Reset : in  std_logic;
+    Reset            : out std_logic);
+  end component xil_scan_reset_control;
+
+  signal preset       : std_logic;
+  signal async_preset : std_logic;
+
+  -- Downgrade Synth 8-3332 warnings
+  attribute DowngradeIPIdentifiedWarnings: string;
+  attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
+
+begin
+
+  -- Internal preset always has active high polarity 
+  preset <= Raw when C_RESET_ACTIVE_HIGH else
+            not Raw;
+
+  -- Make sure asynchronous preset can be controlled during scan test
+  scan_reset_control_i: xil_scan_reset_control
+    port map (
+      Scan_En          => Scan_En,
+      Scan_Reset_Sel   => Scan_Reset_Sel,
+      Scan_Reset       => Scan_Reset,
+      Functional_Reset => preset,
+      Reset            => async_preset);
+
+  -- Generate synchronizer DFFs
+  Synchronize : if C_LEVELS > 1 generate
+    signal sync : std_logic_vector(1 to C_LEVELS) := (others => C_RESET_VALUE);
+    attribute ASYNC_REG : string;
+    attribute ASYNC_REG of sync : signal is "TRUE";
+  begin
+
+    Reset_DFFs : process(Clk)
+    begin
+      if async_preset = '1' then
+        sync <= (sync'range  => C_RESET_VALUE); 
+      elsif Clk'event and Clk = '1' then
+        for I in C_LEVELS downto 2 loop
+          sync(I) <= sync(I-1);
+        end loop;
+        sync(1) <= Raw;
+      end if;
+    end process;
+
+    Synced <= sync(C_LEVELS);
+  end generate Synchronize;
+
+  -- 1 synchronizer DFF
+  Single_Synchronize : if C_LEVELS = 1 generate
+    signal sync : std_logic := C_RESET_VALUE;
+  begin
+
+    Reset_DFFs : process(Clk)
+    begin
+      if async_preset = '1' then
+        sync <= C_RESET_VALUE;
+      elsif Clk'event and Clk = '1' then
+        sync <= Raw;
+      end if;
+    end process;
+
+    Synced <= sync;
+  end generate Single_Synchronize;
+
+  -- No synchronizer DFFs, connect input to output directly
+  No_Synchronize : if C_LEVELS = 0 generate
+  begin
+    Synced <= Raw;
+  end generate No_Synchronize;
+
+end architecture IMP;  -- mb_sync_reset
+
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.mb_sync_bit;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity pulse_sync is
+  generic(
+    C_LEVELS          : natural := 2;
+    C_TMR             : natural := 0;
+    C_LATE_ACK        : natural := 0;
+    C_USE_TMR_DISABLE : integer := 0);
+  port(
+    FromAVote       : in  std_logic_vector(PULSE_SYNC_Pos);
+    FromBVote       : in  std_logic_vector(PULSE_SYNC_Pos);
+    ToVote          : out std_logic_vector(PULSE_SYNC_Pos);
+    Clk_Src         : in  std_logic;
+    Clk_Dst         : in  std_logic;
+    Rst_Src         : in  std_logic;
+    Rst_Dst         : in  std_logic;
+    TMR_Disable_Src : in  std_logic;
+    TMR_Disable_Dst : in  std_logic;
+    Pulse_Src       : in  std_logic;
+    Pulse_Keep_Src  : out std_logic;
+    Pulse_Ack_Src   : out std_logic;
+    Pulse_Dst       : out std_logic);
+end pulse_sync;
+
+architecture IMP of pulse_sync is
+
+  component mb_sync_bit
+  generic(
+    C_LEVELS            : natural;
+    C_RESET_VALUE       : std_logic;
+    C_RESET_SYNCHRONOUS : boolean;
+    C_RESET_ACTIVE_HIGH : boolean);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic;
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic;
+    Scan_Reset     : in  std_logic;
+    Raw            : in  std_logic;
+    Synced         : out std_logic);
+  end component;
+
+  signal pulseQ_src            : std_logic;
+  signal pulse_ack_src_I       : std_logic;
+  signal pulse_keep_src_I      : std_logic;
+  signal pulse_keepD_src       : std_logic;
+  signal pulse_keepD_src_voted : std_logic;
+  signal pulse_ack_dst         : std_logic;
+  signal pulse_keep_dst        : std_logic; 
+  signal pulse_keepQ_dst       : std_logic; 
+  signal pulse_keepQQ_dst      : std_logic; 
+  signal pulseD_dst            : std_logic;
+  signal pulseD_dst_voted      : std_logic;
+  
+begin
+
+  ---------------------------------------------------------------------------------------
+  -- Edge detect means that pulse need to be transferred from Src to
+  -- Dst clk region regardless of clock ratio between Clk_Src and Clk_Dst
+  ---------------------------------------------------------------------------------------
+  --  
+  --             Clk_Src                  |             Clk_Dst
+  --                                      |                         ____
+  -- Pulse------------                    |             ---------->|    |    ____
+  --       |   ____   |     ____          |            |           |    |   |    |
+  --       |  |    |   --->|    |   ____  |   ______   |  ____Vote>|Edge|-->| FF |-> Pulse
+  --        ->| FF |------>|Edge|  |    | |  |      |  | |    |    |    |   |_/\_| 
+  --          |_/\_| Vote->|Keep|->| FF |--->| Sync |--->| FF |--->|    |
+  --                 ----->|____|  |_/\_| |  |______| |  |_/\_|  | |____|
+  --                |                     |           |          | 
+  --                |  ______             |           |   ____   |  
+  --                | |      |            |           |  |    |  |
+  -- Pulse Ack <------| Sync |<---------------C_LATE_ACK-| FF |<- 
+  --                  |______|            |              |_/\_|
+  --                                      |
+  --                                      
+  --------------------------------------------------------------------------------------
+
+  -- Clock once to enable rising edge detect
+  Pulse_Src_DFF : process (Clk_Src) is
+  begin
+    if Clk_Src'event and Clk_Src = '1' then
+      if Rst_Src = '1' then
+        pulseQ_src <= '0';
+      else
+        pulseQ_src <= Pulse_Src;
+      end if;
+    end if;
+  end process Pulse_Src_DFF;
+
+  -- Detect rising Edge on Src and Ack (synced) from Dst
+  Pulse_Keep_Logic : process (pulseQ_src, Pulse_Src, pulse_ack_src_I, pulse_keep_src_I) is
+  begin
+    if Pulse_Src = '0' and pulse_ack_src_I = '1' then
+      pulse_keepD_src <= '0'; -- Pulse not active in Clk_Src and Ack from Clk_Dst region, done
+    elsif pulseQ_src = '0' and Pulse_Src = '1' then 
+      pulse_keepD_src <= '1'; -- Rising edge, set keep
+    else
+      pulse_keepD_src <= pulse_keep_src_I; -- else keep value
+    end if;
+  end process Pulse_Keep_Logic;
+
+  TMR_Yes : if (C_TMR /= 0) generate
+    signal tmr_disable_src_b : boolean;
+    signal tmr_disable_dst_b : boolean;
+  begin
+    tmr_disable_src_b <= TMR_Disable_Src = '1' and C_USE_TMR_DISABLE = 1;
+    tmr_disable_dst_b <= TMR_Disable_Dst = '1' and C_USE_TMR_DISABLE = 1;
+
+    ToVote(PULSE_SYNC_PULSE_Pos) <= pulseD_dst;
+    ToVote(PULSE_SYNC_KEEP_Pos)  <= pulse_keepD_src;
+
+    pulse_keepD_src_voted <= vote(pulse_keepD_src,
+                                  FromAVote(PULSE_SYNC_KEEP_Pos),
+                                  FromBVote(PULSE_SYNC_KEEP_Pos), tmr_disable_src_b);
+
+    pulseD_dst_voted <= vote(pulseD_dst,
+                             FromAVote(PULSE_SYNC_PULSE_Pos),
+                             FromBVote(PULSE_SYNC_PULSE_Pos), tmr_disable_dst_b);
+
+  end generate TMR_Yes; 
+
+  TMR_No : if (C_TMR = 0) generate
+    ToVote <= (others => '0');
+
+    pulse_keepD_src_voted <= pulse_keepD_src;
+    pulseD_dst_voted      <= pulseD_dst;
+  end generate TMR_No; 
+  
+  -- Keep DFF
+  Pulse_Src_Keep_DFF : process (Clk_Src) is
+  begin
+    if Clk_Src'event and Clk_Src = '1' then
+      if Rst_Src = '1' then
+        pulse_keep_src_I <= '0';
+      else
+        pulse_keep_src_I <= pulse_keepD_src_voted;
+      end if;
+    end if;
+  end process Pulse_Src_Keep_DFF;
+
+  Pulse_Keep_Src <= pulse_keep_src_I;
+  
+  -- Sync keep to Clk_Dst region
+  Pulse_Keep_Keep_Sync_I: mb_sync_bit
+  generic map(
+    C_LEVELS            => C_LEVELS,
+    C_RESET_VALUE       => '0',
+    C_RESET_SYNCHRONOUS => true,
+    C_RESET_ACTIVE_HIGH => true)
+  port map(
+    Clk            => Clk_Dst,
+    Rst            => Rst_Dst,
+    Scan_En        => '0',
+    Scan_Reset_Sel => '0',
+    Scan_Reset     => '0',
+    Raw            => pulse_keep_src_I,
+    Synced         => pulse_keep_dst);
+
+  -- Clock once to enable rising edge detect
+  Pulse_Dst_Ack_DFF : process (Clk_Dst) is
+  begin
+    if Clk_Dst'event and Clk_Dst = '1' then
+      if Rst_Dst = '1' then
+        pulse_keepQ_dst <= '0';
+        pulse_keepQQ_dst <= '0';
+      else
+        pulse_keepQQ_dst <= pulse_keepQ_dst;
+        pulse_keepQ_dst <= pulse_keep_dst;
+      end if;
+    end if;
+  end process Pulse_Dst_Ack_DFF;
+
+  -- Detect Edge
+  Pulse_Dst_Edge_Logic : process (pulse_keepQ_dst, pulse_keep_dst) is
+  begin
+    if pulse_keepQ_dst = '0' and pulse_keep_dst = '1' then
+      pulseD_dst <= '1'; -- Rising edge
+    else
+      pulseD_dst <= '0';
+    end if;  
+  end process Pulse_Dst_Edge_Logic;
+    
+  -- Clock output 
+  Pulse_Dst_DFF : process (Clk_Dst) is
+  begin
+    if Clk_Dst'event and Clk_Dst = '1' then
+      if Rst_Dst = '1' then
+        Pulse_Dst <= '0';
+      else
+        Pulse_Dst <= pulseD_dst_voted;
+      end if;
+    end if;
+  end process Pulse_Dst_DFF;
+
+  Early_Ack : if C_LATE_ACK = 0 generate
+  begin
+    pulse_ack_dst <= pulse_keepQ_dst;
+  end generate Early_Ack;
+
+  Late_Ack : if C_LATE_ACK = 1 generate
+  begin
+    pulse_ack_dst <= pulse_keepQQ_dst;
+  end generate Late_Ack;
+  
+  -- Sync ack back to Clk_Src region to remove keep
+  Pulse_Ack_Sync_I: mb_sync_bit
+  generic map(
+    C_LEVELS            => C_LEVELS,
+    C_RESET_VALUE       => '0',
+    C_RESET_SYNCHRONOUS => true,
+    C_RESET_ACTIVE_HIGH => true)
+  port map(
+    Clk            => Clk_Src,
+    Rst            => Rst_Src,
+    Scan_En        => '0',
+    Scan_Reset_Sel => '0',
+    Scan_Reset     => '0',
+    -- ToDo generic for delayed ack
+    Raw            => pulse_ack_dst,
+    Synced         => pulse_ack_src_I);
+
+   Pulse_Ack_Src <= pulse_ack_src_I;
+  
+end architecture IMP;   -- irq_sync
+
+
+
+
+-------------------------------------------------------------------------------
+-- divide_part.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        divide_part.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              divide_part.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-19    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity Divide_part is
+  generic (
+    C_TARGET    : TARGET_FAMILY_TYPE;
+    C_USE_SRL16 : string;
+    Ratio       : natural;
+    First       : boolean := true
+    );
+  port (
+    Config_Reset : in  std_logic;
+    Clk          : in  std_logic;
+    Rst          : in  std_logic;
+    Clk_En       : in  std_logic;
+    Clk_En_Out   : out std_logic
+    );
+
+end entity Divide_part;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture VHDL_RTL of Divide_part is
+  
+  component XIL_SRL16E is
+    generic (
+      C_TARGET    : TARGET_FAMILY_TYPE;
+      C_USE_SRL16 : string;
+      C_STATIC    : boolean := false;
+      INIT        : bit_vector);
+    port (
+      Config_Reset : in  std_logic;
+      Q            : out std_logic;
+      A0           : in  std_logic;
+      A1           : in  std_logic;
+      A2           : in  std_logic;
+      A3           : in  std_logic;
+      CE           : in  std_logic;
+      CLK          : in  std_logic;
+      D            : in  std_logic);
+  end component XIL_SRL16E;
+  
+  component XIL_SRLC16E is
+    generic (
+      C_TARGET    : TARGET_FAMILY_TYPE;
+      C_USE_SRL16 : string;
+      INIT        : bit_vector);
+    port (
+      Config_Reset : in  std_logic;
+      Q            : out std_logic;
+      Q15          : out std_logic;
+      A0           : in  std_logic;
+      A1           : in  std_logic;
+      A2           : in  std_logic;
+      A3           : in  std_logic;
+      CE           : in  std_logic;
+      CLK          : in  std_logic;
+      D            : in  std_logic);
+  end component XIL_SRLC16E;
+  
+  signal loop_Bit   : std_logic;
+  signal loop_Bit_i : std_logic;
+
+  -- Set clock enable during reset
+  signal Clk_En_i   : std_logic;
+
+  -- Previous cycle reset, used to determine when to shift in a 1
+  signal Rst_d1     : std_logic := '0';
+
+  -- This prevents an X from showing up in ModelSim
+  -- by simulating the default value in the hardware
+  signal Clk_En_Out_i : std_logic := '0';
+
+  constant Nr_Of_SRL16      : natural                      := 1 + ((Ratio-1)/16);
+  constant Last_SRL16_Ratio : natural                      := ((Ratio-1) mod 16);
+  constant A                : std_logic_vector(3 downto 0) :=
+    std_logic_vector(to_unsigned(Last_SRL16_Ratio, 4));
+
+begin  -- architecture VHDL_RTL
+  
+  One_SRL16 : if (Nr_Of_SRL16 = 1) generate
+  begin
+    SRL16E_I : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,     -- [string]
+        INIT        => X"0001")         -- [bit_vector]
+      port map (
+        Config_Reset => Config_Reset,   -- [in  std_logic]
+        CE           => Clk_En_i,       -- [in  std_logic]
+        D            => loop_Bit_i,     -- [in  std_logic]
+        Clk          => Clk,            -- [in  std_logic]
+        A0           => A(0),           -- [in  std_logic]
+        A1           => A(1),           -- [in  std_logic]
+        A2           => A(2),           -- [in  std_logic]
+        A3           => A(3),           -- [in  std_logic]
+        Q            => loop_Bit);      -- [out std_logic]
+  end generate One_SRL16;
+
+  Two_SRL16 : if (Nr_Of_SRL16 = 2) generate
+
+    signal shift   : std_logic;
+    signal shift_i : std_logic;
+    -- signal Emptys : std_logic_vector(0 to Nr_Of_SRL16);
+  begin
+    -- Shift in 0's during reset
+    shift_i <= shift;
+
+    -- The first SRLC16E
+    SRLC16E_1 : XIL_SRLC16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,     -- [string]
+        INIT        => X"0001")         -- [bit_vector]
+      port map (
+        Config_Reset => Config_Reset,   -- [in  std_logic]
+        CE           => Clk_En_i,       -- [in  std_logic]
+        D            => loop_Bit_i,     -- [in  std_logic]
+        Clk          => Clk,            -- [in  std_logic]
+        A0           => '1',            -- [in  std_logic]
+        A1           => '1',            -- [in  std_logic]
+        A2           => '1',            -- [in  std_logic]
+        A3           => '1',            -- [in  std_logic]
+        Q15          => shift,          -- [out  std_logic]
+        Q            => open);          -- [out std_logic]
+
+    SRL16E_2 : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,     -- [string]
+        INIT        => X"0000")         -- [bit_vector]
+      port map (
+        Config_Reset => Config_Reset,   -- [in  std_logic]
+        CE           => Clk_En_i,       -- [in  std_logic]
+        D            => shift_i,        -- [in  std_logic]
+        Clk          => Clk,            -- [in  std_logic]
+        A0           => A(0),           -- [in  std_logic]
+        A1           => A(1),           -- [in  std_logic]
+        A2           => A(2),           -- [in  std_logic]
+        A3           => A(3),           -- [in  std_logic]
+        Q            => loop_Bit);      -- [out std_logic]
+  end generate Two_SRL16;
+
+  More_Than_Two : if (Nr_Of_SRL16 > 2) generate
+
+    signal shifts   : std_logic_vector(1 to Nr_Of_SRL16-1);
+    signal shifts_i : std_logic_vector(1 to Nr_Of_SRL16-1);
+    -- signal Emptys : std_logic_vector(0 to Nr_Of_SRL16);
+  begin
+
+    -- Shift in 0's during reset
+    Shifts_I_Rst : for I in 1 to Nr_Of_SRL16-1 generate
+       shifts_i(I) <= shifts(I);
+    end generate Shifts_I_Rst;
+
+    -- The first SRLC16E
+    SRLC16E_1 : XIL_SRLC16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,     -- [string]
+        INIT        => X"0001")         -- [bit_vector]
+      port map (
+        Config_Reset => Config_Reset,   -- [in  std_logic]
+        CE           => Clk_En_i,       -- [in  std_logic]
+        D            => loop_Bit_i,     -- [in  std_logic]
+        Clk          => Clk,            -- [in  std_logic]
+        A0           => '1',            -- [in  std_logic]
+        A1           => '1',            -- [in  std_logic]
+        A2           => '1',            -- [in  std_logic]
+        A3           => '1',            -- [in  std_logic]
+        Q15          => shifts(1),      -- [out  std_logic]
+        Q            => open);          -- [out std_logic]
+
+    The_Rest : for I in 1 to Nr_Of_SRL16-2 generate
+    begin
+      SRLC16E_I : XIL_SRLC16E
+        generic map (
+          C_TARGET    => C_TARGET,
+          C_USE_SRL16 => C_USE_SRL16,    -- [string]
+          INIT        => X"0000")        -- [bit_vector]
+        port map (
+          Config_Reset => Config_Reset,  -- [in  std_logic]
+          CE           => Clk_En_i,      -- [in  std_logic]
+          D            => shifts_i(I),   -- [in  std_logic]
+          Clk          => Clk,           -- [in  std_logic]
+          A0           => '1',           -- [in  std_logic]
+          A1           => '1',           -- [in  std_logic]
+          A2           => '1',           -- [in  std_logic]
+          A3           => '1',           -- [in  std_logic]
+          Q15          => shifts(I+1),   -- [out  std_logic]
+          Q            => open);         -- [out std_logic]
+
+    end generate The_Rest;
+
+    -- The last SRL16
+    SRL16E_n : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,               -- [string]
+        INIT        => X"0000")                   -- [bit_vector]
+      port map (
+        Config_Reset => Config_Reset,             -- [in  std_logic]
+        CE           => Clk_En_i,                 -- [in  std_logic]
+        D            => shifts_i(Nr_Of_SRL16-1),  -- [in  std_logic]
+        Clk          => Clk,                      -- [in  std_logic]
+        A0           => A(0),                     -- [in  std_logic]
+        A1           => A(1),                     -- [in  std_logic]
+        A2           => A(2),                     -- [in  std_logic]
+        A3           => A(3),                     -- [in  std_logic]
+        Q            => loop_Bit);                -- [out std_logic]
+
+  end generate More_Than_Two;
+
+  -- Store if the previous cycle was a reset
+  Clk_Rst_D1 : process (Clk) is
+  begin
+    if Clk'event and Clk = '1' then   -- rising clock edge
+      Rst_d1 <= Rst;
+    end if;
+  end process Clk_Rst_D1;
+
+  -- Set clock enable during reset, Rst_d1 is necessary to load
+  -- the 1 bit in from loop_bit_i
+  clk_en_i   <= Clk_En;-- or Rst or Rst_d1;
+
+  -- Loops around from previous interrupt, or inserts after reset
+  -- The reset pulse must be at least 17 cycles
+  loop_Bit_i <= loop_Bit; --(loop_Bit or Rst_d1);
+
+  -- Same signal, but internal version has default value for
+  -- simulation
+  Clk_En_Out <= Clk_En_Out_i;
+
+  -----------------------------------------------------------------------------
+  -- If the SRL16 is the first in a series then the output is a clean single
+  -- clock pulse
+  -----------------------------------------------------------------------------
+  Is_First : if (First) generate
+    Clk_En_Out_i <= loop_Bit;
+  end generate Is_First;
+
+
+  -----------------------------------------------------------------------------
+  -- If not the first the output has to be masked so that it produce a single
+  -- clock pulse
+  -----------------------------------------------------------------------------
+  not_First : if (not First) generate
+    signal Out1 : std_logic;
+  begin
+
+    Out1_DFF : process (Clk) is
+    begin  -- process Out1_DFF
+      if Clk'event and Clk = '1' then   -- rising clock edge
+        Out1 <= loop_Bit;
+      end if;
+    end process Out1_DFF;
+
+    Out2_DFF : process (Clk) is
+    begin  -- process Out2_DFF
+      if Clk'event and Clk = '1' then   -- rising clock edge
+        if (Out1 = '1') then
+          Clk_En_Out_i <= Clk_En;
+        end if;
+      end if;
+    end process Out2_DFF;
+    
+  end generate not_First;
+end architecture VHDL_RTL;
+
+
+-------------------------------------------------------------------------------
+-- fit_module.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011-2012,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        fit_module.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--              fit_module.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-19    First Version
+-- stefana  2012-05-30    Fixed log2 function
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity FIT_Module is
+  generic (
+    C_TARGET          : TARGET_FAMILY_TYPE;
+    C_TMR             : integer := 0;
+    C_USE_TMR_DISABLE : integer := 0;
+    C_VOTE_SIZE       : integer := 0;
+    C_USE_SRL16       : string;
+    C_USE_FIT         : integer := 1;
+    C_NO_CLOCKS       : integer := 6216;  -- The number of clocks between each interrupt
+    C_INACCURACY      : integer := 5      -- The maximum inaccuracy of the number
+                                          -- of clocks allowed in per thousands
+    );
+  port (
+    Config_Reset : in  std_logic;
+    Clk          : in  std_logic;
+    Reset        : in  boolean;
+    TMR_Disable  : in  std_logic;
+    FromAVote    : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote    : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote       : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    Toggle       : out std_logic;
+    Interrupt    : out std_logic);
+end entity FIT_Module;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.all;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+architecture VHDL_RTL of FIT_Module is
+
+  constant C_NO_CLOCKS_MIN : integer := 3;
+
+  component Divide_Part is
+    generic (
+      C_TARGET    : TARGET_FAMILY_TYPE;
+      C_USE_SRL16 : string;
+      Ratio       : natural;
+      First       : boolean);
+    port (
+      Config_Reset : in  std_logic;
+      Clk          : in  std_logic;
+      Rst          : in  std_logic;
+      Clk_En       : in  std_logic;
+      Clk_En_Out   : out std_logic);
+  end component Divide_Part;
+
+  component MB_MUXCY_XORCY is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE);
+    port (
+      O  : out std_logic;
+      LO : out std_logic;
+      CI : in  std_logic;
+      DI : in  std_logic;
+      S  : in  std_logic);
+  end component MB_MUXCY_XORCY;
+
+  -- log2 function returns the number of bits required to encode x choices
+  function log2(x : natural) return integer is
+    variable i : integer := 0;
+  begin
+    if x = 0 then return 0;
+    elsif x > 2**30 then return 31;
+    else
+      while 2**i < x loop
+        i := i+1;
+      end loop;
+      return i;
+    end if;
+  end function log2;
+
+  -----------------------------------------------------------------------------
+  -- All supported architectures have the SRL16C primitive, we will actually
+  -- looking for factorials upto 128 (upto 7 SRL16s in a chain)
+  -- looking for any more is not efficient since 128 can be done with 7 LUTs in
+  -- a normal counter
+  -----------------------------------------------------------------------------
+  constant MAX_DIV_FACTOR : natural := 128;
+
+  subtype SRL16_DIV_TYPE is natural range 2 to MAX_DIV_FACTOR;
+  type FACTORS_LIST_TYPE is array (natural range 1 to 15) of SRL16_DIV_TYPE;
+
+  type FACTORS_TYPE is
+  record
+    Good_Divide   : boolean;
+    Nr_Of_Factors : natural;
+    Factor_List   : FACTORS_LIST_TYPE;
+    Nr_Of_SRL16s  : natural;
+  end record FACTORS_TYPE;
+
+  -----------------------------------------------------------------------------
+  -- Trying to divide R into integer values of values 2-16 until the end result
+  -- is between 2-16.
+  --
+  -- This function returns a FACTORS_TYPE which contains:
+  -- FACTOR_LIST   - List of factors
+  -- Nr_Of_Factors - Number of factors / Number of divide_parts needed
+  -- Nr_Of_SRL16s  - Number of SRL16s
+  -- Good_Divide   - Whether the number could be factored
+  -----------------------------------------------------------------------------
+  function Get_Factors (R : natural) return FACTORS_TYPE is
+    variable N      : natural := R;
+    variable Result : FACTORS_TYPE;
+    variable no     : natural := 1;
+    variable Found  : boolean;
+  begin  -- function Get_Factors
+    -- Initialize values
+    Result.Nr_Of_Factors := 0;
+    Result.Nr_Of_SRL16s  := 0;
+    Result.Factor_List   := (2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
+
+    -- Check if we can do it in one SRL16
+    if (N < 16) then
+      Result.FACTOR_LIST(1) := N;
+      Result.Nr_Of_Factors  := 1;
+      Result.Good_Divide    := true;
+      Result.Nr_Of_SRL16s   := 1;
+      return Result;
+    end if;
+
+    -- Each time through this loop it finds a factor
+    -- The factor gets added to FACTOR_LIST(no)
+    -- The Nr_Of_SRL16s is increased appropriately
+    while N /= 1 loop
+      Found := false;
+      -- Trying first with a single SRL16 since it the most efficient implementation
+      --
+      -- Find largest factor from 16 down to 2, because no matter what value
+      -- it is in this range, it will use a single SRL16
+      for I in 16 downto 2 loop
+        if ((N mod I = 0)) then         -- Found factor
+          Result.FACTOR_LIST(no) := I;
+          Result.Nr_Of_SRL16s    := Result.Nr_Of_SRL16s + 1;
+          N                      := N / I;
+          no                     := no + 1;
+          Found                  := true;
+          exit;
+        end if;
+      end loop;  -- I
+
+      -- No factor from 2 to 16
+      if (not(Found)) then
+        -- Trying from 17 upto MAX_DIV_FACTOR to find if a chain of SRL16 can
+        -- be used
+        -- Find the smallest value for the smallest chain
+        for I in 17 to MAX_DIV_FACTOR loop
+          if ((N mod I = 0)) then       -- Found factor
+            Result.FACTOR_LIST(no) := I;
+            Result.Nr_Of_SRL16s    := Result.Nr_Of_SRL16s + (1 + ((I-1)/16));
+            N                      := N / I;
+            no                     := no + 1;
+            Found                  := true;
+            exit;
+          end if;
+        end loop;  -- I
+      end if;
+
+      -- No factor from 2 to MAX_DIV_FACTOR
+      if (not(Found)) then
+        -- Could not factor
+        Result.Good_Divide := false;
+        exit;
+      end if;
+    end loop;
+    if (found) then
+      Result.Good_Divide   := true;
+      Result.Nr_Of_Factors := no-1;
+    end if;
+    return Result;
+  end function Get_Factors;
+
+  -----------------------------------------------------------------------------
+  -- Trying to find a ratio that is within 1.5% of the asked ratio and that the
+  -- ratio can be implemented with SRL16.
+  -----------------------------------------------------------------------------
+  function Find_Best_Factors (R : natural) return FACTORS_TYPE is
+    constant Proc_Diff : natural := R*C_INACCURACY/1000;  -- Calculate the max difference
+                                                          -- for the maximum inaccuracy
+    variable Result    : FACTORS_TYPE;
+  begin  -- function Find_Best_Factors
+    Result := Get_Factors(R);
+
+    if (Result.Good_Divide) then
+      return Result;
+    end if;
+
+    -- This if statement gets rid of a warning if C_INACCURACY = 0
+    if (Proc_Diff > 0) then
+      for I in 1 to Proc_Diff loop
+        Result := Get_Factors(R+I);
+        if (Result.Good_Divide) then
+          return Result;
+        end if;
+        Result := Get_Factors(R-I);
+        if (Result.Good_Divide) then
+          return Result;
+        end if;
+      end loop;  -- I
+    end if;  -- Proc_Diff > 0
+
+    Result.Good_Divide := false;
+    return Result;
+  end function Find_Best_Factors;
+
+begin  -- architecture VHDL_RTL
+
+  Implement_FIT : if (C_USE_FIT /= 0 and C_NO_CLOCKS >= C_NO_CLOCKS_MIN) generate
+
+    constant Nr_Of_Bits     : natural := log2(C_NO_CLOCKS-1);
+    constant Divide_Factors : FACTORS_TYPE := Find_Best_Factors(C_NO_CLOCKS);
+    signal Interrupt_i : std_logic := '0';
+    signal rst_i       : std_logic;
+    signal toggle_i    : std_logic;
+
+  begin
+
+    -----------------------------------------------------------------------------
+    -- handle the reset
+    -----------------------------------------------------------------------------
+    rst_i <= '1' when Reset else '0';
+
+    -----------------------------------------------------------------------------
+    -- A clean and good ratio was found that was within the 1.5% limit, so
+    -- implement the fit_timer division using SRL16s but only if the number of
+    -- SRL16 is less than what is needed for a standard down-counter
+    --
+    -- ex. the value 127*127 = 16129 can be split into two SRL16 chain where each
+    -- chain is 8 SRL16 => a total of 16 SRL16. But a 14-bit counter can count to
+    -- 16129 and it will only consume 14 LUTs so it's more area efficient
+    -----------------------------------------------------------------------------
+    Using_SRL16s : if (Divide_Factors.Good_Divide) and
+                      (Divide_Factors.Nr_Of_SRL16s <= Nr_Of_Bits) and (C_TMR = 0) generate
+
+      signal Clk_En_I : std_logic_vector(0 to Divide_Factors.Nr_Of_Factors);
+
+    begin
+      Clk_En_I(0) <= '1';
+
+      SRL16s : for I in 1 to Divide_Factors.Nr_Of_Factors generate
+      begin
+
+        Divide_I : Divide_Part
+          generic map (
+            C_TARGET    => C_TARGET,
+            C_USE_SRL16 => C_USE_SRL16,                    -- [string]
+            Ratio       => Divide_Factors.FACTOR_LIST(I),  -- [natural range 2 to 16]
+            First       => (I = 1))                        -- [boolean]
+          port map (
+            Config_Reset => Config_Reset,                  -- [in  std_logic]
+            Clk          => Clk,                           -- [in  std_logic]
+            Rst          => rst_i,                         -- [in  std_logic]
+            Clk_En       => Clk_En_I(I-1),                 -- [in  std_logic]
+            Clk_En_Out   => Clk_En_I(I));                  -- [out std_logic]
+
+      end generate SRL16s;
+
+      Interrupt_i <= Clk_En_I(Divide_Factors.Nr_Of_Factors);
+
+      ToVote <= (others => '0');
+    end generate Using_SRL16s;
+
+    -----------------------------------------------------------------------------
+    -- Couldn't find a good ratio within the 1.5% limit so implement the fit_timer
+    -- generation using a standard counter or
+    -- the number of SRL16 is greater than the number of LUTS a standard down-counter needs
+    -----------------------------------------------------------------------------
+    Using_Counter : if (not Divide_Factors.Good_Divide) or
+                       (Divide_Factors.Nr_Of_SRL16s > Nr_Of_Bits) or (C_TMR /= 0) generate
+
+      constant New_Value : std_logic_vector(0 to Nr_Of_Bits-1) :=
+        std_logic_vector(to_unsigned(natural(C_NO_CLOCKS-2), Nr_Of_Bits));
+
+      signal Cnt         : std_logic_vector(0 to Nr_Of_Bits-1);
+      signal New_Cnt     : std_logic_vector(0 to Nr_Of_Bits-1);
+      signal Carry       : std_logic_vector(0 to Nr_Of_Bits);
+      signal Count       : std_logic_vector(0 to Nr_Of_Bits-1) := New_Value;
+      signal rst_cnt     : std_logic                           := '0';
+
+    begin
+
+      -- Reset the counter
+      rst_cnt <= Interrupt_i or rst_i;
+
+      Carry(Nr_Of_Bits) <= '0';         -- Always subtracting
+
+      All_Bits : for I in Nr_Of_Bits-1 downto 0 generate
+      begin
+        -- New_Cnt counts up
+        -- New_Cnt(I) <= not(Count(I)) when Interrupt_i = '0' else New_Value(I);
+        New_Cnt(I) <= not(Count(I));
+
+        MUXCY_XORCY_L_I1 : MB_MUXCY_XORCY
+          generic map (
+            C_TARGET => C_TARGET)
+          port map (
+            DI => Count(I),             -- [in  std_logic S = 0]
+            CI => Carry(I+1),           -- [in  std_logic S = 1]
+            S  => New_Cnt(I),           -- [in  std_logic (Select)]
+            LO => Carry(I),             -- [out std_logic]
+            O  => Cnt(I));              -- [out std_logic]
+
+      end generate All_Bits;
+
+      TMR_No : if (C_TMR = 0) generate
+      begin
+        -- Count goes from all 1's during interrupt_i
+        -- then C_NO_CLOCKS-1 down to 0 between interrupts
+        Counter : process (Clk) is
+        begin  -- process Counter
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            if rst_cnt = '1' then
+              Count       <= New_Value;
+              Interrupt_i <= '0';
+            else
+              Count       <= Cnt;
+              Interrupt_i <= not Carry(0);
+            end if;
+          end if;
+        end process Counter;
+
+        ToVote(FIT_COUNT_Pos)     <= (others => '0');
+        ToVote(FIT_INTERRUPT_Pos) <= '0';
+
+      end generate TMR_No;
+
+      TMR_Yes : if (C_TMR /= 0) generate
+        signal tmr_disable_b : boolean;
+        signal Interrupt_i_d : std_logic;
+        signal Count_d       : std_logic_vector(0 to Nr_Of_Bits-1);
+      begin
+
+        tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+        Counter_Logic : process (rst_cnt, Cnt, Carry) is
+        begin
+          if rst_cnt = '1' then
+            Count_d       <= New_Value;
+            Interrupt_i_d <= '0';
+          else
+            Count_d       <= Cnt;
+            Interrupt_i_d <= not Carry(0);
+          end if;
+        end process Counter_Logic;
+
+        ToVote(FIT_COUNT_Pos'low + Count_d'length - 1 downto FIT_COUNT_Pos'low) <= Count_d;
+        ToVote(FIT_COUNT_Pos'high downto FIT_COUNT_POs'low + Count_d'length )   <= (others => '0');
+
+        ToVote(FIT_INTERRUPT_Pos) <= Interrupt_i_d;
+
+        Counter_DFF : process (Clk) is
+        begin
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            Count       <= vote(Count_d,
+                                FromAVote(FIT_COUNT_Pos'low + Count_d'length - 1 downto FIT_COUNT_Pos'low),
+                                FromBVote(FIT_COUNT_Pos'low + Count_d'length - 1 downto FIT_COUNT_Pos'low),
+                                tmr_disable_b);
+            Interrupt_i <= vote(Interrupt_i_d,FromAVote(FIT_INTERRUPT_Pos),FromBVote(FIT_INTERRUPT_Pos),
+                                tmr_disable_b);
+          end if;
+        end process Counter_DFF;
+
+      end generate TMR_Yes;
+
+    end generate Using_Counter;
+
+    Interrupt <= Interrupt_i;
+
+    TMR_No_Toggle : if (C_TMR = 0) generate
+    begin
+
+      Toggle_Handler : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          if Reset then
+            toggle_i <= '0';
+          elsif Interrupt_i = '1' then
+            toggle_i <= not toggle_i;
+          end if;
+        end if;
+      end process Toggle_Handler;
+
+      ToVote(FIT_TOGGLE_Pos) <= '0';
+
+    end generate TMR_No_Toggle;
+
+    TMR_Yes_Toggle : if (C_TMR /= 0) generate
+      signal tmr_disable_b  : boolean;
+      signal toggle_i_d     : std_logic;
+    begin
+
+      tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+      Toggle_Logic : process (Reset, toggle_i, Interrupt_i) is
+      begin
+        if Reset then
+          toggle_i_d <= '0';
+        elsif Interrupt_i = '1' then
+          toggle_i_d <= not toggle_i;
+        else
+          toggle_i_d <= toggle_i;
+        end if;
+      end process Toggle_Logic;
+
+      Toggle_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          toggle_i <= vote(toggle_i_d,FromAVote(FIT_TOGGLE_Pos),FromBVote(FIT_TOGGLE_Pos),tmr_disable_b);
+        end if;
+      end process Toggle_DFF;
+
+      ToVote(FIT_TOGGLE_Pos) <= toggle_i_d;
+
+    end generate TMR_Yes_Toggle;
+
+    Toggle <= toggle_i;
+
+  end generate Implement_FIT;
+
+  Nothing : if (C_USE_FIT = 0 or C_NO_CLOCKS < C_NO_CLOCKS_MIN) generate
+  begin
+    Interrupt <= '0';
+    Toggle    <= '0';
+    ToVote    <= (others => '0');
+  end generate Nothing;
+
+end architecture VHDL_RTL;
+
+
+-------------------------------------------------------------------------------
+-- gpi_module.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        gpi_module.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:   
+--              gpi_module.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran   2007-12-19    First Version
+--   stefana 2012-03-20    Added interrupt
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity GPI_Module is
+  generic (
+    C_USE_GPI       : integer;
+    C_GPI_SIZE      : integer;
+    C_GPI_INTERRUPT : integer);
+  port (
+    Clk           : in  std_logic;
+    Reset         : in  boolean;
+    Config_Reset  : in  std_logic;
+    GPI_Read      : in  std_logic;
+    GPI           : in  std_logic_vector(C_GPI_SIZE-1 downto 0);
+    GPI_In        : out std_logic_vector(C_GPI_SIZE-1 downto 0);
+    GPI_Interrupt : out std_logic
+    );
+end entity GPI_Module;
+
+architecture IMP of GPI_Module is
+
+begin  -- architecture IMP
+
+  Using_GPI : if (C_USE_GPI /= 0) generate
+    signal GPI_Sampled : std_logic_vector(C_GPI_SIZE-1 downto 0);
+  begin
+
+    ----------------------------------------------------------------------------------------------
+    -- Hold GPI_In signal in constant reset until we want to read the values.
+    -- This allows us to just ORing all IO registers which we want to read
+    ----------------------------------------------------------------------------------------------
+    GPI_Sampling : process (Clk) is
+    begin  -- process GPI_Sampling
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if (GPI_Read = '0' or Config_Reset = '1') then       -- synchronous reset (active high)
+          GPI_In <= (others => '0');
+        else
+          GPI_In <= GPI;
+        end if;
+        if Config_Reset = '1' then
+          GPI_Sampled <= (others => '0');
+        else
+          GPI_Sampled <= GPI;
+        end if;
+      end if;
+    end process GPI_Sampling;
+
+    ----------------------------------------------------------------------------------------------
+    -- Generate interupt pulse whenever input differs from sampled value according to setting
+    ----------------------------------------------------------------------------------------------
+    Use_GPI_Interrupt : if (C_GPI_INTERRUPT /= 0) generate
+      constant Zero : std_logic_vector(C_GPI_SIZE-1 downto 0) := (others => '0');
+    begin
+
+      GPI_Interrupt_DFF : process (Clk) is
+      begin  -- process GPI_Interrupt_DFF
+        if Clk'event and Clk = '1' then  -- rising clock edge
+          if Reset then
+            GPI_Interrupt <= '0';
+          elsif (C_GPI_INTERRUPT = 1 and (GPI_Sampled /= GPI))              or    -- Both
+                (C_GPI_INTERRUPT = 2 and (not GPI_Sampled and GPI) /= Zero) or    -- Rising
+                (C_GPI_INTERRUPT = 3 and (GPI_Sampled and not GPI) /= Zero) then  -- Falling
+            GPI_Interrupt <= '1';
+          else
+            GPI_Interrupt <= '0';
+          end if;
+        end if;
+      end process GPI_Interrupt_DFF;
+
+    end generate Use_GPI_Interrupt;
+
+    No_GPI_Interrupt : if (C_GPI_INTERRUPT = 0) generate
+    begin
+      GPI_Interrupt <= '0';
+    end generate No_GPI_Interrupt;
+
+  end generate Using_GPI;
+
+  No_GPI : if (C_USE_GPI = 0) generate
+  begin
+    GPI_In        <= (others => '0');
+    GPI_Interrupt <= '0';
+  end generate No_GPI;
+  
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- gpo_module.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        gpo_module.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:   
+--              gpo_module.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-19    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity GPO_Module is
+  
+  generic (
+    C_TMR             : integer := 0;
+    C_USE_TMR_DISABLE : integer := 0;
+    C_VOTE_SIZE       : integer := 0;
+    C_USE_GPO         : integer := 1;
+    C_GPO_SIZE        : integer range 1 to 32 := 32;
+    C_GPO_INIT        : std_logic_vector(31 downto 0) := (others => '0'));
+  port (
+    Clk         : in  std_logic;
+    Reset       : in  boolean;
+    GPO_Write   : in  std_logic;
+    Write_Data  : in  std_logic_vector(31 downto 0);
+    TMR_Disable : in  std_logic;
+    FromAVote   : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote   : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote      : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    GPO         : out std_logic_vector(C_GPO_SIZE-1 downto 0));    
+end entity GPO_Module;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+architecture IMP of GPO_Module is
+
+  signal gpo_io_i : std_logic_vector(C_GPO_SIZE-1 downto 0);
+  
+begin  -- architecture IMP
+
+  TMR_No : if (C_TMR = 0 and C_USE_GPO /= 0) generate
+  begin
+
+      GPO_DFF : process (Clk) is
+      begin  -- process GPO_DFF
+        if Clk'event and Clk = '1' then  -- rising clock edge
+          if Reset then                  -- synchronous reset (active high)
+            gpo_io_i <= C_GPO_INIT(gpo_io_i'range);
+          elsif (GPO_Write = '1') then
+            gpo_io_i <= Write_Data(gpo_io_i'range);
+          end if;
+        end if;
+      end process GPO_DFF;
+      
+    ToVote <= (others => '0');
+
+  end generate TMR_No;
+
+  TMR_Yes : if (C_TMR /= 0 and C_USE_GPO /= 0) generate
+    signal tmr_disable_b : boolean;
+    signal gpo_io_i_d    : std_logic_vector(C_GPO_SIZE-1 downto 0);
+  begin
+    
+    tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+     GPO_logic : process (Reset, GPO_Write, Write_Data, gpo_io_i) is
+    begin 
+      if Reset then
+        gpo_io_i_d <= C_GPO_INIT(gpo_io_i'range);
+      elsif (GPO_Write = '1') then
+        gpo_io_i_d <= Write_Data(gpo_io_i'range);
+      else
+        gpo_io_i_d <= gpo_io_i;
+      end if;
+    end process GPO_Logic;
+
+    ToVote(gpo_io_i_d'range)                          <= gpo_io_i_d;
+    ToVote(C_MAX_GPO_SIZE-1 downto gpo_io_i_d'high+1) <= (others => '0');
+    
+    GPO_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        gpo_io_i <= vote(gpo_io_i_d, FromAVote(gpo_io_i_d'range), FromBVote(gpo_io_i_d'range),tmr_disable_b); 
+      end if;
+    end process GPO_DFF;
+
+  end generate TMR_Yes;
+  
+  Empty : if (C_USE_GPO = 0) generate
+  begin
+    gpo_io_i <= (others => '0');
+    ToVote   <= (others => '0');
+  end generate Empty;
+
+  GPO <= gpo_io_i;
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- intr_ctrl.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011-2012,2016,2018 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        intr_ctrl.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              intr_ctrl.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2008-01-08    First Version
+--   stefan 2011-12-28    Added Fast Interrupt
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity intr_ctrl is
+
+  generic (
+    C_TARGET            : TARGET_FAMILY_TYPE;
+    C_TMR               : integer := 0;
+    C_USE_TMR_DISABLE   : integer := 0;
+    C_VOTE_SIZE         : integer := 0;
+    C_USE_COMB_MUX      : integer := 0;
+    C_ADDR_WIDTH        : integer range 32 to 64 := 32;
+    C_INTC_ENABLED      : std_logic_vector(31 downto 0);
+    C_INTC_LEVEL_EDGE   : std_logic_vector(31 downto 0);
+    C_INTC_POSITIVE     : std_logic_vector(31 downto 0);
+    C_INTC_ASYNC_INTR   : std_logic_vector(31 downto 0);
+    C_INTC_HAS_FAST     : integer range 0 to 1  := 0;
+    C_INTC_ADDR_WIDTH   : integer range 5 to 64 := 32;
+    C_INTC_NUM_SYNC_FF  : integer range 0 to 7  := 2;
+    C_INTC_BASE_VECTORS : std_logic_vector(63 downto 0);
+    C_USE_LUTRAM        : string);
+  port (
+    Clk               : in  std_logic;
+    Reset             : in  boolean;
+    TMR_Disable       : in  std_logic;
+    FromAVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote            : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    INTR              : in  std_logic_vector(31 downto 0);
+    INTR_ACK          : in  std_logic_vector(1 downto 0);
+    INTR_ADDR         : out std_logic_vector(C_ADDR_WIDTH-1 downto 0);
+    INTC_WRITE_CIAR   : in  std_logic;
+    INTC_WRITE_CIER   : in  std_logic;
+    INTC_WRITE_CIMR   : in  std_logic;
+    INTC_WRITE_CIVAR  : in  std_logic;
+    INTC_WRITE_CIVEAR : in  std_logic;
+    INTC_CIVAR_ADDR   : in  std_logic_vector(4 downto 0);
+    Write_Data        : in  std_logic_vector(31 downto 0);
+    INTC_READ_CISR    : in  std_logic;
+    INTC_READ_CIPR    : in  std_logic;
+    INTC_IRQ          : out std_logic;
+    INTC_CISR         : out std_logic_vector(31 downto 0);
+    INTC_CIPR         : out std_logic_vector(31 downto 0));
+end entity intr_ctrl;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+use iomodule_v3_1_6.mb_sync_bit;
+
+architecture IMP of intr_ctrl is
+
+  component MB_FDR is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE;
+      INIT : bit := '0');
+    port(
+      Q  : out std_logic;
+      C  : in  std_logic;
+      D  : in  std_logic;
+      R  : in  std_logic);
+  end component MB_FDR;
+
+  component mb_sync_bit is
+  generic(
+    C_LEVELS            : natural   := 2;
+    C_RESET_VALUE       : std_logic := '0';
+    C_RESET_SYNCHRONOUS : boolean   := true;
+    C_RESET_ACTIVE_HIGH : boolean   := true);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic;
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic;
+    Scan_Reset     : in  std_logic;
+    Raw            : in  std_logic;
+    Synced         : out std_logic);
+  end component mb_sync_bit;
+
+  constant C_ENABLED_NONE : boolean := (C_INTC_ENABLED = (31 downto 0  => '0'));
+  constant C_ENABLED_MSH  : boolean := (C_INTC_ENABLED(31 downto 16) /= X"0000");
+  constant C_CIVAR_WIDTH  : integer := Boolean'Pos(C_ENABLED_MSH) + 4;
+  constant C_CIVAR_SIZE   : integer := 2 ** C_CIVAR_WIDTH;
+
+  constant C_BASE_VECTORS : std_logic_vector(63 downto 0) :=
+    (C_INTC_BASE_VECTORS and X"FFFFFFFFFFFFFF80") or X"0000000000000010";
+  constant C_DEFAULT_ADDR : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) :=
+    C_BASE_VECTORS(C_ADDR_WIDTH - 1 downto 0);
+
+  constant USE_LUTRAM : boolean := C_USE_LUTRAM = "yes";
+
+  signal interrupt    : std_logic_vector(31 downto 0);
+  signal intr_present : std_logic_vector(31 downto 0);
+  signal cisr         : std_logic_vector(31 downto 0);
+  signal cier         : std_logic_vector(31 downto 0);
+  signal cipr         : std_logic_vector(31 downto 0);
+  signal rst_cipr_rd  : std_logic;
+  signal rst_cipr_rd_voted : std_logic;
+  signal civr         : std_logic_vector(4 downto 0);
+  signal fast_ack     : std_logic_vector(31 downto 0);
+  signal cimr         : std_logic_vector(31 downto 0);
+
+  signal tmr_disable_b : boolean;
+
+begin
+
+  tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1 and C_TMR = 1;
+
+  All_INTR_Bits : for I in 31 downto 0 generate
+  begin
+
+    Using_Intr : if (C_INTC_ENABLED(I) = '1') generate
+    begin
+
+      -- Clean the interrupt signals
+      -- All internal sources are considered clean and only external needs to be registred once
+      Ext_Intr : if (I > 15) generate
+        constant C_RESET_VALUE : std_logic :=  not C_INTC_POSITIVE(I);
+        signal synced_intr : std_logic;
+      begin
+
+        -- Synchronize the interrupt signals
+        Async_Gen : if C_INTC_ASYNC_INTR(I) = '1' generate
+          signal reset_std : std_logic;
+        begin
+
+          reset_std <= '1' when reset else '0';
+          
+          sync_bit_i : mb_sync_bit
+          generic map(
+            C_LEVELS            => C_INTC_NUM_SYNC_FF,
+            C_RESET_VALUE       => C_RESET_VALUE,
+            C_RESET_SYNCHRONOUS => true,
+            C_RESET_ACTIVE_HIGH => true)
+          port map(
+            Clk            => Clk,
+            Rst            => reset_std,
+            Scan_En        => '0',
+            Scan_Reset_Sel => '0',
+            Scan_Reset     => '0',
+            Raw            => INTR(I),
+            Synced         => synced_intr);
+          
+        end generate Async_Gen;
+
+        Sync_Gen: if C_INTC_ASYNC_INTR(I) = '0' generate
+        begin
+          synced_intr <= INTR(i);
+        end generate Sync_Gen;
+
+        Clean_TMR_No : if (C_TMR = 0) generate
+        begin
+
+          Clean_Signal : process (Clk) is
+          begin  -- process Clean_Signal
+            if Clk'event and Clk = '1' then  -- rising clock edge
+              if Reset then                  -- synchronous reset (active high)
+                interrupt(I) <= not C_INTC_POSITIVE(I);
+              else
+                interrupt(I) <= synced_intr;
+              end if;
+            end if;
+          end process Clean_Signal;
+
+          ToVote(IRQ_INTERRUPT_Pos'low + I) <= '0';
+
+        end generate Clean_TMR_No;
+
+        Clean_TMR_Yes : if (C_TMR /= 0) generate
+          signal interrupt_d : std_logic;
+        begin
+
+          Clean_Signal : process (Reset,synced_intr) is
+          begin
+            if Reset then
+              interrupt_d <= not C_INTC_POSITIVE(I);
+            else
+              interrupt_d <= synced_intr;
+            end if;
+          end process Clean_Signal;
+
+          ToVote(IRQ_INTERRUPT_Pos'low + I) <= interrupt_d;
+
+          Clean_Signal_DFF : process (Clk) is
+          begin
+            if Clk'event and Clk = '1' then
+              interrupt(I) <= vote(interrupt_d,
+                                   FromAVote(IRQ_INTERRUPT_Pos'low+I),
+                                   FromBVote(IRQ_INTERRUPT_Pos'low+I), tmr_disable_b);
+            end if;
+          end process Clean_Signal_DFF;
+
+        end generate Clean_TMR_Yes;
+
+        -- Detect External Interrupt
+        Level : if (C_INTC_LEVEL_EDGE(I) = '0') generate
+        begin
+          intr_present(I) <= interrupt(I) xnor C_INTC_POSITIVE(I);
+        end generate Level;
+
+        Edge_TMR_No : if (C_TMR = 0) generate
+        begin
+
+          Edge : if (C_INTC_LEVEL_EDGE(I) = '1') generate
+          begin
+            Reg_INTR : process (Clk) is
+              variable s1 : std_logic;
+            begin  -- process Reg_INTR
+              if Clk'event and Clk = '1' then  -- rising clock edge
+                if Reset then                  -- synchronous reset (active high)
+                  intr_present(I) <= '0';
+                  s1              := not C_INTC_POSITIVE(I);
+                else
+                  intr_present(I) <= '0';
+                  if (C_INTC_POSITIVE(I) = '0') and (s1 = '1') and (interrupt(I) = '0') then
+                    intr_present(I) <= '1';
+                  end if;
+                  if (C_INTC_POSITIVE(I) = '1') and (s1 = '0') and (interrupt(I) = '1') then
+                    intr_present(I) <= '1';
+                  end if;
+                  s1 := interrupt(I);
+                end if;
+              end if;
+            end process Reg_INTR;
+          end generate Edge;
+
+          ToVote(IRQ_INTR_PRESENT_Pos'low + I) <= '0';
+
+        end generate Edge_TMR_No;
+
+        Edge_TMR_Yes : if (C_TMR /= 0) generate
+        begin
+
+          Edge : if (C_INTC_LEVEL_EDGE(I) = '1') generate
+            signal intr_present_d : std_logic;
+            signal s1   : std_logic;
+          begin
+
+            Reg_INTR_Logic : process (Reset, s1, interrupt) is
+            begin
+              if Reset then
+                intr_present_d <= '0';
+              else
+                if ((C_INTC_POSITIVE(I) = '0') and (s1 = '1') and (interrupt(I) = '0')) or
+                   ((C_INTC_POSITIVE(I) = '1') and (s1 = '0') and (interrupt(I) = '1')) then
+                  intr_present_d <= '1';
+                else
+                  intr_present_d <= '0';
+                end if;
+              end if;
+            end process Reg_INTR_Logic;
+
+            ToVote(IRQ_INTR_PRESENT_Pos'low + I) <= intr_present_d;
+
+            Reg_INTR_DFF : process (Clk) is
+            begin  -- process Reg_INTR
+              if Clk'event and Clk = '1' then  -- rising clock edge
+                if (Reset) then
+                  s1 <= not C_INTC_POSITIVE(I);
+                else
+                  s1 <= interrupt(I);   -- no need to vote s1 as it follows interrupt which is voted
+                end if;
+                intr_present(I) <= vote(intr_present_d,
+                                        FromAVote(IRQ_INTR_PRESENT_Pos'low+I),
+                                        FromBVote(IRQ_INTR_PRESENT_Pos'low+I), tmr_disable_b);
+              end if;
+            end process Reg_INTR_DFF;
+
+          end generate Edge;
+
+          Level : if (C_INTC_LEVEL_EDGE(I) = '0') generate
+          begin
+            ToVote(IRQ_INTR_PRESENT_Pos'low + I) <= '0';
+          end generate Level;
+
+        end generate Edge_TMR_Yes;
+
+      end generate Ext_Intr;
+
+      Internal_Intr : if (I < 16) generate
+      begin
+        -- Internal source is always one-clock long and active high, no need to detect an edge
+        intr_present(I)                       <= INTR(I);
+        interrupt(I)                          <= '0'; -- Unused
+        ToVote(IRQ_INTR_PRESENT_Pos'low + I)  <= '0'; -- no need to vote as it follows INTR
+        ToVote(IRQ_INTERRUPT_Pos'low + I)     <= '0'; -- no need to vote as it is not used
+      end generate Internal_Intr;
+
+      CISR_CIER_TMR_No : if (C_TMR = 0) generate
+      begin
+
+        CISR_Reg : process (Clk) is
+        begin  -- process CISR_Reg
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            if Reset then                  -- synchronous reset (active high)
+              cisr(I) <= '0';
+            else
+              if (intr_present(I) = '1') then
+                cisr(I) <= '1';
+              elsif (INTC_WRITE_CIAR = '1' and Write_Data(I) = '1') or (fast_ack(I) = '1') then
+                cisr(I) <= '0';
+              end if;
+            end if;
+          end if;
+        end process CISR_Reg;
+
+        CIER_Reg : process (Clk) is
+        begin  -- process CIER_Reg
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            if Reset then                  -- synchronous reset (active high)
+              cier(I) <= '0';
+            elsif (INTC_WRITE_CIER = '1') then
+              cier(I) <= Write_Data(I);
+            end if;
+          end if;
+        end process CIER_Reg;
+
+        ToVote(IRQ_CISR_Pos'low + I) <= '0';
+        ToVote(IRQ_CIER_Pos'low + I) <= '0';
+
+      end generate CISR_CIER_TMR_No;
+
+      CISR_CIER_TMR_Yes : if (C_TMR /= 0) generate
+        signal cisr_d : std_logic;
+        signal cier_d : std_logic;
+      begin
+
+        CISR_Logic : process (Reset, intr_present, INTC_WRITE_CIAR, Write_Data, fast_ack, cisr) is
+        begin
+          if Reset then
+            cisr_d <= '0';
+          else
+            if (intr_present(I) = '1') then
+              cisr_d <= '1';
+            elsif (INTC_WRITE_CIAR = '1' and Write_Data(I) = '1') or (fast_ack(I) = '1') then
+              cisr_d <= '0';
+            else
+              cisr_d <= cisr(I);
+            end if;
+          end if;
+        end process CISR_Logic;
+
+        ToVote(IRQ_CISR_Pos'low + I) <= cisr_d;
+
+        CISR_DFF : process (Clk) is
+        begin  -- process CISR_Reg
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            cisr(I) <= vote(cisr_d, FromAVote(IRQ_CISR_Pos'low + I), FromBVote(IRQ_CISR_Pos'low + I), tmr_disable_b);
+          end if;
+        end process CISR_DFF;
+
+        CIER_Reg : process (Reset, INTC_WRITE_CIER, Write_Data, cier) is
+        begin
+          if Reset then
+            cier_d <= '0';
+          elsif (INTC_WRITE_CIER = '1') then
+            cier_d <= Write_Data(I);
+          else
+            cier_d <= cier(I);
+          end if;
+        end process CIER_Reg;
+
+        ToVote(IRQ_CIER_Pos'low + I) <= cier_d;
+
+        CIER_DFF : process (Clk) is
+        begin  -- process CIER_Reg
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            cier(I) <= vote(cier_d, FromAVote(IRQ_CIER_Pos'low + I), FromBVote(IRQ_CIER_Pos'low + I), tmr_disable_b);
+          end if;
+        end process CIER_DFF;
+
+      end generate CISR_CIER_TMR_Yes;
+
+      cipr(I) <= cisr(I) and cier(I);
+
+    end generate Using_Intr;
+
+    Not_Using_Intr : if (C_INTC_ENABLED(I) = '0') generate
+    begin
+      interrupt(I)                         <= '0';
+      intr_present(I)                      <= '0';
+      cier(I)                              <= '0';
+      cisr(I)                              <= '0';
+      cipr(I)                              <= '0';
+      ToVote(IRQ_INTERRUPT_Pos'low    + I) <= '0';
+      ToVote(IRQ_INTR_PRESENT_Pos'low + I) <= '0';
+      ToVote(IRQ_CISR_Pos'low         + I) <= '0';
+      ToVote(IRQ_CIER_Pos'low         + I) <= '0';
+    end generate Not_Using_Intr;
+
+    Using_CIMR : if (C_INTC_ENABLED(I) = '1') and (C_INTC_HAS_FAST = 1) generate
+    begin
+
+      CIMR_TMR_No : if (C_TMR = 0) generate
+      begin
+
+        CIMR_Reg : process (Clk) is
+        begin  -- process CIMR_Reg
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            if Reset then                  -- synchronous reset (active high)
+              cimr(I) <= '0';
+            elsif (INTC_WRITE_CIMR = '1') then
+              cimr(I) <= Write_Data(I);
+            end if;
+          end if;
+        end process CIMR_Reg;
+
+        ToVote(IRQ_CIMR_Pos'low + I) <= '0';
+
+      end generate CIMR_TMR_No;
+
+      CIMR_TMR_Yes: if (C_TMR /= 0) generate
+        signal cimr_d : std_logic;
+      begin
+
+        CIMR_Logic : process (Reset, cimr, INTC_WRITE_CIMR, Write_Data) is
+        begin
+          if Reset then
+            cimr_d <= '0';
+          elsif (INTC_WRITE_CIMR = '1') then
+            cimr_d <= Write_Data(I);
+          else
+            cimr_d <= cimr(I);
+          end if;
+        end process CIMR_Logic;
+
+        ToVote(IRQ_CIMR_Pos'low + I) <= cimr_d;
+
+        CIMR_DFF : process (Clk) is
+        begin  -- process CIMR_Reg
+          if Clk'event and Clk = '1' then  -- rising clock edge
+            cimr(I) <= vote(cimr_d, FromAVote(IRQ_CIMR_Pos'low + I), FromBVote(IRQ_CIMR_Pos'low + I), tmr_disable_b);
+          end if;
+        end process CIMR_DFF;
+
+      end generate CIMR_TMR_Yes;
+
+    end generate Using_CIMR;
+
+    Not_Using_CIMR : if (C_INTC_ENABLED(I) = '0') or (C_INTC_HAS_FAST = 0) generate
+    begin
+      cimr(I) <= '0';
+      ToVote(IRQ_CIMR_Pos'low + I) <= '0';
+    end generate Not_Using_CIMR;
+
+  end generate All_INTR_Bits;
+
+  Using_Fast : if C_INTC_HAS_FAST = 1 and not C_ENABLED_NONE generate
+    subtype byte_res_vec is std_logic_vector(2 downto 0);
+    type byte_res_array is array (3 downto 0) of byte_res_vec;
+
+    subtype mux_res_vec is std_logic_vector(4 downto 0);
+    type mux_res_array is array (4 downto 0) of mux_res_vec;
+
+    type civar_type is array (C_CIVAR_SIZE - 1 downto 0) of std_logic_vector(C_INTC_ADDR_WIDTH - 3 downto 0);
+
+    constant Idle         : std_logic_vector(1 downto 0) := "00";
+    constant Interrupting : std_logic_vector(1 downto 0) := "01";
+    constant Handling     : std_logic_vector(1 downto 0) := "10";
+    constant Acknowledge  : std_logic_vector(1 downto 0) := "11";
+
+    signal byte_zeros       : std_logic_vector(3 downto 0);
+    signal byte_res         : byte_res_array;
+    signal mux_res          : mux_res_array;
+    signal fast_state       : std_logic_vector(1 downto 0);
+    signal do_fast_ack      : std_logic;
+    signal civar            : civar_type := (others => C_DEFAULT_ADDR(C_INTC_ADDR_WIDTH - 1 downto 2));
+    signal civar_read_addr  : std_logic_vector(C_CIVAR_WIDTH - 1 downto 0);
+    signal civar_write_addr : std_logic_vector(C_CIVAR_WIDTH - 1 downto 0);
+    signal intr_addr_i      : std_logic_vector(C_INTC_ADDR_WIDTH - 3 downto 0);
+    signal early_ack        : std_logic;
+    signal has_fast         : std_logic;
+
+    attribute ram_style            : string;
+    attribute ram_style of civar   : signal is "distributed";
+    attribute ram_extract          : string;
+    attribute ram_extract of civar : signal is C_USE_LUTRAM;
+
+  begin
+
+    -- Calculate first bit set to get highest priority interrupt number (civr)
+    Calc_Byte_Res: for I in 0 to 3 generate
+    begin
+      byte_zeros(I)  <= '1' when cipr(8*I+7 downto 8*I) = "00000000" else '0';
+
+      byte_res(I)(2) <= '1' when cipr(8*I+3 downto 8*I) = "0000" else '0';
+
+      byte_res(I)(1) <= '0' when cipr(8*I+0) = '1' or cipr(8*I+1) = '1' else
+                        '1' when cipr(8*I+2) = '1' or cipr(8*I+3) = '1' else
+                        '0' when cipr(8*I+4) = '1' or cipr(8*I+5) = '1' else
+                        '1';
+
+      byte_res(I)(0) <= '0' when cipr(8*I+0)= '1' else
+                        '1' when cipr(8*I+1)= '1' else
+                        '0' when cipr(8*I+2)= '1' else
+                        '1' when cipr(8*I+3)= '1' else
+                        '0' when cipr(8*I+4)= '1' else
+                        '1' when cipr(8*I+5)= '1' else
+                        '0' when cipr(8*I+6)= '1' else
+                        '1';
+    end generate Calc_Byte_Res;
+
+    mux_res(4) <= "00000";
+    Mux_the_Results: for I in natural range 3 downto 0 generate
+    begin
+      mux_res(I) <= mux_res(I+1) when byte_zeros(I) = '1' else
+                    std_logic_vector(to_unsigned(I,2)) & byte_res(I);
+    end generate Mux_the_Results;
+
+    Fast_FSM_TMR_No : if (C_TMR = 0) generate
+    begin
+
+      -- Handle interrupt occurrence and acknowledge
+      Fast_FSM : process(Clk)
+      begin
+        if Clk'event and Clk = '1' then
+          if Reset then                   -- synchronous reset (active high)
+            fast_state  <= Idle;
+            INTC_IRQ    <= '0';
+            civr        <= (others => '0');
+            do_fast_ack <= '0';
+          else
+            case fast_state is
+              when Idle =>                -- wait for interrupt
+                if byte_zeros /= "1111" then
+                  fast_state <= Interrupting;
+                end if;
+                INTC_IRQ    <= '0';
+                civr        <= mux_res(0);
+                do_fast_ack <= '0';
+              when Interrupting =>        -- wait for first ack
+                if INTR_ACK = "01" then
+                  fast_state  <= Handling;
+                  INTC_IRQ    <= '0';
+                  do_fast_ack <= early_ack and has_fast;
+                else
+                  INTC_IRQ    <= '1';
+                  do_fast_ack <= '0';
+                end if;
+              when Handling =>            -- wait for second ack
+                if INTR_ACK(1) = '1' then
+                  fast_state  <= Acknowledge;
+                  do_fast_ack <= not early_ack and has_fast;
+                else
+                  do_fast_ack <= '0';
+                end if;
+                INTC_IRQ <= '0';
+              when Acknowledge =>         -- wait until acknowledged in cisr
+                fast_state  <= Idle;
+                do_fast_ack <= '0';
+                INTC_IRQ    <= '0';
+              when others =>
+                null;
+            end case;
+          end if;
+        end if;
+      end process Fast_FSM;
+
+      ToVote(IRQ_FAST_STATE_Pos)  <= (others => '0');
+      ToVote(IRQ_INTC_IRQ_Pos)    <= '0';
+      ToVote(IRQ_CIVR_Pos)        <= (others => '0');
+      ToVote(IRQ_DO_FAST_ACK_Pos) <= '0';
+
+    end generate Fast_FSM_TMR_No;
+
+    Fast_FSM_TMR_Yes : if (C_TMR /= 0) generate
+      signal fast_state_d  : std_logic_vector(1 downto 0);
+      signal INTC_IRQ_d    : std_logic;
+      signal civr_d        : std_logic_vector(4 downto 0);
+      signal do_fast_ack_d : std_logic;
+    begin
+      -- Handle interrupt occurrence and acknowledge
+      Fast_FSM_Logic : process(Reset, fast_state, civr, do_fast_ack,
+                               byte_zeros, mux_res, early_ack, has_fast, INTR_ACK)
+      begin
+        if Reset then
+          fast_state_d  <= Idle;
+          INTC_IRQ_d    <= '0';
+          civr_d        <= (others => '0');
+          do_fast_ack_d <= '0';
+        else
+          case fast_state is
+            when Idle =>                -- wait for interrupt
+              if byte_zeros /= "1111" then
+                fast_state_d <= Interrupting;
+              else
+                fast_state_d <= fast_state;
+              end if;
+              INTC_IRQ_d    <= '0';
+              civr_d        <= mux_res(0);
+              do_fast_ack_d <= '0';
+            when Interrupting =>        -- wait for first ack
+              if INTR_ACK = "01" then
+                fast_state_d  <= Handling;
+                INTC_IRQ_d    <= '0';
+                do_fast_ack_d <= early_ack and has_fast;
+              else
+                fast_state_d  <= fast_state;
+                INTC_IRQ_d    <= '1';
+                do_fast_ack_d <= '0';
+              end if;
+              civr_d        <= civr;
+            when Handling =>            -- wait for second ack
+              if INTR_ACK(1) = '1' then
+                fast_state_d  <= Acknowledge;
+                do_fast_ack_d <= not early_ack and has_fast;
+              else
+                fast_state_d  <= fast_state;
+                do_fast_ack_d <= '0';
+              end if;
+              civr_d     <= civr;
+              INTC_IRQ_d <= '0';
+            when Acknowledge =>         -- wait until acknowledged in cisr
+              fast_state_d  <= Idle;
+              do_fast_ack_d <= '0';
+              INTC_IRQ_d    <= '0';
+              civr_d        <= civr;
+            when others =>
+              null;
+            end case;
+        end if;
+      end process Fast_FSM_Logic;
+
+      ToVote(IRQ_FAST_STATE_Pos)  <= fast_state_d;
+      ToVote(IRQ_INTC_IRQ_Pos)    <= INTC_IRQ_d;
+      ToVote(IRQ_CIVR_Pos)        <= civr_d;
+      ToVote(IRQ_DO_FAST_ACK_Pos) <= do_fast_ack_d;
+
+      Fast_FSM_DFF : process(Clk)
+      begin
+        if Clk'event and Clk = '1' then
+          fast_state  <= vote(fast_state_d,
+                              FromAVote(IRQ_FAST_STATE_Pos),
+                              FromBVote(IRQ_FAST_STATE_Pos), tmr_disable_b);
+          INTC_IRQ    <= vote(INTC_IRQ_d,
+                              FromAVote(IRQ_INTC_IRQ_Pos),
+                              FromBVote(IRQ_INTC_IRQ_Pos), tmr_disable_b);
+          civr        <= vote(civr_d,
+                              FromAVote(IRQ_CIVR_Pos),
+                              FromBVote(IRQ_CIVR_Pos), tmr_disable_b);
+          do_fast_ack <= vote(do_fast_ack_d,
+                              FromAVote(IRQ_DO_FAST_ACK_Pos),
+                              FromBVote(IRQ_DO_FAST_ACK_Pos), tmr_disable_b);
+        end if;
+      end process Fast_FSM_DFF;
+
+    end generate Fast_FSM_TMR_Yes;
+
+    Fast_Ack_Assign : process(civr, do_fast_ack)
+    begin
+      fast_ack <= (others => '0');
+      fast_ack(to_integer(unsigned(civr))) <= do_fast_ack;
+    end process Fast_Ack_Assign;
+
+    early_ack <= C_INTC_LEVEL_EDGE(to_integer(unsigned(civr)));
+    has_fast  <= cimr(to_integer(unsigned(civr)));
+
+    -- Vector address registers implemented as a LUTRAM
+    civar_write_addr <= INTC_CIVAR_ADDR(C_CIVAR_WIDTH - 1 downto 0);
+    civar_read_addr  <= civr(C_CIVAR_WIDTH - 1 downto 0);
+
+    Using_EA: if C_INTC_ADDR_WIDTH > 32 generate
+      signal write_data_hi : std_logic_vector(C_INTC_ADDR_WIDTH - 1 downto 32);
+      signal write_data_lo : std_logic_vector(31 downto 2);
+    begin
+      write_data_hi  <= Write_Data(C_INTC_ADDR_WIDTH - 33 downto 0);
+      write_data_lo  <= Write_Data(31 downto 2);
+
+      Using_LUTRAM: if USE_LUTRAM generate
+      begin
+
+        civar_reg : process(Clk)
+        begin
+          if Clk'event and Clk = '1' then
+            if (INTC_WRITE_CIVAR = '1') then
+              civar(to_integer(unsigned(civar_write_addr)))(29 downto 0) <= write_data_lo;
+            end if;
+            if (INTC_WRITE_CIVEAR = '1') then
+              civar(to_integer(unsigned(civar_write_addr)))(C_INTC_ADDR_WIDTH - 3 downto 30) <= write_data_hi;
+            end if;
+            intr_addr_i <= civar(to_integer(unsigned(civar_read_addr)));
+          end if;
+        end process civar_reg;
+
+      end generate Using_LUTRAM;
+
+      Not_Using_LUTRAM: if not USE_LUTRAM generate
+      begin
+
+        civar_reg : process(Clk)
+        begin
+          if Clk'event and Clk = '1' then
+            if (Reset) then
+              civar       <= (others => C_DEFAULT_ADDR(C_INTC_ADDR_WIDTH - 1 downto 2));
+              intr_addr_i <= (others => '0');
+            else
+              if (INTC_WRITE_CIVAR = '1') then
+                civar(to_integer(unsigned(civar_write_addr)))(29 downto 0) <= write_data_lo;
+              end if;
+              if (INTC_WRITE_CIVEAR = '1') then
+                civar(to_integer(unsigned(civar_write_addr)))(C_INTC_ADDR_WIDTH - 3 downto 30) <= write_data_hi;
+              end if;
+              intr_addr_i <= civar(to_integer(unsigned(civar_read_addr)));
+            end if;
+          end if;
+        end process civar_reg;
+
+      end generate Not_Using_LUTRAM;
+    end generate Using_EA;
+
+    Not_Using_EA: if C_INTC_ADDR_WIDTH <= 32 generate
+      signal write_data_i : std_logic_vector(C_INTC_ADDR_WIDTH - 3 downto 0);
+    begin
+      write_data_i <= Write_Data(C_INTC_ADDR_WIDTH - 1 downto 2);
+
+      Using_LUTRAM: if USE_LUTRAM generate
+      begin
+
+        civar_reg : process(Clk)
+        begin
+          if Clk'event and Clk = '1' then
+            if (INTC_WRITE_CIVAR = '1') then
+              civar(to_integer(unsigned(civar_write_addr))) <= write_data_i;
+              intr_addr_i <= civar(to_integer(unsigned(civar_read_addr)));
+            else
+              intr_addr_i <= civar(to_integer(unsigned(civar_read_addr)));
+            end if;
+          end if;
+        end process civar_reg;
+
+      end generate Using_LUTRAM;
+
+      Not_Using_LUTRAM: if not USE_LUTRAM generate
+      begin
+
+        civar_reg : process(Clk)
+        begin
+          if Clk'event and Clk = '1' then
+            if (Reset) then
+              civar       <= (others => C_DEFAULT_ADDR(C_INTC_ADDR_WIDTH - 1 downto 2));
+              intr_addr_i <= (others => '0');
+            elsif (INTC_WRITE_CIVAR = '1') then
+              civar(to_integer(unsigned(civar_write_addr))) <= write_data_i;
+              intr_addr_i <= civar(to_integer(unsigned(civar_read_addr)));
+            else
+              intr_addr_i <= civar(to_integer(unsigned(civar_read_addr)));
+            end if;
+          end if;
+        end process civar_reg;
+
+      end generate Not_Using_LUTRAM;
+    end generate Not_Using_EA;
+
+    INTR_ADDR_Assign : process(intr_addr_i)
+    begin
+      INTR_ADDR <= C_DEFAULT_ADDR;
+      INTR_ADDR(C_INTC_ADDR_WIDTH - 1 downto 2) <= intr_addr_i(C_INTC_ADDR_WIDTH - 3 downto 0);
+    end process INTR_ADDR_Assign;
+
+  end generate Using_Fast;
+
+  Not_Using_Fast : if C_INTC_HAS_FAST = 0 or C_ENABLED_NONE generate
+  begin
+    civr                        <= (others => '0');
+    fast_ack                    <= (others => '0');
+    INTR_ADDR                   <= C_DEFAULT_ADDR;
+    INTC_IRQ                    <= '1' when cipr /= X"00000000" else '0';
+    ToVote(IRQ_FAST_STATE_Pos)  <= (others => '0');
+    ToVote(IRQ_INTC_IRQ_Pos)    <= '0';
+    ToVote(IRQ_CIVR_Pos)        <= (others => '0');
+    ToVote(IRQ_DO_FAST_ACK_Pos) <= '0';
+  end generate Not_Using_Fast;
+
+  cisr_rd_dff : process (Clk) is
+  begin  -- process cisr_rd_dff
+    if Clk'event and Clk = '1' then   -- rising clock edge
+      if (INTC_READ_CISR = '0' or Reset) then  -- synchronous reset (active high)
+        INTC_CISR <= (others => '0');
+      else
+        INTC_CISR <= cisr;
+      end if;
+    end if;
+  end process cisr_rd_dff;
+
+  rst_cipr_rd <= not(INTC_READ_CIPR);
+
+  ToVote(IRQ_RST_CIPR_RD_Pos) <= rst_cipr_rd;
+
+  rst_cipr_rd_voted <= vote(rst_cipr_rd,
+                            FromAVote(IRQ_RST_CIPR_RD_Pos),
+                            FromBVote(IRQ_RST_CIPR_RD_Pos), tmr_disable_b, C_TMR);
+
+  cipr_rd_dff_all : for I in 0 to 31 generate
+  begin
+    fdr_i : MB_FDR
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        Q => INTC_CIPR(I),
+        C => Clk,
+        D => cipr(I),
+        R => rst_cipr_rd_voted);
+  end generate cipr_rd_dff_all;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- pit_module.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016-2017 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        pit_module.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              pit_module.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-19    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity PIT_Module is
+  generic (
+    C_TARGET          : TARGET_FAMILY_TYPE;
+    C_TMR             : integer := 0;
+    C_USE_TMR_DISABLE : integer := 0;
+    C_VOTE_SIZE       : integer := 0;
+    C_USE_PIT         : integer := 0;
+    C_PIT_SIZE        : integer := 16;
+    C_PIT_READABLE    : integer := 1
+    );
+  port (
+    Clk               : in  std_logic;
+    Reset             : in  boolean;
+    Config_Reset      : in  std_logic;
+    TMR_Disable       : in std_logic;
+    FromAVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote            : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    PIT_Count_En      : in  std_logic;
+    PIT_Write_Preload : in  std_logic;
+    PIT_Write_Ctrl    : in  std_logic;
+    PIT_Read          : in  std_logic;
+    Write_Data        : in  std_logic_vector(31 downto 0);
+    PIT_Data          : out std_logic_vector(C_PIT_SIZE-1 downto 0);
+    PIT_Toggle        : out std_logic;
+    PIT_Interrupt     : out std_logic);
+end entity PIT_Module;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+architecture IMP of PIT_Module is
+
+  component MB_MUXCY_XORCY is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE);
+    port (
+      O  : out std_logic;
+      LO : out std_logic;
+      CI : in  std_logic;
+      DI : in  std_logic;
+      S  : in  std_logic);
+  end component MB_MUXCY_XORCY;
+
+  component MB_LUT3 is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE;
+      INIT     : bit_vector := X"00");
+    port (
+      O  : out std_logic;
+      I0 : in  std_logic;
+      I1 : in  std_logic;
+      I2 : in  std_logic);
+  end component MB_LUT3;
+
+  component MB_MULT_AND is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE;
+      INIT : bit := '0');
+    port(
+      LO : out std_logic;
+      I0 : in  std_logic;
+      I1 : in  std_logic);
+  end component MB_MULT_AND;
+
+begin  -- architecture IMP
+
+  Using_PIT : if (C_USE_PIT /= 0) generate
+    signal preload_value   : std_logic_vector(C_PIT_SIZE-1 downto 0);
+    signal preload_written : std_logic;
+
+    signal reload   : std_logic;
+    signal count_en : std_logic;
+
+    signal count_enabled : std_logic;
+
+    -- Counter signals
+    signal count_load_n    : std_logic;
+    signal cnt             : std_logic_vector(C_PIT_SIZE-1 downto 0);
+    signal carry           : std_logic_vector(C_PIT_SIZE   downto 0);
+    signal count           : std_logic_vector(C_PIT_SIZE-1 downto 0);
+    signal count_wrap      : std_logic;
+    signal pit_interrupt_i : std_logic;
+    signal pit_toggle_i    : std_logic;
+  begin
+
+    TMR_No : if (C_TMR = 0) generate
+    begin
+      --------------------------------------------------------------------------------------------------
+      -- Preload register
+      --------------------------------------------------------------------------------------------------
+      PreLoad_Handler : process (Clk) is
+      begin  -- process PreLoad_Handler
+        if Clk'event and Clk = '1' then   -- rising clock edge
+          if Reset then                   -- synchronous reset (active high)
+            preload_value <= (others => '0');
+          elsif (PIT_Write_Preload = '1') then
+            preload_value <= Write_Data(C_PIT_SIZE-1 downto 0);
+          end if;
+        end if;
+      end process PreLoad_Handler;
+
+      --------------------------------------------------------------------------------------------------
+      -- Control Register
+      --------------------------------------------------------------------------------------------------
+      Ctrl_Handler : process (Clk) is
+      begin  -- process Ctrl_Handler
+        if Clk'event and Clk = '1' then   -- rising clock edge
+          if Reset then                   -- synchronous reset (active high)
+            reload          <= '0';
+            count_en        <= '0';
+            count_load_n    <= '1';
+            preload_written <= '0';
+          else
+            preload_written <= PIT_Write_Preload;
+            if (PIT_Write_Ctrl = '1') then
+              reload   <= Write_Data(1);
+              count_en <= Write_Data(0);
+            end if;
+            if ((count_wrap = '1') and (reload = '0') and (count_enabled = '1') and (count_load_n = '1')) then
+              count_en <= '0';
+            end if;
+
+            -- reach -1 and will load_counter with preload value
+            if ((count_wrap = '1') and (reload = '1') and (count_enabled = '1')) then
+              count_load_n <= '0';
+            end if;
+
+            -- if we have written to preload register, load counter with preload value next time we count
+            if (preload_written = '1') then
+              count_load_n <= '0';
+            end if;
+
+            -- Counter is now loaded so remove count_load_n
+            if (count_load_n = '0') and (count_enabled = '1') then
+              count_load_n <= '1';
+            end if;
+
+          end if;
+        end if;
+      end process Ctrl_Handler;
+
+      count_enabled <= count_en and PIT_Count_En;
+
+      Counter : process (Clk) is
+      begin  -- process Counter
+        if Clk'event and Clk = '1' then   -- rising clock edge
+          if Reset then
+            count <= (others => '0');
+          elsif (count_enabled = '1') then
+            count <= cnt;
+          end if;
+        end if;
+      end process Counter;
+
+      Interrupt_Handler : process (Clk) is
+      begin  -- process Interrupt_Handler
+        if Clk'event and Clk = '1' then   -- rising clock edge
+          if Reset then                   -- synchronous reset (active high)
+            pit_interrupt_i <= '0';
+          else
+            pit_interrupt_i <= count_wrap and count_enabled and count_load_n;
+          end if;
+        end if;
+      end process Interrupt_Handler;
+
+      Toggle_Handler : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          if Reset then
+            pit_toggle_i <= '0';
+          elsif pit_interrupt_i = '1' then
+            pit_toggle_i <= not pit_toggle_i;
+          end if;
+        end if;
+      end process Toggle_Handler;
+
+      ToVote <= (others => '0');
+
+    end generate TMR_No;
+
+    --------------------------------------------------------------------------------------------------
+    -- Counter
+    --------------------------------------------------------------------------------------------------
+    Using_FPGA: if (C_TARGET /= RTL) generate
+      signal new_cnt    : std_logic_vector(C_PIT_SIZE-1 downto 0);
+      signal new_cnt_di : std_logic_vector(C_PIT_SIZE-1 downto 0);
+    begin
+    
+      carry(0) <= '0';
+
+      All_Bits : for I in 0 to C_PIT_SIZE - 1 generate
+      begin
+
+        Count_LUT : MB_LUT3
+          generic map(
+            C_TARGET => C_TARGET,
+            INIT => X"72"
+            )
+          port map (
+            O  => new_cnt(I),             -- [out]
+            I0 => count_load_n,           -- [in]
+            I1 => count(I),               -- [in]
+            I2 => preload_value(I));      -- [in]
+
+        MULT_AND_I : MB_MULT_AND
+          generic map(
+            C_TARGET => C_TARGET)
+          port map (
+            I0 => count_load_n,           -- [in]
+            I1 => count(I),               -- [in]
+            LO => new_cnt_di(I));         -- [out]
+
+        MUXCY_XORCY_L_I1 : MB_MUXCY_XORCY
+          generic map(
+            C_TARGET => C_TARGET)
+          port map (
+            DI => new_cnt_di(I),          -- [in  std_logic S = 0]
+            CI => carry(I),               -- [in  std_logic S = 1]
+            S  => new_cnt(I),             -- [in  std_logic (Select)]
+            LO => carry(I+1),             -- [out std_logic]
+            O  => cnt(I));                -- [out std_logic]
+
+      end generate All_Bits;
+
+      count_wrap <= not carry(C_PIT_SIZE);
+
+    end generate Using_FPGA;
+
+    Using_RTL : if (C_TARGET = RTL) generate
+      signal count_extra : std_logic_vector(C_PIT_SIZE downto 0);
+    begin
+      count_extra <= '0' & count;
+      carry       <= std_logic_vector(unsigned(count_extra) - 1);
+      cnt         <= carry(C_PIT_SIZE-1 downto 0) when count_load_n = '1' else
+                     preload_value;
+      count_wrap  <= carry(C_PIT_SIZE);
+    end generate Using_RTL;
+
+    TMR_Yes : if (C_TMR /= 0) generate
+      signal tmr_disable_b     : boolean;
+      signal preload_value_d   : std_logic_vector(C_PIT_SIZE-1 downto 0);
+      signal count_d           : std_logic_vector(C_PIT_SIZE-1 downto 0);
+      signal reload_d          : std_logic;
+      signal count_en_d        : std_logic;
+      signal count_load_n_d    : std_logic;
+      signal preload_written_d : std_logic;
+      signal pit_interrupt_i_d : std_logic;
+      signal pit_toggle_i_d    : std_logic;
+    begin
+
+      tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+      --------------------------------------------------------------------------------------------------
+      -- Preload register
+      -------------------------------------------------------------------------------------------------
+      PreLoad_Handler_Logic : process (Reset, PIT_Write_Preload, Write_Data, preload_value) is
+      begin
+        if Reset then
+          preload_value_d <= (others => '0');
+        elsif (PIT_Write_Preload = '1') then
+          preload_value_d <= Write_Data(C_PIT_SIZE-1 downto 0);
+        else
+          preload_value_d <= preload_value;
+        end if;
+      end process PreLoad_Handler_Logic;
+
+      ToVote(PIT_PRELOAD_VALUE_Pos'low + C_PIT_SIZE - 1 downto PIT_PRELOAD_VALUE_Pos'low) <= preload_value_d;
+      -- Work around spyglass bug report on null range to the left but not to the right
+      spy1_g: if C_PIT_SIZE < 32 generate
+      begin
+        ToVote(PIT_PRELOAD_VALUE_Pos'high downto PIT_PRELOAD_VALUE_Pos'low + C_PIT_SIZE) <= (others => '0');
+      end generate spy1_g;
+
+      PreLoad_Handler_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          preload_value <= vote(preload_value_d,
+                                FromAVote(PIT_PRELOAD_VALUE_Pos),
+                                FromBVote(PIT_PRELOAD_VALUE_Pos), tmr_disable_b);
+        end if;
+      end process PreLoad_Handler_DFF;
+
+      --------------------------------------------------------------------------------------------------
+      -- Control Register
+      --------------------------------------------------------------------------------------------------
+      Ctrl_Handler_Logic : process (Reset, PIT_Write_Preload, PIT_Write_Ctrl, Write_Data, count_wrap,
+                                    reload, count_en, count_enabled, count_load_n, preload_written) is
+      begin
+        if Reset then
+          reload_d          <= '0';
+          count_en_d        <= '0';
+          count_load_n_d    <= '1';
+          preload_written_d <= '0';
+        else
+          if (PIT_Write_Ctrl = '1') then
+            reload_d <= Write_Data(1);
+          else
+            reload_d <= reload;
+          end if;
+
+          if ((count_wrap = '1') and (reload = '0') and (count_enabled = '1') and (count_load_n = '1')) then
+            count_en_d <= '0';
+          elsif (PIT_Write_Ctrl = '1') then
+            count_en_d <= Write_Data(0);
+          else
+            count_en_d <= count_en;
+          end if;
+
+          -- Counter is now loaded so remove count_load_n
+          if (count_load_n = '0') and (count_enabled = '1') then
+            count_load_n_d <= '1';
+          -- if we have written to preload register, load counter with preload value next time we count
+          elsif (preload_written = '1') then
+            count_load_n_d <= '0';
+          -- reach -1 and will load_counter with preload value
+          elsif ((count_wrap = '1') and (reload = '1') and (count_enabled = '1')) then
+            count_load_n_d <= '0';
+          else
+            count_load_n_d <= count_load_n;
+          end if;
+
+          preload_written_d <= PIT_Write_Preload;
+
+        end if;
+      end process Ctrl_Handler_Logic;
+
+      ToVote(PIT_RELOAD_Pos)          <= reload_d;
+      ToVote(PIT_COUNT_EN_Pos)        <= count_en_d;
+      ToVote(PIT_COUNT_LOAD_N_Pos)    <= count_load_n_d;
+      ToVote(PIT_PRELOAD_WRITTEN_Pos) <= preload_written_d;
+
+      Ctrl_Handler_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          reload          <= vote(reload_d,
+                                  FromAVote(PIT_RELOAD_Pos),
+                                  FromBVote(PIT_RELOAD_Pos), tmr_disable_b);
+          count_en        <= vote(count_en_d,
+                                  FromAVote(PIT_COUNT_EN_Pos),
+                                  FromBVote(PIT_COUNT_EN_Pos), tmr_disable_b);
+          count_load_n    <= vote(count_load_n_d,
+                                  FromAVote(PIT_COUNT_LOAD_N_Pos),
+                                  FromBVote(PIT_COUNT_LOAD_N_Pos), tmr_disable_b);
+          preload_written <= vote(preload_written_d,
+                                  FromAVote(PIT_PRELOAD_WRITTEN_Pos),
+                                  FromBVote(PIT_PRELOAD_WRITTEN_Pos), tmr_disable_b);
+        end if;
+      end process Ctrl_Handler_DFF;
+
+      count_enabled <= count_en and PIT_Count_En;
+
+      Counter_Logic : process (Reset, count_enabled, count, cnt) is
+      begin
+        if Reset then
+          count_d <= (others => '0');
+        elsif (count_enabled = '1') then
+          count_d <= cnt;
+        else
+          count_d <= count;
+        end if;
+      end process Counter_Logic;
+
+      ToVote(PIT_COUNT_Pos'low + C_PIT_SIZE - 1 downto PIT_COUNT_Pos'low) <= count_d;
+      -- Work around spyglass bug report on null range to the left but not to the right
+      spy2_g: if C_PIT_SIZE < 32 generate
+      begin
+        ToVote(PIT_COUNT_Pos'high downto PIT_COUNT_Pos'low + C_PIT_SIZE)    <= (others => '0');
+      end generate spy2_g;
+
+      Counter_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          count <= vote(count_d, FromAVote(PIT_COUNT_Pos), FromBVote(PIT_COUNT_Pos),tmr_disable_b);
+        end if;
+      end process Counter_DFF;
+
+      Interrupt_Handler_Logic : process (Reset, count_wrap, count_enabled, count_load_n) is
+      begin
+        if Reset then
+          pit_interrupt_i_d <= '0';
+        else
+          pit_interrupt_i_d <= count_wrap and count_enabled and count_load_n;
+        end if;
+      end process Interrupt_Handler_Logic;
+
+      ToVote(PIT_INTERRUPT_I_Pos) <= pit_interrupt_i_d;
+
+      Interrupt_Handler_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          pit_interrupt_i <= vote(pit_interrupt_i_d,
+                                  FromAVote(PIT_INTERRUPT_I_Pos),
+                                  FromBVote(PIT_INTERRUPT_I_Pos), tmr_disable_b);
+        end if;
+      end process Interrupt_Handler_DFF;
+
+      Toggle_Handler_Logic : process (Reset, pit_toggle_i, pit_interrupt_i) is
+      begin
+        if Reset then
+          pit_toggle_i_d <= '0';
+        elsif pit_interrupt_i = '1' then
+          pit_toggle_i_d <= not pit_toggle_i;
+        else
+          pit_toggle_i_d <= pit_toggle_i;
+        end if;
+      end process Toggle_Handler_Logic;
+
+      ToVote(PIT_TOGGLE_I_Pos) <= pit_toggle_i_d;
+
+      Toggle_Handler_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          pit_toggle_i <= vote(pit_toggle_i_d,
+                               FromAVote(PIT_TOGGLE_I_Pos),
+                               FromBVote(PIT_TOGGLE_I_Pos), tmr_disable_b);
+        end if;
+      end process Toggle_Handler_DFF;
+
+    end generate TMR_Yes;
+
+    PIT_Interrupt <= pit_interrupt_i;
+    PIT_Toggle <= pit_toggle_i;
+
+    --------------------------------------------------------------------------------------------------
+    -- Read register
+    --------------------------------------------------------------------------------------------------
+    Readable_Counter : if (C_PIT_READABLE /= 0) generate
+    begin
+
+      PIT_Read_Handler : process (Clk) is
+      begin  -- process PIT_Read_Handler
+        if Clk'event and Clk = '1' then  -- rising clock edge
+          if PIT_Read = '0' or Config_Reset = '1' then
+            PIT_Data <= (others => '0');
+          else
+            PIT_Data                        <= (others => '0');
+            PIT_Data(C_PIT_SIZE-1 downto 0) <= count;
+          end if;
+        end if;
+      end process PIT_Read_Handler;
+
+    end generate Readable_Counter;
+
+    Dont_Read_Counter: if (C_PIT_READABLE = 0) generate
+    begin
+      PIT_Data <= (others => '0');
+    end generate Dont_Read_Counter;
+
+  end generate Using_PIT;
+
+  Not_Using_Pit : if (C_USE_PIT = 0) generate
+  begin
+    PIT_Data      <= (others => '0');
+    PIT_Interrupt <= '0';
+    PIT_Toggle    <= '0';
+    ToVote        <= (others => '0');
+  end generate Not_Using_Pit;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- uart_control_status.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        uart_control_status.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              uart_control_status.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-18    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+entity Uart_Control_Status is
+  generic (
+    C_TMR             : integer              := 0;
+    C_USE_TMR_DISABLE : integer              := 0;
+    C_VOTE_SIZE       : integer              := 0;
+    C_USE_UART_RX     : integer              := 1;
+    C_USE_UART_TX     : integer              := 1;
+    C_UART_DATA_BITS  : integer range 5 to 8 := 8;
+    C_UART_USE_PARITY : integer              := 0;
+    C_UART_ODD_PARITY : integer              := 0
+    );
+  port (
+    CLK   : in std_logic;
+    Reset : in boolean;
+    Config_Reset        : in std_logic;
+
+    TMR_Disable         : in std_logic;
+    FromAVote           : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote           : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote              : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+    TX_Data_Transmitted : in std_logic;
+    TX_Buffer_Empty     : in std_logic;
+    RX_Data_Received    : in std_logic;
+    RX_Data_Exists      : in std_logic;
+    RX_Frame_Error      : in std_logic;
+    RX_Overrun_Error    : in std_logic;
+    RX_Parity_Error     : in std_logic;
+
+    UART_Status_Read     : in  std_logic;
+    UART_Status          : out std_logic_vector(7 downto 0);
+    UART_Interrupt       : out std_logic;
+    UART_Rx_Interrupt    : out std_logic;
+    UART_Tx_Interrupt    : out std_logic;
+    UART_Error_Interrupt : out std_logic
+    );
+
+end entity Uart_Control_Status;
+
+architecture IMP of Uart_Control_Status is
+
+  signal parity_error  : std_logic;
+  signal frame_error   : std_logic;
+  signal overrun_error : std_logic;
+
+  signal error_interrupt : std_logic;
+
+begin  -- architecture IMP
+
+  --------------------------------------------------------------------------------------------------
+  -- Status register
+  --------------------------------------------------------------------------------------------------
+  UART_Status_DFF: process (Clk) is
+  begin  -- process UART_Status_DFF
+    if Clk'event and Clk = '1' then     -- rising clock edge
+      if (UART_Status_Read = '0' or Config_Reset = '1') then  -- synchronous reset (active high)
+        UART_Status <= (others => '0');
+      else
+        if ((C_USE_UART_RX = 0) or (C_UART_USE_PARITY = 0)) then
+          UART_Status(7) <= '0';
+        else
+          UART_Status(7) <= parity_error;
+        end if;
+        if (C_USE_UART_RX = 0) then
+          UART_Status(6) <= '0';
+          UART_Status(5) <= '0';
+        else
+          UART_Status(6) <= frame_error;
+          UART_Status(5) <= overrun_error;
+        end if;
+        UART_Status(4) <= '0';
+        if (C_USE_UART_TX = 0) then
+          UART_Status(3) <= '0';
+        else
+          UART_Status(3) <= not TX_Buffer_Empty;
+        end if;
+        UART_Status(2) <= '0';
+        UART_Status(1) <= '0';
+        if (C_USE_UART_RX = 0) then
+          UART_Status(0) <= '0';
+        else
+          UART_Status(0) <= RX_Data_Exists;
+        end if;
+      end if;
+    end if;
+  end process UART_Status_DFF;
+
+  --------------------------------------------------------------------------------------------------
+  -- Keep track of errors
+  --------------------------------------------------------------------------------------------------
+
+  TMR_No : if (C_TMR = 0) generate
+  begin
+
+    Error_Flags : process (Clk) is
+    begin  -- process Error_Flags
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then                     -- synchronous reset (active high)
+          parity_error    <= '0';
+          frame_error     <= '0';
+          overrun_error   <= '0';
+          error_interrupt <= '0';
+        else
+          error_interrupt <= '0';
+          if ((C_USE_UART_RX = 0) or (UART_Status_Read = '1')) then
+            parity_error  <= '0';
+            frame_error   <= '0';
+            overrun_error <= '0';
+          end if;
+          if ((C_USE_UART_RX /= 0) and (RX_Frame_Error = '1')) then
+            frame_error     <= '1';
+            error_interrupt <= '1';
+          end if;
+          if ((C_USE_UART_RX /= 0) and (RX_Overrun_Error = '1')) then
+            overrun_error   <= '1';
+            error_interrupt <= '1';
+          end if;
+          if ((C_USE_UART_RX /= 0) and (C_UART_USE_PARITY /= 0) and (RX_Parity_Error = '1')) then
+            parity_error    <= '1';
+            error_interrupt <= '1';
+          end if;
+        end if;
+      end if;
+    end process Error_Flags;
+
+    ToVote <= (others => '0');
+
+  end generate TMR_No;
+
+  TMR_Yes : if (C_TMR /= 0) generate
+    signal tmr_disable_b     : boolean;
+    signal parity_error_d    : std_logic;
+    signal frame_error_d     : std_logic;
+    signal overrun_error_d   : std_logic;
+    signal error_interrupt_d : std_logic;
+  begin
+
+    tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+    Error_Flags_Logic : process (Reset, parity_error, UART_Status_Read, RX_Frame_Error, RX_Overrun_Error,
+                                 RX_Parity_Error, frame_error, overrun_error) is
+    begin
+      if Reset then
+        parity_error_d    <= '0';
+        frame_error_d     <= '0';
+        overrun_error_d   <= '0';
+        error_interrupt_d <= '0';
+      else
+        if ((C_USE_UART_RX /= 0) and (RX_Frame_Error = '1')) or
+           ((C_USE_UART_RX /= 0) and (RX_Overrun_Error = '1')) or
+           ((C_USE_UART_RX /= 0) and (C_UART_USE_PARITY /= 0) and (RX_Parity_Error = '1')) then
+          error_interrupt_d <= '1';
+        else
+          error_interrupt_d <= '0';
+        end if;
+
+        if ((C_USE_UART_RX /= 0) and (C_UART_USE_PARITY /= 0) and (RX_Parity_Error = '1')) then
+          parity_error_d <= '1';
+        elsif ((C_USE_UART_RX = 0) or (UART_Status_Read = '1')) then
+          parity_error_d <= '0';
+        else
+          parity_error_d <= parity_error;
+        end if;
+
+        if ((C_USE_UART_RX /= 0) and (RX_Frame_Error = '1')) then
+          frame_error_d <= '1';
+        elsif ((C_USE_UART_RX = 0) or (UART_Status_Read = '1')) then
+          frame_error_d <= '0';
+        else
+          frame_error_d <= frame_error;
+        end if;
+
+        if ((C_USE_UART_RX /= 0) and (RX_Overrun_Error = '1')) then
+          overrun_error_d <= '1';
+        elsif ((C_USE_UART_RX = 0) or (UART_Status_Read = '1')) then
+          overrun_error_d <= '0';
+        else
+          overrun_error_d <= overrun_error;
+        end if;
+
+      end if;
+    end process Error_Flags_Logic;
+
+    ToVote(PARITY_ERROR_Pos)    <= parity_error_d;
+    ToVote(FRAME_ERROR_Pos)     <= frame_error_d;
+    ToVote(OVERRUN_ERROR_Pos)   <= overrun_error_d;
+    ToVote(ERROR_INTERRUPT_Pos) <= error_interrupt_d;
+
+    Error_Flags_DFF : process (Clk) is
+    begin  -- process Error_Flags
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        parity_error    <= vote(parity_error_d,
+                                FromAVote(PARITY_ERROR_Pos),
+                                FromBVote(PARITY_ERROR_Pos), tmr_disable_b);
+        frame_error     <= vote(frame_error_d,
+                                FromAVote(FRAME_ERROR_Pos),
+                                FromBVote(FRAME_ERROR_Pos), tmr_disable_b);
+        overrun_error   <= vote(overrun_error_d,
+                                FromAVote(OVERRUN_ERROR_Pos),
+                                FromBVote(OVERRUN_ERROR_Pos), tmr_disable_b);
+        error_interrupt <= vote(error_interrupt_d,
+                                FromAVote(ERROR_INTERRUPT_Pos),
+                                FromBVote(ERROR_INTERRUPT_Pos), tmr_disable_b);
+      end if;
+    end process Error_Flags_DFF;
+
+  end generate TMR_Yes;
+
+  --------------------------------------------------------------------------------------------------
+  -- Interrupt generation
+  --------------------------------------------------------------------------------------------------
+  UART_Error_Interrupt <= error_interrupt;
+  UART_Rx_Interrupt    <= RX_Data_Received;
+  UART_Tx_Interrupt    <= TX_Data_Transmitted;
+  UART_Interrupt       <= error_interrupt or RX_Data_Received or TX_Data_Transmitted;
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- uart_receive.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        uart_receive.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              uart_receive.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-18    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity UART_Receive is
+  generic (
+    C_TARGET          : TARGET_FAMILY_TYPE;
+    C_TMR             : integer := 0;
+    C_USE_TMR_DISABLE : integer := 0;
+    C_VOTE_SIZE       : integer := 0;
+    C_USE_SRL16       : string;
+    C_DATA_BITS       : integer range 5 to 8 := 8;
+    C_USE_PARITY      : integer              := 0;
+    C_ODD_PARITY      : integer              := 1
+    );
+  port (
+    Config_Reset : in std_logic;
+    Clk          : in std_logic;
+    Reset        : in boolean;
+    EN_16x_Baud  : in std_logic;
+
+    RX               : in  std_logic;
+    Read_RX_Data     : in  std_logic;
+    TMR_Disable      : in  std_logic;
+    FromAVote        : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote        : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote           : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    RX_Data          : out std_logic_vector(C_DATA_BITS-1 downto 0);
+    RX_Data_Received : out std_logic;
+    RX_Data_Exists   : out std_logic;
+    RX_Frame_Error   : out std_logic;
+    RX_Overrun_Error : out std_logic;
+    RX_Parity_Error  : out std_logic
+    );
+
+end entity UART_Receive;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+architecture IMP of UART_Receive is
+
+  component XIL_SRL16E is
+    generic (
+      C_TARGET    : TARGET_FAMILY_TYPE;
+      C_USE_SRL16 : string;
+      C_STATIC    : boolean := false;
+      INIT        : bit_vector);
+    port (
+      Config_Reset : in  std_logic;
+      Q            : out std_logic;
+      A0           : in  std_logic;
+      A1           : in  std_logic;
+      A2           : in  std_logic;
+      A3           : in  std_logic;
+      CE           : in  std_logic;
+      CLK          : in  std_logic;
+      D            : in  std_logic);
+  end component XIL_SRL16E;
+
+  component MB_FDSE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '1');
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    S  : in  std_logic);
+  end component MB_FDSE;
+
+  component MB_FDRE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0');
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    R  : in  std_logic);
+  end component MB_FDRE;
+
+  signal previous_RX             : std_logic;
+  signal start_Edge_Detected_Bit : std_logic;
+  signal mid_Start_Bit           : std_logic;
+  signal recycle                 : std_logic;
+  signal sample_Point            : std_logic;
+  signal stop_Bit_Position       : std_logic;
+
+  function Calc_Length return integer is
+  begin  -- function Calc_Length
+    if (C_USE_PARITY = 1) then
+      return 1 + C_DATA_BITS;
+    else
+      return C_DATA_BITS;
+    end if;
+  end function Calc_Length;
+
+  constant SERIAL_TO_PAR_LENGTH : integer := Calc_Length;
+  constant STOP_BIT_POS         : integer := SERIAL_TO_PAR_LENGTH;
+  constant DATA_LSB_POS         : integer := SERIAL_TO_PAR_LENGTH;
+  constant CALC_PAR_POS         : integer := SERIAL_TO_PAR_LENGTH;
+
+  signal new_rx_data_write  : std_logic;
+  signal new_rx_data        : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
+  signal serial_to_parallel : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
+  signal rx_data_exists_i   : std_logic;
+  signal rx_frame_error_i   : std_logic;
+  signal rx_parity_error_i  : std_logic;
+
+  signal rx_1 : std_logic;
+  signal rx_2 : std_logic;
+
+  signal rx_data_i : std_logic_vector(C_DATA_BITS-1 downto 0);
+
+  -- Preserve signals after synthesis for simulation UART support
+  attribute KEEP : string;
+  attribute KEEP of rx_frame_error_i  : signal is "TRUE";
+  attribute KEEP of rx_parity_error_i : signal is "TRUE";
+  attribute KEEP of new_rx_data_write : signal is "TRUE";
+  attribute KEEP of new_rx_data       : signal is "TRUE";
+
+begin  -- architecture IMP
+
+  TMR_No : if (C_TMR = 0) generate
+    signal start_Edge_Detected : boolean;
+    signal running             : boolean;
+    signal mid_Start_Bit_or_Config_Reset : std_logic;
+  begin
+
+    ToVote <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Double sample to avoid meta-stability
+    -----------------------------------------------------------------------------
+    RX_Sampling : process (Clk)
+    begin  -- process RX_Sampling
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then                     -- asynchronous reset (active high)
+          rx_1 <= '1';
+          rx_2 <= '1';
+        else
+          rx_1 <= RX;
+          rx_2 <= rx_1;
+        end if;
+      end if;
+    end process RX_Sampling;
+
+    -----------------------------------------------------------------------------
+    -- Detect a falling edge on RX and start a new receiption if idle
+    -----------------------------------------------------------------------------
+    Prev_RX_DFF : process (Clk) is
+    begin  -- process Prev_RX_DFF
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then
+          previous_RX <= '0';
+        else
+          if (EN_16x_Baud = '1') then
+            previous_RX <= rx_2;
+          end if;
+        end if;
+      end if;
+    end process Prev_RX_DFF;
+
+    Start_Edge_DFF : process (Clk) is
+    begin  -- process Start_Edge_DFF
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then
+          start_Edge_Detected <= false;
+        else
+          if (EN_16x_Baud = '1') then
+            start_Edge_Detected <= not running and (previous_RX = '1') and (rx_2 = '0');
+          end if;
+        end if;
+      end if;
+    end process Start_Edge_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Running is '1' during a receiption
+    -----------------------------------------------------------------------------
+    Running_DFF : process (Clk) is
+    begin  -- process Running_DFF
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then                     -- asynchronous reset (active high)
+          running <= false;
+        else
+          if (EN_16x_Baud = '1') then
+            if (start_Edge_Detected) then
+              running <= true;
+            elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
+              running <= false;
+            end if;
+          end if;
+        end if;
+      end if;
+    end process Running_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Delay start_Edge_Detected 7 clocks to get the mid-point in a bit
+    -- The address needs to be 6 "0110" to get a delay of 7.
+    -----------------------------------------------------------------------------
+
+    start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
+
+    Mid_Start_Bit_SRL16 : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,               -- [string]
+        INIT        => X"0000")
+      port map (
+        Config_Reset => Config_Reset,             -- [in  std_logic]
+        CE           => EN_16x_Baud,              -- [in  std_logic]
+        D            => start_Edge_Detected_Bit,  -- [in  std_logic]
+        Clk          => Clk,                      -- [in  std_logic]
+        A0           => '0',                      -- [in  std_logic]
+        A1           => '1',                      -- [in  std_logic]
+        A2           => '1',                      -- [in  std_logic]
+        A3           => '0',                      -- [in  std_logic]
+        Q            => mid_Start_Bit);           -- [out std_logic]
+
+    mid_Start_Bit_or_Config_Reset <= mid_Start_Bit or Config_Reset;
+
+    -- Keep regenerating new values into the 16 clock delay
+    -- Starting with the first mid_Start_Bit and for every new sample_points
+    -- until stop_Bit_Position is reached
+    recycle <= not (stop_Bit_Position) and (mid_Start_Bit or sample_Point);
+
+    Delay_16 : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,       -- [string]
+        INIT        => X"0000")
+      port map (
+        Config_Reset => Config_Reset,     -- [in  std_logic]
+        CE           => EN_16x_Baud,      -- [in  std_logic]
+        D            => recycle,          -- [in  std_logic]
+        Clk          => Clk,              -- [in  std_logic]
+        A0           => '1',              -- [in  std_logic]
+        A1           => '1',              -- [in  std_logic]
+        A2           => '1',              -- [in  std_logic]
+        A3           => '1',              -- [in  std_logic]
+        Q            => sample_Point);    -- [out std_logic]
+
+    -----------------------------------------------------------------------------
+    -- Detect when the stop bit is received
+    -----------------------------------------------------------------------------
+    Stop_Bit_Handler : process (Clk) is
+    begin  -- process Stop_Bit_Handler
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then                     -- asynchronous reset (active high)
+          stop_Bit_Position <= '0';
+        else
+          if (EN_16x_Baud = '1') then
+            if (stop_Bit_Position = '0') then
+              -- Start bit has reached the end of the shift register (Stop bit position)
+              stop_Bit_Position <= sample_Point and new_rx_data(STOP_BIT_POS);
+            elsif (sample_Point = '1') then
+              -- if stop_Bit_Position = '1', then clear it at the next sample_Point
+              stop_Bit_Position <= '0';
+            end if;
+          end if;
+        end if;
+      end if;
+    end process Stop_Bit_Handler;
+
+    -----------------------------------------------------------------------------
+    -- Parity handling
+    -----------------------------------------------------------------------------
+    Using_Parity : if (C_USE_PARITY = 1) generate
+      signal calc_Parity : std_logic;
+      signal parity      : std_logic;
+    begin
+
+      Using_Odd_Parity : if (C_ODD_PARITY = 1) generate
+      begin
+        Parity_Bit : MB_FDSE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT     => '1')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => EN_16x_Baud,            -- [in  std_logic]
+            D  => calc_Parity,            -- [in  std_logic]
+            S  => mid_Start_Bit_or_Config_Reset); -- [in std_logic]
+      end generate Using_Odd_Parity;
+
+      Using_Even_Parity : if (C_ODD_PARITY = 0) generate
+      begin
+        Parity_Bit : MB_FDRE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT     => '0')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => EN_16x_Baud,            -- [in  std_logic]
+            D  => calc_Parity,            -- [in  std_logic]
+            R  => mid_Start_Bit_or_Config_Reset);  -- [in std_logic]
+      end generate Using_Even_Parity;
+
+      calc_Parity <= parity when (stop_Bit_Position or not sample_Point) = '1'
+                     else parity xor rx_2;
+
+      rx_parity_error_i <= (EN_16x_Baud and sample_Point) and (new_rx_data(CALC_PAR_POS)) and
+                           not stop_Bit_Position
+                           when running and (rx_2 /= Parity) else '0';
+    end generate Using_Parity;
+
+    Not_Using_Parity : if (C_USE_PARITY = 0) generate
+    begin
+      rx_parity_error_i <= '0';
+    end generate Not_Using_Parity;
+
+
+    -----------------------------------------------------------------------------
+    -- Data part
+    -----------------------------------------------------------------------------
+
+    new_rx_data(0) <= rx_2;
+
+    Convert_Serial_To_Parallel : for I in 1 to serial_to_parallel'length generate
+    begin
+
+      serial_to_parallel(I) <= new_rx_data(I) when (stop_Bit_Position or not sample_Point) = '1'
+                               else new_rx_data(I-1);
+
+      First_Bit : if (I = 1) generate
+      begin
+        First_Bit_I : MB_FDSE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT     => '0')                  -- [bit]
+          port map (
+            Q  => new_rx_data(I),         -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => EN_16x_Baud,            -- [in  std_logic]
+            D  => serial_to_parallel(I),  -- [in  std_logic]
+            S  => mid_Start_Bit_or_Config_Reset); -- [in std_logic]
+      end generate First_Bit;
+
+      Rest_Bits : if (I /= 1) generate
+      begin
+        Others_I : MB_FDRE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT     => '0')                  -- [bit]
+          port map (
+            Q  => new_rx_data(I),         -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => EN_16x_Baud,            -- [in  std_logic]
+            D  => serial_to_parallel(I),  -- [in  std_logic]
+            R  => mid_Start_Bit_or_Config_Reset); -- [in std_logic]
+      end generate Rest_Bits;
+
+    end generate Convert_Serial_To_Parallel;
+
+    -----------------------------------------------------------------------------
+    -- Write in the received word when the stop_bit has been received and it is a
+    -- '1'
+    -----------------------------------------------------------------------------
+    NEW_RX_DATA_Write_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset then
+          new_rx_data_write <= '0';
+        else
+          new_rx_data_Write <= stop_Bit_Position and rx_2 and sample_Point and EN_16x_Baud;
+        end if;
+      end if;
+    end process NEW_RX_DATA_Write_DFF;
+
+    Rx_Data_Exist_Handler : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset then
+          rx_data_exists_i <= '0';
+        else
+          if (new_rx_data_write = '1') then
+            rx_data_exists_i <= '1';
+          end if;
+          if (Read_RX_Data = '1') then
+            rx_data_exists_i <= '0';
+          end if;
+        end if;
+      end if;
+    end process Rx_Data_Exist_Handler;
+
+    Receive_Register : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset then
+          rx_data_i <= (others => '0');
+        elsif (NEW_RX_DATA_Write = '1') then
+          rx_data_i <= new_rx_data(DATA_LSB_POS - C_DATA_BITS + 1 to DATA_LSB_POS);
+        end if;
+      end if;
+    end process Receive_Register;
+
+    UART_Read: process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        if Read_RX_Data = '0' or Config_Reset = '1' then
+          RX_Data <= (others => '0');
+        else
+          RX_Data <= rx_data_i;
+        end if;
+      end if;
+    end process UART_Read;
+
+  end generate TMR_No;
+
+  RX_Data_Received <= new_rx_data_write;
+  rx_frame_error_i <= stop_Bit_Position and sample_Point and EN_16x_Baud and not rx_2;
+  RX_Overrun_Error <= rx_data_exists_i and new_rx_data_write;
+  RX_Data_Exists   <= rx_data_exists_i;
+
+
+  TMR_Yes : if (C_TMR /= 0) generate
+    signal start_Edge_Detected       : boolean;
+    signal running                   : boolean;
+
+    signal tmr_disable_b             : boolean;
+    -- Voted signals before DFF
+    signal previous_RX_d             : std_logic;
+    signal start_Edge_Detected_d     : boolean;
+    signal running_d                 : boolean;
+    signal recycle_voted             : std_logic;
+    signal stop_Bit_Position_d       : std_logic;
+    signal mid_Start_Bit_voted       : std_logic;
+    signal mid_Start_Bit_voted_or_Config_Reset : std_logic;
+    signal serial_to_parallel_voted  : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
+    signal new_rx_data_write_d       : std_logic;
+    signal rx_data_exists_i_d        : std_logic;
+    signal rx_data_i_d               : std_logic_vector(C_DATA_BITS-1 downto 0);
+    signal RX_Data_d                 : std_logic_vector(C_DATA_BITS-1 downto 0);
+  begin
+
+    tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+    -----------------------------------------------------------------------------
+    -- Double sample to avoid meta-stability
+    -----------------------------------------------------------------------------
+    RX_Sampling : process (Clk)
+    begin  -- process RX_Sampling
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        if Reset then                     -- asynchronous reset (active high)
+          rx_1 <= '1';
+          rx_2 <= '1';
+        else
+          rx_1 <= RX;
+          rx_2 <= rx_1;
+        end if;
+      end if;
+    end process RX_Sampling;
+
+    -----------------------------------------------------------------------------
+    -- Detect a falling edge on RX and start a new receiption if idle
+    -----------------------------------------------------------------------------
+    Prev_RX_Logic : process (Reset, EN_16x_Baud, rx_2, previous_RX) is
+    begin
+      if Reset then
+        previous_RX_d <= '0';
+      else
+        if (EN_16x_Baud = '1') then
+          previous_RX_d <= rx_2;
+        else
+          previous_RX_d <= previous_RX;
+        end if;
+       end if;
+    end process Prev_RX_Logic;
+
+    ToVote(UART_RX_PREVIOUS_RX_Pos) <= previous_RX_d;
+
+    Prev_RX_DFF : process (Clk) is
+    begin  -- process Prev_RX_DFF
+      if Clk'event and Clk = '1' then     -- rising clock edge
+         previous_RX <= vote(previous_RX_d,
+                             FromAVote(UART_RX_PREVIOUS_RX_Pos),
+                             FromBVote(UART_RX_PREVIOUS_RX_Pos), tmr_disable_b);
+      end if;
+    end process Prev_RX_DFF;
+
+    Start_Edge_Logic : process (Reset, EN_16x_Baud, running, previous_RX, rx_2, start_Edge_Detected) is
+    begin
+      if Reset then
+        start_Edge_Detected_d <= false;
+      else
+        if (EN_16x_Baud = '1') then
+          start_Edge_Detected_d <= not running and (previous_RX = '1') and (rx_2 = '0');
+        else
+          start_Edge_Detected_d <= start_Edge_Detected;
+        end if;
+      end if;
+    end process Start_Edge_Logic;
+
+    ToVote(UART_RX_START_EDGE_DETECTED_Pos) <= '1' when start_Edge_Detected_d else
+                                               '0';
+
+    Start_Edge_DFF : process (Clk) is
+    begin  -- process Start_Edge_DFF
+      if Clk'event and Clk = '1' then     -- rising clock edge
+        start_Edge_Detected <= vote(start_Edge_Detected_d,
+                                    FromAVote(UART_RX_START_EDGE_DETECTED_Pos),
+                                    FromBVote(UART_RX_START_EDGE_DETECTED_Pos), tmr_disable_b);
+      end if;
+    end process Start_Edge_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Running is '1' during a receiption
+    -----------------------------------------------------------------------------
+    Running_Logic : process (Reset, EN_16x_Baud, start_Edge_Detected, sample_Point, stop_Bit_Position, running) is
+    begin
+      if Reset then
+        running_d <= false;
+      else
+        if (EN_16x_Baud = '1') then
+          if (start_Edge_Detected) then
+            running_d <= true;
+          elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
+            running_d <= false;
+          else
+            running_d <= running;
+          end if;
+        else
+          running_d <= running;
+        end if;
+      end if;
+    end process Running_Logic;
+
+    ToVote(UART_RX_RUNNING_Pos) <= '1' when running_d else
+                                   '0';
+
+    Running_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        running <= vote(running_d, FromAVote(UART_RX_RUNNING_Pos), FromBVote(UART_RX_RUNNING_Pos),tmr_disable_b);
+      end if;
+    end process Running_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Delay start_Edge_Detected 7 clocks to get the mid-point in a bit
+    -- The address needs to be 6 "0110" to get a delay of 7.
+    -----------------------------------------------------------------------------
+
+    start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
+
+    Mid_Start_Bit_SRL16 : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,               -- [string]
+        INIT        => X"0000")
+      port map (
+        Config_Reset => Config_Reset,             -- [in  std_logic]
+        CE           => EN_16x_Baud,              -- [in  std_logic]
+        D            => start_Edge_Detected_Bit,  -- [in  std_logic]
+        Clk          => Clk,                      -- [in  std_logic]
+        A0           => '0',                      -- [in  std_logic]
+        A1           => '1',                      -- [in  std_logic]
+        A2           => '1',                      -- [in  std_logic]
+        A3           => '0',                      -- [in  std_logic]
+        Q            => mid_Start_Bit);           -- [out std_logic]
+
+    ToVote(UART_RX_MID_START_BIT_Pos) <= mid_Start_Bit;
+
+    mid_Start_Bit_voted <= vote(mid_Start_Bit,
+                                FromAVote(UART_RX_MID_START_BIT_Pos),
+                                FromBVote(UART_RX_MID_START_BIT_Pos), tmr_disable_b);
+
+    mid_Start_Bit_voted_or_Config_Reset <= mid_Start_Bit_voted or Config_Reset;
+
+    -- Keep regenerating new values into the 16 clock delay
+    -- Starting with the first mid_Start_Bit and for every new sample_points
+    -- until stop_Bit_Position is reached
+    recycle  <= not (stop_Bit_Position) and (mid_Start_Bit or sample_Point);
+
+    ToVote(UART_RX_RECYCLE_Pos) <= recycle;
+
+    recycle_voted <= vote(recycle, FromAVote(UART_RX_RECYCLE_Pos), FromBVote(UART_RX_RECYCLE_Pos), tmr_disable_b);
+
+    Delay_16 : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,       -- [string]
+        INIT        => X"0000")
+      port map (
+        Config_Reset => Config_Reset,     -- [in  std_logic]
+        CE           => EN_16x_Baud,      -- [in  std_logic]
+        D            => recycle_voted,    -- [in  std_logic]
+        Clk          => Clk,              -- [in  std_logic]
+        A0           => '1',              -- [in  std_logic]
+        A1           => '1',              -- [in  std_logic]
+        A2           => '1',              -- [in  std_logic]
+        A3           => '1',              -- [in  std_logic]
+        Q            => sample_Point);    -- [out std_logic]
+
+    -----------------------------------------------------------------------------
+    -- Detect when the stop bit is received
+    -----------------------------------------------------------------------------
+    Stop_Bit_Handler_Logic : process (Reset, EN_16x_Baud, stop_Bit_Position, sample_Point, new_rx_data) is
+    begin
+      if Reset then
+        stop_Bit_Position_d <= '0';
+      else
+        if (EN_16x_Baud = '1') then
+          if (stop_Bit_Position = '0') then
+            -- Start bit has reached the end of the shift register (Stop bit position)
+            stop_Bit_Position_d <= sample_Point and new_rx_data(STOP_BIT_POS);
+          elsif (sample_Point = '1') then
+            -- if stop_Bit_Position = '1', then clear it at the next sample_Point
+            stop_Bit_Position_d <= '0';
+          else
+            stop_Bit_Position_d <= stop_Bit_Position;
+          end if;
+        else
+          stop_Bit_Position_d <= stop_Bit_Position;
+        end if;
+      end if;
+    end process Stop_Bit_Handler_Logic;
+
+    ToVote(UART_RX_STOP_BIT_POSITION_Pos) <= stop_Bit_Position_d;
+
+    Stop_Bit_Handler_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        stop_Bit_Position <= vote(stop_Bit_Position_d,
+                                  FromAVote(UART_RX_STOP_BIT_POSITION_Pos),
+                                  FromBVote(UART_RX_STOP_BIT_POSITION_Pos), tmr_disable_b);
+      end if;
+    end process Stop_Bit_Handler_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Parity handling
+    -----------------------------------------------------------------------------
+    Using_Parity : if (C_USE_PARITY = 1) generate
+      signal calc_Parity       : std_logic;
+      signal parity            : std_logic;
+      signal calc_Parity_voted : std_logic;
+    begin
+
+      Using_Odd_Parity : if (C_ODD_PARITY = 1) generate
+      begin
+        Parity_Bit : MB_FDSE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT => '1')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => EN_16x_Baud,            -- [in  std_logic]
+            D  => calc_Parity_Voted,      -- [in  std_logic]
+            S  => mid_Start_Bit_Voted_or_Config_Reset);   -- [in std_logic]
+      end generate Using_Odd_Parity;
+
+      Using_Even_Parity : if (C_ODD_PARITY = 0) generate
+      begin
+        Parity_Bit : MB_FDRE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT => '0')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => EN_16x_Baud,            -- [in  std_logic]
+            D  => calc_Parity_Voted,      -- [in  std_logic]
+            R  => mid_Start_Bit_Voted_or_Config_Reset);   -- [in std_logic]
+      end generate Using_Even_Parity;
+
+      calc_Parity <= parity when (stop_Bit_Position or not sample_Point) = '1'
+                     else parity xor rx_2;
+
+      ToVote(UART_RX_CALC_PARITY_Pos) <= calc_Parity;
+
+      calc_Parity_Voted <= vote(calc_Parity,
+                                FromAVote(UART_RX_CALC_PARITY_Pos),
+                                FromBVote(UART_RX_CALC_PARITY_Pos), tmr_disable_b);
+
+      rx_parity_error_i <= (EN_16x_Baud and sample_Point) and (new_rx_data(CALC_PAR_POS)) and
+                           not stop_Bit_Position
+                           when running and (rx_2 /= Parity) else '0';
+
+
+    end generate Using_Parity;
+
+    Not_Using_Parity : if (C_USE_PARITY = 0) generate
+    begin
+      rx_parity_error_i <= '0';
+      ToVote(UART_RX_CALC_PARITY_Pos) <= '0';
+    end generate Not_Using_Parity;
+
+
+    -----------------------------------------------------------------------------
+    -- Data part
+    -----------------------------------------------------------------------------
+
+    new_rx_data(0) <= rx_2;
+
+    ToVote(UART_RX_SERIAL_TO_PARALLEL_Pos'low + serial_to_parallel'length -1 downto
+           UART_RX_SERIAL_TO_PARALLEL_Pos'low) <= serial_to_parallel;
+    ToVote(UART_RX_SERIAL_TO_PARALLEL_Pos'high downto
+           UART_RX_SERIAL_TO_PARALLEL_Pos'low + serial_to_parallel'length) <= (others => '0');
+
+    serial_to_parallel_voted <=
+      vote(serial_to_parallel,
+           FromAVote(UART_RX_SERIAL_TO_PARALLEL_Pos'low + serial_to_parallel'length - 1 downto
+                     UART_RX_SERIAL_TO_PARALLEL_Pos'low),
+           FromBVote(UART_RX_SERIAL_TO_PARALLEL_Pos'low + serial_to_parallel'length - 1 downto
+                     UART_RX_SERIAL_TO_PARALLEL_Pos'low), tmr_disable_b);
+
+    Convert_Serial_To_Parallel : for I in 1 to serial_to_parallel'length generate
+    begin
+
+      serial_to_parallel(I) <= new_rx_data(I) when (stop_Bit_Position or not sample_Point) = '1'
+                               else new_rx_data(I-1);
+
+      First_Bit : if (I = 1) generate
+      begin
+        First_Bit_I : MB_FDSE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT => '0')                        -- [bit]
+          port map (
+            Q  => new_rx_data(I),               -- [out std_logic]
+            C  => Clk,                          -- [in  std_logic]
+            CE => EN_16x_Baud,                  -- [in  std_logic]
+            D  => serial_to_parallel_voted(I),  -- [in  std_logic]
+            S  => mid_Start_Bit_Voted_or_Config_Reset);  -- [in std_logic]
+      end generate First_Bit;
+
+      Rest_Bits : if (I /= 1) generate
+      begin
+        Others_I : MB_FDRE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT => '0')                        -- [bit]
+          port map (
+            Q  => new_rx_data(I),               -- [out std_logic]
+            C  => Clk,                          -- [in  std_logic]
+            CE => EN_16x_Baud,                  -- [in  std_logic]
+            D  => serial_to_parallel_voted(I),  -- [in  std_logic]
+            R  => mid_Start_Bit_Voted_or_Config_Reset);  -- [in std_logic]
+      end generate Rest_Bits;
+
+    end generate Convert_Serial_To_Parallel;
+
+    -----------------------------------------------------------------------------
+    -- Write in the received word when the stop_bit has been received and it is a
+    -- '1'
+    -----------------------------------------------------------------------------
+    NEW_RX_DATA_Write_Logic : process (Reset, stop_Bit_Position, rx_2, sample_Point, EN_16x_Baud) is
+    begin
+      if Reset then
+        new_rx_data_write_d <= '0';
+      else
+        new_rx_data_Write_d <= stop_Bit_Position and rx_2 and sample_Point and EN_16x_Baud;
+      end if;
+    end process NEW_RX_DATA_Write_Logic;
+
+    ToVote(UART_RX_NEW_RX_DATA_WRITE_Pos) <= new_rx_data_write_d;
+
+    NEW_RX_DATA_Write_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        new_rx_data_write <= vote(new_rx_data_write_d,
+                                  FromAVote(UART_RX_NEW_RX_DATA_WRITE_Pos),
+                                  FromBVote(UART_RX_NEW_RX_DATA_WRITE_Pos), tmr_disable_b);
+      end if;
+    end process NEW_RX_DATA_Write_DFF;
+
+    Rx_Data_Exist_Handler_Logic : process (Reset, Read_RX_Data, new_rx_data_write, rx_data_exists_i) is
+    begin
+      if Reset then
+        rx_data_exists_i_d <= '0';
+      else
+        if (Read_RX_Data = '1') then
+          rx_data_exists_i_d <= '0';
+        elsif (new_rx_data_write = '1') then
+          rx_data_exists_i_d <= '1';
+        else
+          rx_data_exists_i_d <= rx_data_exists_i;
+        end if;
+      end if;
+    end process Rx_Data_Exist_Handler_Logic;
+
+    ToVote(UART_RX_DATA_EXISTS_Pos) <= rx_data_exists_i_d;
+
+    Rx_Data_Exist_Handler_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        rx_data_exists_i <= vote(rx_data_exists_i_d,
+                                 FromAVote(UART_RX_DATA_EXISTS_Pos),
+                                 FromBVote(UART_RX_DATA_EXISTS_Pos), tmr_disable_b);
+      end if;
+    end process Rx_Data_Exist_Handler_DFF;
+
+    Receive_Register_Logic : process (Reset, new_rx_data_write, new_rx_data, rx_data_i) is
+    begin
+      if Reset then
+        rx_data_i_d <= (others => '0');
+      elsif (new_rx_data_write = '1') then
+        rx_data_i_d <= new_rx_data(DATA_LSB_POS - C_DATA_BITS + 1 to DATA_LSB_POS);
+      else
+        rx_data_i_d <= rx_data_i;
+      end if;
+    end process Receive_Register_Logic;
+
+    ToVote(UART_RX_DATA_I_Pos'low+rx_data_i_d'length-1 downto UART_RX_DATA_I_Pos'low) <= rx_data_i_d;
+
+    -- Work around spyglass bug report on null range to the left but not to the right
+    spy1_g: if C_DATA_BITS < 8 generate
+    begin
+      ToVote(UART_RX_DATA_I_Pos'high downto UART_RX_DATA_I_Pos'low+rx_data_i_d'length)  <= (others => '0');
+    end generate spy1_g;
+
+    Receive_Register_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        rx_data_i <= vote(rx_data_i_d,
+                          FromAVote(UART_RX_DATA_I_Pos'low+rx_data_i_d'length-1 downto UART_RX_DATA_I_Pos'low),
+                          FromBVote(UART_RX_DATA_I_Pos'low+rx_data_i_d'length-1 downto UART_RX_DATA_I_Pos'low),
+                          tmr_disable_b);
+      end if;
+    end process Receive_Register_DFF;
+
+    UART_Read_Logic: process (Read_RX_Data, rx_data_i, Config_Reset) is
+    begin
+      if Read_RX_Data = '0' or Config_Reset = '1' then
+        RX_Data_d <= (others => '0');
+      else
+        RX_Data_d <= rx_data_i;
+      end if;
+    end process UART_Read_Logic;
+
+    ToVote(UART_RX_DATA_Pos'low+RX_Data_d'length-1 downto UART_RX_DATA_Pos'low)  <= RX_Data_d;
+
+    -- Work around spyglass bug report on null range to the left but not to the right
+    spy2_g: if C_DATA_BITS < 8 generate
+    begin
+      ToVote(UART_RX_DATA_Pos'high downto UART_RX_DATA_Pos'low+RX_Data_d'length) <= (others => '0');
+    end generate spy2_g;
+
+    UART_Read: process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        RX_Data <= vote(RX_Data_d,
+                        FromAVote(UART_RX_DATA_Pos'low+RX_Data_d'length-1 downto UART_RX_DATA_Pos'low),
+                        FromBVote(UART_RX_DATA_Pos'low+RX_Data_d'length-1 downto UART_RX_DATA_Pos'low),
+                        tmr_disable_b);
+      end if;
+    end process UART_Read;
+
+  end generate TMR_Yes;
+
+  RX_Frame_Error  <= rx_frame_error_i;
+  RX_Parity_Error <= rx_parity_error_i;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- uart_transmit.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        uart_transmit.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              uart_transmit.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran  2007-12-18    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity UART_Transmit is
+  generic (
+    C_TARGET          : TARGET_FAMILY_TYPE;
+    C_TMR             : integer := 0;
+    C_USE_TMR_DISABLE : integer := 0;
+    C_VOTE_SIZE       : integer := 0;
+    C_USE_SRL16       : string;
+    C_DATA_BITS       : integer range 5 to 8 := 8;
+    C_USE_PARITY      : integer              := 0;
+    C_ODD_PARITY      : integer              := 1
+    );
+  port (
+    Config_Reset : in std_logic;
+    Clk          : in std_logic;
+    Reset        : in boolean;
+    EN_16x_Baud  : in std_logic;
+
+    TMR_Disable         : in std_logic;
+    FromAVote           : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote           : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote              : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    TX                  : out std_logic;
+    Write_TX_Data       : in  std_logic;
+    TX_Data             : in  std_logic_vector(C_DATA_BITS-1 downto 0);
+    TX_Data_Transmitted : out std_logic;
+    TX_Buffer_Empty     : out std_logic
+    );
+
+end entity UART_Transmit;
+
+library ieee;
+use ieee.numeric_std.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+architecture IMP of UART_Transmit is
+
+  component XIL_SRL16E is
+    generic (
+      C_TARGET    : TARGET_FAMILY_TYPE;
+      C_USE_SRL16 : string;
+      C_STATIC    : boolean := false;
+      INIT        : bit_vector);
+    port (
+      Config_Reset : in  std_logic;
+      Q            : out std_logic;
+      A0           : in  std_logic;
+      A1           : in  std_logic;
+      A2           : in  std_logic;
+      A3           : in  std_logic;
+      CE           : in  std_logic;
+      CLK          : in  std_logic;
+      D            : in  std_logic);
+  end component XIL_SRL16E;
+
+  component MB_MUXCY is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE);
+    port (
+      LO : out std_logic;
+      CI : in  std_logic;
+      DI : in  std_logic;
+      S  : in  std_logic);
+  end component MB_MUXCY;
+
+  component MB_XORCY is
+    generic (
+      C_TARGET : TARGET_FAMILY_TYPE);
+    port (
+      O  : out std_logic;
+      CI : in  std_logic;
+      LI : in  std_logic);
+  end component MB_XORCY;
+
+  component MB_FDSE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '1');
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    S  : in  std_logic);
+  end component MB_FDSE;
+
+  component MB_FDRE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0');
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    R  : in  std_logic);
+  end component MB_FDRE;
+
+  component MB_MUXF5 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE);
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic);
+  end component MB_MUXF5;
+
+  component MB_MUXF6 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE);
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic);
+  end component MB_MUXF6;
+
+  -- signals for parity
+  signal parity           : std_logic;
+  signal calc_Parity      : std_logic;
+  signal tx_Run1          : std_logic;
+  signal select_Parity    : std_logic;
+  signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
+
+  signal div16          : std_logic;
+  signal tx_Data_Enable : std_logic;
+  signal tx_Start       : std_logic;
+  signal tx_DataBits    : std_logic;
+  signal tx_Run         : std_logic;
+
+  signal cnt_cy          : std_logic_vector(1 to 3);
+  signal h_Cnt           : std_logic_vector(0 to 2);
+  signal sum_cnt         : std_logic_vector(0 to 2);
+  signal mux_sel         : std_logic_vector(0 to 2);
+  signal mux_sel_is_zero : std_logic;
+
+  constant mux_sel_init : std_logic_vector(0 to 2) :=
+    std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
+
+  signal mux_01      : std_logic;
+  signal mux_23      : std_logic;
+  signal mux_45      : std_logic;
+  signal mux_67      : std_logic;
+  signal mux_0123    : std_logic;
+  signal mux_4567    : std_logic;
+  signal mux_Out     : std_logic;
+  signal serial_Data : std_logic;
+
+  signal data_is_sent      : std_logic;
+  signal tx_buffer_empty_i : std_logic;
+  signal tx_i              : std_logic;
+  signal fifo_DOut         : std_logic_vector(0 to C_DATA_BITS-1);
+
+  -- Preserve signals after synthesis for simulation UART support
+  attribute KEEP : string;
+  attribute KEEP of tx_buffer_empty_i : signal is "TRUE";
+  attribute KEEP of tx_i              : signal is "TRUE";
+
+begin  -- architecture IMP
+
+  TMR_No : if (C_TMR = 0) generate
+    signal tx_Data_Enable_or_Config_Reset : std_logic;
+    signal tx_Start_or_Config_Reset       : std_logic;
+  begin
+
+    ToVote <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Divide the EN_16x_Baud by 16 to get the correct baudrate
+    -----------------------------------------------------------------------------
+    DIV16_SRL16E : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,       -- [string]
+        INIT        => X"0001")
+      port map (
+        Config_Reset => Config_Reset,     -- [in  std_logic]
+        CE           => EN_16x_Baud,      -- [in  std_logic]
+        D            => div16,            -- [in  std_logic]
+        Clk          => Clk,              -- [in  std_logic]
+        A0           => '1',              -- [in  std_logic]
+        A1           => '1',              -- [in  std_logic]
+        A2           => '1',              -- [in  std_logic]
+        A3           => '1',              -- [in  std_logic]
+        Q            => div16);           -- [out std_logic]
+
+    FDRE_I : MB_FDRE
+      generic map (
+        C_TARGET    => C_TARGET,
+        INIT => '0')                      -- [bit]
+      port map (
+        Q  => tx_Data_Enable,             -- [out std_logic]
+        C  => Clk,                        -- [in  std_logic]
+        CE => EN_16x_Baud,                -- [in  std_logic]
+        D  => div16,                      -- [in  std_logic]
+        R  => tx_Data_Enable_or_Config_Reset);  -- [in std_logic]
+
+    tx_Data_Enable_or_Config_Reset <= tx_Data_Enable or Config_Reset;
+    
+    -----------------------------------------------------------------------------
+    -- tx_start is '1' for the start bit in a transmission
+    -----------------------------------------------------------------------------
+    TX_Start_DFF : process (Clk) is
+    begin  -- process TX_Start_DFF
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if Reset then                 -- asynchronous reset (active high)
+          tx_Start <= '0';
+        else
+          tx_Start <= not(tx_Run) and (tx_Start or (not(tx_buffer_empty_i) and tx_Data_Enable));
+        end if;
+      end if;
+    end process TX_Start_DFF;
+
+    tx_Start_or_Config_Reset <= tx_Start or Config_Reset;
+    
+    -----------------------------------------------------------------------------
+    -- tx_DataBits is '1' during all databits transmission
+    -----------------------------------------------------------------------------
+    TX_Data_DFF : process (Clk) is
+    begin  -- process TX_Data_DFF
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if Reset then                  -- asynchronous reset (active high)
+          tx_DataBits <= '0';
+        else
+          tx_DataBits <= not(data_is_sent) and (tx_DataBits or (tx_Start and tx_Data_Enable));
+        end if;
+      end if;
+    end process TX_Data_DFF;
+
+    -- only decrement during data bits transfer
+    cnt_cy(3) <= not tx_DataBits;
+
+    Counter : for I in 2 downto 0 generate
+    begin
+
+      ---------------------------------------------------------------------------
+      -- If mux_sel is zero then reload with the init value else decrement
+      ---------------------------------------------------------------------------
+      h_Cnt(I) <= mux_sel_init(I) when mux_sel_is_zero = '1' else not mux_sel(I);
+
+      -- Don't need the last muxcy, cnt_cy(0) is not used anywhere
+      Used_MuxCY: if I> 0 generate
+      begin
+        MUXCY_L_I : MB_MUXCY
+          generic map(
+            C_TARGET => C_TARGET)
+          port map (
+            DI => mux_sel(I),               -- [in  std_logic]
+            CI => cnt_cy(I+1),              -- [in  std_logic]
+            S  => h_cnt(I),                 -- [in  std_logic]
+            LO => cnt_cy(I));               -- [out std_logic]
+      end generate Used_MuxCY;
+
+      XORCY_I : MB_XORCY
+        generic map(
+          C_TARGET => C_TARGET)
+        port map (
+          LI => h_cnt(I),                 -- [in  std_logic]
+          CI => cnt_cy(I+1),              -- [in  std_logic]
+          O  => sum_cnt(I));              -- [out std_logic]
+    end generate Counter;
+
+    Mux_Addr_DFF : process (Clk) is
+    begin  -- process Mux_Addr_DFF
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if Reset then                 -- asynchronous reset (active high)
+          mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1, mux_sel'length));
+        else
+          if (tx_Data_Enable = '1') then
+            mux_sel <= sum_cnt;
+          end if;
+        end if;
+      end if;
+    end process Mux_Addr_DFF;
+
+    -- Detecting when mux_sel is zero ie. all data bits is transfered
+    mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
+
+    -- Read out the next data from the transmit fifo when the data has been
+    -- transmitted
+    Data_is_Sent_DFF : process (Clk) is
+    begin  -- process Data_is_Sent_DFF
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if Reset then                 -- asynchronous reset (active high)
+          data_is_sent <= '0';
+        else
+          data_is_sent <= tx_Data_Enable and mux_sel_is_zero;
+        end if;
+      end if;
+    end process Data_is_Sent_DFF;
+
+    TX_Data_Transmitted <= data_is_sent;
+
+    -----------------------------------------------------------------------------
+    -- Select which bit within the data word to transmit
+    -----------------------------------------------------------------------------
+
+    -- Need special treatment for inserting the parity bit because of parity generation
+    Parity_Bit_Insertion : process (parity, select_Parity, fifo_DOut) is
+    begin  -- process Parity_Bit_Insertion
+      data_to_transfer <= fifo_DOut;
+      if (select_Parity = '1') then
+        data_to_transfer(C_DATA_BITS-1) <= parity;
+      end if;
+    end process Parity_Bit_Insertion;
+
+    mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else data_to_transfer(0);
+    mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else data_to_transfer(2);
+
+    Data_Bits_Is_5 : if (C_DATA_BITS = 5) generate
+    begin
+      mux_45 <= data_to_transfer(4);
+      mux_67 <= '0';
+    end generate Data_Bits_Is_5;
+
+    Data_Bits_Is_6 : if (C_DATA_BITS = 6) generate
+    begin
+      mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4);
+      mux_67 <= '0';
+    end generate Data_Bits_Is_6;
+
+    Data_Bits_Is_7 : if (C_DATA_BITS = 7) generate
+    begin
+      mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4);
+      mux_67 <= data_to_transfer(6);
+    end generate Data_Bits_Is_7;
+
+    Data_Bits_Is_8 : if (C_DATA_BITS = 8) generate
+    begin
+      mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4);
+      mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else data_to_transfer(6);
+    end generate Data_Bits_Is_8;
+
+    MUX_F5_1 : MB_MUXF5
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        O  => mux_0123,                   -- [out std_logic]
+        I0 => mux_01,                     -- [in  std_logic]
+        I1 => mux_23,                     -- [in  std_logic]
+        S  => mux_sel(1));                -- [in std_logic]
+
+    MUX_F5_2 : MB_MUXF5
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        O  => mux_4567,                   -- [out std_logic]
+        I0 => mux_45,                     -- [in  std_logic]
+        I1 => mux_67,                     -- [in  std_logic]
+        S  => mux_sel(1));                -- [in std_logic]
+
+    MUXF6_I : MB_MUXF6
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        O  => mux_out,                    -- [out std_logic]
+        I0 => mux_0123,                   -- [in  std_logic]
+        I1 => mux_4567,                   -- [in  std_logic]
+        S  => mux_sel(0));                -- [in std_logic]
+
+    Serial_Data_DFF : process (Clk) is
+    begin  -- process Serial_Data_DFF
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if Reset then                 -- asynchronous reset (active high)
+          serial_Data <= '0';
+        else
+          serial_Data <= mux_Out;
+        end if;
+      end if;
+    end process Serial_Data_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Force a '0' when tx_start is '1', Start_bit
+    -- Force a '1' when tx_run is '0',   Idle
+    -- otherwise put out the serial_data
+    -----------------------------------------------------------------------------
+    Serial_Out_DFF : process (Clk) is
+    begin  -- process Serial_Out_DFF
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        if Reset then                 -- asynchronous reset (active high)
+          tx_i <= '1';
+        else
+          tx_i <= (not(tx_run) or serial_Data) and not(tx_Start);
+        end if;
+      end if;
+    end process Serial_Out_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Parity handling
+    -----------------------------------------------------------------------------
+    Using_Parity : if (C_USE_PARITY = 1) generate
+    begin
+
+      Using_Odd_Parity : if (C_ODD_PARITY = 1) generate
+      begin
+        Parity_Bit : MB_FDSE
+          generic map(
+            C_TARGET => C_TARGET,
+            INIT => '1')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => tx_Data_Enable,         -- [in  std_logic]
+            D  => calc_Parity,            -- [in  std_logic]
+            S  => tx_Start_or_Config_Reset);  -- [in std_logic]
+      end generate Using_Odd_Parity;
+
+      Using_Even_Parity : if (C_ODD_PARITY = 0) generate
+      begin
+        Parity_Bit : MB_FDRE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT => '0')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => tx_Data_Enable,         -- [in  std_logic]
+            D  => calc_Parity,            -- [in  std_logic]
+            R  => tx_Start_or_Config_Reset);  -- [in std_logic]
+      end generate Using_Even_Parity;
+
+      calc_Parity <= parity xor serial_data;
+
+      tx_Run_DFF : process (Clk) is
+      begin  -- process tx_Run_DFF
+        if Clk'event and Clk = '1' then  -- rising clock edge
+          if Reset then                 -- asynchronous reset (active high)
+            tx_Run1 <= '0';
+          else
+            if (tx_Data_Enable = '1') then
+              tx_Run1 <= tx_DataBits;
+            end if;
+          end if;
+        end if;
+      end process tx_Run_DFF;
+
+      tx_Run <= tx_Run1 or tx_DataBits;
+
+      Select_Parity_DFF : process (Clk) is
+      begin  -- process Select_Parity_DFF
+        if Clk'event and Clk = '1' then  -- rising clock edge
+          if Reset then                 -- asynchronous reset (active high)
+            select_Parity <= '0';
+          else
+            if (tx_Data_Enable = '1') then
+              select_Parity <= mux_sel_is_zero;
+            end if;
+          end if;
+        end if;
+      end process Select_Parity_DFF;
+    end generate Using_Parity;
+
+    No_Parity : if (C_USE_PARITY = 0) generate
+    begin
+      tx_Run1       <= '0';
+      calc_Parity   <= '0';
+      parity        <= '0';
+      tx_Run        <= tx_DataBits;
+      select_Parity <= '0';
+    end generate No_Parity;
+
+    Data_To_Transmit: process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset then
+          fifo_DOut <= (others => '0');
+        elsif (Write_TX_Data = '1') then
+          fifo_DOut <= TX_Data;
+        end if;
+      end if;
+    end process Data_To_Transmit;
+
+    TX_Reg_Status: process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset then
+          tx_buffer_empty_i <= '1';
+        else
+          if Write_TX_Data = '1' then
+            tx_buffer_empty_i <= '0';
+          end if;
+          if (data_is_sent = '1') then
+            tx_buffer_empty_i <= '1';
+          end if;
+        end if;
+      end if;
+    end process TX_Reg_Status;
+
+    TX_Buffer_Empty <= tx_buffer_empty_i;
+
+  end generate TMR_No;
+
+  TMR_Yes : if (C_TMR /= 0) generate
+    signal tmr_disable_b        : boolean;
+    signal div16_voted          : std_logic;
+    signal tx_Data_Enable_voted : std_logic;
+    signal tx_Data_Enable_voted_or_Config_Reset : std_logic;
+    signal tx_Start_d           : std_logic;
+    signal tx_DataBits_d        : std_logic;
+    signal mux_sel_d            : std_logic_vector(0 to 2);
+    signal data_is_sent_d       : std_logic;
+    signal TX_d                 : std_logic;
+    signal select_Parity_d      : std_logic;
+    signal fifo_DOut_d          : std_logic_vector(0 to C_DATA_BITS-1);
+    signal tx_buffer_empty_i_d  : std_logic;
+    signal serial_Data_d        : std_logic;
+  begin
+
+    tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+    -----------------------------------------------------------------------------
+    -- Divide the EN_16x_Baud by 16 to get the correct baudrate
+    -----------------------------------------------------------------------------
+    DIV16_SRL16E : XIL_SRL16E
+      generic map (
+        C_TARGET    => C_TARGET,
+        C_USE_SRL16 => C_USE_SRL16,       -- [string]
+        INIT        => X"0001")
+      port map (
+        Config_Reset => Config_Reset,     -- [in  std_logic]
+        CE           => EN_16x_Baud,      -- [in  std_logic]
+        D            => div16_voted,      -- [in  std_logic]
+        Clk          => Clk,              -- [in  std_logic]
+        A0           => '1',              -- [in  std_logic]
+        A1           => '1',              -- [in  std_logic]
+        A2           => '1',              -- [in  std_logic]
+        A3           => '1',              -- [in  std_logic]
+        Q            => div16);           -- [out std_logic]
+
+    ToVote(UART_TX_DIV16_Pos) <= div16;
+
+    div16_voted <= vote(div16, FromAVote(UART_TX_DIV16_Pos), FromBVote(UART_TX_DIV16_Pos), tmr_disable_b);
+
+    FDRE_I : MB_FDRE
+      generic map (
+        C_TARGET    => C_TARGET,
+        INIT => '0')                      -- [bit]
+      port map (
+        Q  => tx_Data_Enable,             -- [out std_logic]
+        C  => Clk,                        -- [in  std_logic]
+        CE => EN_16x_Baud,                -- [in  std_logic]
+        D  => div16_voted,                -- [in  std_logic]
+        R  => tx_Data_Enable_voted_or_Config_Reset); -- [in std_logic]
+
+    ToVote(UART_TX_DATA_ENABLE_Pos) <= tx_Data_Enable;
+
+    tx_Data_Enable_voted <= vote(tx_Data_Enable,
+                                 FromAVote(UART_TX_DATA_ENABLE_Pos),
+                                 FromBVote(UART_TX_DATA_ENABLE_Pos), tmr_disable_b);
+
+    tx_Data_Enable_voted_or_Config_Reset <= tx_Data_Enable_voted or Config_Reset;
+
+    -----------------------------------------------------------------------------
+    -- tx_start is '1' for the start bit in a transmission
+    -----------------------------------------------------------------------------
+    TX_Start_Logic : process (Reset, tx_Run, tx_Start, tx_buffer_empty_i, tx_Data_Enable) is
+    begin
+      if Reset then
+        tx_Start_d <= '0';
+      else
+        tx_Start_d <= not(tx_Run) and (tx_Start or (not(tx_buffer_empty_i) and tx_Data_Enable));
+      end if;
+    end process TX_Start_Logic;
+
+    ToVote(UART_TX_START_Pos) <= tx_Start_d;
+
+    TX_Start_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then  -- rising clock edge
+        tx_Start <= vote(tx_Start_d, FromAVote(UART_TX_START_Pos), FromBVote(UART_TX_START_Pos), tmr_disable_b);
+      end if;
+    end process TX_Start_DFF;
+
+    -----------------------------------------------------------------------------
+    -- tx_DataBits is '1' during all databits transmission
+    -----------------------------------------------------------------------------
+    TX_Data_Logic : process (Reset, data_is_sent, tx_DataBits, tx_Start, tx_Data_Enable) is
+    begin
+      if Reset then
+        tx_DataBits_d <= '0';
+      else
+        tx_DataBits_d <= not(data_is_sent) and (tx_DataBits or (tx_Start and tx_Data_Enable));
+      end if;
+    end process TX_Data_Logic;
+
+    ToVote(UART_TX_DATABITS_Pos) <= tx_DataBits_d;
+
+    TX_Data_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        tx_DataBits <= vote(tx_DataBits_d,
+                            FromAVote(UART_TX_DATABITS_Pos),
+                            FromBVote(UART_TX_DATABITS_Pos), tmr_disable_b);
+      end if;
+    end process TX_Data_DFF;
+
+    -- only decrement during data bits transfer
+    cnt_cy(3) <= not tx_DataBits;
+
+    Counter : for I in 2 downto 0 generate
+    begin
+
+      ---------------------------------------------------------------------------
+      -- If mux_sel is zero then reload with the init value else decrement
+      ---------------------------------------------------------------------------
+      h_Cnt(I) <= mux_sel_init(I) when mux_sel_is_zero = '1' else not mux_sel(I);
+
+      -- Don't need the last muxcy, cnt_cy(0) is not used anywhere
+      Used_MuxCY: if I> 0 generate
+      begin
+        MUXCY_L_I : MB_MUXCY
+          generic map(
+            C_TARGET => C_TARGET)
+          port map (
+            DI => mux_sel(I),               -- [in  std_logic]
+            CI => cnt_cy(I+1),              -- [in  std_logic]
+            S  => h_cnt(I),                 -- [in  std_logic]
+            LO => cnt_cy(I));               -- [out std_logic]
+      end generate Used_MuxCY;
+
+      XORCY_I : MB_XORCY
+        generic map(
+          C_TARGET => C_TARGET)
+        port map (
+          LI => h_cnt(I),                 -- [in  std_logic]
+          CI => cnt_cy(I+1),              -- [in  std_logic]
+          O  => sum_cnt(I));              -- [out std_logic]
+    end generate Counter;
+
+    Mux_Addr_Logic : process (Reset,tx_Data_Enable, sum_cnt, mux_sel) is
+    begin  -- process Mux_Addr_DFF
+      if Reset then                 -- asynchronous reset (active high)
+        mux_sel_d <= std_logic_vector(to_unsigned(C_DATA_BITS-1, mux_sel'length));
+      else
+        if (tx_Data_Enable = '1') then
+          mux_sel_d <= sum_cnt;
+        else
+          mux_sel_d <= mux_sel;
+        end if;
+      end if;
+    end process Mux_Addr_Logic;
+
+    ToVote(UART_TX_MUX_SEL_Pos) <= mux_sel_d;
+
+    Mux_Addr_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        mux_sel <= vote(mux_sel_d, FromAVote(UART_TX_MUX_SEL_Pos), FromBVote(UART_TX_MUX_SEL_Pos), tmr_disable_b);
+      end if;
+    end process Mux_Addr_DFF;
+
+    -- Detecting when mux_sel is zero ie. all data bits is transfered
+    mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
+
+    -- Read out the next data from the transmit fifo when the data has been
+    -- transmitted
+    Data_is_Sent_Logic : process (Reset, tx_Data_Enable, mux_sel_is_zero) is
+    begin
+      if Reset then
+        data_is_sent_d <= '0';
+      else
+        data_is_sent_d <= tx_Data_Enable and mux_sel_is_zero;
+      end if;
+    end process Data_is_Sent_Logic;
+
+    ToVote(UART_TX_DATA_IS_SENT_Pos) <= data_is_sent_d;
+
+    Data_is_Sent_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        data_is_sent <= vote(data_is_sent_d,
+                             FromAVote(UART_TX_DATA_IS_SENT_Pos),
+                             FromBVote(UART_TX_DATA_IS_SENT_Pos), tmr_disable_b);
+      end if;
+    end process Data_is_Sent_DFF;
+
+    TX_Data_Transmitted <= data_is_sent;
+
+    -----------------------------------------------------------------------------
+    -- Select which bit within the data word to transmit
+    -----------------------------------------------------------------------------
+
+    -- Need special treatment for inserting the parity bit because of parity generation
+    Parity_Bit_Insertion : process (parity, select_Parity, fifo_DOut) is
+    begin  -- process Parity_Bit_Insertion
+      data_to_transfer <= fifo_DOut;
+      if (select_Parity = '1') then
+        data_to_transfer(C_DATA_BITS-1) <= parity;
+      end if;
+    end process Parity_Bit_Insertion;
+
+    mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else data_to_transfer(0);
+    mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else data_to_transfer(2);
+
+    Data_Bits_Is_5 : if (C_DATA_BITS = 5) generate
+    begin
+      mux_45 <= data_to_transfer(4);
+      mux_67 <= '0';
+    end generate Data_Bits_Is_5;
+
+    Data_Bits_Is_6 : if (C_DATA_BITS = 6) generate
+    begin
+      mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4);
+      mux_67 <= '0';
+    end generate Data_Bits_Is_6;
+
+    Data_Bits_Is_7 : if (C_DATA_BITS = 7) generate
+    begin
+      mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4);
+      mux_67 <= data_to_transfer(6);
+    end generate Data_Bits_Is_7;
+
+    Data_Bits_Is_8 : if (C_DATA_BITS = 8) generate
+    begin
+      mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else data_to_transfer(4);
+      mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else data_to_transfer(6);
+    end generate Data_Bits_Is_8;
+
+    MUX_F5_1 : MB_MUXF5
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        O  => mux_0123,                   -- [out std_logic]
+        I0 => mux_01,                     -- [in  std_logic]
+        I1 => mux_23,                     -- [in  std_logic]
+        S  => mux_sel(1));                -- [in std_logic]
+
+    MUX_F5_2 : MB_MUXF5
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        O  => mux_4567,                   -- [out std_logic]
+        I0 => mux_45,                     -- [in  std_logic]
+        I1 => mux_67,                     -- [in  std_logic]
+        S  => mux_sel(1));                -- [in std_logic]
+
+    MUXF6_I : MB_MUXF6
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        O  => mux_out,                    -- [out std_logic]
+        I0 => mux_0123,                   -- [in  std_logic]
+        I1 => mux_4567,                   -- [in  std_logic]
+        S  => mux_sel(0));                -- [in std_logic]
+
+    Serial_Data_Logic : process (Reset, mux_Out) is
+    begin
+      if Reset then
+        serial_Data_d <= '0';
+      else
+        serial_Data_d <= mux_Out;
+      end if;
+    end process Serial_Data_Logic;
+
+    ToVote(UART_TX_SERIAL_DATA_Pos) <= serial_Data_d;
+
+    Serial_Data_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        serial_Data <= vote(serial_Data_d,
+                            FromAVote(UART_TX_SERIAL_DATA_Pos),
+                            FromBVote(UART_TX_SERIAL_DATA_Pos), tmr_disable_b);
+      end if;
+    end process Serial_Data_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Force a '0' when tx_start is '1', Start_bit
+    -- Force a '1' when tx_run is '0',   Idle
+    -- otherwise put out the serial_data
+    -----------------------------------------------------------------------------
+    Serial_Out_Logic : process (Reset, tx_run, serial_Data, tx_Start) is
+    begin
+      if Reset then
+        TX_d <= '1';
+      else
+        TX_d <= (not(tx_run) or serial_Data) and not(tx_Start);
+      end if;
+    end process Serial_Out_Logic;
+
+    ToVote(UART_TX_Pos) <= TX_d;
+
+    Serial_Out_DFF : process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        tx_i <= vote(TX_d, FromAVote(UART_TX_Pos), FromBVote(UART_TX_Pos), tmr_disable_b);
+      end if;
+    end process Serial_Out_DFF;
+
+    -----------------------------------------------------------------------------
+    -- Parity handling
+    -----------------------------------------------------------------------------
+    Using_Parity : if (C_USE_PARITY = 1) generate
+      signal calc_Parity_voted    : std_logic;
+      signal tx_Run1_d            : std_logic;
+      signal serial_Data_d        : std_logic;
+    begin
+
+      Using_Odd_Parity : if (C_ODD_PARITY = 1) generate
+      begin
+        Parity_Bit : MB_FDSE
+          generic map(
+            C_TARGET => C_TARGET,
+            INIT => '1')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => tx_Data_Enable_voted,   -- [in  std_logic]
+            D  => calc_Parity_voted,      -- [in  std_logic]
+            S  => tx_Start_d);            -- [in std_logic]
+      end generate Using_Odd_Parity;
+
+      Using_Even_Parity : if (C_ODD_PARITY = 0) generate
+      begin
+        Parity_Bit : MB_FDRE
+          generic map (
+            C_TARGET => C_TARGET,
+            INIT => '0')                  -- [bit]
+          port map (
+            Q  => Parity,                 -- [out std_logic]
+            C  => Clk,                    -- [in  std_logic]
+            CE => tx_Data_Enable_voted,   -- [in  std_logic]
+            D  => calc_Parity_voted,      -- [in  std_logic]
+            R  => tx_Start_d);            -- [in std_logic]
+      end generate Using_Even_Parity;
+
+      calc_Parity <= parity xor serial_data;
+
+      calc_Parity_voted <= vote(calc_Parity,
+                                FromAVote(UART_TX_CALC_PARITY_Pos),
+                                FromBVote(UART_TX_CALC_PARITY_Pos), tmr_disable_b);
+
+      ToVote(UART_TX_CALC_PARITY_Pos) <= calc_Parity;
+
+      tx_Run_Logic : process (Reset, tx_Data_Enable, tx_DataBits, tx_Run1) is
+      begin
+        if Reset then
+          tx_Run1_d <= '0';
+        else
+          if (tx_Data_Enable = '1') then
+            tx_Run1_d <= tx_DataBits;
+          else
+            tx_Run1_d <= tx_Run1;
+          end if;
+        end if;
+      end process tx_Run_Logic;
+
+      ToVote(UART_TX_RUN_Pos) <= tx_Run1_d;
+
+      tx_Run_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          tx_Run1 <= vote(tx_Run1_d, FromAVote(UART_TX_RUN_Pos), FromBVote(UART_TX_RUN_Pos), tmr_disable_b);
+        end if;
+      end process tx_Run_DFF;
+
+      tx_Run <= tx_Run1 or tx_DataBits;
+
+      Select_Parity_Logic: process (Reset, tx_Data_Enable, mux_sel_is_zero, select_Parity) is
+      begin
+        if Reset then
+          select_Parity_d <= '0';
+        else
+          if (tx_Data_Enable = '1') then
+            select_Parity_d <= mux_sel_is_zero;
+          else
+            select_Parity_d <= select_Parity;
+          end if;
+        end if;
+      end process Select_Parity_Logic;
+
+      ToVote(UART_TX_SEL_PARITY_Pos) <= select_Parity_d;
+
+      Select_Parity_DFF : process (Clk) is
+      begin
+        if Clk'event and Clk = '1' then
+          select_Parity <= vote(select_Parity_d,
+                                FromAVote(UART_TX_SEL_PARITY_Pos),
+                                FromBVote(UART_TX_SEL_PARITY_Pos), tmr_disable_b);
+        end if;
+      end process Select_Parity_DFF;
+
+    end generate Using_Parity;
+
+    No_Parity : if (C_USE_PARITY = 0) generate
+    begin
+      tx_Run1                         <= '0';
+      calc_Parity                     <= '0';
+      parity                          <= '0';
+      tx_Run                          <= tx_DataBits;
+      select_Parity                   <= '0';
+      select_Parity_d                 <= '0';
+      ToVote(UART_TX_CALC_PARITY_Pos) <= '0';
+      ToVote(UART_TX_RUN_Pos)         <= '0';
+      ToVote(UART_TX_SEL_PARITY_Pos)  <= '0';
+    end generate No_Parity;
+
+    Data_To_Transmit_Logic: process (Reset, Write_TX_Data, TX_Data, fifo_DOut) is
+    begin
+      if Reset then
+        fifo_DOut_d <= (others => '0');
+      elsif (Write_TX_Data = '1') then
+        fifo_DOut_d <= TX_Data;
+      else
+        fifo_DOut_d <= fifo_DOut;
+      end if;
+    end process Data_To_Transmit_Logic;
+
+    ToVote(UART_TX_FIFO_DOUT_Pos'low+fifo_DOut'length-1 downto UART_TX_FIFO_DOUT_Pos'low) <= fifo_DOut_d;
+
+    -- Work around spyglass bug report on null range to the left but not to the right
+    spy_g: if C_DATA_BITS < 8 generate
+    begin
+      ToVote(UART_TX_FIFO_DOUT_Pos'high downto UART_TX_FIFO_DOUT_Pos'low+fifo_DOut'length)  <= (others => '0');
+    end generate spy_g;
+
+    Data_To_Transmit_DFF: process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        fifo_DOut <= vote(fifo_DOut_d,
+                          FromAVote(UART_TX_FIFO_DOUT_Pos'low+fifo_DOut'length-1 downto UART_TX_FIFO_DOUT_Pos'low),
+                          FromBVote(UART_TX_FIFO_DOUT_Pos'low+fifo_DOut'length-1 downto UART_TX_FIFO_DOUT_Pos'low),
+                          tmr_disable_b);
+      end if;
+    end process Data_To_Transmit_DFF;
+
+    TX_Reg_Status_Logic: process (Reset, Write_TX_Data, data_is_sent, tx_buffer_empty_i) is
+    begin
+      if Reset then
+        tx_buffer_empty_i_d <= '1';
+      else
+        if (data_is_sent = '1') then
+          tx_buffer_empty_i_d <= '1';
+        elsif Write_TX_Data = '1' then
+          tx_buffer_empty_i_d <= '0';
+        else
+          tx_buffer_empty_i_d <= tx_buffer_empty_i;
+        end if;
+      end if;
+    end process TX_Reg_Status_Logic;
+
+    ToVote(UART_TX_BUFFER_EMPTY_Pos) <= tx_buffer_empty_i_d;
+
+    TX_Reg_Status_DFF: process (Clk) is
+    begin
+      if Clk'event and Clk = '1' then
+        tx_buffer_empty_i <= vote(tx_buffer_empty_i_d,
+                                  FromAVote(UART_TX_BUFFER_EMPTY_Pos),
+                                  FromBVote(UART_TX_BUFFER_EMPTY_Pos), tmr_disable_b);
+      end if;
+    end process TX_Reg_Status_DFF;
+
+    TX_Buffer_Empty <= tx_buffer_empty_i;
+
+  end generate TMR_Yes;
+
+  TX <= tx_i;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- uart_core.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        uart_core.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--            uart
+--              uart_core
+--
+-------------------------------------------------------------------------------
+-- Author:          roland
+--
+-- History:
+--   roland  2019-12-01    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+entity UART_Core is
+  generic (
+    C_TARGET             : TARGET_FAMILY_TYPE;
+    C_FREQ               : integer              := 100000000;
+    C_TMR                : integer              := 0;
+    C_USE_TMR_DISABLE    : integer              := 0;
+    C_VOTE_SIZE          : integer              := 0;
+    C_USE_SRL16          : string;
+    C_UART_PROG_BAUDRATE : integer              := 0;
+    C_UART_BAUDRATE      : integer              := 9600;
+    C_USE_UART_RX        : integer              := 1;
+    C_USE_UART_TX        : integer              := 1;
+    C_UART_DATA_BITS     : integer range 5 to 8 := 8;
+    C_UART_USE_PARITY    : integer              := 0;
+    C_UART_ODD_PARITY    : integer              := 0);
+  port (
+    Clk                  : in  std_logic;
+    Reset                : in  boolean;
+    Config_Reset         : in  std_logic;
+
+    TMR_Disable          : in  std_logic;
+    FromAVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote               : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+    TX                   : out std_logic;
+    Write_TX_Data        : in  std_logic;
+    Write_Data           : in  std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    Write_Baud           : in  std_logic;
+    Write_Baud_Data      : in  std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+
+    RX                   : in  std_logic;
+    Read_RX_Data         : in  std_logic;
+    RX_Data_Received     : out std_logic;
+    RX_Data              : out std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+
+    UART_Status_Read     : in  std_logic;
+    UART_Status          : out std_logic_vector(7 downto 0);
+    UART_Interrupt       : out std_logic;
+    UART_Rx_Interrupt    : out std_logic;
+    UART_Tx_Interrupt    : out std_logic;
+    UART_Error_Interrupt : out std_logic);
+end entity UART_Core;
+
+architecture IMP of UART_Core is
+
+  component FIT_Module is
+    generic (
+      C_TARGET          : TARGET_FAMILY_TYPE;
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_USE_SRL16       : string;
+      C_USE_FIT         : integer;
+      C_NO_CLOCKS       : integer;      -- The number of clocks between each interrupt
+      C_INACCURACY      : integer);     -- The maximum inaccuracy of the number
+    port (
+      Config_Reset : in  std_logic;
+      Clk          : in  std_logic;
+      Reset        : in  boolean;
+      TMR_Disable  : in  std_logic;
+      FromAVote    : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote    : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote       : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      Toggle       : out std_logic;
+      Interrupt    : out std_logic);
+  end component FIT_Module;
+
+  component UART_Transmit is
+    generic (
+      C_TARGET          : TARGET_FAMILY_TYPE;
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_USE_SRL16       : string;
+      C_DATA_BITS       : integer range 5 to 8;
+      C_USE_PARITY      : integer;
+      C_ODD_PARITY      : integer);
+    port (
+      Config_Reset : in std_logic;
+      Clk          : in std_logic;
+      Reset        : in boolean;
+      EN_16x_Baud  : in std_logic;
+
+      TMR_Disable         : in  std_logic;
+      FromAVote           : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote           : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote              : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      TX                  : out std_logic;
+      Write_TX_Data       : in  std_logic;
+      TX_Data             : in  std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+      TX_Data_Transmitted : out std_logic;
+      TX_Buffer_Empty     : out std_logic);
+  end component UART_Transmit;
+
+  component UART_Receive is
+    generic (
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_TARGET          : TARGET_FAMILY_TYPE;
+      C_USE_SRL16       : string;
+      C_DATA_BITS       : integer range 5 to 8;
+      C_USE_PARITY      : integer;
+      C_ODD_PARITY      : integer);
+    port (
+      Config_Reset : in std_logic;
+      Clk          : in std_logic;
+      Reset        : in boolean;
+      EN_16x_Baud  : in std_logic;
+
+      RX               : in  std_logic;
+      Read_RX_Data     : in  std_logic;
+      TMR_Disable      : in  std_logic;
+      FromAVote        : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote        : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote           : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      RX_Data          : out std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+      RX_Data_Received : out std_logic;
+      RX_Data_Exists   : out std_logic;
+      RX_Frame_Error   : out std_logic;
+      RX_Overrun_Error : out std_logic;
+      RX_Parity_Error  : out std_logic);
+  end component UART_Receive;
+
+  component Uart_Control_Status is
+    generic (
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_USE_UART_RX     : integer;
+      C_USE_UART_TX     : integer;
+      C_UART_DATA_BITS  : integer range 5 to 8;
+      C_UART_USE_PARITY : integer;
+      C_UART_ODD_PARITY : integer);
+    port (
+      CLK   : in std_logic;
+      Reset : in boolean;
+      Config_Reset : in std_logic;      
+
+      TMR_Disable : in  std_logic;
+      FromAVote   : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote   : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote      : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+      TX_Data_Transmitted : in std_logic;
+      TX_Buffer_Empty     : in std_logic;
+      RX_Data_Received    : in std_logic;
+      RX_Data_Exists      : in std_logic;
+      RX_Frame_Error      : in std_logic;
+      RX_Overrun_Error    : in std_logic;
+      RX_Parity_Error     : in std_logic;
+
+      UART_Status_Read     : in  std_logic;
+      UART_Status          : out std_logic_vector(7 downto 0);
+      UART_Interrupt       : out std_logic;
+      UART_Rx_Interrupt    : out std_logic;
+      UART_Tx_Interrupt    : out std_logic;
+      UART_Error_Interrupt : out std_logic);
+  end component Uart_Control_Status;
+
+  --------------------------------------------------------------------------------------------------
+  -- Calculate FIT period for generating 16*C_UART_BAUDRATE
+  --------------------------------------------------------------------------------------------------
+  function FIT_PERIOD (FREQ : integer; BAUDRATE : integer ) return natural is
+    constant C_BAUDRATE_16_BY_2 : integer := (16 * BAUDRATE) / 2;
+    constant C_REMAINDER        : integer := FREQ rem (16 * BAUDRATE);
+    constant C_RATIO            : integer := FREQ / (16 * BAUDRATE);
+  begin
+    if (C_BAUDRATE_16_BY_2 < C_REMAINDER) then
+      return (C_RATIO + 1);
+    else
+      return C_RATIO;
+    end if;
+  end function FIT_PERIOD;
+
+  -- Enable for Divide by 16 UART clock
+  signal en_16x_baud          : std_logic;
+
+  -- TX Control
+  signal tx_data_transmitted  : std_logic;
+  signal tx_buffer_empty      : std_logic;
+
+  -- RX Control
+  signal rx_data_received_i   : std_logic;
+  signal rx_data_exists       : std_logic;
+  signal rx_frame_error       : std_logic;
+  signal rx_overrun_error     : std_logic;
+  signal rx_parity_error      : std_logic;
+
+begin  -- architecture IMP
+
+  Using_UART_TX : if (C_USE_UART_TX /= 0) generate
+  begin
+
+    UART_TX_I1 : UART_Transmit
+      generic map (
+        C_TARGET          => C_TARGET,
+        C_TMR             => C_TMR,
+        C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+        C_VOTE_SIZE       => UART_TRANSMIT_Pos'high-UART_TRANSMIT_Pos'low+1,
+        C_USE_SRL16       => C_USE_SRL16,
+        C_DATA_BITS       => C_UART_DATA_BITS,
+        C_USE_PARITY      => C_UART_USE_PARITY,
+        C_ODD_PARITY      => C_UART_ODD_PARITY)
+      port map (
+        Config_Reset => Config_Reset,
+        Clk          => Clk,
+        Reset        => Reset,
+        EN_16x_Baud  => en_16x_baud,
+
+        TMR_Disable         => TMR_Disable,
+        FromAVote           => FromAVote(UART_TRANSMIT_Pos),
+        FromBVote           => FromBVote(UART_TRANSMIT_Pos),
+        ToVote              => ToVote(UART_TRANSMIT_Pos),
+        TX                  => Tx,
+        Write_TX_Data       => Write_TX_Data,
+        TX_Data             => Write_Data(C_UART_DATA_BITS-1 downto 0),
+        TX_Data_Transmitted => tx_data_transmitted,
+        TX_Buffer_Empty     => tx_buffer_empty);
+  end generate Using_UART_TX;
+
+  No_UART_TX : if (C_USE_UART_TX = 0) generate
+  begin
+    tx_buffer_empty           <= '0';
+    tx_data_transmitted       <= '0';
+    Tx                        <= '0';
+    ToVote(UART_TRANSMIT_Pos) <= (others => '0');
+  end generate No_UART_TX;
+
+  Using_UART_RX : if (C_USE_UART_RX /= 0) generate
+  begin
+
+    UART_RX_I1 : UART_Receive
+      generic map (
+        C_TARGET          => C_TARGET,
+        C_TMR             => C_TMR,
+        C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+        C_VOTE_SIZE       => UART_RECEIVE_Pos'high-UART_RECEIVE_Pos'low+1,
+        C_USE_SRL16       => C_USE_SRL16,
+        C_DATA_BITS       => C_UART_DATA_BITS,
+        C_USE_PARITY      => C_UART_USE_PARITY,
+        C_ODD_PARITY      => C_UART_ODD_PARITY)
+      port map (
+        Config_Reset => Config_Reset,
+        Clk          => Clk,
+        Reset        => Reset,
+        EN_16x_Baud  => en_16x_baud,
+
+        RX               => RX,
+        Read_RX_Data     => Read_RX_Data,
+        TMR_Disable      => TMR_Disable,
+        FromAVote        => FromAVote(UART_RECEIVE_Pos),
+        FromBVote        => FromBVote(UART_RECEIVE_Pos),
+        ToVote           => ToVote(UART_RECEIVE_Pos),
+        RX_Data          => RX_Data,
+        RX_Data_Received => rx_data_received_i,
+        RX_Data_Exists   => rx_data_exists,
+        RX_Frame_Error   => rx_frame_error,
+        RX_Overrun_Error => rx_overrun_error,
+        RX_Parity_Error  => rx_parity_error);
+  end generate Using_UART_RX;
+
+  No_UART_RX : if (C_USE_UART_RX = 0) generate
+  begin
+    RX_Data                  <= (others => '0');
+    rx_data_received_i       <= '0';
+    rx_data_exists           <= '0';
+    rx_frame_error           <= '0';
+    rx_overrun_error         <= '0';
+    rx_parity_error          <= '0';
+    ToVote(UART_RECEIVE_Pos) <= (others => '0');
+  end generate No_UART_RX;
+
+  RX_Data_Received <= rx_data_received_i;
+  
+  Using_UART : if ((C_USE_UART_RX /= 0) or (C_USE_UART_TX /= 0)) generate
+  begin
+
+    No_Dynamic_BaudRate: if C_UART_PROG_BAUDRATE = 0 generate
+    begin
+      UART_FIT_I : FIT_Module
+        generic map (
+          C_TARGET          => C_TARGET,
+          C_TMR             => C_TMR,
+          C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+          C_VOTE_SIZE       => UART_BAUD_FIT_Pos'high-UART_BAUD_FIT_Pos'low+1,
+          C_USE_SRL16       => C_USE_SRL16,
+          C_USE_FIT         => 1,
+          C_NO_CLOCKS       => FIT_PERIOD(C_FREQ, C_UART_BAUDRATE),
+          C_INACCURACY      => 0)
+        port map (
+          Config_Reset => Config_Reset,
+          Clk          => Clk,
+          Reset        => Reset,
+          TMR_Disable  => TMR_Disable,
+          FromAVote    => FromAVote(UART_BAUD_FIT_Pos),
+          FromBVote    => FromBVote(UART_BAUD_FIT_Pos),
+          ToVote       => ToVote(UART_BAUD_FIT_Pos),
+          Toggle       => open,
+          Interrupt    => en_16x_baud);
+
+      ToVote(UART_BAUD_REG_Pos)  <= (others => '0');
+      ToVote(UART_BAUD_CNT_Pos)  <= (others => '0');
+      ToVote(UART_BAUD_EN16_Pos) <= '0';
+
+    end generate No_Dynamic_BaudRate;
+
+    Programmable_BaudRate_TMR_No: if C_UART_PROG_BAUDRATE /= 0 and C_TMR = 0 generate
+      signal baudrate_cnt : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+      signal baudrate_reg : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+    begin
+
+      ToVote(UART_BAUD_FIT_Pos) <= (others => '0');
+
+      BaudRate_Counter : process (Clk)
+      begin  -- process BaudRate_Counter
+        if Clk'event and Clk = '1' then  -- rising clock edge
+          if Reset then                  -- synchronous reset (active high)
+            baudrate_reg <=
+              std_logic_vector(to_unsigned(FIT_PERIOD(C_FREQ, C_UART_BAUDRATE) - 1, baudrate_reg'length));
+            baudrate_cnt <= (others => '0');
+            en_16x_baud  <= '0';
+          else
+            en_16x_baud <= '0';
+            if baudrate_cnt = "00000000000000000000" then
+              baudrate_cnt <= baudrate_reg;
+              en_16x_baud  <= '1';
+            else
+              baudrate_cnt <= std_logic_vector(unsigned(baudrate_cnt) - 1);
+            end if;
+            if Write_Baud = '1' then
+              baudrate_reg <= Write_Baud_Data;
+              baudrate_cnt <= (others => '0');
+            end if;
+          end if;
+        end if;
+      end process BaudRate_Counter;
+
+      ToVote(UART_BAUD_REG_Pos)  <= (others => '0');
+      ToVote(UART_BAUD_CNT_Pos)  <= (others => '0');
+      ToVote(UART_BAUD_EN16_Pos) <= '0';
+
+    end generate Programmable_BaudRate_TMR_No;
+
+    Programmable_BaudRate_TMR_Yes: if C_UART_PROG_BAUDRATE /= 0 and C_TMR = 1 generate
+      signal baudrate_cnt   : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+      signal baudrate_reg   : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+      signal baudrate_cnt_d : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+      signal baudrate_reg_d : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+      signal en_16x_baud_d  : std_logic;
+      signal tmr_disable_b  : boolean;
+    begin
+
+      ToVote(UART_BAUD_FIT_Pos) <= (others => '0');
+
+      tmr_disable_b <= TMR_Disable = '1' and C_USE_TMR_DISABLE = 1;
+
+      BaudRate_Counter_Logic : process (Reset, baudrate_reg, baudrate_cnt, Write_Baud, Write_Baud_Data)
+      begin
+        if Reset then
+          baudrate_reg_d <=
+            std_logic_vector(to_unsigned(FIT_PERIOD(C_FREQ, C_UART_BAUDRATE) - 1, baudrate_reg'length));
+          baudrate_cnt_d <= (others => '0');
+          en_16x_baud_d  <= '0';
+        else
+          if baudrate_cnt = "00000000000000000000" then
+            baudrate_cnt_d <= baudrate_reg;
+            en_16x_baud_d  <= '1';
+          else
+            baudrate_cnt_d <= std_logic_vector(unsigned(baudrate_cnt) - 1);
+            en_16x_baud_d  <= '0';
+          end if;
+          if Write_Baud = '1' then
+            baudrate_reg_d <= Write_Baud_Data;
+            baudrate_cnt_d <= (others => '0');
+          else
+            baudrate_reg_d <= baudrate_reg;
+          end if;
+        end if;
+      end process BaudRate_Counter_Logic;
+
+      ToVote(UART_BAUD_REG_Pos)  <= baudrate_reg_d;
+      ToVote(UART_BAUD_CNT_Pos)  <= baudrate_cnt_d;
+      ToVote(UART_BAUD_EN16_Pos) <= en_16x_baud_d;
+
+      BaudRate_Counter_DFF : process (Clk)
+      begin
+        if Clk'event and Clk = '1' then
+          baudrate_reg <= vote(baudrate_reg_d,
+                               FromAVote(UART_BAUD_REG_Pos),
+                               FromBVote(UART_BAUD_REG_Pos), tmr_disable_b);
+          baudrate_cnt <= vote(baudrate_cnt_d,
+                               FromAVote(UART_BAUD_CNT_Pos),
+                               FromBVote(UART_BAUD_CNT_Pos), tmr_disable_b);
+          en_16x_baud  <= vote(en_16x_baud_d,
+                               FromAVote(UART_BAUD_EN16_Pos),
+                               FromBVote(UART_BAUD_EN16_Pos), tmr_disable_b);
+        end if;
+      end process BaudRate_Counter_DFF;
+
+    end generate Programmable_BaudRate_TMR_Yes;
+
+    Uart_Control_Status_I1 : Uart_Control_Status
+      generic map (
+        C_TMR             => C_TMR,
+        C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+        C_VOTE_SIZE       => UART_CONTROL_Pos'high-UART_CONTROL_Pos'low+1,
+        C_USE_UART_RX     => C_USE_UART_RX,
+        C_USE_UART_TX     => C_USE_UART_TX,
+        C_UART_DATA_BITS  => C_UART_DATA_BITS,
+        C_UART_USE_PARITY => C_UART_USE_PARITY,
+        C_UART_ODD_PARITY => C_UART_ODD_PARITY)
+      port map (
+        CLK                  => CLK,
+        Reset                => Reset,
+        Config_Reset         => Config_Reset,
+        TMR_Disable          => TMR_Disable,
+        FromAVote            => FromAVote(UART_CONTROL_Pos),
+        FromBVote            => FromBVote(UART_CONTROL_Pos),
+        ToVote               => ToVote(UART_CONTROL_Pos),
+        TX_Data_Transmitted  => tx_data_transmitted,
+        TX_Buffer_Empty      => tx_buffer_empty,
+        RX_Data_Received     => rx_data_received_i,
+        RX_Data_Exists       => rx_data_exists,
+        RX_Frame_Error       => rx_frame_error,
+        RX_Overrun_Error     => rx_overrun_error,
+        RX_Parity_Error      => rx_parity_error,
+        UART_Status_Read     => UART_Status_Read,
+        UART_Status          => uart_status,
+        UART_Interrupt       => UART_Interrupt,
+        UART_Rx_Interrupt    => UART_RX_Interrupt,
+        UART_Tx_Interrupt    => UART_TX_Interrupt,
+        UART_Error_Interrupt => UART_Error_Interrupt);
+  end generate Using_UART;
+
+  No_UART : if ((C_USE_UART_RX = 0) and (C_USE_UART_TX = 0)) generate
+  begin
+    uart_status                <= (others => '0');
+    UART_Interrupt             <= '0';
+    uart_rx_interrupt          <= '0';
+    uart_tx_interrupt          <= '0';
+    uart_error_interrupt       <= '0';
+    ToVote(UART_BAUD_FIT_Pos)  <= (others => '0');
+    ToVote(UART_BAUD_REG_Pos)  <= (others => '0');
+    ToVote(UART_BAUD_CNT_Pos)  <= (others => '0');
+    ToVote(UART_BAUD_EN16_Pos) <= '0';
+    ToVote(UART_CONTROL_Pos)   <= (others => '0');
+  end generate No_UART;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- uart.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2016 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        uart.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              uart.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          roland
+--
+-- History:
+--   roland  2019-12-01    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+entity UART is
+  generic (
+    C_TARGET             : TARGET_FAMILY_TYPE;
+    C_FREQ               : integer              := 100000000;
+    C_UART_FREQ          : integer              := 100000000;
+    C_TMR                : integer              := 0;
+    C_USE_TMR_DISABLE    : integer              := 0;
+    C_VOTE_SIZE          : integer              := 0;
+    C_USE_SRL16          : string;
+    C_UART_PROG_BAUDRATE : integer              := 0;
+    C_UART_ASYNC         : integer              := 0;
+    C_UART_NUM_SYNC_FF   : integer              := 2;
+    C_UART_BAUDRATE      : integer              := 9600;
+    C_USE_UART_RX        : integer              := 1;
+    C_USE_UART_TX        : integer              := 1;
+    C_UART_DATA_BITS     : integer range 5 to 8 := 8;
+    C_UART_USE_PARITY    : integer              := 0;
+    C_UART_ODD_PARITY    : integer              := 0);
+  port (
+    Clk                  : in std_logic;
+    UART_Clk             : in std_logic;
+    Reset                : in std_logic;
+    Config_Reset         : in std_logic;
+    Reset_UART_Clk       : in std_logic;
+    
+    TMR_Disable          : in  std_logic;
+    FromAVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote               : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+    TX                   : out std_logic;
+    Write_TX_Data        : in  std_logic;
+    Write_Baud           : in  std_logic;
+    Write_Data           : in  std_logic_vector(31 downto 0);
+
+    RX                   : in  std_logic;
+    Read_RX_Data         : in  std_logic;
+    Read_RX_Wait         : out std_logic;
+    Read_RX_Ready        : out  std_logic;
+    RX_Data              : out std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+
+    UART_Status_Read     : in  std_logic;
+    UART_Status_Wait     : out std_logic;
+    UART_Status_Ready    : out std_logic;
+    UART_Status          : out std_logic_vector(7 downto 0);
+    UART_Interrupt       : out std_logic;
+    UART_Rx_Interrupt    : out std_logic;
+    UART_Tx_Interrupt    : out std_logic;
+    UART_Error_Interrupt : out std_logic);
+end entity UART;
+
+architecture IMP of Uart is
+
+  component UART_Core is
+  generic (
+    C_TARGET             : TARGET_FAMILY_TYPE;
+    C_FREQ               : integer              := 100000000;
+    C_TMR                : integer              := 0;
+    C_USE_TMR_DISABLE    : integer              := 0;
+    C_VOTE_SIZE          : integer              := 0;
+    C_USE_SRL16          : string;
+    C_UART_PROG_BAUDRATE : integer              := 0;
+    C_UART_BAUDRATE      : integer              := 9600;
+    C_USE_UART_RX        : integer              := 1;
+    C_USE_UART_TX        : integer              := 1;
+    C_UART_DATA_BITS     : integer range 5 to 8 := 8;
+    C_UART_USE_PARITY    : integer              := 0;
+    C_UART_ODD_PARITY    : integer              := 0);
+  port (
+    Clk                  : in std_logic;
+    Reset                : in boolean;
+    Config_Reset         : in std_logic;
+
+    TMR_Disable          : in  std_logic;
+    FromAVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote               : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+    TX                   : out std_logic;
+    Write_TX_Data        : in  std_logic;
+    Write_Data           : in  std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    Write_Baud           : in  std_logic;
+    Write_Baud_Data      : in  std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+
+    RX                   : in  std_logic;
+    Read_RX_Data         : in  std_logic;
+    RX_Data_Received     : out std_logic;
+    RX_Data              : out std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+
+    UART_Status_Read     : in  std_logic;
+    UART_Status          : out std_logic_vector(7 downto 0);
+    UART_Interrupt       : out std_logic;
+    UART_Rx_Interrupt    : out std_logic;
+    UART_Tx_Interrupt    : out std_logic;
+    UART_Error_Interrupt : out std_logic);
+  end component UART_Core;
+
+  component mb_sync_bit is
+  generic(
+    C_LEVELS            : natural   := 2;
+    C_RESET_VALUE       : std_logic := '0';
+    C_RESET_SYNCHRONOUS : boolean   := true;
+    C_RESET_ACTIVE_HIGH : boolean   := true);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic;
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic;
+    Scan_Reset     : in  std_logic;
+    Raw            : in  std_logic;
+    Synced         : out std_logic);
+  end component mb_sync_bit;
+
+  component mb_sync_vec is
+  generic(
+    C_LEVELS            : natural   := 2;
+    C_RESET_VALUE       : std_logic := '0';
+    C_RESET_SYNCHRONOUS : boolean   := true;
+    C_RESET_ACTIVE_HIGH : boolean   := true;
+    C_WIDTH             : natural);
+  port(
+    Clk            : in  std_logic;
+    Rst            : in  std_logic := '0';
+    Scan_En        : in  std_logic;
+    Scan_Reset_Sel : in  std_logic := '0';
+    Scan_Reset     : in  std_logic := '0';
+    Raw            : in  std_logic_vector(0 to C_WIDTH-1);
+    Synced         : out std_logic_vector(0 to C_WIDTH-1));
+  end component mb_sync_vec;
+
+  component pulse_sync is
+  generic(
+    C_LEVELS          : natural := 2;
+    C_TMR             : natural := 0;
+    C_LATE_ACK        : natural := 0;
+    C_USE_TMR_DISABLE : integer := 0);
+  port(
+    FromAVote       : in  std_logic_vector(PULSE_SYNC_Pos);
+    FromBVote       : in  std_logic_vector(PULSE_SYNC_Pos);
+    ToVote          : out std_logic_vector(PULSE_SYNC_Pos);
+
+    Clk_Src         : in  std_logic;
+    Clk_Dst         : in  std_logic;
+    Rst_Src         : in  std_logic;
+    Rst_Dst         : in  std_logic;
+    TMR_Disable_Src : in  std_logic;
+    TMR_Disable_Dst : in  std_logic;
+    Pulse_Src       : in  std_logic;
+    Pulse_Keep_Src  : out std_logic;
+    Pulse_Ack_Src   : out std_logic;
+    Pulse_Dst       : out std_logic);
+  end component pulse_sync;
+
+  signal reset_b  : boolean;
+  signal ToVote_i : std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+begin  -- architecture IMP
+
+  reset_b <= Reset = '1';
+
+  No_Async_UART: if C_UART_ASYNC = 0 generate
+  begin  
+
+    -- Not used
+    ToVote_i(UART_ASYNC_Pos) <= (others => '0');
+    UART_Status_Wait         <= '0';
+    UART_Status_Ready        <= '0';
+    Read_RX_Wait             <= '0';
+    Read_RX_Ready            <= '0';
+    
+    UART_Core_I : UART_Core
+      generic map (
+        C_TARGET             => C_TARGET,
+        C_FREQ               => C_FREQ,
+        C_TMR                => C_TMR,
+        C_USE_TMR_DISABLE    => C_USE_TMR_DISABLE,
+        C_VOTE_SIZE          => UART_CORE_Pos'high-UART_CORE_Pos'low+1,
+        C_USE_SRL16          => C_USE_SRL16,
+        C_UART_PROG_BAUDRATE => C_UART_PROG_BAUDRATE,
+        C_UART_BAUDRATE      => C_UART_BAUDRATE,
+        C_USE_UART_RX        => C_USE_UART_RX,
+        C_USE_UART_TX        => C_USE_UART_TX,
+        C_UART_DATA_BITS     => C_UART_DATA_BITS,
+        C_UART_USE_PARITY    => C_UART_USE_PARITY,
+        C_UART_ODD_PARITY    => C_UART_ODD_PARITY)
+      port map (
+        Config_Reset         => Config_Reset,
+        Clk                  => Clk,
+        Reset                => reset_b,
+
+        TMR_Disable          => TMR_Disable,
+        FromAVote            => FromAVote(UART_CORE_Pos),
+        FromBVote            => FromBVote(UART_CORE_Pos),
+        ToVote               => ToVote_i(UART_CORE_Pos),
+
+        TX                   => TX,
+        Write_TX_Data        => Write_TX_Data,
+        Write_Data           => Write_Data(C_UART_DATA_BITS-1 downto 0),
+        Write_Baud           => Write_Baud,
+        Write_Baud_Data      => Write_Data(C_UART_PROG_CNT_SIZE-1 downto 0),
+        
+        RX                   => RX,
+        Read_RX_Data         => Read_RX_Data,
+        RX_Data_Received     => open,
+        RX_Data              => RX_Data,
+        
+        UART_Status_Read     => UART_Status_Read,
+        UART_Status          => UART_Status,
+        UART_Interrupt       => UART_Interrupt,
+        UART_Rx_Interrupt    => UART_Rx_Interrupt,
+        UART_Tx_Interrupt    => UART_Tx_Interrupt,
+        UART_Error_Interrupt => UART_Error_Interrupt);
+
+  end generate No_Async_UART;
+
+  Async_UART: if C_UART_ASYNC = 1 generate
+    signal reset_std                         : std_logic;
+    signal reset_uart_clk_b                  : boolean;
+    signal tmr_disable_b                     : boolean;
+    signal tmr_disable_raw_uart_clk          : std_logic;
+    signal tmr_disable_uart_clk              : std_logic;
+    signal write_tx_data_uart_clk            : std_logic;
+    signal write_data_clk                    : std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    signal write_data_clkD                   : std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    signal write_baud_uart_clk               : std_logic;
+    signal baud_data_clk                     : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+    signal baud_data_clkD                    : std_logic_vector(C_UART_PROG_CNT_SIZE-1 downto 0);
+    signal read_rx_uart_clk                  : std_logic;
+    signal read_rx_uart_clkQ                 : std_logic;
+    signal read_rx_ack_clk                   : std_logic;
+    signal read_rx_ack_clkQ                  : std_logic;
+    signal read_rx_keep                      : std_logic;
+    signal read_rx_pulse_tovote_clk          : std_logic;
+    signal read_rx_pulse_voted_clk           : std_logic;
+    signal rx_data_tovote_uart_clk           : std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    signal rx_data_voted_uart_clk            : std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    signal rx_data_uart_clk                  : std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+    signal rx_data_received_uart_clk         : std_logic;
+    signal rx_data_received_clk              : std_logic;
+    signal uart_status_read_uart_clk         : std_logic; -- 1 cycle read pulse in UART_Clk region
+    signal uart_status_read_uart_clkQ        : std_logic; -- 1 cycle read pulse in UART_Clk region
+    signal uart_status_read_tovote_uart_clk  : std_logic; -- 1 cycle read pulse in UART_Clk region
+    signal uart_status_read_voted_uart_clk   : std_logic; -- 1 cycle read pulse in UART_Clk region
+    signal uart_status_read_ack_clk          : std_logic;
+    signal uart_status_read_ack_clkQ         : std_logic;
+    signal uart_status_read_keep             : std_logic;
+    signal uart_status_read_pulse_tovote_clk : std_logic;
+    signal uart_status_read_pulse_voted_clk  : std_logic;
+    signal uart_status_uart_clk              : std_logic_vector(7 downto 0);
+    signal uart_status_tovote_uart_clk       : std_logic_vector(7 downto 0);
+    signal uart_status_voted_uart_clk        : std_logic_vector(7 downto 0);
+    signal uart_rx_interrupt_uart_clk        : std_logic;
+    signal uart_rx_interrupt_clk             : std_logic;
+    signal uart_tx_interrupt_uart_clk        : std_logic;
+    signal uart_tx_interrupt_clk             : std_logic;
+    signal uart_error_interrupt_uart_clk     : std_logic;
+    signal uart_error_interrupt_clk          : std_logic;
+  begin
+
+    TMR_Yes : if (C_TMR /= 0) generate
+
+      Use_TMR_Disable: if C_USE_TMR_DISABLE = 1 generate
+      begin
+        
+        TMR_Disable_Sync_I: mb_sync_bit
+        generic map(
+          C_LEVELS            => C_UART_NUM_SYNC_FF,
+          C_RESET_VALUE       => '1',
+          C_RESET_SYNCHRONOUS => true,
+          C_RESET_ACTIVE_HIGH => true)
+        port map(
+          Clk            => UART_Clk,
+          Rst            => Reset_UART_Clk,
+          Scan_En        => '0',
+          Scan_Reset_Sel => '0',
+          Scan_Reset     => '0',
+          Raw            => TMR_Disable,
+          Synced         => tmr_disable_raw_uart_clk);
+
+        TMR_Disable_UART_Clk_DFF : process (UART_Clk) is
+        begin
+          if UART_Clk'event and UART_Clk = '1' then
+            tmr_disable_uart_clk <= vote(tmr_disable_raw_uart_clk,
+                                         FromAVote(TMR_DISABLE_UART_CLK_Pos),
+                                         FromBVote(TMR_DISABLE_UART_CLK_Pos),
+                                         false);
+          end if;
+        end process TMR_Disable_UART_Clk_DFF;
+
+        ToVote_i(TMR_DISABLE_UART_Clk_Pos) <= tmr_disable_raw_uart_clk;
+        
+        tmr_disable_b          <= TMR_Disable = '1';
+        
+      end generate Use_TMR_Disable;
+
+      No_Use_TMR_Disable: if C_USE_TMR_DISABLE = 0 generate
+      begin
+        tmr_disable_raw_uart_clk           <= '0';
+        tmr_disable_uart_clk               <= '0';
+        tmr_disable_b                      <= false;
+        ToVote_i(TMR_DISABLE_UART_Clk_Pos) <= '0';
+      end generate No_Use_TMR_Disable;
+
+    end generate TMR_Yes; 
+
+    TMR_No : if (C_TMR = 0) generate
+    begin
+      tmr_disable_raw_uart_clk           <= '0';
+      tmr_disable_uart_clk               <= '0';
+      tmr_disable_b                      <= false;
+      ToVote_i(TMR_DISABLE_UART_Clk_Pos) <= '0';
+    end generate TMR_No; 
+
+    reset_uart_clk_b <= Reset_UART_Clk = '1';
+
+    UART_Core_I : UART_Core
+      generic map (
+        C_TARGET             => C_TARGET,
+        C_FREQ               => C_UART_FREQ,
+        C_TMR                => C_TMR,
+        C_USE_TMR_DISABLE    => C_USE_TMR_DISABLE,
+        C_VOTE_SIZE          => UART_CORE_Pos'high-UART_CORE_Pos'low+1,
+        C_USE_SRL16          => C_USE_SRL16,
+        C_UART_PROG_BAUDRATE => C_UART_PROG_BAUDRATE,
+        C_UART_BAUDRATE      => C_UART_BAUDRATE,
+        C_USE_UART_RX        => C_USE_UART_RX,
+        C_USE_UART_TX        => C_USE_UART_TX,
+        C_UART_DATA_BITS     => C_UART_DATA_BITS,
+        C_UART_USE_PARITY    => C_UART_USE_PARITY,
+        C_UART_ODD_PARITY    => C_UART_ODD_PARITY)
+      port map (
+        Config_Reset         => Reset_UART_Clk,
+        Clk                  => UART_Clk,
+        Reset                => reset_uart_clk_b,
+
+        TMR_Disable          => tmr_disable_uart_clk,
+        FromAVote            => FromAVote(UART_CORE_Pos),
+        FromBVote            => FromBVote(UART_CORE_Pos),
+        ToVote               => ToVote_i(UART_CORE_Pos),
+
+        TX                   => TX,   -- In UART_Clk domain
+        Write_TX_Data        => write_tx_data_uart_clk,
+        Write_Data           => write_data_clk, -- Stable when write_tx_data_uart_clk is asserted
+        Write_Baud           => write_baud_uart_clk,
+        Write_Baud_Data      => baud_data_clk, -- Stable when write_baud_uart_clk is asserted
+
+        RX                   => RX,   -- In UART_Clk domain
+        Read_RX_Data         => read_rx_uart_clk,
+        RX_Data_Received     => rx_data_received_uart_clk,
+        RX_Data              => rx_data_uart_clk,
+        
+        UART_Status_Read     => uart_status_read_uart_clk,
+        UART_Status          => uart_status_uart_clk,
+        UART_Interrupt       => open,
+        UART_Rx_Interrupt    => uart_rx_interrupt_uart_clk,
+        UART_Tx_Interrupt    => uart_tx_interrupt_uart_clk,
+        UART_Error_Interrupt => uart_error_interrupt_uart_clk);
+
+    Write_TX_Data_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 0,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(WRITE_TX_DATA_POS),
+      FromBVote       => FromBVote(WRITE_TX_DATA_POS),
+      ToVote          => ToVote_i(WRITE_TX_DATA_POS),
+      Clk_Src         => Clk,
+      Clk_Dst         => UART_Clk,
+      Rst_Src         => Reset,
+      Rst_Dst         => Reset_UART_Clk,
+      TMR_Disable_Src => TMR_Disable,
+      TMR_Disable_Dst => tmr_disable_uart_clk,
+      Pulse_Src       => Write_TX_Data,
+      Pulse_Keep_Src  => open,
+      Pulse_Ack_Src   => open,
+      Pulse_Dst       => write_tx_data_uart_clk);
+
+    Write_Data_P : process(Reset, Write_TX_Data, Write_Data, write_data_clk) is
+    begin
+      if Reset = '1' then
+        write_data_clkD <= (others => '0');
+      elsif Write_TX_Data = '1' then
+        write_data_clkD <= Write_Data(C_UART_DATA_BITS-1 downto 0);
+      else
+        write_data_clkD <= write_data_clk;
+      end if;
+    end process Write_Data_P;
+
+    ToVote_i(WRITE_DATA_Pos'low+write_data_clkD'length-1 downto WRITE_DATA_Pos'low) <= write_data_clkD;
+
+    -- Work around spyglass bug report on null range to the left but not to the right
+    spy1_g: if C_UART_DATA_BITS < 8 generate
+    begin
+      ToVote_i(WRITE_DATA_Pos'high downto WRITE_DATA_Pos'low+write_data_clkD'length)  <= (others => '0');
+    end generate spy1_g;
+    
+    Write_Data_DFF : process (Clk)
+    begin
+      if Clk'event and Clk = '1' then
+        write_data_clk <= vote(write_data_clkD,
+                               FromAVote(WRITE_DATA_Pos),
+                               FromBVote(WRITE_DATA_Pos),
+                               tmr_disable_b, C_TMR);
+      end if;
+    end process Write_Data_DFF;
+    
+    Write_Baud_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 0,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(WRITE_BAUD_Pos),
+      FromBVote       => FromBVote(WRITE_BAUD_Pos),
+      ToVote          => ToVote_i(WRITE_BAUD_Pos),
+      Clk_Src         => Clk,
+      Clk_Dst         => UART_Clk,
+      Rst_Src         => Reset,
+      Rst_Dst         => Reset_UART_Clk,
+      TMR_Disable_Src => TMR_Disable,
+      TMR_Disable_Dst => tmr_disable_uart_clk,
+      Pulse_Src       => Write_Baud,
+      Pulse_Keep_Src  => open,
+      Pulse_Ack_Src   => open,
+      Pulse_Dst       => write_baud_uart_clk);
+
+    Baud_Data_P : process(Reset, Write_Baud, Write_Data, baud_data_clk) is
+    begin
+      if Reset = '1' then
+        baud_data_clkD <= (others => '0');
+      elsif Write_Baud = '1' then
+        baud_data_clkD <= Write_Data(C_UART_PROG_CNT_SIZE-1 downto 0);
+      else
+        baud_data_clkD <= baud_data_clk;
+      end if;
+    end process Baud_Data_P;
+
+    ToVote_i(BAUD_DATA_Pos) <= baud_data_clkD;
+    
+    TX_Baud_Data_DFF : process (Clk)
+    begin
+      if Clk'event and Clk = '1' then
+        baud_data_clk <= vote(baud_data_clkD,
+                              FromAVote(BAUD_DATA_Pos),
+                              FromBVote(BAUD_DATA_Pos),
+                              tmr_disable_b, C_TMR);
+      end if;
+    end process TX_Baud_Data_DFF;
+    
+    RX_Data_Received_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 0,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(RX_DATA_RECEIVED_Pos),
+      FromBVote       => FromBVote(RX_DATA_RECEIVED_Pos),
+      ToVote          => ToVote_i(RX_DATA_RECEIVED_Pos),
+      Clk_Src         => UART_Clk,
+      Clk_Dst         => Clk,
+      Rst_Src         => Reset_UART_Clk,
+      Rst_Dst         => Reset,
+      TMR_Disable_Src => tmr_disable_uart_clk,
+      TMR_Disable_Dst => TMR_Disable,
+      Pulse_Src       => rx_data_received_uart_clk,
+      Pulse_Keep_Src  => open,
+      Pulse_Ack_Src   => open,
+      Pulse_Dst       => rx_data_received_clk);
+
+    Read_RX_Data_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 1,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(READ_RX_DATA_Pos),
+      FromBVote       => FromBVote(READ_RX_DATA_Pos),
+      ToVote          => ToVote_i(READ_RX_DATA_Pos),
+      Clk_Src         => Clk,
+      Clk_Dst         => UART_Clk,
+      Rst_Src         => Reset,
+      Rst_Dst         => Reset_UART_Clk,
+      TMR_Disable_Src => TMR_Disable,
+      TMR_Disable_Dst => tmr_disable_uart_clk,
+      Pulse_Src       => Read_RX_Data,
+      Pulse_Keep_Src  => read_rx_keep,
+      Pulse_Ack_Src   => read_rx_ack_clk,
+      Pulse_Dst       => read_rx_uart_clk);
+
+    -- Create Read RX Data pulse on returning acknowledged read
+    Read_RX_Ack_DFF : process (Clk)
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset = '1' then
+          read_rx_ack_clkQ <= '0';
+        else
+          read_rx_ack_clkQ <= read_rx_ack_clk;
+        end if;
+      end if;
+    end process Read_RX_Ack_DFF;
+
+    -- Vote to handle any misalignment when synchronizing in the different TMR instances
+    read_rx_pulse_tovote_clk <= '1' when read_rx_ack_clk  = '0' and
+                                         read_rx_ack_clkQ = '1' else
+                                         '0';
+    
+    ToVote_i(READ_RX_PULSE_Pos) <= read_rx_pulse_tovote_clk;
+
+    Read_RX_Pulse_DFF : process (Clk)
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset = '1' then
+          read_rx_pulse_voted_clk <= '0';
+        else
+          read_rx_pulse_voted_clk <= vote(read_rx_pulse_tovote_clk,
+                                          FromAVote(READ_RX_PULSE_Pos),
+                                          FromBVote(READ_RX_PULSE_Pos),
+                                          tmr_disable_b, C_TMR);
+        end if;
+      end if;
+    end process Read_RX_Pulse_DFF;
+
+    Read_RX_DFF : process (UART_Clk)
+    begin
+      if UART_Clk'event and UART_Clk = '1' then
+        if Reset_UART_Clk = '1' then
+          read_rx_uart_clkQ <= '0';
+        else
+          read_rx_uart_clkQ <= read_rx_uart_clk;
+        end if;
+      end if;
+    end process Read_RX_DFF;
+    
+    RX_Data_Logic : process (Reset_UART_Clk, read_rx_uart_clkQ, rx_data_uart_clk, rx_data_voted_uart_clk)
+    begin
+      if Reset_UART_Clk = '1' then
+        rx_data_tovote_uart_clk <= (others => '0');
+      elsif read_rx_uart_clkQ = '1' then
+        rx_data_tovote_uart_clk <= rx_data_uart_clk;
+      else
+        rx_data_tovote_uart_clk <= rx_data_voted_uart_clk;
+      end if;
+    end process RX_Data_Logic;
+    
+   ToVote_i(RX_DATA_Pos'low+rx_data_tovote_uart_clk'length-1 downto RX_DATA_Pos'low) <= rx_data_tovote_uart_clk;
+
+    -- Work around spyglass bug report on null range to the left but not to the right
+    spy2_g: if C_UART_DATA_BITS < 8 generate
+    begin
+      ToVote_i(RX_DATA_Pos'high downto RX_DATA_Pos'low+rx_data_tovote_uart_clk'length)  <= (others => '0');
+    end generate spy2_g;
+    
+    RX_Data_DFF : process (UART_Clk)
+    begin
+      if UART_Clk'event and UART_Clk = '1' then
+        -- Stable in Clk region due to system events (sync of UART Status Read)
+        rx_data_voted_uart_clk <= vote(rx_data_tovote_uart_clk,
+                                       FromAVote(RX_DATA_Pos),
+                                       FromBVote(RX_DATA_Pos),
+                                       tmr_disable_b, C_TMR);
+      end if;
+    end process RX_Data_DFF;
+
+    RX_Data <= rx_data_voted_uart_clk when read_rx_pulse_voted_clk = '1' else
+               (others => '0');
+
+    Read_RX_Wait  <= read_rx_keep or read_rx_ack_clkQ;
+    Read_RX_Ready <= read_rx_pulse_voted_clk;
+
+    UART_Status_Read_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 1,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(UART_STATUS_READ_Pos),
+      FromBVote       => FromBVote(UART_STATUS_READ_Pos),
+      ToVote          => ToVote_i(UART_STATUS_READ_Pos),
+      Clk_Src         => Clk,
+      Clk_Dst         => UART_Clk,
+      Rst_Src         => Reset,
+      Rst_Dst         => Reset_UART_Clk,
+      TMR_Disable_Src => TMR_Disable,
+      TMR_Disable_Dst => tmr_disable_uart_clk,
+      Pulse_Src       => UART_Status_Read,
+      Pulse_Keep_Src  => uart_status_read_keep,
+      Pulse_Ack_Src   => uart_status_read_ack_clk,
+      Pulse_Dst       => uart_status_read_uart_clk);
+
+    -- Create Read UART Status pulse on returning acknowledged read
+    UART_Status_Read_Ack_DFF : process (Clk)
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset = '1' then
+          uart_status_read_ack_clkQ <= '0';
+        else
+          uart_status_read_ack_clkQ <= uart_status_read_ack_clk;
+        end if;
+      end if;
+    end process UART_Status_Read_Ack_DFF;
+      
+    -- Vote to handle any misalignment when synchronizing in the different TMR instances
+    uart_status_read_pulse_tovote_clk <= '1' when uart_status_read_ack_clk  = '0' and
+                                                  uart_status_read_ack_clkQ = '1' else
+                                         '0';
+
+    ToVote_i(UART_STATUS_READ_PULSE_Pos) <= uart_status_read_pulse_tovote_clk;
+    
+    UART_Status_Read_Pulse_DFF : process (Clk)
+    begin
+      if Clk'event and Clk = '1' then
+        if Reset = '1' then
+          uart_status_read_pulse_voted_clk <= '0';
+        else
+          uart_status_read_pulse_voted_clk <= vote(uart_status_read_pulse_tovote_clk,
+                                                   FromAVote(UART_STATUS_READ_PULSE_Pos),
+                                                   FromBVote(UART_STATUS_READ_PULSE_Pos),
+                                                   tmr_disable_b, C_TMR);
+        end if;
+      end if;
+    end process UART_Status_Read_Pulse_DFF;
+
+    UART_Status_Read_DFF : process (UART_Clk)
+    begin
+      if UART_Clk'event and UART_Clk = '1' then
+        if Reset_UART_Clk = '1' then
+          uart_status_read_uart_clkQ <= '0';
+        else
+          uart_status_read_uart_clkQ <= uart_status_read_uart_clk;
+        end if;
+      end if;
+    end process UART_Status_Read_DFF;
+
+    UART_Status_Logic : process (Reset_UART_Clk, uart_status_read_uart_clkQ, uart_status_uart_clk, uart_status_voted_uart_clk)
+    begin
+      if Reset_UART_Clk = '1' then
+        uart_status_tovote_uart_clk <= (others => '0');
+      elsif uart_status_read_uart_clkQ = '1' then
+        uart_status_tovote_uart_clk <= uart_status_uart_clk;
+      else
+        uart_status_tovote_uart_clk <= uart_status_voted_uart_clk;
+      end if;
+    end process UART_Status_Logic;
+
+    ToVote_i(UART_STATUS_Pos) <= uart_status_tovote_uart_clk;
+    
+    UART_Status_DFF : process (UART_Clk)
+    begin
+      if UART_Clk'event and UART_Clk = '1' then
+        -- Stable in Clk region due to system events (sync of UART Status Read)
+        uart_status_voted_uart_clk <= vote(uart_status_tovote_uart_clk,
+                                           FromAVote(UART_STATUS_Pos),
+                                           FromBVote(UART_STATUS_Pos),
+                                           tmr_disable_b, C_TMR);
+      end if;
+    end process UART_Status_DFF;
+
+    UART_Status <= uart_status_voted_uart_clk when uart_status_read_pulse_voted_clk = '1' else
+                   (others => '0');
+
+    UART_Status_Wait  <= uart_status_read_keep or uart_status_read_ack_clkQ;
+    UART_Status_Ready <= uart_status_read_pulse_voted_clk;
+    
+    UART_RX_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 0,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(UART_RX_INTERRUPT_Pos),
+      FromBVote       => FromBVote(UART_RX_INTERRUPT_Pos),
+      ToVote          => ToVote_i(UART_RX_INTERRUPT_Pos),
+      Clk_Src         => UART_Clk,
+      Clk_Dst         => Clk,
+      Rst_Src         => Reset_UART_Clk,
+      Rst_Dst         => Reset,
+      TMR_Disable_Src => tmr_disable_uart_clk,
+      TMR_Disable_Dst => TMR_Disable,
+      Pulse_Src       => uart_rx_interrupt_uart_clk,
+      Pulse_Keep_Src  => open,
+      Pulse_Ack_Src   => open,
+      Pulse_Dst       => uart_rx_interrupt_clk);
+
+    UART_TX_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 0,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(UART_TX_INTERRUPT_Pos),
+      FromBVote       => FromBVote(UART_TX_INTERRUPT_Pos),
+      ToVote          => ToVote_i(UART_TX_INTERRUPT_Pos),
+      Clk_Src         => UART_Clk,
+      Clk_Dst         => Clk,
+      Rst_Src         => Reset_UART_Clk,
+      Rst_Dst         => Reset,
+      TMR_Disable_Src => tmr_disable_uart_clk,
+      TMR_Disable_Dst => TMR_Disable,
+      Pulse_Src       => uart_tx_interrupt_uart_clk,
+      Pulse_Keep_Src  => open,
+      Pulse_Ack_Src   => open,
+      Pulse_Dst       => uart_tx_interrupt_clk);
+
+    Error_Sync: pulse_sync
+    generic map(
+      C_LEVELS          => C_UART_NUM_SYNC_FF,
+      C_TMR             => C_TMR,
+      C_LATE_ACK        => 0,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE)
+    port map(
+      FromAVote       => FromAVote(UART_ERROR_INTERRUPT_Pos),
+      FromBVote       => FromBVote(UART_ERROR_INTERRUPT_Pos),
+      ToVote          => ToVote_i(UART_ERROR_INTERRUPT_Pos),
+      Clk_Src         => UART_Clk,
+      Clk_Dst         => Clk,
+      Rst_Src         => Reset_UART_Clk,
+      Rst_Dst         => Reset,
+      TMR_Disable_Src => tmr_disable_uart_clk,
+      TMR_Disable_Dst => TMR_Disable,
+      Pulse_Src       => uart_error_interrupt_uart_clk,
+      Pulse_Keep_Src  => open,
+      Pulse_Ack_Src   => open,
+      Pulse_Dst       => uart_error_interrupt_clk);
+
+   UART_Rx_Interrupt    <= uart_rx_interrupt_clk;
+   UART_Tx_Interrupt    <= uart_tx_interrupt_clk;
+   UART_Error_Interrupt <= uart_error_interrupt_clk;
+    
+   UART_Interrupt  <= uart_rx_interrupt_clk or uart_tx_interrupt_clk or uart_error_interrupt_clk;
+
+  end generate Async_UART;
+
+  
+  TMR_Yes : if (C_TMR = 1) generate
+    ToVote <= ToVote_i;
+  end generate TMR_Yes; 
+
+  TMR_No : if (C_TMR = 0) generate
+    ToVote <= (others => '0');
+  end generate TMR_No; 
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- iomodule_core.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011-2012,2016,2018 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        iomodule_core.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:
+--              iomodule_core.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran   2007-12-18    First Version
+--   stefana 2012-03-20    Added GPI interrupt
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#" cx
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+entity Iomodule_core is
+
+  generic (
+    C_TARGET               : TARGET_FAMILY_TYPE;
+    C_FREQ                 : integer               := 100000000;
+    C_USE_CONFIG_RESET     : integer               := 0;
+    C_AVOID_PRIMITIVES     : integer               := 0;
+    C_TMR                  : integer               := 0;
+    C_USE_TMR_DISABLE      : integer               := 0;
+
+    -- UART generics
+    C_USE_UART_RX          : integer               := 0;
+    C_USE_UART_TX          : integer               := 0;
+    C_UART_BAUDRATE        : integer               := 9600;
+    C_UART_DATA_BITS       : integer range 5 to 8  := 8;
+    C_UART_USE_PARITY      : integer               := 0;
+    C_UART_ODD_PARITY      : integer               := 0;
+    C_UART_RX_INTERRUPT    : integer               := 0;
+    C_UART_TX_INTERRUPT    : integer               := 0;
+    C_UART_ERROR_INTERRUPT : integer               := 0;
+    C_UART_PROG_BAUDRATE   : integer               := 0;
+    C_UART_FREQ            : integer               := 100000000;
+    C_UART_ASYNC           : integer               := 0;
+    C_UART_NUM_SYNC_FF     : integer               := 2;
+
+    -- FIT generics
+    C_USE_FIT1             : integer               := 0;
+    C_FIT1_No_CLOCKS       : integer               := 1000;
+    C_FIT1_INTERRUPT       : integer               := 0;
+    C_USE_FIT2             : integer               := 0;
+    C_FIT2_No_CLOCKS       : integer               := 1000;
+    C_FIT2_INTERRUPT       : integer               := 0;
+    C_USE_FIT3             : integer               := 0;
+    C_FIT3_No_CLOCKS       : integer               := 1000;
+    C_FIT3_INTERRUPT       : integer               := 0;
+    C_USE_FIT4             : integer               := 0;
+    C_FIT4_No_CLOCKS       : integer               := 1000;
+    C_FIT4_INTERRUPT       : integer               := 0;
+
+    -- PIT generics
+    C_USE_PIT1       : integer               := 0;
+    C_PIT1_SIZE      : integer               := 32;
+    C_PIT1_READABLE  : integer               := 1;
+    C_PIT1_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT1_INTERRUPT : integer               := 0;
+    C_USE_PIT2       : integer               := 0;
+    C_PIT2_SIZE      : integer               := 32;
+    C_PIT2_READABLE  : integer               := 1;
+    C_PIT2_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT2_INTERRUPT : integer               := 0;
+    C_USE_PIT3       : integer               := 0;
+    C_PIT3_SIZE      : integer               := 32;
+    C_PIT3_READABLE  : integer               := 1;
+    C_PIT3_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT3_INTERRUPT : integer               := 0;
+    C_USE_PIT4       : integer               := 0;
+    C_PIT4_SIZE      : integer               := 32;
+    C_PIT4_READABLE  : integer               := 1;
+    C_PIT4_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT4_INTERRUPT : integer               := 0;
+
+    -- GPO Generics
+    C_USE_GPO1  : integer := 0;
+    C_GPO1_SIZE : integer range 1 to 32 := 32;
+    C_GPO1_INIT : std_logic_vector(31 downto 0) := (others => '0');
+    C_USE_GPO2  : integer := 0;
+    C_GPO2_SIZE : integer range 1 to 32 := 32;
+    C_GPO2_INIT : std_logic_vector(31 downto 0) := (others => '0');
+    C_USE_GPO3  : integer := 0;
+    C_GPO3_SIZE : integer range 1 to 32 := 32;
+    C_GPO3_INIT : std_logic_vector(31 downto 0) := (others => '0');
+    C_USE_GPO4  : integer := 0;
+    C_GPO4_SIZE : integer range 1 to 32 := 32;
+    C_GPO4_INIT : std_logic_vector(31 downto 0) := (others => '0');
+
+    -- GPI Generics
+    C_USE_GPI1       : integer := 0;
+    C_GPI1_SIZE      : integer range 1 to 32 := 32;
+    C_GPI1_INTERRUPT : integer               := 0;
+    C_USE_GPI2       : integer := 0;
+    C_GPI2_SIZE      : integer range 1 to 32 := 32;
+    C_GPI2_INTERRUPT : integer               := 0;
+    C_USE_GPI3       : integer := 0;
+    C_GPI3_SIZE      : integer range 1 to 32 := 32;
+    C_GPI3_INTERRUPT : integer               := 0;
+    C_USE_GPI4       : integer := 0;
+    C_GPI4_SIZE      : integer range 1 to 32 := 32;
+    C_GPI4_INTERRUPT : integer               := 0;
+
+    -- Interrupt Handler Generics
+    C_ADDR_WIDTH        : integer range 32 to 64    := 32;
+    C_INTC_USE_EXT_INTR : integer                   := 0;
+    C_INTC_INTR_SIZE    : integer range 1 to 16     := 1;
+    C_INTC_LEVEL_EDGE   : std_logic_vector(15 downto 0) := X"0000";
+    C_INTC_POSITIVE     : std_logic_vector(15 downto 0) := X"0000";
+    C_INTC_HAS_FAST     : integer range 0 to 1      := 0;
+    C_INTC_ADDR_WIDTH   : integer range 5 to 64     := 32;
+    C_INTC_BASE_VECTORS : std_logic_vector(63 downto 0) := X"0000000000000000";
+    C_INTC_ASYNC_INTR   : std_logic_vector(15 downto 0) := X"FFFF";
+    C_INTC_NUM_SYNC_FF  : integer range 0 to 7      := 2
+    );
+
+  port (
+    Config_Reset : in std_logic := '0';
+    CLK          : in std_logic;
+    Rst          : in std_logic;
+    TMR_Rst      : in std_logic;
+    TMR_Disable  : in std_logic;
+
+    -- TMR voting inbetween redundant IO Modules
+    ToVote       : out std_logic_vector(1023 downto 0);
+    FromAVote    : in  std_logic_vector(1023 downto 0);
+    FromBVote    : in  std_logic_vector(1023 downto 0);
+
+    -- UART I/O
+    UART_Clk       : in std_logic;
+    UART_Rst       : in std_logic;
+    UART_Rx        : in  std_logic;
+    UART_Tx        : out std_logic;
+    UART_Interrupt : out std_logic;
+
+    -- FIT I/O
+    FIT1_Interrupt : out std_logic;
+    FIT1_Toggle    : out std_logic;
+    FIT2_Interrupt : out std_logic;
+    FIT2_Toggle    : out std_logic;
+    FIT3_Interrupt : out std_logic;
+    FIT3_Toggle    : out std_logic;
+    FIT4_Interrupt : out std_logic;
+    FIT4_Toggle    : out std_logic;
+
+    -- PIT I/O
+    PIT1_Enable    : in  std_logic;
+    PIT1_Interrupt : out std_logic;
+    PIT1_Toggle    : out std_logic;
+    PIT2_Enable    : in  std_logic;
+    PIT2_Interrupt : out std_logic;
+    PIT2_Toggle    : out std_logic;
+    PIT3_Enable    : in  std_logic;
+    PIT3_Interrupt : out std_logic;
+    PIT3_Toggle    : out std_logic;
+    PIT4_Enable    : in  std_logic;
+    PIT4_Interrupt : out std_logic;
+    PIT4_Toggle    : out std_logic;
+
+    -- GPO IO
+    GPO1 : out std_logic_vector(C_GPO1_SIZE-1 downto 0);
+    GPO2 : out std_logic_vector(C_GPO2_SIZE-1 downto 0);
+    GPO3 : out std_logic_vector(C_GPO3_SIZE-1 downto 0);
+    GPO4 : out std_logic_vector(C_GPO4_SIZE-1 downto 0);
+
+    -- GPI IO
+    GPI1           : in  std_logic_vector(C_GPI1_SIZE-1 downto 0);
+    GPI1_Interrupt : out std_logic;
+    GPI2           : in  std_logic_vector(C_GPI2_SIZE-1 downto 0);
+    GPI2_Interrupt : out std_logic;
+    GPI3           : in  std_logic_vector(C_GPI3_SIZE-1 downto 0);
+    GPI3_Interrupt : out std_logic;
+    GPI4           : in  std_logic_vector(C_GPI4_SIZE-1 downto 0);
+    GPI4_Interrupt : out std_logic;
+
+    -- Interrupt IO
+    INTC_Interrupt         : in  std_logic_vector(C_INTC_INTR_SIZE-1 downto 0);
+    INTC_IRQ               : out std_logic;
+    INTC_Processor_Ack     : in  std_logic_vector(1 downto 0);
+    INTC_Interrupt_Address : out std_logic_vector(C_ADDR_WIDTH-1 downto 0);
+
+    -- Register access
+    PIT1_Read          : in  std_logic;
+    PIT1_Write_Preload : in  std_logic;
+    PIT1_Write_Ctrl    : in  std_logic;
+    PIT2_Read          : in  std_logic;
+    PIT2_Write_Preload : in  std_logic;
+    PIT2_Write_Ctrl    : in  std_logic;
+    PIT3_Read          : in  std_logic;
+    PIT3_Write_Preload : in  std_logic;
+    PIT3_Write_Ctrl    : in  std_logic;
+    PIT4_Read          : in  std_logic;
+    PIT4_Write_Preload : in  std_logic;
+    PIT4_Write_Ctrl    : in  std_logic;
+    GPI1_Read          : in  std_logic;
+    GPI2_Read          : in  std_logic;
+    GPI3_Read          : in  std_logic;
+    GPI4_Read          : in  std_logic;
+    UART_TX_Write      : in  std_logic;
+    UART_Baud_Write    : in  std_logic;
+    GPO1_Write         : in  std_logic;
+    GPO2_Write         : in  std_logic;
+    GPO3_Write         : in  std_logic;
+    GPO4_Write         : in  std_logic;
+    UART_Status_Read   : in  std_logic;
+    UART_Status_Wait   : out std_logic;
+    UART_Status_Ready  : out std_logic;
+    UART_Rx_Read       : in  std_logic;
+    UART_Rx_Wait       : out std_logic;
+    UART_Rx_Ready      : out std_logic;
+    INTC_WRITE_CIAR    : in  std_logic;
+    INTC_WRITE_CIER    : in  std_logic;
+    INTC_WRITE_CIMR    : in  std_logic;
+    INTC_WRITE_CIVAR   : in  std_logic;
+    INTC_WRITE_CIVEAR  : in  std_logic;
+    INTC_CIVAR_ADDR    : in  std_logic_vector(4 downto 0);
+    INTC_READ_CISR     : in  std_logic;
+    INTC_READ_CIPR     : in  std_logic;
+    Write_Data         : in  std_logic_vector(31 downto 0);
+    Read_Data          : out std_logic_vector(31 downto 0)
+    );
+
+end entity Iomodule_core;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.all;
+use iomodule_v3_1_6.iomodule_vote_pkg.all;
+
+architecture IMP of iomodule_core is
+
+  component UART is
+  generic (
+    C_TARGET             : TARGET_FAMILY_TYPE;
+    C_FREQ               : integer              := 100000000;
+    C_UART_FREQ          : integer              := 100000000;
+    C_TMR                : integer              := 0;
+    C_USE_TMR_DISABLE    : integer              := 0;
+    C_VOTE_SIZE          : integer              := 0;
+    C_USE_SRL16          : string;
+    C_UART_PROG_BAUDRATE : integer              := 0;
+    C_UART_ASYNC         : integer              := 0;
+    C_UART_NUM_SYNC_FF   : integer              := 2;
+    C_UART_BAUDRATE      : integer              := 9600;
+    C_USE_UART_RX        : integer              := 1;
+    C_USE_UART_TX        : integer              := 1;
+    C_UART_DATA_BITS     : integer range 5 to 8 := 8;
+    C_UART_USE_PARITY    : integer              := 0;
+    C_UART_ODD_PARITY    : integer              := 0);
+  port (
+    Clk                  : in std_logic;
+    UART_Clk             : in std_logic;
+    Reset                : in std_logic;
+    Config_Reset         : in std_logic;
+    Reset_UART_Clk       : in std_logic;
+
+    TMR_Disable          : in std_logic;
+    FromAVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    FromBVote            : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+    ToVote               : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+
+    TX                   : out std_logic;
+    Write_TX_Data        : in  std_logic;
+    Write_Baud           : in  std_logic;
+    Write_Data           : in  std_logic_vector(31 downto 0);
+
+    RX                   : in  std_logic;
+    Read_RX_Data         : in  std_logic;
+    Read_RX_Wait         : out std_logic;
+    Read_RX_Ready        : out std_logic;
+    RX_Data              : out std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+
+    UART_Status_Read     : in  std_logic;
+    UART_Status_Wait     : out std_logic;
+    UART_Status_Ready    : out std_logic;
+    UART_Status          : out std_logic_vector(7 downto 0);
+    UART_Interrupt       : out std_logic;
+    UART_Rx_Interrupt    : out std_logic;
+    UART_Tx_Interrupt    : out std_logic;
+    UART_Error_Interrupt : out std_logic);
+  end component UART;
+
+  component FIT_Module is
+    generic (
+      C_TARGET          : TARGET_FAMILY_TYPE;
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_USE_SRL16       : string;
+      C_USE_FIT         : integer;
+      C_NO_CLOCKS       : integer;      -- The number of clocks between each interrupt
+      C_INACCURACY      : integer);     -- The maximum inaccuracy of the number
+    port (
+      Config_Reset : in  std_logic;
+      Clk          : in  std_logic;
+      Reset        : in  boolean;
+      TMR_Disable  : in std_logic;
+      FromAVote    : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote    : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote       : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      Toggle       : out std_logic;
+      Interrupt    : out std_logic);
+  end component FIT_Module;
+
+  component PIT_Module is
+    generic (
+      C_TARGET          : TARGET_FAMILY_TYPE;
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_USE_PIT         : integer;
+      C_PIT_SIZE        : integer;
+      C_PIT_READABLE    : integer);
+    port (
+      Clk               : in  std_logic;
+      Reset             : in  boolean;
+      Config_Reset      : in  std_logic;
+      TMR_Disable       : in std_logic;
+      FromAVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote            : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      PIT_Count_En      : in  std_logic;
+      PIT_Write_Preload : in  std_logic;
+      PIT_Write_Ctrl    : in  std_logic;
+      PIT_Read          : in  std_logic;
+      Write_Data        : in  std_logic_vector(31 downto 0);
+      PIT_Data          : out std_logic_vector(C_PIT_SIZE-1 downto 0);
+      PIT_Toggle        : out std_logic;
+      PIT_Interrupt     : out std_logic);
+  end component PIT_Module;
+
+  component GPO_Module is
+    generic (
+      C_TMR             : integer := 0;
+      C_USE_TMR_DISABLE : integer := 0;
+      C_VOTE_SIZE       : integer := 0;
+      C_USE_GPO         : integer := 1;
+      C_GPO_SIZE        : integer range 1 to 32 := 32;
+      C_GPO_INIT        : std_logic_vector(31 downto 0) := (others => '0'));
+    port (
+      Clk         : in  std_logic;
+      Reset       : in  boolean;
+      GPO_Write   : in  std_logic;
+      Write_Data  : in  std_logic_vector(31 downto 0);
+      TMR_Disable : in std_logic;
+      FromAVote   : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote   : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote      : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      GPO         : out std_logic_vector(C_GPO_SIZE-1 downto 0));
+  end component GPO_Module;
+
+  component GPI_Module is
+    generic (
+      C_USE_GPI       : integer;
+      C_GPI_SIZE      : integer;
+      C_GPI_INTERRUPT : integer);
+    port (
+      Clk           : in  std_logic;
+      Reset         : in  boolean;
+      Config_Reset  : in  std_logic;
+      GPI_Read      : in  std_logic;
+      GPI           : in  std_logic_vector(C_GPI_SIZE-1 downto 0);
+      GPI_In        : out std_logic_vector(C_GPI_SIZE-1 downto 0);
+      GPI_Interrupt : out std_logic);
+  end component GPI_Module;
+
+  component intr_ctrl is
+    generic (
+      C_TARGET            : TARGET_FAMILY_TYPE;
+      C_TMR               : integer := 0;
+      C_USE_TMR_DISABLE   : integer := 0;
+      C_VOTE_SIZE         : integer := 0;
+      C_ADDR_WIDTH        : integer range 32 to 64 := 32;
+      C_INTC_ENABLED      : std_logic_vector(31 downto 0);
+      C_INTC_LEVEL_EDGE   : std_logic_vector(31 downto 0);
+      C_INTC_POSITIVE     : std_logic_vector(31 downto 0);
+      C_INTC_ASYNC_INTR   : std_logic_vector(31 downto 0);
+      C_INTC_HAS_FAST     : integer range 0 to 1;
+      C_INTC_ADDR_WIDTH   : integer range 5 to 64;
+      C_INTC_NUM_SYNC_FF  : integer range 0 to 7;
+      C_INTC_BASE_VECTORS : std_logic_vector(63 downto 0);
+      C_USE_LUTRAM        : string);
+    port (
+      Clk               : in  std_logic;
+      Reset             : in  boolean;
+      TMR_Disable       : in  std_logic;
+      FromAVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      FromBVote         : in  std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      ToVote            : out std_logic_vector(C_VOTE_SIZE-1 downto 0);
+      INTR              : in  std_logic_vector(31 downto 0);
+      INTR_ACK          : in  std_logic_vector(1 downto 0);
+      INTR_ADDR         : out std_logic_vector(C_ADDR_WIDTH-1 downto 0);
+      INTC_WRITE_CIAR   : in  std_logic;
+      INTC_WRITE_CIER   : in  std_logic;
+      INTC_WRITE_CIMR   : in  std_logic;
+      INTC_WRITE_CIVAR  : in  std_logic;
+      INTC_WRITE_CIVEAR : in  std_logic;
+      INTC_CIVAR_ADDR   : in  std_logic_vector(4 downto 0);
+      Write_Data        : in  std_logic_vector(31 downto 0);
+      INTC_READ_CISR    : in  std_logic;
+      INTC_READ_CIPR    : in  std_logic;
+      INTC_IRQ          : out std_logic;
+      INTC_CISR         : out std_logic_vector(31 downto 0);
+      INTC_CIPR         : out std_logic_vector(31 downto 0));
+  end component intr_ctrl;
+
+  --------------------------------------------------------------------------------------------------
+  -- Interrupt functions and constant calculation
+  --------------------------------------------------------------------------------------------------
+  function int2std (i : integer) return std_logic is
+  begin  -- function int2std
+    if (i = 0) then
+      return '0';
+    else
+      return '1';
+    end if;
+  end function int2std;
+
+  function INTR_IMPLEMENTED return std_logic_vector is
+    variable t : std_logic_vector(31 downto 0);
+  begin
+    t(31 downto 16) := (others => '0');
+    if (C_INTC_USE_EXT_INTR /= 0) then
+      t(C_INTC_INTR_SIZE+15 downto 16) := (others => '1');
+    end if;
+    t(15) := '0';
+    t(14) := int2std(C_GPI4_INTERRUPT);
+    t(13) := int2std(C_GPI3_INTERRUPT);
+    t(12) := int2std(C_GPI2_INTERRUPT);
+    t(11) := int2std(C_GPI1_INTERRUPT);
+    t(10) := int2std(C_FIT4_INTERRUPT);
+    t(9)  := int2std(C_FIT3_INTERRUPT);
+    t(8)  := int2std(C_FIT2_INTERRUPT);
+    t(7)  := int2std(C_FIT1_INTERRUPT);
+    t(6)  := int2std(C_PIT4_INTERRUPT);
+    t(5)  := int2std(C_PIT3_INTERRUPT);
+    t(4)  := int2std(C_PIT2_INTERRUPT);
+    t(3)  := int2std(C_PIT1_INTERRUPT);
+    t(2)  := int2std(C_UART_RX_INTERRUPT);
+    t(1)  := int2std(C_UART_TX_INTERRUPT);
+    t(0)  := int2std(C_UART_ERROR_INTERRUPT);
+    return t;
+  end function INTR_IMPLEMENTED;
+
+  constant C_INTR_IMPL : std_logic_vector(31 downto 0) := INTR_IMPLEMENTED;
+
+  -----------------------------------------------------------------------------
+  -- bool_to_string conversion for C_AVOID_PRIMITIVES
+  -----------------------------------------------------------------------------
+  function bool_to_string (b : boolean) return string is
+  begin  -- function bool_to_string
+    if (b) then
+      return "yes";
+    else
+      return "no";
+    end if;
+  end function bool_to_string;
+
+  constant C_USE_SRL16  : string := bool_to_string(((C_AVOID_PRIMITIVES = 0) or (C_AVOID_PRIMITIVES = 2)) and (C_TARGET /= RTL));
+  constant C_USE_LUTRAM : string := bool_to_string(((C_AVOID_PRIMITIVES = 0) or (C_AVOID_PRIMITIVES = 1)) and (C_TARGET /= RTL));
+
+  signal reset   : boolean;
+  --------------------------------------------------------------------------------------------------
+  -- GPI signal
+  --------------------------------------------------------------------------------------------------
+  signal gpi1_in          : std_logic_vector(C_GPI1_SIZE-1 downto 0);
+  signal gpi1_interrupt_i : std_logic;
+  signal gpi2_in          : std_logic_vector(C_GPI2_SIZE-1 downto 0);
+  signal gpi2_interrupt_i : std_logic;
+  signal gpi3_in          : std_logic_vector(C_GPI3_SIZE-1 downto 0);
+  signal gpi3_interrupt_i : std_logic;
+  signal gpi4_in          : std_logic_vector(C_GPI4_SIZE-1 downto 0);
+  signal gpi4_interrupt_i : std_logic;
+
+  --------------------------------------------------------------------------------------------------
+  -- UART signals
+  --------------------------------------------------------------------------------------------------
+  signal uart_rx_data         : std_logic_vector(C_UART_DATA_BITS-1 downto 0);
+  signal uart_status          : std_logic_vector(7 downto 0);
+  signal uart_rx_interrupt    : std_logic;
+  signal uart_tx_interrupt    : std_logic;
+  signal uart_error_interrupt : std_logic;
+
+  --------------------------------------------------------------------------------------------------
+  -- FIT signals
+  --------------------------------------------------------------------------------------------------
+  signal fit1_interrupt_i : std_logic;
+  signal fit2_interrupt_i : std_logic;
+  signal fit3_interrupt_i : std_logic;
+  signal fit4_interrupt_i : std_logic;
+
+  --------------------------------------------------------------------------------------------------
+  -- PIT signals
+  --------------------------------------------------------------------------------------------------
+  signal pit1_interrupt_i : std_logic;
+  signal pit1_count_en    : std_logic;
+  signal pit1_data        : std_logic_vector(C_PIT1_SIZE-1 downto 0);
+  signal pit2_interrupt_i : std_logic;
+  signal pit2_count_en    : std_logic;
+  signal pit2_data        : std_logic_vector(C_PIT2_SIZE-1 downto 0);
+  signal pit3_interrupt_i : std_logic;
+  signal pit3_count_en    : std_logic;
+  signal pit3_data        : std_logic_vector(C_PIT3_SIZE-1 downto 0);
+  signal pit4_interrupt_i : std_logic;
+  signal pit4_count_en    : std_logic;
+  signal pit4_data        : std_logic_vector(C_PIT4_SIZE-1 downto 0);
+
+  --------------------------------------------------------------------------------------------------
+  -- INTC signals
+  --------------------------------------------------------------------------------------------------
+  signal intr      : std_logic_vector(31 downto 0);
+  signal intc_cisr : std_logic_vector(31 downto 0);
+  signal intc_cipr : std_logic_vector(31 downto 0);
+
+
+  signal config_reset_i : std_logic;
+
+  --------------------------------------------------------------------------------------------------
+  -- TMR
+  --------------------------------------------------------------------------------------------------
+  signal ToVote_i      : std_logic_vector(VOTE_SIZE-1 downto 0);
+  signal FromAVote_i   : std_logic_vector(VOTE_SIZE-1 downto 0);
+  signal FromBVote_i   : std_logic_vector(VOTE_SIZE-1 downto 0);
+
+begin  -- architecture IMP
+
+  TMR_Yes : if (C_TMR /= 0) generate
+  begin
+    ToVote(ToVote_i'range)                     <= ToVote_i;
+    ToVote(ToVote'high downto ToVote_i'high+1) <= (others => '0');
+    FromAVote_i                                <= FromAVote(FromAVote_i'range);
+    FromBVote_i                                <= FromBVote(FromBVote_i'range);
+  end generate TMR_Yes;
+
+  TMR_No : if (C_TMR = 0) generate
+  begin
+    ToVote      <= (others => '0');
+    FromAVote_i <= (others => '0');
+    FromBVote_i <= (others => '0');
+  end generate TMR_No;
+
+  Reset <= (Rst = '1');
+
+  config_reset_i <= Config_Reset when C_USE_CONFIG_RESET /= 0 else '0';
+
+  --------------------------------------------------------------------------------------------------
+  -- UART Section
+  --------------------------------------------------------------------------------------------------
+  UART_I1 : UART
+    generic map (
+      C_TARGET             => C_TARGET,
+      C_FREQ               => C_FREQ,
+      C_UART_FREQ          => C_UART_FREQ,
+      C_TMR                => C_TMR,
+      C_USE_TMR_DISABLE    => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE          => UART_high-UART_low+1,
+      C_USE_SRL16          => C_USE_SRL16,
+      C_UART_PROG_BAUDRATE => C_UART_PROG_BAUDRATE,
+      C_UART_ASYNC         => C_UART_ASYNC,
+      C_UART_NUM_SYNC_FF   => C_UART_NUM_SYNC_FF,
+      C_UART_BAUDRATE      => C_UART_BAUDRATE,
+      C_USE_UART_RX        => C_USE_UART_RX,
+      C_USE_UART_TX        => C_USE_UART_TX,
+      C_UART_DATA_BITS     => C_UART_DATA_BITS,
+      C_UART_USE_PARITY    => C_UART_USE_PARITY,
+      C_UART_ODD_PARITY    => C_UART_ODD_PARITY)
+    port map (
+      Clk                  => Clk,
+      UART_Clk             => UART_Clk,
+      Reset                => Rst,
+      Config_Reset         => config_reset_i,
+      Reset_UART_Clk       => UART_Rst,
+        
+      TMR_Disable          => TMR_Disable,
+      FromAVote            => FromAVote_i(UART_Pos),
+      FromBVote            => FromBVote_i(UART_Pos),
+      ToVote               => ToVote_i(UART_Pos),
+
+      TX                   => UART_Tx,
+      Write_TX_Data        => UART_TX_Write,
+      Write_Baud           => UART_Baud_Write,
+      Write_Data           => Write_Data,
+
+      RX                   => UART_RX,
+      Read_RX_Data         => UART_Rx_Read,
+      Read_RX_Wait         => UART_Rx_Wait,
+      Read_RX_Ready        => UART_Rx_Ready,
+      RX_Data              => uart_rx_data,
+        
+      UART_Status_Read     => UART_Status_Read,
+      UART_Status_Wait     => UART_Status_Wait,
+      UART_Status_Ready    => UART_Status_Ready,
+      UART_Status          => uart_status,
+      UART_Interrupt       => UART_Interrupt,
+      UART_Rx_Interrupt    => uart_rx_interrupt,
+      UART_Tx_Interrupt    => uart_tx_interrupt,
+      UART_Error_Interrupt => uart_error_interrupt);
+
+  --------------------------------------------------------------------------------------------------
+  -- FIT Section
+  --------------------------------------------------------------------------------------------------
+  FIT_I1 : FIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => FIT1_Pos'high-FIT1_Pos'low+1,
+      C_USE_SRL16       => C_USE_SRL16,
+      C_USE_FIT         => C_USE_FIT1,
+      C_NO_CLOCKS       => C_FIT1_NO_CLOCKS,
+      C_INACCURACY      => 0)
+    port map (
+      Config_Reset => config_reset_i,
+      Clk          => Clk,
+      Reset        => Reset,
+      TMR_Disable  => TMR_Disable,
+      FromAVote    => FromAVote_i(FIT1_Pos),
+      FromBVote    => FromBVote_i(FIT1_Pos),
+      ToVote       => ToVote_i(FIT1_Pos),
+      Toggle       => FIT1_Toggle,
+      Interrupt    => fit1_interrupt_i);
+
+  FIT1_Interrupt <= fit1_interrupt_i;
+
+  FIT_I2 : FIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => FIT2_Pos'high-FIT2_Pos'low+1,
+      C_USE_SRL16       => C_USE_SRL16,
+      C_USE_FIT         => C_USE_FIT2,
+      C_NO_CLOCKS       => C_FIT2_NO_CLOCKS,
+      C_INACCURACY      => 0)
+    port map (
+      Config_Reset => config_reset_i,
+      Clk          => Clk,
+      Reset        => Reset,
+      TMR_Disable  => TMR_Disable,
+      FromAVote    => FromAVote_i(FIT2_Pos),
+      FromBVote    => FromBVote_i(FIT2_Pos),
+      ToVote       => ToVote_i(FIT2_Pos),
+      Toggle       => FIT2_Toggle,
+      Interrupt    => fit2_interrupt_i);
+
+  FIT2_Interrupt <= fit2_interrupt_i;
+
+  FIT_I3 : FIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => FIT3_Pos'high-FIT3_Pos'low+1,
+      C_USE_SRL16       => C_USE_SRL16,
+      C_USE_FIT         => C_USE_FIT3,
+      C_NO_CLOCKS       => C_FIT3_NO_CLOCKS,
+      C_INACCURACY      => 0)
+    port map (
+      Config_Reset => config_reset_i,
+      Clk          => Clk,
+      Reset        => Reset,
+      TMR_Disable  => TMR_Disable,
+      FromAVote    => FromAVote_i(FIT3_Pos),
+      FromBVote    => FromBVote_i(FIT3_Pos),
+      ToVote       => ToVote_i(FIT3_Pos),
+      Toggle       => FIT3_Toggle,
+      Interrupt    => fit3_interrupt_i);
+
+  FIT3_Interrupt <= fit3_interrupt_i;
+
+  FIT_I4 : FIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => FIT4_Pos'high-FIT4_Pos'low+1,
+      C_USE_SRL16       => C_USE_SRL16,
+      C_USE_FIT         => C_USE_FIT4,
+      C_NO_CLOCKS       => C_FIT4_NO_CLOCKS,
+      C_INACCURACY      => 0)
+    port map (
+      Config_Reset => config_reset_i,
+      Clk          => Clk,
+      Reset        => Reset,
+      TMR_Disable  => TMR_Disable,
+      FromAVote    => FromAVote_i(FIT4_Pos),
+      FromBVote    => FromBVote_i(FIT4_Pos),
+      ToVote       => ToVote_i(FIT4_Pos),
+      Toggle       => FIT4_Toggle,
+      Interrupt    => fit4_interrupt_i);
+
+  FIT4_Interrupt <= fit4_interrupt_i;
+
+  --------------------------------------------------------------------------------------------------
+  -- PIT Section
+  --------------------------------------------------------------------------------------------------
+
+  pit1_count_en <= '1'              when C_PIT1_PRESCALER = 0 else
+                   fit1_interrupt_i when C_PIT1_PRESCALER = 1 else
+                   fit2_interrupt_i when C_PIT1_PRESCALER = 2 else
+                   fit3_interrupt_i when C_PIT1_PRESCALER = 3 else
+                   fit4_interrupt_i when C_PIT1_PRESCALER = 4 else
+                   pit2_interrupt_i when C_PIT1_PRESCALER = 6 else
+                   pit3_interrupt_i when C_PIT1_PRESCALER = 7 else
+                   pit4_interrupt_i when C_PIT1_PRESCALER = 8 else
+                   PIT1_Enable      when C_PIT1_PRESCALER = 9 else
+                   '0';
+
+  PIT_I1 : PIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => PIT1_Pos'high-PIT1_Pos'low+1,
+      C_USE_PIT         => C_USE_PIT1,
+      C_PIT_SIZE        => C_PIT1_SIZE,
+      C_PIT_READABLE    => C_PIT1_READABLE)
+    port map (
+      Clk               => Clk,
+      Reset             => Reset,
+      Config_Reset      => config_reset_i,
+      TMR_Disable       => TMR_Disable,
+      FromAVote         => FromAVote_i(PIT1_Pos),
+      FromBVote         => FromBVote_i(PIT1_Pos),
+      ToVote            => ToVote_i(PIT1_Pos),
+      PIT_Count_En      => pit1_count_en,
+      PIT_Write_Preload => PIT1_Write_Preload,
+      PIT_Write_Ctrl    => PIT1_Write_Ctrl,
+      PIT_Read          => PIT1_Read,
+      Write_Data        => Write_Data,
+      PIT_Data          => pit1_data,
+      PIT_Toggle        => PIT1_Toggle,
+      PIT_Interrupt     => pit1_interrupt_i);
+
+  PIT1_Interrupt <= pit1_interrupt_i;
+
+  pit2_count_en <= '1'              when C_PIT2_PRESCALER = 0 else
+                   fit1_interrupt_i when C_PIT2_PRESCALER = 1 else
+                   fit2_interrupt_i when C_PIT2_PRESCALER = 2 else
+                   fit3_interrupt_i when C_PIT2_PRESCALER = 3 else
+                   fit4_interrupt_i when C_PIT2_PRESCALER = 4 else
+                   pit1_interrupt_i when C_PIT2_PRESCALER = 5 else
+                   pit3_interrupt_i when C_PIT2_PRESCALER = 7 else
+                   pit4_interrupt_i when C_PIT2_PRESCALER = 8 else
+                   PIT2_Enable      when C_PIT2_PRESCALER = 9 else
+                   '0';
+
+  PIT_I2 : PIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => PIT2_Pos'high-PIT2_Pos'low+1,
+      C_USE_PIT         => C_USE_PIT2,
+      C_PIT_SIZE        => C_PIT2_SIZE,
+      C_PIT_READABLE    => C_PIT2_READABLE)
+    port map (
+      Clk               => Clk,
+      Reset             => Reset,
+      Config_Reset      => config_reset_i,
+      TMR_Disable       => TMR_Disable,
+      FromAVote         => FromAVote_i(PIT2_Pos),
+      FromBVote         => FromBVote_i(PIT2_Pos),
+      ToVote            => ToVote_i(PIT2_Pos),
+      PIT_Count_En      => pit2_count_en,
+      PIT_Write_Preload => PIT2_Write_Preload,
+      PIT_Write_Ctrl    => PIT2_Write_Ctrl,
+      PIT_Read          => PIT2_Read,
+      Write_Data        => Write_Data,
+      PIT_Data          => pit2_data,
+      PIT_Toggle        => PIT2_Toggle,
+      PIT_Interrupt     => pit2_interrupt_i);
+
+  PIT2_Interrupt <= pit2_interrupt_i;
+
+  pit3_count_en <= '1'              when C_PIT3_PRESCALER = 0 else
+                   fit1_interrupt_i when C_PIT3_PRESCALER = 1 else
+                   fit2_interrupt_i when C_PIT3_PRESCALER = 2 else
+                   fit3_interrupt_i when C_PIT3_PRESCALER = 3 else
+                   fit4_interrupt_i when C_PIT3_PRESCALER = 4 else
+                   pit1_interrupt_i when C_PIT3_PRESCALER = 5 else
+                   pit2_interrupt_i when C_PIT3_PRESCALER = 6 else
+                   pit4_interrupt_i when C_PIT3_PRESCALER = 8 else
+                   PIT3_Enable      when C_PIT3_PRESCALER = 9 else
+                   '0';
+
+  PIT_I3 : PIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => PIT3_Pos'high-PIT3_Pos'low+1,
+      C_USE_PIT         => C_USE_PIT3,
+      C_PIT_SIZE        => C_PIT3_SIZE,
+      C_PIT_READABLE    => C_PIT3_READABLE)
+    port map (
+      Clk               => Clk,
+      Reset             => Reset,
+      Config_Reset      => config_reset_i,
+      TMR_Disable       => TMR_Disable,
+      FromAVote         => FromAVote_i(PIT3_Pos),
+      FromBVote         => FromBVote_i(PIT3_Pos),
+      ToVote            => ToVote_i(PIT3_Pos),
+      PIT_Count_En      => pit3_count_en,
+      PIT_Write_Preload => PIT3_Write_Preload,
+      PIT_Write_Ctrl    => PIT3_Write_Ctrl,
+      PIT_Read          => PIT3_Read,
+      Write_Data        => Write_Data,
+      PIT_Data          => pit3_data,
+      PIT_Toggle        => PIT3_Toggle,
+      PIT_Interrupt     => pit3_interrupt_i);
+
+  PIT3_Interrupt <= pit3_interrupt_i;
+
+  pit4_count_en <= '1'              when C_PIT4_PRESCALER = 0 else
+                   fit1_interrupt_i when C_PIT4_PRESCALER = 1 else
+                   fit2_interrupt_i when C_PIT4_PRESCALER = 2 else
+                   fit3_interrupt_i when C_PIT4_PRESCALER = 3 else
+                   fit4_interrupt_i when C_PIT4_PRESCALER = 4 else
+                   pit1_interrupt_i when C_PIT4_PRESCALER = 5 else
+                   pit2_interrupt_i when C_PIT4_PRESCALER = 6 else
+                   pit3_interrupt_i when C_PIT4_PRESCALER = 7 else
+                   PIT4_Enable      when C_PIT4_PRESCALER = 9 else
+                   '0';
+
+  PIT_I4 : PIT_Module
+    generic map (
+      C_TARGET          => C_TARGET,
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => PIT4_Pos'high-PIT4_Pos'low+1,
+      C_USE_PIT         => C_USE_PIT4,
+      C_PIT_SIZE        => C_PIT4_SIZE,
+      C_PIT_READABLE    => C_PIT4_READABLE)
+    port map (
+      Clk               => Clk,
+      Reset             => Reset,
+      Config_Reset      => config_reset_i,
+      TMR_Disable       => TMR_Disable,
+      FromAVote         => FromAVote_i(PIT4_Pos),
+      FromBVote         => FromBVote_i(PIT4_Pos),
+      ToVote            => ToVote_i(PIT4_Pos),
+      PIT_Count_En      => pit4_count_en,
+      PIT_Write_Preload => PIT4_Write_Preload,
+      PIT_Write_Ctrl    => PIT4_Write_Ctrl,
+      PIT_Read          => PIT4_Read,
+      Write_Data        => Write_Data,
+      PIT_Data          => pit4_data,
+      PIT_Toggle        => PIT4_Toggle,
+      PIT_Interrupt     => pit4_interrupt_i);
+
+  PIT4_Interrupt <= pit4_interrupt_i;
+
+  GPO_I1 : GPO_Module
+    generic map (
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => GPO1_Pos'high-GPO1_Pos'low+1,
+      C_USE_GPO         => C_USE_GPO1,
+      C_GPO_SIZE        => C_GPO1_SIZE,
+      C_GPO_INIT        => C_GPO1_INIT)
+    port map (
+      Clk         => Clk,
+      Reset       => Reset,
+      GPO_Write   => GPO1_Write,
+      Write_Data  => Write_Data,
+      TMR_Disable => TMR_Disable,
+      FromAVote   => FromAVote_i(GPO1_Pos),
+      FromBVote   => FromBVote_i(GPO1_Pos),
+      ToVote      => ToVote_i(GPO1_Pos),
+      GPO         => GPO1);
+
+  GPO_I2 : GPO_Module
+    generic map (
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => GPO2_Pos'high-GPO2_Pos'low+1,
+      C_USE_GPO         => C_USE_GPO2,
+      C_GPO_SIZE        => C_GPO2_SIZE,
+      C_GPO_INIT        => C_GPO2_INIT)
+    port map (
+      Clk         => Clk,
+      Reset       => Reset,
+      GPO_Write   => GPO2_Write,
+      Write_Data  => Write_Data,
+      TMR_Disable => TMR_Disable,
+      FromAVote   => FromAVote_i(GPO2_Pos),
+      FromBVote   => FromBVote_i(GPO2_Pos),
+      ToVote      => ToVote_i(GPO2_Pos),
+      GPO         => GPO2);
+
+  GPO_I3 : GPO_Module
+    generic map (
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => GPO3_Pos'high-GPO3_Pos'low+1,
+      C_USE_GPO         => C_USE_GPO3,
+      C_GPO_SIZE        => C_GPO3_SIZE,
+      C_GPO_INIT        => C_GPO3_INIT)
+    port map (
+      Clk         => Clk,
+      Reset       => Reset,
+      GPO_Write   => GPO3_Write,
+      Write_Data  => Write_Data,
+      TMR_Disable => TMR_Disable,
+      FromAVote   => FromAVote_i(GPO3_Pos),
+      FromBVote   => FromBVote_i(GPO3_Pos),
+      ToVote      => ToVote_i(GPO3_Pos),
+      GPO         => GPO3);
+
+  GPO_I4 : GPO_Module
+    generic map (
+      C_TMR             => C_TMR,
+      C_USE_TMR_DISABLE => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE       => GPO4_Pos'high-GPO4_Pos'low+1,
+      C_USE_GPO         => C_USE_GPO4,
+      C_GPO_SIZE        => C_GPO4_SIZE,
+      C_GPO_INIT        => C_GPO4_INIT)
+    port map (
+      Clk         => Clk,
+      Reset       => Reset,
+      GPO_Write   => GPO4_Write,
+      Write_Data  => Write_Data,
+      TMR_Disable => TMR_Disable,
+      FromAVote   => FromAVote_i(GPO4_Pos),
+      FromBVote   => FromBVote_i(GPO4_Pos),
+      ToVote      => ToVote_i(GPO4_Pos),
+      GPO         => GPO4);
+
+  --------------------------------------------------------------------------------------------------
+  -- GPI Section
+  --------------------------------------------------------------------------------------------------
+  GPI_I1 : GPI_Module
+    generic map (
+      C_USE_GPI       => C_USE_GPI1,
+      C_GPI_SIZE      => C_GPI1_SIZE,
+      C_GPI_INTERRUPT => C_GPI1_INTERRUPT)
+    port map (
+      Clk           => Clk,
+      Reset         => Reset,
+      Config_Reset  => config_reset_i,
+      GPI_Read      => GPI1_Read,
+      GPI           => GPI1,
+      gpi_in        => gpi1_in,
+      GPI_Interrupt => gpi1_interrupt_i);
+
+  GPI1_Interrupt <= gpi1_interrupt_i;
+
+  GPI_I2 : GPI_Module
+    generic map (
+      C_USE_GPI       => C_USE_GPI2,
+      C_GPI_SIZE      => C_GPI2_SIZE,
+      C_GPI_INTERRUPT => C_GPI2_INTERRUPT)
+    port map (
+      Clk           => Clk,
+      Reset         => Reset,
+      Config_Reset  => config_reset_i,
+      GPI_Read      => GPI2_Read,
+      GPI           => GPI2,
+      gpi_in        => gpi2_in,
+      GPI_Interrupt => gpi2_interrupt_i);
+
+  GPI2_Interrupt <= gpi2_interrupt_i;
+
+  GPI_I3 : GPI_Module
+    generic map (
+      C_USE_GPI       => C_USE_GPI3,
+      C_GPI_SIZE      => C_GPI3_SIZE,
+      C_GPI_INTERRUPT => C_GPI3_INTERRUPT)
+    port map (
+      Clk           => Clk,
+      Reset         => Reset,
+      Config_Reset  => config_reset_i,
+      GPI_Read      => GPI3_Read,
+      GPI           => GPI3,
+      gpi_in        => gpi3_in,
+      GPI_Interrupt => gpi3_interrupt_i);
+
+  GPI3_Interrupt <= gpi3_interrupt_i;
+
+  GPI_I4 : GPI_Module
+    generic map (
+      C_USE_GPI       => C_USE_GPI4,
+      C_GPI_SIZE      => C_GPI4_SIZE,
+      C_GPI_INTERRUPT => C_GPI4_INTERRUPT)
+    port map (
+      Clk           => Clk,
+      Reset         => Reset,
+      Config_Reset  => config_reset_i,
+      GPI_Read      => GPI4_Read,
+      GPI           => GPI4,
+      gpi_in        => gpi4_in,
+      GPI_Interrupt => gpi4_interrupt_i);
+
+  GPI4_Interrupt <= gpi4_interrupt_i;
+
+  --------------------------------------------------------------------------------------------------
+  -- Interrupt Handler section
+  --------------------------------------------------------------------------------------------------
+  Intr_Assign : if C_INTC_INTR_SIZE < 16 generate
+  begin
+    intr(31 downto C_INTC_INTR_SIZE+16) <= (others => '0');
+  end generate Intr_Assign;
+
+  intr(C_INTC_INTR_SIZE+15 downto 16) <= INTC_Interrupt;
+  intr(15)                            <= '0';
+  intr(14)                            <= gpi4_interrupt_i;
+  intr(13)                            <= gpi3_interrupt_i;
+  intr(12)                            <= gpi2_interrupt_i;
+  intr(11)                            <= gpi1_interrupt_i;
+  intr(10)                            <= fit4_interrupt_i;
+  intr(9)                             <= fit3_interrupt_i;
+  intr(8)                             <= fit2_interrupt_i;
+  intr(7)                             <= fit1_interrupt_i;
+  intr(6)                             <= pit4_interrupt_i;
+  intr(5)                             <= pit3_interrupt_i;
+  intr(4)                             <= pit2_interrupt_i;
+  intr(3)                             <= pit1_interrupt_i;
+  intr(2)                             <= uart_rx_interrupt;
+  intr(1)                             <= uart_tx_interrupt;
+  intr(0)                             <= uart_error_interrupt;
+
+  intr_ctrl_I1 : intr_ctrl
+    generic map (
+      C_TARGET            => C_TARGET,
+      C_TMR               => C_TMR,
+      C_USE_TMR_DISABLE   => C_USE_TMR_DISABLE,
+      C_VOTE_SIZE         => IRQ_Pos'high-IRQ_Pos'low+1,
+      C_ADDR_WIDTH        => C_ADDR_WIDTH,
+      C_INTC_LEVEL_EDGE   => C_INTC_LEVEL_EDGE & X"FFFF",
+      C_INTC_POSITIVE     => C_INTC_POSITIVE & X"FFFF",
+      C_INTC_ASYNC_INTR   => C_INTC_ASYNC_INTR & X"0000",
+      C_INTC_ENABLED      => C_INTR_IMPL,
+      C_INTC_HAS_FAST     => C_INTC_HAS_FAST,
+      C_INTC_ADDR_WIDTH   => C_INTC_ADDR_WIDTH,
+      C_INTC_NUM_SYNC_FF  => C_INTC_NUM_SYNC_FF,
+      C_INTC_BASE_VECTORS => C_INTC_BASE_VECTORS,
+      C_USE_LUTRAM        => C_USE_LUTRAM)
+    port map (
+      Clk               => Clk,
+      Reset             => Reset,
+      TMR_Disable       => TMR_Disable,
+      FromAVote         => FromAVote_i(IRQ_Pos),
+      FromBVote         => FromBVote_i(IRQ_Pos),
+      ToVote            => ToVote_i(IRQ_Pos),
+      INTR              => intr,
+      INTR_ACK          => INTC_Processor_Ack,
+      INTR_ADDR         => INTC_Interrupt_Address,
+      INTC_WRITE_CIAR   => INTC_WRITE_CIAR,
+      INTC_WRITE_CIER   => INTC_WRITE_CIER,
+      INTC_WRITE_CIMR   => INTC_WRITE_CIMR,
+      INTC_WRITE_CIVAR  => INTC_WRITE_CIVAR,
+      INTC_WRITE_CIVEAR => INTC_WRITE_CIVEAR,
+      INTC_CIVAR_ADDR   => INTC_CIVAR_ADDR,
+      Write_Data        => Write_Data,
+      INTC_READ_CISR    => INTC_READ_CISR,
+      INTC_READ_CIPR    => INTC_READ_CIPR,
+      INTC_IRQ          => INTC_IRQ,
+      INTC_CISR         => intc_cisr,
+      INTC_CIPR         => intc_cipr);
+
+  --------------------------------------------------------------------------------------------------
+  -- Read MUX section
+  --------------------------------------------------------------------------------------------------
+  Simple_OR_Mux : process (gpi1_in, gpi2_in, gpi3_in, gpi4_in, intc_cipr, intc_cisr, pit1_data,
+                           pit2_data, pit3_data, pit4_data, uart_rx_data, uart_status) is
+    variable u1  : std_logic_vector(31 downto 0);
+    variable u2  : std_logic_vector(31 downto 0);
+    variable gi1 : std_logic_vector(31 downto 0);
+    variable gi2 : std_logic_vector(31 downto 0);
+    variable gi3 : std_logic_vector(31 downto 0);
+    variable gi4 : std_logic_vector(31 downto 0);
+    variable pi1 : std_logic_vector(31 downto 0);
+    variable pi2 : std_logic_vector(31 downto 0);
+    variable pi3 : std_logic_vector(31 downto 0);
+    variable pi4 : std_logic_vector(31 downto 0);
+  begin  -- process Simple_OR_Mux
+    u1  := (others => '0');
+    u2  := (others => '0');
+    gi1 := (others => '0');
+    gi2 := (others => '0');
+    gi3 := (others => '0');
+    gi4 := (others => '0');
+    pi1 := (others => '0');
+    pi2 := (others => '0');
+    pi3 := (others => '0');
+    pi4 := (others => '0');
+
+    if (C_USE_UART_RX /= 0) then
+      u1(uart_rx_data'range) := uart_rx_data;
+    end if;
+
+    if ((C_USE_UART_TX /= 0) or (C_USE_UART_RX /= 0)) then
+      u2(uart_status'range) := uart_status;
+    end if;
+
+    if (C_USE_GPI1 /= 0) then
+      gi1(gpi1_in'range) := gpi1_in;
+    end if;
+
+    if (C_USE_GPI2 /= 0) then
+      gi2(gpi2_in'range) := gpi2_in;
+    end if;
+
+    if (C_USE_GPI3 /= 0) then
+      gi3(gpi3_in'range) := gpi3_in;
+    end if;
+
+    if (C_USE_GPI4 /= 0) then
+      gi4(gpi4_in'range) := gpi4_in;
+    end if;
+
+    if (C_USE_PIT1 /= 0) then
+      pi1(pit1_data'range) := pit1_data;
+    end if;
+
+    if (C_USE_PIT2 /= 0) then
+      pi2(pit2_data'range) := pit2_data;
+    end if;
+
+    if (C_USE_PIT3 /= 0) then
+      pi3(pit3_data'range) := pit3_data;
+    end if;
+
+    if (C_USE_PIT4 /= 0) then
+      pi4(pit4_data'range) := pit4_data;
+    end if;
+
+    Read_Data <= u1 or u2 or gi1 or gi2 or gi3 or gi4 or pi1 or pi2 or pi3 or pi4 or intc_cisr or intc_cipr;
+
+  end process Simple_OR_Mux;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- pselect_mask.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011,2015 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        pselect_mask.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              pselect_mask.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity pselect_mask is
+
+  generic (
+    C_AW   : integer                   := 32;
+    C_BAR  : std_logic_vector(0 to 63) := X"0000000000020000";
+    C_MASK : std_logic_vector(0 to 63) := X"000000000007C000"
+    );
+  port (
+    A     : in  std_logic_vector(0 to C_AW-1);
+    Valid : in  std_logic;
+    CS    : out std_logic
+    );
+
+end entity pselect_mask;
+
+architecture imp of pselect_mask is
+
+  function Nr_Of_Ones (S : std_logic_vector) return natural is
+    variable tmp : natural := 0;
+  begin  -- function Nr_Of_Ones
+    for I in S'range loop
+      if (S(I) = '1') then
+        tmp := tmp + 1;
+      end if;
+    end loop;  -- I
+    return tmp;
+  end function Nr_Of_Ones;
+
+  function fix_AB (B : boolean; I : integer) return integer is
+  begin  -- function fix_AB
+    if (not B) then
+      return I + 1;
+    else
+      return I;
+    end if;
+  end function fix_AB;
+
+  constant Nr      : integer := Nr_Of_Ones(C_MASK(64 - C_AW to 63));
+  constant Use_CIN : boolean := ((Nr mod 4) = 0);
+  constant AB      : integer := fix_AB(Use_CIN, Nr);
+  
+  signal A_Bus : std_logic_vector(0 to AB);
+  signal BAR   : std_logic_vector(0 to AB);
+
+-------------------------------------------------------------------------------
+-- Begin architecture section
+-------------------------------------------------------------------------------
+begin  -- VHDL_RTL
+
+  Make_Busses : process (A,Valid) is
+    variable tmp : natural;
+  begin  -- process Make_Busses
+    tmp   := 0;
+    A_Bus <= (others => '0');
+    BAR   <= (others => '0');
+    for I in 0 to C_AW - 1 loop
+      if (C_MASK(64 - C_AW + I) = '1') then
+        A_Bus(tmp) <= A(I);
+        BAR(tmp)   <= C_BAR(64 - C_AW + I);
+        tmp        := tmp + 1;
+      end if;
+    end loop;  -- I
+    if (not Use_CIN) then
+      BAR(tmp) <= '1';
+      A_Bus(tmp) <= Valid;
+    end if;
+  end process Make_Busses;
+
+  CS <= Valid when A_Bus=BAR else '0';
+
+end imp;
+
+
+-------------------------------------------------------------------------------
+-- iomodule.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2011-2015,2018 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        iomodule.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:   
+--              iomodule.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+--
+-- History:
+--   goran   2008-01-08    First Version
+--   stefana 2012-03-20    Added GPI interrupt
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_core;
+use iomodule_v3_1_6.pselect_mask;
+
+entity iomodule is
+  generic (
+    C_FAMILY                   : string                    := "Virtex7";
+    C_FREQ                     : integer                   := 100000000;
+    C_INSTANCE                 : string                    := "iomodule";
+    C_USE_CONFIG_RESET         : integer                   := 0;
+    C_AVOID_PRIMITIVES         : integer                   := 0;
+    C_TMR                      : integer                   := 0;
+    C_USE_TMR_DISABLE          : integer                   := 0;
+
+    -- Local Memory Bus generics
+    C_HIGHADDR                 : std_logic_vector(0 to 63) := X"0000000000000000";
+    C_BASEADDR                 : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_MASK                     : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_IO_HIGHADDR              : std_logic_vector(0 to 63) := X"0000000000000000";
+    C_IO_BASEADDR              : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_IO_MASK                  : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_LMB_AWIDTH               : integer                   := 32;
+    C_LMB_DWIDTH               : integer                   := 32;
+    C_LMB_PROTOCOL             : integer                   := 0;
+
+    -- IO Bus
+    C_USE_IO_BUS           : integer               := 0;
+    
+    -- UART generics
+    C_USE_UART_RX          : integer               := 0;
+    C_USE_UART_TX          : integer               := 0;
+    C_UART_BAUDRATE        : integer               := 9600;
+    C_UART_DATA_BITS       : integer range 5 to 8  := 8;
+    C_UART_USE_PARITY      : integer               := 0;
+    C_UART_ODD_PARITY      : integer               := 0;
+    C_UART_RX_INTERRUPT    : integer               := 0;
+    C_UART_TX_INTERRUPT    : integer               := 0;
+    C_UART_ERROR_INTERRUPT : integer               := 0;
+    C_UART_PROG_BAUDRATE   : integer               := 0;
+    C_UART_FREQ            : integer               := 100000000;
+    C_UART_ASYNC           : integer               := 0;
+    C_UART_NUM_SYNC_FF     : integer               := 2;
+    
+    -- FIT generics
+    C_USE_FIT1        : integer               := 0;
+    C_FIT1_No_CLOCKS  : integer               := 6216;
+    C_FIT1_INTERRUPT  : integer               := 0;
+    C_USE_FIT2        : integer               := 0;
+    C_FIT2_No_CLOCKS  : integer               := 6216;
+    C_FIT2_INTERRUPT  : integer               := 0;
+    C_USE_FIT3        : integer               := 0;
+    C_FIT3_No_CLOCKS  : integer               := 6216;
+    C_FIT3_INTERRUPT  : integer               := 0;
+    C_USE_FIT4        : integer               := 0;
+    C_FIT4_No_CLOCKS  : integer               := 6216;
+    C_FIT4_INTERRUPT  : integer               := 0;
+
+    -- PIT generics
+    C_USE_PIT1       : integer               := 0;
+    C_PIT1_SIZE      : integer range 1 to 32 := 32;
+    C_PIT1_READABLE  : integer               := 1;
+    C_PIT1_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT1_INTERRUPT : integer               := 0;
+    C_USE_PIT2       : integer               := 0;
+    C_PIT2_SIZE      : integer range 1 to 32 := 32;
+    C_PIT2_READABLE  : integer               := 1;
+    C_PIT2_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT2_INTERRUPT : integer               := 0;
+    C_USE_PIT3       : integer               := 0;
+    C_PIT3_SIZE      : integer range 1 to 32 := 32;
+    C_PIT3_READABLE  : integer               := 1;
+    C_PIT3_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT3_INTERRUPT : integer               := 0;
+    C_USE_PIT4       : integer               := 0;
+    C_PIT4_SIZE      : integer range 1 to 32 := 32;
+    C_PIT4_READABLE  : integer               := 1;
+    C_PIT4_PRESCALER : integer range 0 to 9  := 0;
+    C_PIT4_INTERRUPT : integer               := 0;
+
+    -- GPO Generics
+    C_USE_GPO1  : integer := 0;
+    C_GPO1_SIZE : integer range 1 to 32 := 32;
+    C_GPO1_INIT : std_logic_vector(31 downto 0) := (others => '0');
+    C_USE_GPO2  : integer := 0;
+    C_GPO2_SIZE : integer range 1 to 32 := 32;
+    C_GPO2_INIT : std_logic_vector(31 downto 0) := (others => '0');
+    C_USE_GPO3  : integer := 0;
+    C_GPO3_SIZE : integer range 1 to 32 := 32;
+    C_GPO3_INIT : std_logic_vector(31 downto 0) := (others => '0');
+    C_USE_GPO4  : integer := 0;
+    C_GPO4_SIZE : integer range 1 to 32 := 32;
+    C_GPO4_INIT : std_logic_vector(31 downto 0) := (others => '0');
+
+    -- GPI Generics
+    C_USE_GPI1       : integer := 0;
+    C_GPI1_SIZE      : integer range 1 to 32 := 32;
+    C_GPI1_INTERRUPT : integer               := 0;
+    C_USE_GPI2       : integer := 0;
+    C_GPI2_SIZE      : integer range 1 to 32 := 32;
+    C_GPI2_INTERRUPT : integer               := 0;
+    C_USE_GPI3       : integer := 0;
+    C_GPI3_SIZE      : integer range 1 to 32 := 32;
+    C_GPI3_INTERRUPT : integer               := 0;
+    C_USE_GPI4       : integer := 0;
+    C_GPI4_SIZE      : integer range 1 to 32 := 32;
+    C_GPI4_INTERRUPT : integer               := 0;
+
+    -- Interrupt Handler Generics
+    C_INTC_USE_EXT_INTR : integer                       := 0;
+    C_INTC_INTR_SIZE    : integer range 1 to 16         := 1;
+    C_INTC_LEVEL_EDGE   : std_logic_vector(15 downto 0) := X"0000";
+    C_INTC_POSITIVE     : std_logic_vector(15 downto 0) := X"FFFF";
+    C_INTC_HAS_FAST     : integer range 0 to 1          := 0;
+    C_INTC_ADDR_WIDTH   : integer range 5 to 64         := 32;
+    C_INTC_BASE_VECTORS : std_logic_vector(63 downto 0) := X"0000000000000000";
+    C_INTC_ASYNC_INTR   : std_logic_vector(15 downto 0) := X"FFFF";
+    C_INTC_NUM_SYNC_FF  : integer range 0 to 7          := 2
+    );
+  port (
+    Clk          : in std_logic;
+    Rst          : in std_logic;
+    Config_Reset : in std_logic := '0';
+    TMR_Rst      : in std_logic;
+    TMR_Disable  : in std_logic;
+    
+    -- TMR voting inbetween redundant IO Modules
+    ToVote       : out std_logic_vector(1023 downto 0);
+    FromAVote    : in  std_logic_vector(1023 downto 0);
+    FromBVote    : in  std_logic_vector(1023 downto 0);
+
+    -- IO Interface
+    IO_Addr_Strobe  : out std_logic;
+    IO_Read_Strobe  : out std_logic;
+    IO_Write_Strobe : out std_logic;
+    IO_Address      : out std_logic_vector(C_LMB_AWIDTH-1 downto 0);
+    IO_Byte_Enable  : out std_logic_vector((C_LMB_DWIDTH/8 - 1) downto 0);
+    IO_Write_Data   : out std_logic_vector(C_LMB_DWIDTH-1 downto 0);
+    IO_Read_Data    : in  std_logic_vector(C_LMB_DWIDTH-1 downto 0);
+    IO_Ready        : in  std_logic;
+
+    -- UART I/O
+    UART_Clk       : in std_logic;
+    UART_Rst       : in std_logic;
+    UART_Rx        : in  std_logic;
+    UART_Tx        : out std_logic;
+    UART_Interrupt : out std_logic;
+
+    -- FIT I/O
+    FIT1_Interrupt : out std_logic;
+    FIT1_Toggle    : out std_logic;
+    FIT2_Interrupt : out std_logic;
+    FIT2_Toggle    : out std_logic;
+    FIT3_Interrupt : out std_logic;
+    FIT3_Toggle    : out std_logic;
+    FIT4_Interrupt : out std_logic;
+    FIT4_Toggle    : out std_logic;
+
+    -- PIT I/O
+    PIT1_Enable    : in  std_logic;
+    PIT1_Interrupt : out std_logic;
+    PIT1_Toggle    : out std_logic;
+    PIT2_Enable    : in  std_logic;
+    PIT2_Interrupt : out std_logic;
+    PIT2_Toggle    : out std_logic;
+    PIT3_Enable    : in  std_logic;
+    PIT3_Interrupt : out std_logic;
+    PIT3_Toggle    : out std_logic;
+    PIT4_Enable    : in  std_logic;
+    PIT4_Interrupt : out std_logic;
+    PIT4_Toggle    : out std_logic;
+
+    -- GPO IO
+    GPO1 : out std_logic_vector(C_GPO1_SIZE-1 downto 0);
+    GPO2 : out std_logic_vector(C_GPO2_SIZE-1 downto 0);
+    GPO3 : out std_logic_vector(C_GPO3_SIZE-1 downto 0);
+    GPO4 : out std_logic_vector(C_GPO4_SIZE-1 downto 0);
+
+    -- GPI IO
+    GPI1           : in  std_logic_vector(C_GPI1_SIZE-1 downto 0);
+    GPI1_Interrupt : out std_logic;
+    GPI2           : in  std_logic_vector(C_GPI2_SIZE-1 downto 0);
+    GPI2_Interrupt : out std_logic;
+    GPI3           : in  std_logic_vector(C_GPI3_SIZE-1 downto 0);
+    GPI3_Interrupt : out std_logic;
+    GPI4           : in  std_logic_vector(C_GPI4_SIZE-1 downto 0);
+    GPI4_Interrupt : out std_logic;
+
+    -- Interrupt IO
+    INTC_Interrupt         : in  std_logic_vector(C_INTC_INTR_SIZE-1 downto 0);
+    INTC_IRQ               : out std_logic;
+    INTC_Processor_Ack     : in  std_logic_vector(1 downto 0);
+    INTC_Interrupt_Address : out std_logic_vector(((C_INTC_ADDR_WIDTH+31) / 64) * (C_INTC_ADDR_WIDTH-32) + 31 downto 0);
+    INTC_IRQ_OUT           : out std_logic;
+
+    -- Local Memory Bus, LMB
+    LMB_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB_AddrStrobe  : in  std_logic;
+    LMB_ReadStrobe  : in  std_logic;
+    LMB_WriteStrobe : in  std_logic;
+    LMB_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl_Ready        : out std_logic;
+    Sl_Wait         : out std_logic;
+    Sl_UE           : out std_logic;
+    Sl_CE           : out std_logic
+    );
+
+end entity iomodule;
+
+library iomodule_v3_1_6;
+use iomodule_v3_1_6.iomodule_funcs.all;
+
+architecture IMP of iomodule is
+
+  component iomodule_core is
+    generic (
+      C_TARGET           : TARGET_FAMILY_TYPE;
+      C_FREQ             : integer := 100000000;
+      C_USE_CONFIG_RESET : integer := 0;
+      C_AVOID_PRIMITIVES : integer := 0;
+      C_TMR              : integer := 0;
+      C_USE_TMR_DISABLE  : integer := 0;
+
+      -- UART generics
+      C_USE_UART_RX          : integer;
+      C_USE_UART_TX          : integer;
+      C_UART_BAUDRATE        : integer;
+      C_UART_DATA_BITS       : integer range 5 to 8;
+      C_UART_USE_PARITY      : integer;
+      C_UART_ODD_PARITY      : integer;
+      C_UART_RX_INTERRUPT    : integer;
+      C_UART_TX_INTERRUPT    : integer;
+      C_UART_ERROR_INTERRUPT : integer;
+      C_UART_PROG_BAUDRATE   : integer;
+      C_UART_FREQ            : integer;
+      C_UART_ASYNC           : integer;
+      C_UART_NUM_SYNC_FF     : integer;
+
+      -- FIT generics
+      C_USE_FIT1       : integer;
+      C_FIT1_No_CLOCKS : integer;
+      C_FIT1_INTERRUPT : integer;
+      C_USE_FIT2       : integer;
+      C_FIT2_No_CLOCKS : integer;
+      C_FIT2_INTERRUPT : integer;
+      C_USE_FIT3       : integer;
+      C_FIT3_No_CLOCKS : integer;
+      C_FIT3_INTERRUPT : integer;
+      C_USE_FIT4       : integer;
+      C_FIT4_No_CLOCKS : integer;
+      C_FIT4_INTERRUPT : integer;
+
+      -- PIT generics
+      C_USE_PIT1       : integer;
+      C_PIT1_SIZE      : integer;
+      C_PIT1_READABLE  : integer;
+      C_PIT1_PRESCALER : integer range 0 to 9;
+      C_PIT1_INTERRUPT : integer;
+      C_USE_PIT2       : integer;
+      C_PIT2_SIZE      : integer;
+      C_PIT2_READABLE  : integer;
+      C_PIT2_PRESCALER : integer range 0 to 9;
+      C_PIT2_INTERRUPT : integer;
+      C_USE_PIT3       : integer;
+      C_PIT3_SIZE      : integer;
+      C_PIT3_READABLE  : integer;
+      C_PIT3_PRESCALER : integer range 0 to 9;
+      C_PIT3_INTERRUPT : integer;
+      C_USE_PIT4       : integer;
+      C_PIT4_SIZE      : integer;
+      C_PIT4_READABLE  : integer;
+      C_PIT4_PRESCALER : integer range 0 to 9;
+      C_PIT4_INTERRUPT : integer;
+
+      -- GPO Generics
+      C_USE_GPO1  : integer                       := 0;
+      C_GPO1_SIZE : integer range 1 to 32         := 32;
+      C_GPO1_INIT : std_logic_vector(31 downto 0) := (others => '0');
+      C_USE_GPO2  : integer                       := 0;
+      C_GPO2_SIZE : integer range 1 to 32         := 32;
+      C_GPO2_INIT : std_logic_vector(31 downto 0) := (others => '0');
+      C_USE_GPO3  : integer                       := 0;
+      C_GPO3_SIZE : integer range 1 to 32         := 32;
+      C_GPO3_INIT : std_logic_vector(31 downto 0) := (others => '0');
+      C_USE_GPO4  : integer                       := 0;
+      C_GPO4_SIZE : integer range 1 to 32         := 32;
+      C_GPO4_INIT : std_logic_vector(31 downto 0) := (others => '0');
+
+      -- GPI Generics
+      C_USE_GPI1       : integer               := 0;
+      C_GPI1_SIZE      : integer range 1 to 32 := 32;
+      C_GPI1_INTERRUPT : integer               := 0;
+      C_USE_GPI2       : integer               := 0;
+      C_GPI2_SIZE      : integer range 1 to 32 := 32;
+      C_GPI2_INTERRUPT : integer               := 0;
+      C_USE_GPI3       : integer               := 0;
+      C_GPI3_SIZE      : integer range 1 to 32 := 32;
+      C_GPI3_INTERRUPT : integer               := 0;
+      C_USE_GPI4       : integer               := 0;
+      C_GPI4_SIZE      : integer range 1 to 32 := 32;
+      C_GPI4_INTERRUPT : integer               := 0;
+
+      -- Interrupt Handler Generics
+      C_ADDR_WIDTH        : integer range 32 to 64;
+      C_INTC_USE_EXT_INTR : integer;
+      C_INTC_INTR_SIZE    : integer range 1 to 16;
+      C_INTC_LEVEL_EDGE   : std_logic_vector(15 downto 0);
+      C_INTC_POSITIVE     : std_logic_vector(15 downto 0);
+      C_INTC_HAS_FAST     : integer range 0 to 1;
+      C_INTC_ADDR_WIDTH   : integer range 5 to 64;
+      C_INTC_BASE_VECTORS : std_logic_vector(63 downto 0);
+      C_INTC_ASYNC_INTR   : std_logic_vector(15 downto 0) := X"FFFF";
+      C_INTC_NUM_SYNC_FF  : integer range 0 to 7);
+    port (
+      Config_Reset : in std_logic := '0';
+      CLK          : in std_logic;
+      Rst          : in std_logic;
+      TMR_Rst      : in std_logic;
+      TMR_Disable  : in std_logic;
+
+      -- TMR voting inbetween redundant IO Modules
+      ToVote       : out std_logic_vector(1023 downto 0);
+      FromAVote    : in  std_logic_vector(1023 downto 0);
+      FromBVote    : in  std_logic_vector(1023 downto 0);
+
+      -- UART I/O
+      UART_Clk       : in std_logic;
+      UART_Rst       : in std_logic;
+      UART_Rx        : in  std_logic;
+      UART_Tx        : out std_logic;
+      UART_Interrupt : out std_logic;
+
+      -- FIT I/O
+      FIT1_Interrupt : out std_logic;
+      FIT1_Toggle    : out std_logic;
+      FIT2_Interrupt : out std_logic;
+      FIT2_Toggle    : out std_logic;
+      FIT3_Interrupt : out std_logic;
+      FIT3_Toggle    : out std_logic;
+      FIT4_Interrupt : out std_logic;
+      FIT4_Toggle    : out std_logic;
+
+      -- PIT I/O
+      PIT1_Enable    : in  std_logic;
+      PIT1_Interrupt : out std_logic;
+      PIT1_Toggle    : out std_logic;
+      PIT2_Enable    : in  std_logic;
+      PIT2_Interrupt : out std_logic;
+      PIT2_Toggle    : out std_logic;
+      PIT3_Enable    : in  std_logic;
+      PIT3_Interrupt : out std_logic;
+      PIT3_Toggle    : out std_logic;
+      PIT4_Enable    : in  std_logic;
+      PIT4_Interrupt : out std_logic;
+      PIT4_Toggle    : out std_logic;
+
+      -- GPO IO
+      GPO1 : out std_logic_vector(C_GPO1_SIZE-1 downto 0);
+      GPO2 : out std_logic_vector(C_GPO2_SIZE-1 downto 0);
+      GPO3 : out std_logic_vector(C_GPO3_SIZE-1 downto 0);
+      GPO4 : out std_logic_vector(C_GPO4_SIZE-1 downto 0);
+
+      -- GPI IO
+      GPI1           : in  std_logic_vector(C_GPI1_SIZE-1 downto 0);
+      GPI1_Interrupt : out std_logic;
+      GPI2           : in  std_logic_vector(C_GPI2_SIZE-1 downto 0);
+      GPI2_Interrupt : out std_logic;
+      GPI3           : in  std_logic_vector(C_GPI3_SIZE-1 downto 0);
+      GPI3_Interrupt : out std_logic;
+      GPI4           : in  std_logic_vector(C_GPI4_SIZE-1 downto 0);
+      GPI4_Interrupt : out std_logic;
+
+      -- Interrupt IO
+      INTC_Interrupt         : in  std_logic_vector(C_INTC_INTR_SIZE-1 downto 0);
+      INTC_IRQ               : out std_logic;
+      INTC_Processor_Ack     : in  std_logic_vector(1 downto 0);
+      INTC_Interrupt_Address : out std_logic_vector(C_ADDR_WIDTH-1 downto 0);
+
+      -- Register access
+      PIT1_Read          : in  std_logic;
+      PIT1_Write_Preload : in  std_logic;
+      PIT1_Write_Ctrl    : in  std_logic;
+      PIT2_Read          : in  std_logic;
+      PIT2_Write_Preload : in  std_logic;
+      PIT2_Write_Ctrl    : in  std_logic;
+      PIT3_Read          : in  std_logic;
+      PIT3_Write_Preload : in  std_logic;
+      PIT3_Write_Ctrl    : in  std_logic;
+      PIT4_Read          : in  std_logic;
+      PIT4_Write_Preload : in  std_logic;
+      PIT4_Write_Ctrl    : in  std_logic;
+      GPI1_Read          : in  std_logic;
+      GPI2_Read          : in  std_logic;
+      GPI3_Read          : in  std_logic;
+      GPI4_Read          : in  std_logic;
+      UART_TX_Write      : in  std_logic;
+      UART_Baud_Write    : in  std_logic;
+      GPO1_Write         : in  std_logic;
+      GPO2_Write         : in  std_logic;
+      GPO3_Write         : in  std_logic;
+      GPO4_Write         : in  std_logic;
+      UART_Status_Read   : in  std_logic;
+      UART_Status_Wait   : out std_logic;
+      UART_Status_Ready  : out std_logic;
+      UART_Rx_Read       : in  std_logic;
+      UART_Rx_Wait       : out std_logic;
+      UART_Rx_Ready      : out std_logic;
+      INTC_WRITE_CIAR    : in  std_logic;
+      INTC_WRITE_CIER    : in  std_logic;
+      INTC_WRITE_CIMR    : in  std_logic;
+      INTC_WRITE_CIVAR   : in  std_logic;
+      INTC_WRITE_CIVEAR  : in  std_logic;
+      INTC_CIVAR_ADDR    : in  std_logic_vector(4 downto 0);
+      INTC_READ_CISR     : in  std_logic;
+      INTC_READ_CIPR     : in  std_logic;
+      Write_Data         : in  std_logic_vector(31 downto 0);
+      Read_Data          : out std_logic_vector(31 downto 0));
+  end component iomodule_core;
+
+  component pselect_mask
+    generic (
+      C_AW   : integer                   := 32;
+      C_BAR  : std_logic_vector(0 to 63) := X"0000000000000000";
+      C_MASK : std_logic_vector(0 to 63) := X"0000000000800000");
+    port (
+      A     : in  std_logic_vector(0 to C_AW - 1);
+      CS    : out std_logic;
+      Valid : in  std_logic);
+  end component;
+
+  function c_use(size : integer) return integer is
+  begin
+    if size = 0 then
+      return 0;
+    else
+      return 1;
+    end if;
+  end function c_use;
+
+  -- Interrupt controller extended address
+  constant C_INTC_HAS_AE : integer := Boolean'Pos(C_INTC_ADDR_WIDTH > 32);
+  constant C_ADDR_WIDTH  : natural := ((C_INTC_ADDR_WIDTH + 31) / 64) * (C_INTC_ADDR_WIDTH - 32) + 32;
+
+  -- Target
+  constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
+  
+  -- Register Address Map
+  constant C_UART_RX      : std_logic_vector(0 to 4) := "00000";
+  constant C_UART_TX      : std_logic_vector(0 to 4) := "00001";
+  constant C_UART_STATUS  : std_logic_vector(0 to 4) := "00010";
+  constant C_IRQ_MODE     : std_logic_vector(0 to 4) := "00011";
+  constant C_GPO1         : std_logic_vector(0 to 4) := "00100";
+  constant C_GPO2         : std_logic_vector(0 to 4) := "00101";
+  constant C_GPO3         : std_logic_vector(0 to 4) := "00110";
+  constant C_GPO4         : std_logic_vector(0 to 4) := "00111";
+  constant C_GPI1         : std_logic_vector(0 to 4) := "01000";
+  constant C_GPI2         : std_logic_vector(0 to 4) := "01001";
+  constant C_GPI3         : std_logic_vector(0 to 4) := "01010";
+  constant C_GPI4         : std_logic_vector(0 to 4) := "01011";
+  constant C_IRQ_STATUS   : std_logic_vector(0 to 4) := "01100";
+  constant C_IRQ_PENDING  : std_logic_vector(0 to 4) := "01101";
+  constant C_IRQ_ENABLE   : std_logic_vector(0 to 4) := "01110";
+  constant C_IRQ_ACK      : std_logic_vector(0 to 4) := "01111";
+  constant C_PIT1_PRELOAD : std_logic_vector(0 to 4) := "10000";
+  constant C_PIT1_COUNTER : std_logic_vector(0 to 4) := "10001";
+  constant C_PIT1_CONTROL : std_logic_vector(0 to 4) := "10010";
+  constant C_UART_BAUD    : std_logic_vector(0 to 4) := "10011";
+  constant C_PIT2_PRELOAD : std_logic_vector(0 to 4) := "10100";
+  constant C_PIT2_COUNTER : std_logic_vector(0 to 4) := "10101";
+  constant C_PIT2_CONTROL : std_logic_vector(0 to 4) := "10110";
+  constant C_SPARE2       : std_logic_vector(0 to 4) := "10111";
+  constant C_PIT3_PRELOAD : std_logic_vector(0 to 4) := "11000";
+  constant C_PIT3_COUNTER : std_logic_vector(0 to 4) := "11001";
+  constant C_PIT3_CONTROL : std_logic_vector(0 to 4) := "11010";
+  constant C_SPARE3       : std_logic_vector(0 to 4) := "11011";
+  constant C_PIT4_PRELOAD : std_logic_vector(0 to 4) := "11100";
+  constant C_PIT4_COUNTER : std_logic_vector(0 to 4) := "11101";
+  constant C_PIT4_CONTROL : std_logic_vector(0 to 4) := "11110";
+  constant C_SPARE4       : std_logic_vector(0 to 4) := "11111";
+
+  signal lmb_reg_select     : std_logic;
+  signal lmb_io_select      : std_logic;
+  signal lmb_io_select_keep : std_logic;
+  signal lmb_abus_Q         : std_logic_vector(2 - C_INTC_HAS_FAST - C_INTC_HAS_AE to 6);
+  signal lmb_reg_read       : std_logic;
+  signal lmb_reg_read_Q     : std_logic;
+  signal lmb_reg_write      : std_logic;
+  signal io_ready_Q         : std_logic;
+  signal io_bus_read_data   : std_logic_vector(C_LMB_DWIDTH-1 downto 0);
+  
+  -- Register access
+  signal wen                : std_logic;
+  signal regaddr            : std_logic_vector(0 to 4);
+  signal pit1_read          : std_logic;
+  signal pit1_write_preload : std_logic;
+  signal pit1_write_ctrl    : std_logic;
+  signal pit2_read          : std_logic;
+  signal pit2_write_preload : std_logic;
+  signal pit2_write_ctrl    : std_logic;
+  signal pit3_read          : std_logic;
+  signal pit3_write_preload : std_logic;
+  signal pit3_write_ctrl    : std_logic;
+  signal pit4_read          : std_logic;
+  signal pit4_write_preload : std_logic;
+  signal pit4_write_ctrl    : std_logic;
+  signal gpi1_read          : std_logic;
+  signal gpi2_read          : std_logic;
+  signal gpi3_read          : std_logic;
+  signal gpi4_read          : std_logic;
+  signal uart_tx_write      : std_logic;
+  signal gpo1_write         : std_logic;
+  signal gpo2_write         : std_logic;
+  signal gpo3_write         : std_logic;
+  signal gpo4_write         : std_logic;
+  signal uart_status_read   : std_logic;
+  signal uart_status_wait   : std_logic;
+  signal uart_status_ready  : std_logic;
+  signal uart_rx_read       : std_logic;
+  signal uart_rx_wait       : std_logic;
+  signal uart_rx_ready      : std_logic;
+  signal uart_baud_write    : std_logic;
+  signal intc_write_ciar    : std_logic;
+  signal intc_write_cier    : std_logic;
+  signal intc_write_cimr    : std_logic;
+  signal intc_write_civar   : std_logic;
+  signal intc_write_civear  : std_logic;
+  signal intc_read_cisr     : std_logic;
+  signal intc_read_cipr     : std_logic;
+  signal write_data         : std_logic_vector(31 downto 0);
+  signal io_reg_read_data   : std_logic_vector(31 downto 0);
+
+  signal fit1_interrupt_i : std_logic;
+  signal fit2_interrupt_i : std_logic;
+  signal fit3_interrupt_i : std_logic;
+  signal fit4_interrupt_i : std_logic;
+  signal pit1_interrupt_i : std_logic;
+  signal pit2_interrupt_i : std_logic;
+  signal pit3_interrupt_i : std_logic;
+  signal pit4_interrupt_i : std_logic;
+
+  signal intc_irq_i       : std_logic;
+
+  signal One : std_logic;               -- tied to '1';
+
+  -- Preserve signals after synthesis for simulation UART support
+  attribute KEEP : string;
+  attribute KEEP of uart_tx_write : signal is "TRUE";
+  attribute KEEP of write_data    : signal is "TRUE";
+
+  signal config_reset_i : std_logic;
+
+begin  -- architecture IMP
+
+  config_reset_i <= Config_Reset when C_USE_CONFIG_RESET /= 0 else '0';
+
+  -----------------------------------------------------------------------------
+  -- Do the LMB address decoding
+  -----------------------------------------------------------------------------
+  One <= '1';
+  -- Detect if IO Module register is accessed
+  pselect_mask_reg : pselect_mask
+    generic map (
+      C_AW   => LMB_ABus'length,
+      C_BAR  => C_BASEADDR,
+      C_MASK => C_MASK)
+    port map (
+      A     => LMB_ABus,
+      CS    => lmb_reg_select,
+      Valid => One);
+
+  -- Remember address, read, write and write data
+  AccessReg : process(Clk) is
+  begin
+    if (Clk'event and Clk = '1') then
+      if config_reset_i = '1' then
+        lmb_abus_Q <= (others => '0');
+
+        lmb_reg_read_Q <= '0';
+        lmb_reg_read   <= '0';
+        lmb_reg_write  <= '0';
+
+        Write_Data(31 downto 0) <= (others => '0');
+      else
+        lmb_abus_Q <= LMB_ABus(LMB_ABus'high-LMB_ABus_Q'length+1-2 to LMB_ABus'high-2);
+
+        if (uart_status_read = '1' or uart_rx_read = '1') and C_UART_ASYNC = 1 then
+          lmb_reg_read_Q <= '0';
+        else
+          lmb_reg_read_Q <= lmb_reg_read;
+        end if;
+        lmb_reg_read   <= LMB_ReadStrobe  and lmb_reg_select and LMB_AddrStrobe;
+        lmb_reg_write  <= LMB_WriteStrobe and lmb_reg_select and LMB_AddrStrobe;
+
+        Write_Data(31 downto 0) <= LMB_WriteDBus(0 to 31);  -- Data to write to IO module
+      end if;
+    end if;
+  end process AccessReg;
+
+  Using_IO_Bus : if (C_USE_IO_BUS /= 0) generate
+
+    signal io_read_keep   : std_logic;
+
+  begin
+    
+    -- Detect if IO Module IO extension is accessed
+    pselect_mask_io : pselect_mask
+      generic map (
+        C_AW   => LMB_ABus'length,
+        C_BAR  => C_IO_BASEADDR,
+        C_MASK => C_IO_MASK)
+      port map (
+        A     => LMB_ABus,
+        CS    => lmb_io_select,
+        Valid => One);
+
+    AccessIO : process(Clk) is
+    begin
+      if (Clk'event and Clk = '1') then
+        if Rst = '1' or TMR_Rst = '1' then
+          IO_Addr_Strobe     <= '0';
+          IO_Read_Strobe     <= '0';
+          IO_Write_Strobe    <= '0';
+          IO_Address         <= (others => '0');
+          IO_Byte_Enable     <= (others => '0');
+          IO_Write_Data      <= (others => '0');
+          lmb_io_select_keep <= '0';
+          io_read_keep       <= '0';
+        elsif lmb_io_select = '1' and LMB_AddrStrobe = '1' then
+          IO_Addr_Strobe     <= '1';
+          IO_Read_Strobe     <= LMB_ReadStrobe;
+          IO_Write_Strobe    <= LMB_WriteStrobe;
+          IO_Address         <= LMB_ABus;
+          IO_Byte_Enable     <= LMB_BE;
+          IO_Write_Data      <= LMB_WriteDBus;
+          lmb_io_select_keep <= '1';
+          io_read_keep       <= LMB_ReadStrobe;
+        else
+          if IO_Ready = '1' then
+            lmb_io_select_keep <= '0';
+            io_read_keep       <= '0';
+          end if;
+          IO_Addr_Strobe  <= '0';
+          IO_Read_Strobe  <= '0';
+          IO_Write_Strobe <= '0';
+        end if;
+      end if;
+    end process AccessIO;
+
+    ReadyReg : process(Clk) is
+    begin
+      if (Clk'event and Clk = '1') then
+        if config_reset_i = '1' then
+          io_ready_Q <= '0';
+        else
+          io_ready_Q <= lmb_io_select_keep and IO_Ready;
+        end if;
+      end if;
+    end process ReadyReg;
+
+    ReadDataReg : process(Clk) is
+    begin
+      if (Clk'event and Clk = '1') then
+        if config_reset_i = '1' then
+          io_bus_read_data <= (others => '0');
+        else
+          if IO_Ready = '1' and io_read_keep = '1' then
+            io_bus_read_data <= IO_Read_Data;
+          else
+            io_bus_read_data <= (others => '0');
+          end if;
+        end if;
+      end if;
+    end process ReadDataReg;
+    
+  end generate Using_IO_Bus;
+  
+  Not_Using_IO_Bus : if (C_USE_IO_BUS = 0) generate
+    io_ready_Q         <= '0';
+    io_bus_read_data   <= (others => '0');
+    lmb_io_select      <= '0';
+    lmb_io_select_keep <= '0';
+    IO_Addr_Strobe     <= '0';
+    IO_Read_Strobe     <= '0';
+    IO_Write_Strobe    <= '0';
+    IO_Address         <= (others => '0');
+    IO_Byte_Enable     <= (others => '0');
+    IO_Write_Data      <= (others => '0');
+  end generate Not_Using_IO_Bus;
+  
+  -- Data read from IO module
+
+  -- Standard LMB protocol with RAM data read combinatorial through LMB controller 
+  Sl_DBus_LMB_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+  begin
+    Sl_DBus(0 to 31) <= io_reg_read_data(31 downto 0) or io_bus_read_data(31 downto 0);
+  end generate Sl_DBus_LMB_Protocol_0;
+
+  -- Timing optimized LMB protocol with RAM data read clocked in LMB controller
+  -- Sl_DBus needs to be clocked once to match clocked timing of RAM data read clocked
+  -- Only works with MicroBlaze 8-stage pipe and C_LMB_PROTOCOL set to 1 on MicroBlaze
+  Sl_DBus_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+  begin
+    Sl_DBus_DFF : process(Clk) is
+    begin
+      if (Clk'event and Clk = '1') then
+        if config_reset_i = '1' then
+          Sl_DBus <= (others => '0');
+        else        
+          Sl_DBus(0 to 31) <= io_reg_read_data(31 downto 0) or io_bus_read_data(31 downto 0);
+        end if;
+      end if;
+    end process Sl_DBus_DFF;
+  end generate Sl_DBus_LMB_Protocol_1;
+  
+  Sl_Wait <= '1' when lmb_reg_read = '1' or
+                      lmb_io_select_keep = '1' or
+                      ((uart_status_wait = '1' or uart_rx_wait= '1') and C_UART_ASYNC = 1) else
+             '0';
+
+  Sl_UE   <= '0'; -- No Uncorrectable Errors
+  Sl_CE   <= '0'; -- No Correctable Errors
+
+  Sl_Ready <= '1' when lmb_reg_write  = '1' or
+                       lmb_reg_read_Q = '1' or
+                       io_ready_Q = '1' or
+                       ((uart_status_ready = '1' or uart_rx_ready = '1') and C_UART_ASYNC = 1) else
+              '0';
+
+  uart_rx_read       <= '1' when regaddr = C_UART_RX      and lmb_reg_read  = '1' else '0'; 
+  uart_tx_write      <= wen when regaddr = C_UART_TX      and lmb_reg_write = '1' else '0';
+  uart_status_read   <= '1' when regaddr = C_UART_STATUS  and lmb_reg_read  = '1' else '0';
+  uart_baud_write    <= wen when regaddr = C_UART_BAUD    and lmb_reg_write = '1' else '0';
+  intc_write_cimr    <= wen when regaddr = C_IRQ_MODE     and lmb_reg_write = '1' else '0';
+  gpo1_write         <= wen when regaddr = C_GPO1         and lmb_reg_write = '1' else '0';
+  gpo2_write         <= wen when regaddr = C_GPO2         and lmb_reg_write = '1' else '0';
+  gpo3_write         <= wen when regaddr = C_GPO3         and lmb_reg_write = '1' else '0';
+  gpo4_write         <= wen when regaddr = C_GPO4         and lmb_reg_write = '1' else '0';
+  gpi1_read          <= '1' when regaddr = C_GPI1         and lmb_reg_read  = '1' else '0';
+  gpi2_read          <= '1' when regaddr = C_GPI2         and lmb_reg_read  = '1' else '0';
+  gpi3_read          <= '1' when regaddr = C_GPI3         and lmb_reg_read  = '1' else '0';
+  gpi4_read          <= '1' when regaddr = C_GPI4         and lmb_reg_read  = '1' else '0';
+  intc_write_ciar    <= wen when regaddr = C_IRQ_ACK      and lmb_reg_write = '1' else '0';
+  intc_write_cier    <= wen when regaddr = C_IRQ_ENABLE   and lmb_reg_write = '1' else '0';
+  intc_read_cisr     <= '1' when regaddr = C_IRQ_STATUS   and lmb_reg_read  = '1' else '0';
+  intc_read_cipr     <= '1' when regaddr = C_IRQ_PENDING  and lmb_reg_read  = '1' else '0';
+  pit1_read          <= '1' when regaddr = C_PIT1_COUNTER and lmb_reg_read  = '1' else '0';
+  pit1_write_preload <= wen when regaddr = C_PIT1_PRELOAD and lmb_reg_write = '1' else '0';
+  pit1_write_ctrl    <= wen when regaddr = C_PIT1_CONTROL and lmb_reg_write = '1' else '0';
+  pit2_read          <= '1' when regaddr = C_PIT2_COUNTER and lmb_reg_read  = '1' else '0';
+  pit2_write_preload <= wen when regaddr = C_PIT2_PRELOAD and lmb_reg_write = '1' else '0';
+  pit2_write_ctrl    <= wen when regaddr = C_PIT2_CONTROL and lmb_reg_write = '1' else '0';
+  pit3_read          <= '1' when regaddr = C_PIT3_COUNTER and lmb_reg_read  = '1' else '0';
+  pit3_write_preload <= wen when regaddr = C_PIT3_PRELOAD and lmb_reg_write = '1' else '0';
+  pit3_write_ctrl    <= wen when regaddr = C_PIT3_CONTROL and lmb_reg_write = '1' else '0';
+  pit4_read          <= '1' when regaddr = C_PIT4_COUNTER and lmb_reg_read  = '1' else '0';
+  pit4_write_preload <= wen when regaddr = C_PIT4_PRELOAD and lmb_reg_write = '1' else '0';
+  pit4_write_ctrl    <= wen when regaddr = C_PIT4_CONTROL and lmb_reg_write = '1' else '0';
+
+  Using_Fast : if C_INTC_HAS_FAST = 1 and C_INTC_HAS_AE = 0 generate
+  begin
+    intc_write_civar  <= lmb_reg_write when lmb_abus_Q(1) = '1' else '0';
+    intc_write_civear <= '0';
+    wen <= not lmb_abus_Q(1);
+    regaddr <= lmb_abus_Q(2 to 6);
+  end generate Using_Fast;
+
+  Using_Fast_AE : if C_INTC_HAS_FAST = 1 and C_INTC_HAS_AE = 1 generate
+  begin
+    intc_write_civar  <= lmb_reg_write when (lmb_abus_Q(0) = '0' and lmb_abus_Q(1) = '1') or
+                                            (lmb_abus_Q(0) = '1' and lmb_abus_Q(6) = '0') else '0';
+    intc_write_civear <= lmb_reg_write when (lmb_abus_Q(0) = '1' and lmb_abus_Q(6) = '1') else '0';
+    wen <= not (lmb_abus_Q(0) or lmb_abus_Q(1));
+    regaddr <= lmb_abus_Q(2 to 6) when lmb_abus_Q(0) = '0' else
+               lmb_abus_Q(1 to 5);
+  end generate Using_Fast_AE;
+
+  Not_Using_Fast : if C_INTC_HAS_FAST = 0 generate
+  begin
+    intc_write_civar  <= '0';
+    intc_write_civear <= '0';
+    wen <= '1';
+    regaddr <= lmb_abus_Q(2 to 6);
+  end generate Not_Using_Fast;
+
+
+  IOModule_Core_I1: iomodule_core
+    generic map (
+      C_TARGET               => C_TARGET,
+      C_FREQ                 => C_FREQ,
+      C_USE_CONFIG_RESET     => C_USE_CONFIG_RESET,
+      C_AVOID_PRIMITIVES     => C_AVOID_PRIMITIVES,
+      C_TMR                  => C_TMR,
+      C_USE_TMR_DISABLE      => C_USE_TMR_DISABLE,
+
+      -- UART generics
+      C_USE_UART_RX          => C_USE_UART_RX,           -- [integer]
+      C_USE_UART_TX          => C_USE_UART_TX,           -- [integer]
+      C_UART_BAUDRATE        => C_UART_BAUDRATE,         -- [integer]
+      C_UART_DATA_BITS       => C_UART_DATA_BITS,        -- [integer range 5 to 8]
+      C_UART_USE_PARITY      => C_UART_USE_PARITY,       -- [integer]
+      C_UART_ODD_PARITY      => C_UART_ODD_PARITY,       -- [integer]
+      C_UART_RX_INTERRUPT    => C_UART_RX_INTERRUPT,     -- [integer]
+      C_UART_TX_INTERRUPT    => C_UART_TX_INTERRUPT,     -- [integer]
+      C_UART_ERROR_INTERRUPT => C_UART_ERROR_INTERRUPT,  -- [integer]
+      C_UART_PROG_BAUDRATE   => C_UART_PROG_BAUDRATE,    -- [integer]
+      C_UART_FREQ            => C_UART_FREQ,             -- [integer]
+      C_UART_ASYNC           => C_UART_ASYNC,            -- [integer]
+      C_UART_NUM_SYNC_FF     => C_UART_NUM_SYNC_FF,      -- [integer]
+
+      -- FIT generics
+      C_USE_FIT1        => C_USE_FIT1,         -- [integer]
+      C_FIT1_No_CLOCKS  => C_FIT1_No_CLOCKS,   -- [integer]
+      C_FIT1_INTERRUPT  => C_FIT1_INTERRUPT,   -- [integer]
+      C_USE_FIT2        => C_USE_FIT2,         -- [integer]
+      C_FIT2_No_CLOCKS  => C_FIT2_No_CLOCKS,   -- [integer]
+      C_FIT2_INTERRUPT  => C_FIT2_INTERRUPT,   -- [integer]
+      C_USE_FIT3        => C_USE_FIT3,         -- [integer]
+      C_FIT3_No_CLOCKS  => C_FIT3_No_CLOCKS,   -- [integer]
+      C_FIT3_INTERRUPT  => C_FIT3_INTERRUPT,   -- [integer]
+      C_USE_FIT4        => C_USE_FIT4,         -- [integer]
+      C_FIT4_No_CLOCKS  => C_FIT4_No_CLOCKS,   -- [integer]
+      C_FIT4_INTERRUPT  => C_FIT4_INTERRUPT,   -- [integer]
+
+      -- PIT generics
+      C_USE_PIT1           => C_USE_PIT1,            -- [integer]
+      C_PIT1_SIZE          => C_PIT1_SIZE,           -- [integer]
+      C_PIT1_READABLE      => C_PIT1_READABLE,       -- [integer]
+      C_PIT1_PRESCALER     => C_PIT1_PRESCALER,      -- [integer range 0 to 9]
+      C_PIT1_INTERRUPT     => C_PIT1_INTERRUPT,      -- [integer]
+      C_USE_PIT2           => C_USE_PIT2,            -- [integer]
+      C_PIT2_SIZE          => C_PIT2_SIZE,           -- [integer]
+      C_PIT2_READABLE      => C_PIT2_READABLE,       -- [integer]
+      C_PIT2_PRESCALER     => C_PIT2_PRESCALER,      -- [integer range 0 to 9]
+      C_PIT2_INTERRUPT     => C_PIT2_INTERRUPT,      -- [integer]
+      C_USE_PIT3           => C_USE_PIT3,            -- [integer]
+      C_PIT3_SIZE          => C_PIT3_SIZE,           -- [integer]
+      C_PIT3_READABLE      => C_PIT3_READABLE,       -- [integer]
+      C_PIT3_PRESCALER     => C_PIT3_PRESCALER,      -- [integer range 0 to 9]
+      C_PIT3_INTERRUPT     => C_PIT3_INTERRUPT,      -- [integer]
+      C_USE_PIT4           => C_USE_PIT4,            -- [integer]
+      C_PIT4_SIZE          => C_PIT4_SIZE,           -- [integer]
+      C_PIT4_READABLE      => C_PIT4_READABLE,       -- [integer]
+      C_PIT4_PRESCALER     => C_PIT4_PRESCALER,      -- [integer range 0 to 9]
+      C_PIT4_INTERRUPT     => C_PIT4_INTERRUPT,      -- [integer]
+
+      -- GPO Generics
+      C_USE_GPO1  => C_USE_GPO1,
+      C_GPO1_SIZE => C_GPO1_SIZE,
+      C_GPO1_INIT => C_GPO1_INIT,
+      C_USE_GPO2  => C_USE_GPO2,
+      C_GPO2_SIZE => C_GPO2_SIZE,
+      C_GPO2_INIT => C_GPO2_INIT,
+      C_USE_GPO3  => C_USE_GPO3,
+      C_GPO3_SIZE => C_GPO3_SIZE,
+      C_GPO3_INIT => C_GPO3_INIT,
+      C_USE_GPO4  => C_USE_GPO4,
+      C_GPO4_SIZE => C_GPO4_SIZE,
+      C_GPO4_INIT => C_GPO4_INIT,
+
+      -- GPI Generics
+      C_USE_GPI1       => C_USE_GPI1,
+      C_GPI1_SIZE      => C_GPI1_SIZE,
+      C_GPI1_INTERRUPT => C_GPI1_INTERRUPT,
+      C_USE_GPI2       => C_USE_GPI2, 
+      C_GPI2_SIZE      => C_GPI2_SIZE,
+      C_GPI2_INTERRUPT => C_GPI2_INTERRUPT,
+      C_USE_GPI3       => C_USE_GPI3, 
+      C_GPI3_SIZE      => C_GPI3_SIZE,
+      C_GPI3_INTERRUPT => C_GPI3_INTERRUPT,
+      C_USE_GPI4       => C_USE_GPI4, 
+      C_GPI4_SIZE      => C_GPI4_SIZE,
+      C_GPI4_INTERRUPT => C_GPI4_INTERRUPT,
+
+      -- Interrupt Handler Generics
+      C_ADDR_WIDTH        => C_ADDR_WIDTH,
+      C_INTC_USE_EXT_INTR => C_INTC_USE_EXT_INTR,
+      C_INTC_INTR_SIZE    => C_INTC_INTR_SIZE,
+      C_INTC_LEVEL_EDGE   => C_INTC_LEVEL_EDGE,
+      C_INTC_POSITIVE     => C_INTC_POSITIVE,
+      C_INTC_HAS_FAST     => C_INTC_HAS_FAST,
+      C_INTC_ADDR_WIDTH   => C_INTC_ADDR_WIDTH,
+      C_INTC_BASE_VECTORS => C_INTC_BASE_VECTORS,
+      C_INTC_ASYNC_INTR   => C_INTC_ASYNC_INTR,
+      C_INTC_NUM_SYNC_FF  => C_INTC_NUM_SYNC_FF)
+
+    port map (
+      Config_Reset => Config_Reset,
+      CLK          => CLK,
+      Rst          => Rst,
+      TMR_Rst      => TMR_Rst,
+      TMR_Disable  => TMR_Disable,
+
+      -- TMR voting inbetween redundant IO Modules
+      ToVote       => ToVote,
+      FromAVote    => FromAVote,
+      FromBVote    => FromBVote,
+
+      -- UART I/O
+      UART_Clk       => UART_Clk,
+      UART_Rst       => UART_Rst,
+      UART_Rx        => UART_Rx,
+      UART_Tx        => UART_Tx,
+      UART_Interrupt => UART_Interrupt,
+
+      -- FIT I/O
+      FIT1_Interrupt => fit1_interrupt_i,
+      FIT1_Toggle    => FIT1_Toggle,
+      FIT2_Interrupt => fit2_interrupt_i,
+      FIT2_Toggle    => FIT2_Toggle,
+      FIT3_Interrupt => fit3_interrupt_i,
+      FIT3_Toggle    => FIT3_Toggle,
+      FIT4_Interrupt => fit4_interrupt_i,
+      FIT4_Toggle    => FIT4_Toggle,
+
+      -- PIT I/O
+      PIT1_Enable    => PIT1_Enable,
+      PIT1_Interrupt => pit1_interrupt_i,
+      PIT1_Toggle    => PIT1_Toggle,
+      PIT2_Enable    => PIT2_Enable,
+      PIT2_Interrupt => pit2_interrupt_i,
+      PIT2_Toggle    => PIT2_Toggle,
+      PIT3_Enable    => PIT3_Enable,
+      PIT3_Interrupt => pit3_interrupt_i,
+      PIT3_Toggle    => PIT3_Toggle,
+      PIT4_Enable    => PIT4_Enable,
+      PIT4_Interrupt => pit4_interrupt_i,
+      PIT4_Toggle    => PIT4_Toggle,
+
+      -- GPO IO
+      GPO1 => GPO1,
+      GPO2 => GPO2,
+      GPO3 => GPO3,
+      GPO4 => GPO4,
+
+      -- GPI IO
+      GPI1           => GPI1,
+      GPI1_Interrupt => GPI1_Interrupt,
+      GPI2           => GPI2,
+      GPI2_Interrupt => GPI2_Interrupt,
+      GPI3           => GPI3,
+      GPI3_Interrupt => GPI3_Interrupt,
+      GPI4           => GPI4,
+      GPI4_Interrupt => GPI4_Interrupt,
+
+      -- Interrupt IO
+      INTC_Interrupt         => INTC_Interrupt,
+      INTC_IRQ               => intc_irq_i,
+      INTC_Processor_Ack     => INTC_Processor_Ack,
+      INTC_Interrupt_Address => INTC_Interrupt_Address,
+
+      -- Register access
+      PIT1_Read          => pit1_read,
+      PIT1_Write_Preload => pit1_write_preload,
+      PIT1_Write_Ctrl    => pit1_write_ctrl,
+      PIT2_Read          => pit2_read,
+      PIT2_Write_Preload => pit2_write_preload,
+      PIT2_Write_Ctrl    => pit2_write_ctrl,
+      PIT3_Read          => pit3_read,
+      PIT3_Write_Preload => pit3_write_preload,
+      PIT3_Write_Ctrl    => pit3_write_ctrl,
+      PIT4_Read          => pit4_read,
+      PIT4_Write_Preload => pit4_write_preload,
+      PIT4_Write_Ctrl    => pit4_write_ctrl,
+      GPI1_Read          => gpi1_read,
+      GPI2_Read          => gpi2_read,
+      GPI3_Read          => gpi3_read,
+      GPI4_Read          => gpi4_read,
+      UART_TX_Write      => uart_tx_write,
+      UART_Baud_Write    => uart_baud_write,
+      GPO1_Write         => gpo1_write,
+      GPO2_Write         => gpo2_write,
+      GPO3_Write         => gpo3_write,
+      GPO4_Write         => gpo4_write,
+      UART_Status_Read   => uart_status_read,
+      UART_Status_Wait   => uart_status_wait,
+      UART_Status_Ready  => uart_status_ready,
+      UART_Rx_Read       => uart_rx_read,
+      UART_Rx_Wait       => uart_rx_wait,
+      UART_Rx_Ready      => uart_rx_ready,
+      INTC_WRITE_CIAR    => intc_write_ciar,
+      INTC_WRITE_CIER    => intc_write_cier,
+      INTC_WRITE_CIMR    => intc_write_cimr,
+      INTC_WRITE_CIVAR   => intc_write_civar,
+      INTC_WRITE_CIVEAR  => intc_write_civear,
+      INTC_CIVAR_ADDR    => regaddr,
+      INTC_READ_CISR     => intc_read_cisr,
+      INTC_READ_CIPR     => intc_read_cipr,
+      Write_Data         => write_data,
+      Read_Data          => io_reg_read_data);
+
+   INTC_IRQ     <= intc_irq_i;
+   INTC_IRQ_OUT <= intc_irq_i;
+
+   FIT1_Interrupt <= fit1_interrupt_i;
+   FIT2_Interrupt <= fit2_interrupt_i;
+   FIT3_Interrupt <= fit3_interrupt_i;
+   FIT4_Interrupt <= fit4_interrupt_i;
+   PIT1_Interrupt <= pit1_interrupt_i;
+   PIT2_Interrupt <= pit2_interrupt_i;
+   PIT3_Interrupt <= pit3_interrupt_i;
+   PIT4_Interrupt <= pit4_interrupt_i;
+  
+end architecture IMP;
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/lib_cdc_v1_0_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/lib_cdc_v1_0_rfs.vhd
new file mode 100755
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+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/lib_cdc_v1_0_rfs.vhd
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+
+--Generic Help
+--C_CDC_TYPE : Defines the type of CDC needed
+--             0 means pulse synchronizer. Used to transfer one clock pulse 
+--               from prmry domain to scndry domain.
+--             1 means level synchronizer. Used to transfer level signal.
+--             2 means level synchronizer with ack. Used to transfer level 
+--               signal. Input signal should change only when prmry_ack is detected
+--
+--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
+--               Set to 0 when incoming signal is purely floped signal.
+--
+--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
+--                it might be needed.
+--              0 means reset not needed for sync flops 
+--              1 means reset needed for sync flops. i
+--                In this case prmry_resetn should be in prmry clock, 
+--                while scndry_reset should be in scndry clock.
+--
+--C_SINGLE_BIT : CDC should normally be done for single bit signals only. 
+--               However, based on design buses can also be CDC'ed.
+--               0 means it is a bus. In this case input be connected to prmry_vect_in.
+--                 Output is on scndry_vect_out.
+--               1 means it is a single bit. In this case input be connected to prmry_in. 
+--                 Output is on scndry_out.
+--
+--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
+--
+--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
+--                Value of 0, 1 is allowed only for level CDC.
+--                Min value for Pulse CDC is 2
+--
+--Whenever this file is used following XDC constraint has to be added 
+
+--         set_false_path -to [get_pins -hier *cdc_to*/D]        
+
+
+--IO Ports 
+--
+--        prmry_aclk      : clock of originating domain (source domain)
+--        prmry_resetn    : sync reset of originating clock domain (source domain)
+--        prmry_in        : input signal bit. This should be a pure flop output without 
+--                          any combi logic. This is source. 
+--        prmry_vect_in   : bus signal. From Source domain.
+--        prmry_ack       : Ack signal, valid for one clock period, in prmry_aclk domain.
+--                          Used only when C_CDC_TYPE = 2
+--        scndry_aclk     : destination clock.
+--        scndry_resetn   : sync reset of destination domain
+--        scndry_out      : sync'ed output in destination domain. Single bit.
+--        scndry_vect_out : sync'ed output in destination domain. bus.
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_misc.all;
+library unisim;
+use unisim.vcomponents.FDR;
+
+
+
+entity  cdc_sync is
+    generic (
+        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
+                                    -- 0 is pulse synch
+                                    -- 1 is level synch
+                                    -- 2 is ack based level sync
+        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
+                                    -- 0 is reset not needed 
+                                    -- 1 is reset needed 
+        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
+                                    -- 0 is bus input
+                                    -- 1 is single bit input
+        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
+        C_VECTOR_WIDTH              : integer range 0 to 64 := 32               ;
+        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
+            -- Vector Data witdth
+    );
+
+    port (
+        prmry_aclk                  : in  std_logic                             ;               --
+        prmry_resetn                : in  std_logic                             ;               --
+        prmry_in                    : in  std_logic                             ;               --
+        prmry_vect_in               : in  std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
+        prmry_ack                   : out std_logic                             ;
+                                                                                                --
+        scndry_aclk                 : in  std_logic                             ;               --
+        scndry_resetn               : in  std_logic                             ;               --
+                                                                                                --
+        -- Primary to Secondary Clock Crossing                                                  --
+        scndry_out                  : out std_logic                             ;               --
+                                                                                                --
+        scndry_vect_out             : out std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)                           --
+
+    );
+
+end cdc_sync;
+
+-------------------------------------------------------------------------------
+-- Architecture
+-------------------------------------------------------------------------------
+architecture implementation of cdc_sync is
+
+attribute DowngradeIPIdentifiedWarnings : string;
+attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
+
+--attribute DONT_TOUCH : STRING;
+--attribute KEEP : STRING;
+--attribute DONT_TOUCH of implementation : architecture is "yes";
+signal prmry_resetn1             : std_logic := '0';
+signal scndry_resetn1            : std_logic := '0';
+signal prmry_reset2             : std_logic := '0';
+signal scndry_reset2            : std_logic := '0';
+--attribute KEEP of prmry_resetn1 : signal is "true";
+--attribute KEEP of scndry_resetn1 : signal is "true";
+
+-------------------------------------------------------------------------------
+-- Functions
+-------------------------------------------------------------------------------
+
+-- No Functions Declared
+
+-------------------------------------------------------------------------------
+-- Constants Declarations
+-------------------------------------------------------------------------------
+
+-- No Constants Declared
+
+-------------------------------------------------------------------------------
+-- Begin architecture logic
+-------------------------------------------------------------------------------
+begin
+
+HAS_RESET : if C_RESET_STATE = 1 generate
+begin
+prmry_resetn1 <= prmry_resetn;
+scndry_resetn1 <= scndry_resetn;
+
+end generate HAS_RESET;
+
+HAS_NO_RESET : if C_RESET_STATE = 0 generate
+begin
+
+prmry_resetn1 <= '1';
+scndry_resetn1 <= '1';
+
+end generate HAS_NO_RESET;
+
+prmry_reset2 <= not prmry_resetn1;
+scndry_reset2 <= not scndry_resetn1;
+
+
+-- Generate PULSE clock domain crossing
+GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
+
+-- Primary to Secondary
+signal s_out_d1_cdc_to          : std_logic := '0';
+--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
+signal s_out_d2           	: std_logic := '0';
+signal s_out_d3           	: std_logic := '0';
+signal s_out_d4           	: std_logic := '0';
+signal s_out_d5           	: std_logic := '0';
+signal s_out_d6           	: std_logic := '0';
+signal s_out_d7           	: std_logic := '0';
+signal s_out_re           	: std_logic := '0';
+signal prmry_in_xored           : std_logic := '0';
+signal p_in_d1_cdc_from   	: std_logic := '0';
+
+signal srst_d1           	: std_logic := '0';
+signal srst_d2           	: std_logic := '0';
+signal srst_d3           	: std_logic := '0';
+signal srst_d4           	: std_logic := '0';
+signal srst_d5           	: std_logic := '0';
+signal srst_d6           	: std_logic := '0';
+signal srst_d7           	: std_logic := '0';
+
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      	: STRING;
+  ATTRIBUTE async_reg OF REG_P_IN2_cdc_to  			: label IS "true"; 
+  ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2  		: label IS "true"; 
+  ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3  		: label IS "true"; 
+  ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4  		: label IS "true"; 
+  ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5  		: label IS "true"; 
+  ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6  		: label IS "true"; 
+  ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7  		: label IS "true"; 
+
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Pulse Clock Crossing                      **
+    --**                  PRIMARY TO SECONDARY OPEN-ENDED                        **
+    --*****************************************************************************
+
+scndry_vect_out <= (others => '0');
+prmry_ack <= '0';
+
+prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
+ 
+--------------------------------------REG_P_IN : process(prmry_aclk)
+--------------------------------------    begin
+--------------------------------------        if(prmry_aclk'EVENT and prmry_aclk ='1')then
+--------------------------------------            if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+--------------------------------------                p_in_d1_cdc_from  <= '0';
+--------------------------------------            else
+--------------------------------------                p_in_d1_cdc_from  <= prmry_in_xored;
+--------------------------------------            end if;
+--------------------------------------        end if;
+--------------------------------------    end process REG_P_IN;
+
+
+
+REG_P_IN_cdc_from : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_in_d1_cdc_from,
+                              C  => prmry_aclk,
+                              D  => prmry_in_xored,
+                              R  => prmry_reset2
+                            );
+
+
+
+
+
+REG_P_IN2_cdc_to : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d1_cdc_to,
+                              C  => scndry_aclk,
+                              D  => p_in_d1_cdc_from,
+                              R  => scndry_reset2
+                            );
+
+
+
+------------------------------------    P_IN_CROSS2SCNDRY : process(scndry_aclk)
+------------------------------------        begin
+------------------------------------            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+------------------------------------                if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+------------------------------------                    s_out_d2  		<= '0';
+------------------------------------                    s_out_d3  		<= '0';
+------------------------------------                    s_out_d4  		<= '0';
+------------------------------------                    s_out_d5  		<= '0';
+------------------------------------                    s_out_d6  		<= '0';
+------------------------------------                    s_out_d7  		<= '0';
+------------------------------------                    scndry_out          <= '0';
+------------------------------------                else
+------------------------------------                    s_out_d2  		<= s_out_d1_cdc_to;
+------------------------------------                    s_out_d3  		<= s_out_d2;
+------------------------------------                    s_out_d4  		<= s_out_d3;
+------------------------------------                    s_out_d5  		<= s_out_d4;
+------------------------------------                    s_out_d6  		<= s_out_d5;
+------------------------------------                    s_out_d7  		<= s_out_d6;
+------------------------------------                    scndry_out          <= s_out_re;
+------------------------------------                end if;
+------------------------------------            end if;
+------------------------------------        end process P_IN_CROSS2SCNDRY;
+
+
+
+
+P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d2,
+                              C  => scndry_aclk,
+                              D  => s_out_d1_cdc_to,
+                              R  => scndry_reset2
+                            );
+
+
+P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d3,
+                              C  => scndry_aclk,
+                              D  => s_out_d2,
+                              R  => scndry_reset2
+                            );
+
+
+P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d4,
+                              C  => scndry_aclk,
+                              D  => s_out_d3,
+                              R  => scndry_reset2
+                            );
+
+
+P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d5,
+                              C  => scndry_aclk,
+                              D  => s_out_d4,
+                              R  => scndry_reset2
+                            );
+
+
+P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d6,
+                              C  => scndry_aclk,
+                              D  => s_out_d5,
+                              R  => scndry_reset2
+                            );
+
+
+
+P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_out_d7,
+                              C  => scndry_aclk,
+                              D  => s_out_d6,
+                              R  => scndry_reset2
+                            );
+
+
+P_IN_CROSS2SCNDRY_scndry_out : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => scndry_out,
+                              C  => scndry_aclk,
+                              D  => s_out_re,
+                              R  => scndry_reset2
+                            );
+
+s_rst_d1 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d1,
+                              C  => scndry_aclk,
+                              D  => '1',
+                              R  => scndry_reset2
+                            );
+s_rst_d2 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d2,
+                              C  => scndry_aclk,
+                              D  => srst_d1,
+                              R  => scndry_reset2
+                            );
+s_rst_d3 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d3,
+                              C  => scndry_aclk,
+                              D  => srst_d2,
+                              R  => scndry_reset2
+                            );
+
+s_rst_d4 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d4,
+                              C  => scndry_aclk,
+                              D  => srst_d3,
+                              R  => scndry_reset2
+                            );
+
+
+s_rst_d5 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d5,
+                              C  => scndry_aclk,
+                              D  => srst_d4,
+                              R  => scndry_reset2
+                            );
+
+s_rst_d6 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d6,
+                              C  => scndry_aclk,
+                              D  => srst_d5,
+                              R  => scndry_reset2
+                            );
+
+s_rst_d7 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => srst_d7,
+                              C  => scndry_aclk,
+                              D  => srst_d6,
+                              R  => scndry_reset2
+                            );
+
+MTBF_2 : if C_MTBF_STAGES = 2 generate
+begin
+                    s_out_re  <= (s_out_d2 xor s_out_d3) and (srst_d3);
+
+end generate MTBF_2;
+
+MTBF_3 : if C_MTBF_STAGES = 3 generate
+begin
+                    s_out_re  <= (s_out_d3 xor s_out_d4) and (srst_d4);
+
+end generate MTBF_3;
+
+MTBF_4 : if C_MTBF_STAGES = 4 generate
+begin
+                    s_out_re  <= (s_out_d4 xor s_out_d5) and (srst_d5);
+
+end generate MTBF_4;
+
+MTBF_5 : if C_MTBF_STAGES = 5 generate
+begin
+                    s_out_re  <= (s_out_d5 xor s_out_d6) and (srst_d6);
+
+end generate MTBF_5;
+
+MTBF_6 : if C_MTBF_STAGES = 6 generate
+begin
+                    s_out_re  <= (s_out_d6 xor s_out_d7) and (srst_d7);
+
+end generate MTBF_6;
+
+   -- Feed secondary pulse out
+
+end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
+
+
+-- Generate LEVEL clock domain crossing with reset state = 0
+GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
+begin
+-- Primary to Secondary
+
+SINGLE_BIT : if C_SINGLE_BIT = 1 generate 
+
+signal p_level_in_d1_cdc_from        : std_logic := '0';
+signal p_level_in_int        : std_logic := '0';
+signal s_level_out_d1_cdc_to       : std_logic := '0';
+--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
+signal s_level_out_d2       : std_logic := '0';
+signal s_level_out_d3       : std_logic := '0';
+signal s_level_out_d4       : std_logic := '0';
+signal s_level_out_d5       : std_logic := '0';
+signal s_level_out_d6       : std_logic := '0';
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      : STRING;
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to  	: label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6  : label IS "true"; 
+
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Level Clock Crossing                      **
+    --**                        PRIMARY TO SECONDARY                             **
+    --*****************************************************************************
+    -- register is scndry to provide clean ff output to clock crossing logic
+
+scndry_vect_out <= (others => '0');
+prmry_ack <= '0';
+
+
+INPUT_FLOP : if C_FLOP_INPUT = 1 generate
+begin
+
+----------------------------------    REG_PLEVEL_IN : process(prmry_aclk)
+----------------------------------        begin
+----------------------------------            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+----------------------------------                if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+----------------------------------                    p_level_in_d1_cdc_from  <= '0';
+----------------------------------                else
+----------------------------------                    p_level_in_d1_cdc_from  <= prmry_in;
+----------------------------------                end if;
+----------------------------------            end if;
+----------------------------------        end process REG_PLEVEL_IN;
+
+
+REG_PLEVEL_IN_cdc_from : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_in_d1_cdc_from,
+                              C  => prmry_aclk,
+                              D  => prmry_in,
+                              R  => prmry_reset2
+                            );
+
+
+         p_level_in_int <= p_level_in_d1_cdc_from;
+
+end generate INPUT_FLOP;
+
+
+NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
+begin
+
+       p_level_in_int <= prmry_in;
+
+end generate NO_INPUT_FLOP;
+
+
+CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d1_cdc_to,
+                              C  => scndry_aclk,
+                              D  => p_level_in_int,
+                              R  => scndry_reset2
+                            );
+
+
+------------------------------    CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+------------------------------        begin
+------------------------------            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+------------------------------                if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+------------------------------                    s_level_out_d2  <= '0';
+------------------------------                    s_level_out_d3  <= '0';
+------------------------------                    s_level_out_d4  <= '0';
+------------------------------                    s_level_out_d5  <= '0';
+------------------------------                    s_level_out_d6  <= '0';
+------------------------------                else
+------------------------------                    s_level_out_d2  <= s_level_out_d1_cdc_to;
+------------------------------                    s_level_out_d3  <= s_level_out_d2;
+------------------------------                    s_level_out_d4  <= s_level_out_d3;
+------------------------------                    s_level_out_d5  <= s_level_out_d4;
+------------------------------                    s_level_out_d6  <= s_level_out_d5;
+------------------------------                end if;
+------------------------------            end if;
+------------------------------        end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d2,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d1_cdc_to,
+                              R  => scndry_reset2
+                            );
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d3,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d2,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d4,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d3,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d5,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d4,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d6,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d5,
+                              R  => scndry_reset2
+                            );
+
+
+
+
+
+
+
+MTBF_L1 : if C_MTBF_STAGES = 1 generate
+begin
+    scndry_out <= s_level_out_d1_cdc_to;
+                   
+
+end generate MTBF_L1;
+
+MTBF_L2 : if C_MTBF_STAGES = 2 generate
+begin
+
+    scndry_out <= s_level_out_d2;
+                   
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+    
+   scndry_out <= s_level_out_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+    scndry_out <= s_level_out_d4;
+
+               
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+    scndry_out <= s_level_out_d5;
+             
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+    scndry_out <= s_level_out_d6;
+           
+
+end generate MTBF_L6;
+
+end generate SINGLE_BIT;
+
+
+
+MULTI_BIT : if C_SINGLE_BIT = 0 generate 
+
+signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
+signal p_level_in_bus_d1_cdc_from      : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d1_cdc_to       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
+signal s_level_out_bus_d1_cdc_tig       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d2       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d3       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d4       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d5       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d6       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      : STRING;
+  -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2  : SIGNAL IS "true"; 
+  -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3  : SIGNAL IS "true"; 
+  -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4  : SIGNAL IS "true"; 
+  -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5  : SIGNAL IS "true"; 
+  -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6  : SIGNAL IS "true"; 
+
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Level Clock Crossing                      **
+    --**                        PRIMARY TO SECONDARY                             **
+    --*****************************************************************************
+    -- register is scndry to provide clean ff output to clock crossing logic
+
+scndry_out <= '0';
+prmry_ack <= '0';
+
+
+INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
+begin
+
+
+
+-----------------------------------    REG_PLEVEL_IN : process(prmry_aclk)
+-----------------------------------        begin
+-----------------------------------            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+-----------------------------------                if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+-----------------------------------                    p_level_in_bus_d1_cdc_from  <= (others => '0');
+-----------------------------------                else
+-----------------------------------                    p_level_in_bus_d1_cdc_from  <= prmry_vect_in;
+-----------------------------------                end if;
+-----------------------------------            end if;
+-----------------------------------        end process REG_PLEVEL_IN;
+
+FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
+begin
+
+REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_in_bus_d1_cdc_from (i),
+                              C  => prmry_aclk,
+                              D  => prmry_vect_in (i),
+                              R  => prmry_reset2
+                            );
+end generate FOR_REG_PLEVEL_IN;
+
+
+
+
+
+            p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
+
+end generate INPUT_FLOP_BUS;
+
+
+NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
+begin
+
+p_level_in_bus_int <= prmry_vect_in;
+
+end generate NO_INPUT_FLOP_BUS;
+
+FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
+  
+ ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to  : label IS "true"; 
+begin
+
+CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_bus_d1_cdc_to (i),
+                              C  => scndry_aclk,
+                              D  => p_level_in_bus_int (i),
+                              R  => scndry_reset2
+                            );
+end generate FOR_IN_cdc_to;
+
+-----------------------------------------    CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+-----------------------------------------        begin
+-----------------------------------------            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+-----------------------------------------                if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+-----------------------------------------                    s_level_out_bus_d2  <= (others => '0');
+-----------------------------------------                    s_level_out_bus_d3  <= (others => '0');
+-----------------------------------------                    s_level_out_bus_d4  <= (others => '0');
+-----------------------------------------                    s_level_out_bus_d5  <= (others => '0');
+-----------------------------------------                    s_level_out_bus_d6  <= (others => '0');
+-----------------------------------------                else
+-----------------------------------------                    s_level_out_bus_d2  <= s_level_out_bus_d1_cdc_to;
+-----------------------------------------                    s_level_out_bus_d3  <= s_level_out_bus_d2;
+-----------------------------------------                    s_level_out_bus_d4  <= s_level_out_bus_d3;
+-----------------------------------------                    s_level_out_bus_d5  <= s_level_out_bus_d4;
+-----------------------------------------                    s_level_out_bus_d6  <= s_level_out_bus_d5;
+-----------------------------------------                end if;
+-----------------------------------------            end if;
+-----------------------------------------        end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
+  
+ ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2  : label IS "true"; 
+begin
+
+CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_bus_d2 (i),
+                              C  => scndry_aclk,
+                              D  => s_level_out_bus_d1_cdc_to (i),
+                              R  => scndry_reset2
+                            );
+end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
+
+
+FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
+  
+ ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3  : label IS "true"; 
+begin
+
+CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_bus_d3 (i),
+                              C  => scndry_aclk,
+                              D  => s_level_out_bus_d2 (i),
+                              R  => scndry_reset2
+                            );
+end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
+
+
+FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
+  
+ ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4  : label IS "true"; 
+begin
+
+CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_bus_d4 (i),
+                              C  => scndry_aclk,
+                              D  => s_level_out_bus_d3 (i),
+                              R  => scndry_reset2
+                            );
+end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
+
+
+
+FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
+  
+ ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5  : label IS "true"; 
+begin
+
+CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_bus_d5 (i),
+                              C  => scndry_aclk,
+                              D  => s_level_out_bus_d4 (i),
+                              R  => scndry_reset2
+                            );
+end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
+
+
+FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
+  
+ ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6  : label IS "true"; 
+begin
+
+CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_bus_d6 (i),
+                              C  => scndry_aclk,
+                              D  => s_level_out_bus_d5 (i),
+                              R  => scndry_reset2
+                            );
+end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
+
+
+
+MTBF_L1 : if C_MTBF_STAGES = 1 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d1_cdc_to;
+                   
+
+end generate MTBF_L1;
+
+MTBF_L2 : if C_MTBF_STAGES = 2 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d2;
+                   
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+    
+   scndry_vect_out <= s_level_out_bus_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+    scndry_vect_out <= s_level_out_bus_d4;
+
+               
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d5;
+             
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d6;
+           
+
+end generate MTBF_L6;
+
+end generate MULTI_BIT;
+
+
+end generate GENERATE_LEVEL_P_S_CDC;
+
+
+GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
+-- Primary to Secondary
+
+
+signal p_level_in_d1_cdc_from        : std_logic := '0';
+signal p_level_in_int              : std_logic := '0';
+signal s_level_out_d1_cdc_to       : std_logic := '0';
+--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
+signal s_level_out_d2       : std_logic := '0';
+signal s_level_out_d3       : std_logic := '0';
+signal s_level_out_d4       : std_logic := '0';
+signal s_level_out_d5       : std_logic := '0';
+signal s_level_out_d6       : std_logic := '0';
+signal p_level_out_d1_cdc_to       : std_logic := '0';
+--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
+signal p_level_out_d2       : std_logic := '0';
+signal p_level_out_d3       : std_logic := '0';
+signal p_level_out_d4       : std_logic := '0';
+signal p_level_out_d5       : std_logic := '0';
+signal p_level_out_d6       : std_logic := '0';
+signal p_level_out_d7       : std_logic := '0';
+signal scndry_out_int       : std_logic := '0';
+signal prmry_pulse_ack      : std_logic := '0';
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      : STRING;
+  ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to  	: label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6  : label IS "true"; 
+
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2  	  : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3         : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4         : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5         : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6         : label IS "true"; 
+  ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7         : label IS "true"; 
+
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Level Clock Crossing                      **
+    --**                        PRIMARY TO SECONDARY                             **
+    --*****************************************************************************
+    -- register is scndry to provide clean ff output to clock crossing logic
+scndry_vect_out <= (others => '0');
+
+
+INPUT_FLOP : if C_FLOP_INPUT = 1 generate
+begin
+
+------------------------------------------    REG_PLEVEL_IN : process(prmry_aclk)
+------------------------------------------        begin
+------------------------------------------            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+------------------------------------------                if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+------------------------------------------                    p_level_in_d1_cdc_from  <= '0';
+------------------------------------------                else
+------------------------------------------                    p_level_in_d1_cdc_from  <= prmry_in;
+------------------------------------------                end if;
+------------------------------------------            end if;
+------------------------------------------        end process REG_PLEVEL_IN;
+
+
+
+REG_PLEVEL_IN_cdc_from : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_in_d1_cdc_from,
+                              C  => prmry_aclk,
+                              D  => prmry_in,
+                              R  => prmry_reset2
+                            );
+
+
+    p_level_in_int <= p_level_in_d1_cdc_from;
+
+end generate INPUT_FLOP;
+
+
+NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
+begin
+
+    p_level_in_int <= prmry_in;
+
+end generate NO_INPUT_FLOP;
+
+
+CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d1_cdc_to,
+                              C  => scndry_aclk,
+                              D  => p_level_in_int,
+                              R  => scndry_reset2
+                            );
+
+
+------------------------------------------------    CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+------------------------------------------------        begin
+------------------------------------------------            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+------------------------------------------------                if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+------------------------------------------------                    s_level_out_d2  <= '0';
+------------------------------------------------                    s_level_out_d3  <= '0';
+------------------------------------------------                    s_level_out_d4  <= '0';
+------------------------------------------------                    s_level_out_d5  <= '0';
+------------------------------------------------                    s_level_out_d6  <= '0';
+------------------------------------------------                else
+------------------------------------------------                    s_level_out_d2  <= s_level_out_d1_cdc_to;
+------------------------------------------------                    s_level_out_d3  <= s_level_out_d2;
+------------------------------------------------                    s_level_out_d4  <= s_level_out_d3;
+------------------------------------------------                    s_level_out_d5  <= s_level_out_d4;
+------------------------------------------------                    s_level_out_d6  <= s_level_out_d5;
+------------------------------------------------                end if;
+------------------------------------------------            end if;
+------------------------------------------------        end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d2,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d1_cdc_to,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d3,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d2,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d4,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d3,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d5,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d4,
+                              R  => scndry_reset2
+                            );
+
+
+CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => s_level_out_d6,
+                              C  => scndry_aclk,
+                              D  => s_level_out_d5,
+                              R  => scndry_reset2
+                            );
+
+
+
+
+
+
+
+
+---------------------------------------------------    CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
+---------------------------------------------------        begin
+---------------------------------------------------            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+---------------------------------------------------                if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
+---------------------------------------------------                    p_level_out_d1_cdc_to  <= '0';
+---------------------------------------------------                    p_level_out_d2  <= '0';
+---------------------------------------------------                    p_level_out_d3  <= '0';
+---------------------------------------------------                    p_level_out_d4  <= '0';
+---------------------------------------------------                    p_level_out_d5  <= '0';
+---------------------------------------------------                    p_level_out_d6  <= '0';
+---------------------------------------------------                    p_level_out_d7  <= '0';
+---------------------------------------------------                    prmry_ack       <= '0';
+---------------------------------------------------                else
+---------------------------------------------------                    p_level_out_d1_cdc_to  <= scndry_out_int;
+---------------------------------------------------                    p_level_out_d2  <= p_level_out_d1_cdc_to;
+---------------------------------------------------                    p_level_out_d3  <= p_level_out_d2;
+---------------------------------------------------                    p_level_out_d4  <= p_level_out_d3;
+---------------------------------------------------                    p_level_out_d5  <= p_level_out_d4;
+---------------------------------------------------                    p_level_out_d6  <= p_level_out_d5;
+---------------------------------------------------                    p_level_out_d7  <= p_level_out_d6;
+---------------------------------------------------                    prmry_ack       <= prmry_pulse_ack;
+---------------------------------------------------                end if;
+---------------------------------------------------            end if;
+---------------------------------------------------        end process CROSS_PLEVEL_SCNDRY2PRMRY;
+
+
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d1_cdc_to,
+                              C  => prmry_aclk,
+                              D  => scndry_out_int,
+                              R  => prmry_reset2
+                            );
+
+
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d2,
+                              C  => prmry_aclk,
+                              D  => p_level_out_d1_cdc_to,
+                              R  => prmry_reset2
+                            );
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d3,
+                              C  => prmry_aclk,
+                              D  => p_level_out_d2,
+                              R  => prmry_reset2
+                            );
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d4,
+                              C  => prmry_aclk,
+                              D  => p_level_out_d3,
+                              R  => prmry_reset2
+                            );
+
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d5,
+                              C  => prmry_aclk,
+                              D  => p_level_out_d4,
+                              R  => prmry_reset2
+                            );
+
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d6,
+                              C  => prmry_aclk,
+                              D  => p_level_out_d5,
+                              R  => prmry_reset2
+                            );
+
+
+CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => p_level_out_d7,
+                              C  => prmry_aclk,
+                              D  => p_level_out_d6,
+                              R  => prmry_reset2
+                            );
+
+
+CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
+                   generic map(INIT => '0'
+                   )port map (
+                              Q  => prmry_ack,
+                              C  => prmry_aclk,
+                              D  => prmry_pulse_ack,
+                              R  => prmry_reset2
+                            );
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
+begin
+
+    scndry_out_int <= s_level_out_d2;
+    --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
+    prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
+                   
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+    
+   scndry_out_int <= s_level_out_d3;
+   --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
+   prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+    scndry_out_int <= s_level_out_d4;
+   --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
+   prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
+
+               
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+    scndry_out_int <= s_level_out_d5;
+   --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
+   prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
+             
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+    scndry_out_int <= s_level_out_d6;
+   --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
+   prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
+           
+
+end generate MTBF_L6;
+
+       scndry_out <= scndry_out_int;
+
+
+end generate GENERATE_LEVEL_ACK_P_S_CDC;
+
+
+end implementation;
+
+
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
new file mode 100755
index 0000000..a858301
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
@@ -0,0 +1,4463 @@
+-------------------------------------------------------------------------------
+-- lmb_bram_if_funcs.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2001-2015 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        lmb_bram_if_funcs.vhd
+--
+-- Description:     Support functions for lmb_bram_if_cntlr
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--                  lmb_bram_if_funcs.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          stefana
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package lmb_bram_if_funcs is
+
+  type TARGET_FAMILY_TYPE is (
+                              -- pragma xilinx_rtl_off
+                              VIRTEX7,
+                              KINTEX7,
+                              ARTIX7,
+                              ZYNQ,
+                              VIRTEXU,
+                              KINTEXU,
+                              ZYNQUPLUS,
+                              VIRTEXUPLUS,
+                              KINTEXUPLUS,
+                              SPARTAN7,
+                              VERSAL,
+                              -- pragma xilinx_rtl_on
+                              RTL
+                             );
+
+  function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
+
+  -- Get the maximum number of inputs to a LUT.
+  function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
+
+end package lmb_bram_if_funcs;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package body lmb_bram_if_funcs is
+
+  function LowerCase_Char(char : character) return character is
+  begin
+    -- If char is not an upper case letter then return char
+    if char < 'A' or char > 'Z' then
+      return char;
+    end if;
+    -- Otherwise map char to its corresponding lower case character and
+    -- return that
+    case char is
+      when 'A'    => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
+      when 'E'    => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
+      when 'I'    => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
+      when 'M'    => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
+      when 'Q'    => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
+      when 'U'    => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
+      when 'Y'    => return 'y'; when 'Z' => return 'z';
+      when others => return char;
+    end case;
+  end LowerCase_Char;
+
+  -- Returns true if case insensitive string comparison determines that
+  -- str1 and str2 are equal
+  function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
+    CONSTANT len1 : INTEGER := str1'length;
+    CONSTANT len2 : INTEGER := str2'length;
+    VARIABLE equal : BOOLEAN := TRUE;
+  BEGIN
+    IF NOT (len1=len2) THEN
+      equal := FALSE;
+    ELSE
+      FOR i IN str1'range LOOP
+        IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
+          equal := FALSE;
+        END IF;
+      END LOOP;
+    END IF;
+
+    RETURN equal;
+  END Equal_String;
+
+  function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
+  begin  -- function String_To_Family
+    if ((Select_RTL) or Equal_String(S, "rtl")) then
+      return RTL;
+    elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
+      return VIRTEX7;
+    elsif Equal_String(S, "kintex7")  or Equal_String(S, "kintex7l")  or
+          Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
+      return KINTEX7;
+    elsif Equal_String(S, "artix7")  or Equal_String(S, "artix7l")  or Equal_String(S, "aartix7") or
+          Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
+      return ARTIX7;
+    elsif Equal_String(S, "zynq")  or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
+      return ZYNQ;
+    elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
+      return VIRTEXU;
+    elsif Equal_String(S, "kintexu")  or Equal_String(S, "kintexul")  or
+          Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
+      return KINTEXU;
+    elsif Equal_String(S, "zynquplus") or Equal_String(S, "zynquplusRFSOC") then
+      return ZYNQUPLUS;
+    elsif Equal_String(S, "virtexuplus") or Equal_String(S, "virtexuplusHBM") or
+          Equal_String(S, "virtexuplus58g") then
+      return VIRTEXUPLUS;
+    elsif Equal_String(S, "kintexuplus") then
+      return KINTEXUPLUS;
+    elsif Equal_String(S, "spartan7") then
+      return SPARTAN7;
+    elsif Equal_String(S, "versal") or Equal_String(S, "everestea") then
+      return VERSAL;
+    else
+      -- assert (false) report "No known target family" severity failure;
+      return RTL;
+    end if;
+  end function String_To_Family;
+
+  function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
+  begin
+    return 6;
+  end function Family_To_LUT_Size;
+
+end package body lmb_bram_if_funcs;
+
+
+-------------------------------------------------------------------------------
+-- primitives.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        primitives.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              lmb_bram_if_primitives.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+--
+-- History:
+--   rolandp  2015-01-22    First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+----- entity LUT6 -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity MB_LUT6 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT     : bit_vector := X"0000000000000000"
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    I2 : in  std_logic;
+    I3 : in  std_logic;
+    I4 : in  std_logic;
+    I5 : in  std_logic
+  );
+end entity MB_LUT6;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_LUT6 is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+    constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
+  begin
+    process (I0, I1, I2, I3, I4, I5)
+      variable I_reg    : std_logic_vector(5 downto 0);
+      variable I0_v, I1_v, I2_v, I3_v, I4_v, I5_v : std_logic;
+    begin
+      -- Filter unknowns
+      if I0 = '0' then I0_v := '0'; else I0_v := '1'; end if;
+      if I1 = '0' then I1_v := '0'; else I1_v := '1'; end if;
+      if I2 = '0' then I2_v := '0'; else I2_v := '1'; end if;
+      if I3 = '0' then I3_v := '0'; else I3_v := '1'; end if;
+      if I4 = '0' then I4_v := '0'; else I4_v := '1'; end if;
+      if I5 = '0' then I5_v := '0'; else I5_v := '1'; end if;
+      I_reg := TO_STDLOGICVECTOR(I5_v & I4_v & I3_v &  I2_v & I1_v & I0_v);
+      O     <= INIT_reg(TO_INTEGER(unsigned(I_reg)));
+    end process;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: LUT6
+      generic map(
+        INIT    => INIT
+      )
+      port map(
+        O       => O,
+        I0      => I0,
+        I1      => I1,
+        I2      => I2,
+        I3      => I3,
+        I4      => I4,
+        I5      => I5
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MUXCY -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity MB_MUXCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    LO : out std_logic;
+    CI : in  std_logic;
+    DI : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXCY;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXCY is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    LO <= DI when S = '0' else CI;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MUXCY_L
+      port map(
+        LO => LO,
+        CI => CI,
+        DI => DI,
+        S  => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity XORCY -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity MB_XORCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    CI : in  std_logic;
+    LI : in  std_logic
+  );
+end entity MB_XORCY;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_XORCY is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= (CI xor LI);
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: XORCY
+      port map(
+        O  => O,
+        CI => CI,
+        LI => LI
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MUXF7 -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity MB_MUXF7 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXF7;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXF7 is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= I0 when S = '0' else I1;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MUXF7
+      port map(
+        O  => O,
+        I0 => I0,
+        I1 => I1,
+        S  => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity MUXF8 -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity MB_MUXF8 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+end entity MB_MUXF8;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_MUXF8 is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    O <= I0 when S = '0' else I1;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: MUXF8
+      port map(
+        O  => O,
+        I0 => I0,
+        I1 => I1,
+        S  => S
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+----- entity FDRE -----
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity MB_FDRE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0'
+  );
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    R  : in  std_logic
+  );
+end entity MB_FDRE;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+architecture IMP of MB_FDRE is
+begin
+  
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+    function To_StdLogic(A : in bit ) return std_logic is
+    begin
+      if( A = '1' ) then
+        return '1';
+      end if;
+      return '0';
+    end;
+
+    signal q_o : std_logic := To_StdLogic(INIT);
+  begin
+    Q <=  q_o;
+    process(C)
+    begin
+      if (rising_edge(C)) then
+        if (R = '1') then
+          q_o <= '0';
+        elsif (CE = '1') then
+          q_o <= D;
+        end if;
+      end if;
+    end process;
+  end generate Using_RTL;
+  
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+  begin
+    Native: FDRE
+      generic map(
+        INIT => INIT
+      )
+      port map(
+        Q   => Q,
+        C   => C,
+        CE  => CE,
+        D   => D,
+        R   => R
+      );
+  end generate Using_FPGA;
+  
+end architecture IMP;
+
+
+
+-------------------------------------------------------------------------------
+-- xor18.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        xor18.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--              xor18.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity XOR18 is 
+  generic (
+    C_TARGET   : TARGET_FAMILY_TYPE);
+  port (
+    InA : in  std_logic_vector(0 to 17);
+    res : out std_logic);
+end entity XOR18;
+
+architecture IMP of XOR18 is
+
+  component MB_LUT6 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT     : bit_vector := X"0000000000000000"
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    I2 : in  std_logic;
+    I3 : in  std_logic;
+    I4 : in  std_logic;
+    I5 : in  std_logic
+  );
+  end component MB_LUT6;
+
+  component MB_MUXCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    LO : out std_logic;
+    CI : in  std_logic;
+    DI : in  std_logic;
+    S  : in  std_logic
+  );
+  end component MB_MUXCY;
+
+  component MB_XORCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    CI : in  std_logic;
+    LI : in  std_logic
+  );
+  end component MB_XORCY;
+
+begin  -- architecture IMP
+
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+    signal xor6_1   : std_logic;
+    signal xor6_2   : std_logic;
+    signal xor6_3   : std_logic;
+    signal xor18_c1 : std_logic;
+    signal xor18_c2 : std_logic;
+  begin  -- generate Using_LUT6
+
+    XOR6_1_LUT : MB_LUT6
+      generic map(
+        C_TARGET => C_TARGET,
+        INIT => X"6996966996696996")
+      port map(
+        O    => xor6_1,
+        I0   => InA(17),
+        I1   => InA(16),
+        I2   => InA(15),
+        I3   => InA(14),
+        I4   => InA(13),
+        I5   => InA(12));
+
+    XOR_1st_MUXCY : MB_MUXCY
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        DI => '1',
+        CI => '0',
+        S  => xor6_1,
+        LO => xor18_c1);
+
+    XOR6_2_LUT : MB_LUT6
+      generic map(
+        C_TARGET => C_TARGET,
+        INIT => X"6996966996696996")
+      port map(
+        O    => xor6_2,
+        I0   => InA(11),
+        I1   => InA(10),
+        I2   => InA(9),
+        I3   => InA(8),
+        I4   => InA(7),
+        I5   => InA(6));
+
+    XOR_2nd_MUXCY : MB_MUXCY
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        DI => xor6_1,
+        CI => xor18_c1,
+        S  => xor6_2,
+        LO => xor18_c2);
+
+    XOR6_3_LUT : MB_LUT6
+      generic map(
+        C_TARGET => C_TARGET,
+        INIT => X"6996966996696996")
+      port map(
+        O    => xor6_3,
+        I0   => InA(5),
+        I1   => InA(4),
+        I2   => InA(3),
+        I3   => InA(2),
+        I4   => InA(1),
+        I5   => InA(0));
+
+    XOR18_XORCY : MB_XORCY
+      generic map(
+        C_TARGET => C_TARGET)
+      port map (
+        LI => xor6_3,
+        CI => xor18_c2,
+        O  => res);
+    
+  end generate Using_FPGA;
+
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin 
+
+    res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
+           InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
+           InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);    
+
+  end generate Using_RTL;
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- parity.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        parity.vhd
+--
+-- Description:     Generate parity optimally for all target architectures
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--                  parity.vhd
+--                    xor18.vhd
+--                    parity_recursive_LUT6.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          stefana
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity Parity is
+  generic (
+    C_TARGET   : TARGET_FAMILY_TYPE;
+    C_SIZE     : integer := 6
+    );
+  port (
+    InA : in  std_logic_vector(0 to C_SIZE - 1);
+    Res : out std_logic
+    );
+end entity Parity;
+
+architecture IMP of Parity is
+
+  component MB_LUT6 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT     : bit_vector := X"0000000000000000"
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    I2 : in  std_logic;
+    I3 : in  std_logic;
+    I4 : in  std_logic;
+    I5 : in  std_logic
+  );
+  end component MB_LUT6;
+
+  component MB_MUXF7 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+  end component MB_MUXF7;
+  
+  component MB_MUXF8 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+  end component MB_MUXF8;
+
+  -- Non-recursive loop implementation
+  function ParityGen (InA : std_logic_vector) return std_logic is
+    variable result : std_logic;
+  begin
+    result := '0';
+    for I in InA'range loop
+      result := result xor InA(I);
+    end loop;
+    return result;
+  end function ParityGen;
+
+begin  -- architecture IMP
+
+  Using_FPGA : if (C_TARGET /= RTL) generate
+
+    --------------------------------------------------------------------------------------------------
+    -- Single LUT6
+    --------------------------------------------------------------------------------------------------
+    Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
+      signal inA6 : std_logic_vector(0 to 5);
+    begin
+
+      Assign_InA : process (InA) is
+      begin
+        inA6                      <= (others => '0');
+        inA6(0 to InA'length - 1) <= InA;
+      end process Assign_InA;
+
+      XOR6_LUT : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"6996966996696996")
+        port map(
+          O  => Res,
+          I0 => inA6(5),
+          I1 => inA6(4),
+          I2 => inA6(3),
+          I3 => inA6(2),
+          I4 => inA6(1),
+          I5 => inA6(0));
+    end generate Single_LUT6;
+
+    --------------------------------------------------------------------------------------------------
+    -- Two LUT6 and one MUXF7
+    --------------------------------------------------------------------------------------------------
+    Use_MUXF7 : if C_SIZE = 7 generate
+      signal inA7     : std_logic_vector(0 to 6);
+      signal result6  : std_logic;
+      signal result6n : std_logic;
+    begin
+
+      Assign_InA : process (InA) is
+      begin
+        inA7                      <= (others => '0');
+        inA7(0 to InA'length - 1) <= InA;
+      end process Assign_InA;
+
+      XOR6_LUT : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"6996966996696996")
+        port map(
+          O  => result6,
+          I0 => inA7(5),
+          I1 => inA7(4),
+          I2 => inA7(3),
+          I3 => inA7(2),
+          I4 => inA7(1),
+          I5 => inA7(0));
+
+      XOR6_LUT_N : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"9669699669969669") 
+        port map(
+          O  => result6n,
+          I0 => inA7(5),
+          I1 => inA7(4),
+          I2 => inA7(3),
+          I3 => inA7(2),
+          I4 => inA7(1),
+          I5 => inA7(0));
+
+      MUXF7_LUT : MB_MUXF7
+        generic map(
+          C_TARGET => C_TARGET)
+        port map (
+          O  => Res,
+          I0 => result6,
+          I1 => result6n,
+          S  => inA7(6));
+    end generate Use_MUXF7;
+
+    --------------------------------------------------------------------------------------------------
+    -- Four LUT6, two MUXF7 and one MUXF8
+    --------------------------------------------------------------------------------------------------
+    Use_MUXF8 : if C_SIZE = 8 generate
+      signal inA8       : std_logic_vector(0 to 7);
+      signal result6_1  : std_logic;
+      signal result6_1n : std_logic;
+      signal result6_2  : std_logic;
+      signal result6_2n : std_logic;
+      signal result7_1  : std_logic;
+      signal result7_1n : std_logic;
+    begin
+
+      Assign_InA : process (InA) is
+      begin
+        inA8                      <= (others => '0');
+        inA8(0 to InA'length - 1) <= InA;
+      end process Assign_InA;
+
+      XOR6_LUT1 : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"6996966996696996")
+        port map(
+          O  => result6_1,
+          I0 => inA8(5),
+          I1 => inA8(4),
+          I2 => inA8(3),
+          I3 => inA8(2),
+          I4 => inA8(1),
+          I5 => inA8(0));
+
+      XOR6_LUT2_N : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"9669699669969669") 
+        port map(
+          O  => result6_1n,
+          I0 => inA8(5),
+          I1 => inA8(4),
+          I2 => inA8(3),
+          I3 => inA8(2),
+          I4 => inA8(1),
+          I5 => inA8(0));
+
+      MUXF7_LUT1 : MB_MUXF7
+        generic map(
+          C_TARGET => C_TARGET)
+        port map (
+          O  => result7_1,
+          I0 => result6_1,
+          I1 => result6_1n,
+          S  => inA8(6));
+
+      XOR6_LUT3 : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"6996966996696996")
+        port map(
+          O  => result6_2,
+          I0 => inA8(5),
+          I1 => inA8(4),
+          I2 => inA8(3),
+          I3 => inA8(2),
+          I4 => inA8(1),
+          I5 => inA8(0));
+
+      XOR6_LUT4_N : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"9669699669969669") 
+        port map(
+          O  => result6_2n,
+          I0 => inA8(5),
+          I1 => inA8(4),
+          I2 => inA8(3),
+          I3 => inA8(2),
+          I4 => inA8(1),
+          I5 => inA8(0));
+
+      MUXF7_LUT2 : MB_MUXF7
+        generic map(
+          C_TARGET => C_TARGET)
+        port map (
+          O  => result7_1n,
+          I0 => result6_2n,
+          I1 => result6_2,
+          S  => inA8(6));
+
+      MUXF8_LUT : MB_MUXF8
+        generic map(
+          C_TARGET => C_TARGET)
+        port map (
+          O  => res,
+          I0 => result7_1,
+          I1 => result7_1n,
+          S  => inA8(7));
+
+    end generate Use_MUXF8;
+  end generate Using_FPGA;
+
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    Res <= ParityGen(InA);
+  end generate Using_RTL;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- parityenable.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        parity.vhd
+--
+-- Description:     Generate parity optimally for all target architectures
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--                  parity.vhd
+--                    xor18.vhd
+--                    parity_recursive_LUT6.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          stefana
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity ParityEnable is
+  generic (
+    C_TARGET   : TARGET_FAMILY_TYPE;
+    C_SIZE     :     integer := 4
+    );
+  port (
+    InA        : in  std_logic_vector(0 to C_SIZE - 1);
+    Enable     : in  std_logic;
+    Res        : out std_logic
+    );
+end entity ParityEnable;
+
+architecture IMP of ParityEnable is
+
+  -- Non-recursive loop implementation
+  function ParityGen (InA : std_logic_vector) return std_logic is
+    variable result : std_logic;
+  begin
+    result := '0';
+    for I in InA'range loop
+      result := result xor InA(I);
+    end loop;
+    return result;
+  end function ParityGen;
+
+  component MB_LUT6 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT     : bit_vector := X"0000000000000000"
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    I2 : in  std_logic;
+    I3 : in  std_logic;
+    I4 : in  std_logic;
+    I5 : in  std_logic
+  );
+  end component MB_LUT6;
+
+begin  -- architecture IMP
+
+  Using_FPGA: if ( C_TARGET /= RTL ) generate 
+
+    --------------------------------------------------------------------------------------------------
+    -- Single LUT6
+    --------------------------------------------------------------------------------------------------
+    Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
+      signal inA5 : std_logic_vector(0 to 4);
+    begin
+
+      Assign_InA : process (InA) is
+      begin
+        inA5                      <= (others => '0');
+        inA5(0 to InA'length - 1) <= InA;
+      end process Assign_InA;
+
+      XOR6_LUT : MB_LUT6
+        generic map(
+          C_TARGET => C_TARGET,
+          INIT => X"9669699600000000")
+        port map(
+          O  => Res,
+          I0 => InA5(4),
+          I1 => inA5(3),
+          I2 => inA5(2),
+          I3 => inA5(1),
+          I4 => inA5(0),
+          I5 => Enable);
+    end generate Single_LUT6;
+
+  end generate Using_FPGA;
+
+  Using_RTL: if ( C_TARGET = RTL ) generate 
+  begin
+    Res <= Enable and ParityGen(InA);
+  end generate Using_RTL;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- checkbit_handler.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Filename:        gen_checkbits.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93/02
+-------------------------------------------------------------------------------
+-- Structure:   
+--              gen_checkbits.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity checkbit_handler is
+  generic (
+    C_TARGET   : TARGET_FAMILY_TYPE;
+    C_ENCODE   : boolean := true);
+  port (
+    DataIn     : in  std_logic_vector(0 to 31);
+    CheckIn    : in  std_logic_vector(0 to 6);
+    CheckOut   : out std_logic_vector(0 to 6);
+    Syndrome   : out std_logic_vector(0 to 6);
+    Enable_ECC : in  std_logic;
+    UE_Q       : in  std_logic;
+    CE_Q       : in  std_logic;
+    UE         : out std_logic;
+    CE         : out std_logic
+    );
+end entity checkbit_handler;
+
+architecture IMP of checkbit_handler is
+
+  component XOR18 is
+    generic (
+      C_TARGET   : TARGET_FAMILY_TYPE);
+    port (
+      InA : in  std_logic_vector(0 to 17);
+      res : out std_logic);
+  end component XOR18;
+  
+  component Parity is
+    generic (
+      C_TARGET   : TARGET_FAMILY_TYPE;
+      C_SIZE     : integer);
+    port (
+      InA : in  std_logic_vector(0 to C_SIZE - 1);
+      Res : out std_logic);
+  end component Parity;
+
+  component ParityEnable
+    generic (
+      C_TARGET   : TARGET_FAMILY_TYPE;
+      C_SIZE     : integer);
+    port (
+      InA    : in  std_logic_vector(0 to C_SIZE - 1);
+      Enable : in  std_logic;
+      Res    : out std_logic);
+  end component ParityEnable;
+
+  component MB_MUXF7 is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    I0 : in  std_logic;
+    I1 : in  std_logic;
+    S  : in  std_logic
+  );
+  end component MB_MUXF7;
+  
+  signal data_chk0 : std_logic_vector(0 to 17);
+  signal data_chk1 : std_logic_vector(0 to 17);
+  signal data_chk2 : std_logic_vector(0 to 17);
+  signal data_chk3 : std_logic_vector(0 to 14);
+  signal data_chk4 : std_logic_vector(0 to 14);
+  signal data_chk5 : std_logic_vector(0 to 5);
+  
+begin  -- architecture IMP
+  data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
+               DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
+               DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
+
+  data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
+               DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
+               DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
+
+  data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
+               DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
+               DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
+
+  data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
+               DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
+               DataIn(25);
+
+  data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
+               DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
+               DataIn(25);
+
+  data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
+
+  -- Encode bits for writing data
+  Encode_Bits : if (C_ENCODE) generate
+    signal data_chk3_i : std_logic_vector(0 to 17);
+    signal data_chk4_i : std_logic_vector(0 to 17);
+    signal data_chk6   : std_logic_vector(0 to 17);
+  begin
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 0 built up using XOR18
+    ------------------------------------------------------------------------------------------------
+    XOR18_I0 : XOR18
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        InA => data_chk0,               -- [in  std_logic_vector(0 to 17)]
+        res => CheckOut(0));            -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 1 built up using XOR18
+    ------------------------------------------------------------------------------------------------
+    XOR18_I1 : XOR18
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        InA => data_chk1,               -- [in  std_logic_vector(0 to 17)]
+        res => CheckOut(1));            -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 2 built up using XOR18
+    ------------------------------------------------------------------------------------------------
+    XOR18_I2 : XOR18
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        InA => data_chk2,               -- [in  std_logic_vector(0 to 17)]
+        res => CheckOut(2));            -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 3 built up using XOR18
+    ------------------------------------------------------------------------------------------------
+    data_chk3_i <= data_chk3 & "000";
+    XOR18_I3 : XOR18
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        InA => data_chk3_i,             -- [in  std_logic_vector(0 to 17)]
+        res => CheckOut(3));            -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 4 built up using XOR18
+    ------------------------------------------------------------------------------------------------
+    data_chk4_i <= data_chk4 & "000";
+    XOR18_I4 : XOR18
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        InA => data_chk4_i,             -- [in  std_logic_vector(0 to 17)]
+        res => CheckOut(4));            -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 5 built up from 1 LUT6
+    ------------------------------------------------------------------------------------------------
+    Parity_chk5_1 : Parity
+      generic map (
+        C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk5,             -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => CheckOut(5));          -- [out std_logic]
+    
+    ------------------------------------------------------------------------------------------------
+    -- Checkbit 6 built up from 3 LUT7 and 4 LUT6
+    ------------------------------------------------------------------------------------------------
+    data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
+                 DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
+                 DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
+    XOR18_I6 : XOR18
+      generic map (
+        C_TARGET => C_TARGET)       -- [boolean]
+      port map (
+        InA => data_chk6,             -- [in  std_logic_vector(0 to 17)]
+        res => CheckOut(6));            -- [out std_logic]
+
+    -- Unused
+    Syndrome <= (others => '0');
+    UE       <= '0';
+    CE       <= '0';
+  end generate Encode_Bits;
+
+  --------------------------------------------------------------------------------------------------
+  -- Decode bits to get syndrome and UE/CE signals
+  --------------------------------------------------------------------------------------------------
+  Decode_Bits : if (not C_ENCODE) generate
+    signal syndrome_i  : std_logic_vector(0 to 6);
+    signal chk0_1 : std_logic_vector(0 to 3);
+    signal chk1_1 : std_logic_vector(0 to 3);
+    signal chk2_1 : std_logic_vector(0 to 3);
+    signal data_chk3_i : std_logic_vector(0 to 15);
+    signal chk3_1 : std_logic_vector(0 to 1);
+    signal data_chk4_i : std_logic_vector(0 to 15);
+    signal chk4_1 : std_logic_vector(0 to 1);
+    signal data_chk5_i : std_logic_vector(0 to 6);
+    signal data_chk6   : std_logic_vector(0 to 38);
+    signal chk6_1 : std_logic_vector(0 to 5);
+
+    signal syndrome_3_to_5       : std_logic_vector(3 to 5);
+    signal syndrome_3_to_5_multi : std_logic;
+    signal syndrome_3_to_5_zero  : std_logic;
+    signal ue_i_0 : std_logic;
+    signal ue_i_1 : std_logic;
+
+  begin
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
+    ------------------------------------------------------------------------------------------------
+    chk0_1(3) <= CheckIn(0);
+    Parity_chk0_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA                   => data_chk0(0 to 5),  -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res                   => chk0_1(0));  -- [out std_logic]
+    Parity_chk0_2 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA                   => data_chk0(6 to 11),  -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res                   => chk0_1(1));  -- [out std_logic]
+    Parity_chk0_3 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA                   => data_chk0(12 to 17),  -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res                   => chk0_1(2));  -- [out std_logic]
+    Parity_chk0_4 : ParityEnable
+      generic map (C_TARGET => C_TARGET, C_SIZE => 4)
+      port map (
+        InA                   => chk0_1,  -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Enable                => Enable_ECC,  -- [in  std_logic]
+        Res                   => syndrome_i(0));  -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
+    ------------------------------------------------------------------------------------------------
+    chk1_1(3) <= CheckIn(1);
+    Parity_chk1_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk1(0 to 5),       -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk1_1(0));              -- [out std_logic]
+    Parity_chk1_2 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk1(6 to 11),      -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk1_1(1));              -- [out std_logic]
+    Parity_chk1_3 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk1(12 to 17),     -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk1_1(2));              -- [out std_logic]
+    Parity_chk1_4 : ParityEnable      
+      generic map (C_TARGET => C_TARGET, C_SIZE => 4)
+      port map (
+        InA => chk1_1,             -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Enable => Enable_ECC,  -- [in  std_logic]
+        Res => syndrome_i(1));          -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
+    ------------------------------------------------------------------------------------------------
+    chk2_1(3) <= CheckIn(2);
+    Parity_chk2_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk2(0 to 5),       -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk2_1(0));              -- [out std_logic]
+    Parity_chk2_2 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk2(6 to 11),      -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk2_1(1));              -- [out std_logic]
+    Parity_chk2_3 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk2(12 to 17),     -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk2_1(2));              -- [out std_logic]
+    Parity_chk2_4 : ParityEnable
+      generic map (C_TARGET => C_TARGET, C_SIZE => 4)
+      port map (
+        InA => chk2_1,             -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Enable => Enable_ECC,  -- [in  std_logic]
+        Res => syndrome_i(2));          -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
+    ------------------------------------------------------------------------------------------------
+    data_chk3_i <= data_chk3 & CheckIn(3);
+    Parity_chk3_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 8)
+      port map (
+        InA => data_chk3_i(0 to 7),       -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk3_1(0));              -- [out std_logic]
+    Parity_chk3_2 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 8)
+      port map (
+        InA => data_chk3_i(8 to 15),      -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk3_1(1));              -- [out std_logic]
+    Parity_chk3_3 : ParityEnable
+      generic map (C_TARGET => C_TARGET, C_SIZE => 2)
+      port map (
+        InA => chk3_1,                  -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Enable => Enable_ECC,  -- [in  std_logic]
+        Res => syndrome_i(3));              -- [out std_logic]
+
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
+    ------------------------------------------------------------------------------------------------
+    data_chk4_i <= data_chk4 & CheckIn(4);
+    Parity_chk4_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 8)
+      port map (
+        InA => data_chk4_i(0 to 7),       -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk4_1(0));              -- [out std_logic]
+    Parity_chk4_2 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 8)
+      port map (
+        InA => data_chk4_i(8 to 15),      -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk4_1(1));              -- [out std_logic]
+    Parity_chk4_3 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 2)
+      port map (
+        InA => chk4_1,                  -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => syndrome_i(4));              -- [out std_logic]
+
+
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 5 built up from 1 LUT7
+    ------------------------------------------------------------------------------------------------
+    data_chk5_i <= data_chk5 & CheckIn(5);
+    Parity_chk5_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 7)
+      port map (
+        InA => data_chk5_i,             -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => syndrome_i(5));          -- [out std_logic]
+    
+    ------------------------------------------------------------------------------------------------
+    -- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
+    ------------------------------------------------------------------------------------------------
+    data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
+                 DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
+                 DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
+                 DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
+                 DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
+                 CheckIn(1) & CheckIn(0) & CheckIn(6);
+    Parity_chk6_1 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk6(0 to 5),       -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk6_1(0));              -- [out std_logic]
+    Parity_chk6_2 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk6(6 to 11),      -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk6_1(1));              -- [out std_logic]
+    Parity_chk6_3 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => data_chk6(12 to 17),     -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk6_1(2));              -- [out std_logic]
+    Parity_chk6_4 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 7)
+      port map (
+        InA => data_chk6(18 to 24),     -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk6_1(3));              -- [out std_logic]
+    Parity_chk6_5 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 7)
+      port map (
+        InA => data_chk6(25 to 31),     -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk6_1(4));              -- [out std_logic]
+    Parity_chk6_6 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 7)
+      port map (
+        InA => data_chk6(32 to 38),     -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => chk6_1(5));              -- [out std_logic]
+    Parity_chk6_7 : Parity
+      generic map (C_TARGET => C_TARGET, C_SIZE => 6)
+      port map (
+        InA => chk6_1,             -- [in  std_logic_vector(0 to C_SIZE - 1)]
+        Res => syndrome_i(6));          -- [out std_logic]
+
+    Syndrome <= syndrome_i;
+    
+    syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
+    syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
+    syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
+                                       syndrome_3_to_5 = "011" or
+                                       syndrome_3_to_5 = "101") else
+                             '0';
+
+    CE <= '0' when (Enable_ECC = '0') else
+          (syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
+          CE_Q;
+
+    ue_i_0 <= '0' when (Enable_ECC = '0') else
+              '1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
+              UE_Q;
+    ue_i_1 <= '0' when (Enable_ECC = '0') else
+              (syndrome_3_to_5_multi or UE_Q);
+
+    Use_FPGA: if (C_TARGET /= RTL) generate
+      UE_MUXF7 : MB_MUXF7
+        generic map (
+          C_TARGET => C_TARGET)
+        port map (
+          I0 => ue_i_0,
+          I1 => ue_i_1,
+          S  => syndrome_i(6),
+          O  => UE);      
+    end generate Use_FPGA;
+
+    Use_RTL: if (C_TARGET = RTL) generate
+      UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
+    end generate Use_RTL;
+
+    -- Unused
+    CheckOut <= (others => '0');
+  end generate Decode_Bits;
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- correct_one_bit.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        correct_one_bit.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--              correct_one_bit
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity Correct_One_Bit is
+  generic (
+    C_TARGET      : TARGET_FAMILY_TYPE;
+    Correct_Value : std_logic_vector(0 to 6));
+  port (
+    DIn      : in  std_logic;
+    Syndrome : in  std_logic_vector(0 to 6);
+    DCorr    : out std_logic);
+end entity Correct_One_Bit;
+
+architecture IMP of Correct_One_Bit is
+
+  component MB_MUXCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    LO : out std_logic;
+    CI : in  std_logic;
+    DI : in  std_logic;
+    S  : in  std_logic
+  );
+  end component MB_MUXCY;
+
+  component MB_XORCY is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE
+  );
+  port (
+    O  : out std_logic;
+    CI : in  std_logic;
+    LI : in  std_logic
+  );
+  end component MB_XORCY;
+
+  -----------------------------------------------------------------------------
+  -- Find which bit that has a '1'
+  -- There is always one bit which has a '1'
+  -----------------------------------------------------------------------------
+  function find_one (Syn : std_logic_vector(0 to 6)) return natural is
+  begin  -- function find_one
+    for I in 0 to 6 loop
+      if (Syn(I) = '1') then
+        return I;
+      end if;
+    end loop;  -- I
+    return 0;                           -- Should never reach this statement
+  end function find_one;
+
+  constant di_index : natural := find_one(Correct_Value);
+
+  signal corr_sel : std_logic;
+  signal corr_c   : std_logic;
+  signal lut_compare  : std_logic_vector(0 to 5);
+  signal lut_corr_val : std_logic_vector(0 to 5);
+begin  -- architecture IMP
+
+  Remove_DI_Index : process (Syndrome) is
+  begin  -- process Remove_DI_Index
+    if (di_index = 0) then
+      lut_compare  <= Syndrome(1 to 6);
+      lut_corr_val <= Correct_Value(1 to 6);
+    elsif (di_index = 6) then
+      lut_compare  <= Syndrome(0 to 5);
+      lut_corr_val <= Correct_Value(0 to 5);
+    else
+      lut_compare  <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
+      lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
+    end if;
+  end process Remove_DI_Index;
+
+  corr_sel <= '0' when lut_compare = lut_corr_val else '1';
+  
+  Corr_MUXCY : MB_MUXCY
+    generic map(
+      C_TARGET => C_TARGET)
+    port map (
+      DI => Syndrome(di_index),
+      CI => '0',
+      S  => corr_sel,
+      LO => corr_c);
+
+  Corr_XORCY : MB_XORCY
+    generic map(
+      C_TARGET => C_TARGET)
+    port map (
+      LI => DIn,
+      CI => corr_c,
+      O  => DCorr);
+
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- pselect_mask.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        pselect_mask.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              pselect_mask.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          goran
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity pselect_mask is
+
+  generic (
+    C_AW   : integer                   := 32;
+    C_BAR  : std_logic_vector(0 to 63) := X"0000000000020000";
+    C_MASK : std_logic_vector(0 to 63) := X"000000000007C000"
+    );
+  port (
+    A     : in  std_logic_vector(0 to C_AW-1);
+    Valid : in  std_logic;
+    CS    : out std_logic
+    );
+
+end entity pselect_mask;
+
+architecture imp of pselect_mask is
+
+  function Nr_Of_Ones (S : std_logic_vector) return natural is
+    variable tmp : natural := 0;
+  begin  -- function Nr_Of_Ones
+    for I in S'range loop
+      if (S(I) = '1') then
+        tmp := tmp + 1;
+      end if;
+    end loop;  -- I
+    return tmp;
+  end function Nr_Of_Ones;
+
+  function fix_AB (B : boolean; I : integer) return integer is
+  begin  -- function fix_AB
+    if (not B) then
+      return I + 1;
+    else
+      return I;
+    end if;
+  end function fix_AB;
+
+  constant Nr      : integer := Nr_Of_Ones(C_MASK(64 - C_AW to 63));
+  constant Use_CIN : boolean := ((Nr mod 4) = 0);
+  constant AB      : integer := fix_AB(Use_CIN, Nr);
+  
+  signal A_Bus : std_logic_vector(0 to AB);
+  signal BAR   : std_logic_vector(0 to AB);
+
+-------------------------------------------------------------------------------
+-- Begin architecture section
+-------------------------------------------------------------------------------
+begin  -- VHDL_RTL
+
+  Make_Busses : process (A,Valid) is
+    variable tmp : natural;
+  begin  -- process Make_Busses
+    tmp   := 0;
+    A_Bus <= (others => '0');
+    BAR   <= (others => '0');
+    for I in 0 to C_AW - 1 loop
+      if (C_MASK(64 - C_AW + I) = '1') then
+        A_Bus(tmp) <= A(I);
+        BAR(tmp)   <= C_BAR(64 - C_AW + I);
+        tmp        := tmp + 1;
+      end if;
+    end loop;  -- I
+    if (not Use_CIN) then
+      BAR(tmp) <= '1';
+      A_Bus(tmp) <= Valid;
+    end if;
+  end process Make_Busses;
+
+  CS <= Valid when A_Bus=BAR else '0';
+
+end imp;
+
+
+-------------------------------------------------------------------------------
+-- axi_interface.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-------------------------------------------------------------------------------
+-- Filename:        axi_interface.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              axi_interface.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity axi_interface is
+  generic (
+    C_TARGET                : TARGET_FAMILY_TYPE;
+    -- AXI4-Lite slave generics
+    C_S_AXI_BASEADDR        : std_logic_vector       := X"FFFF_FFFF";
+    C_S_AXI_HIGHADDR        : std_logic_vector       := X"0000_0000";
+    C_S_AXI_ADDR_WIDTH      : integer                := 32;
+    C_S_AXI_DATA_WIDTH      : integer                := 32;
+    C_REGADDR_WIDTH         : integer                := 5;    -- Address bits including register offset.
+    C_DWIDTH                : integer                := 32);  -- Width of data bus.
+  port (
+    LMB_Clk : in std_logic;
+    LMB_Rst : in std_logic;
+
+    -- AXI4-Lite SLAVE SINGLE INTERFACE
+    S_AXI_AWADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    S_AXI_AWVALID : in  std_logic;
+    S_AXI_AWREADY : out std_logic;
+    S_AXI_WDATA   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+    S_AXI_WSTRB   : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+    S_AXI_WVALID  : in  std_logic;
+    S_AXI_WREADY  : out std_logic;
+    S_AXI_BRESP   : out std_logic_vector(1 downto 0);
+    S_AXI_BVALID  : out std_logic;
+    S_AXI_BREADY  : in  std_logic;
+    S_AXI_ARADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    S_AXI_ARVALID : in  std_logic;
+    S_AXI_ARREADY : out std_logic;
+    S_AXI_RDATA   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+    S_AXI_RRESP   : out std_logic_vector(1 downto 0);
+    S_AXI_RVALID  : out std_logic;
+    S_AXI_RREADY  : in  std_logic;
+    
+    -- lmb_bram_if_cntlr signals
+    RegWr         : out std_logic;
+    RegWrData     : out std_logic_vector(0 to C_DWIDTH - 1);
+    RegAddr       : out std_logic_vector(0 to C_REGADDR_WIDTH-1);  
+    RegRdData     : in  std_logic_vector(0 to C_DWIDTH - 1));
+end entity axi_interface;
+
+architecture IMP of axi_interface is
+
+  component MB_FDRE is
+  generic (
+    C_TARGET : TARGET_FAMILY_TYPE;
+    INIT : bit := '0'
+  );
+  port(
+    Q  : out std_logic;
+    C  : in  std_logic;
+    CE : in  std_logic;
+    D  : in  std_logic;
+    R  : in  std_logic
+  );
+  end component MB_FDRE;
+  
+  -----------------------------------------------------------------------------
+  -- Signal declaration
+  -----------------------------------------------------------------------------
+  signal new_write_access       : std_logic;
+  signal new_read_access        : std_logic;
+  signal ongoing_write          : std_logic;
+  signal ongoing_read           : std_logic;
+
+  signal S_AXI_RVALID_i         : std_logic;
+
+  signal RegRdData_i            : std_logic_vector(C_DWIDTH - 1 downto 0);
+
+begin  -- architecture IMP
+
+  -----------------------------------------------------------------------------
+  -- Handling the AXI4-Lite bus interface (AR/AW/W)
+  -----------------------------------------------------------------------------
+  
+  -- Detect new transaction.
+  -- Only allow one access at a time
+  new_write_access  <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
+  new_read_access   <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
+
+  -- Acknowledge new transaction.
+  S_AXI_AWREADY <= new_write_access;
+  S_AXI_WREADY  <= new_write_access;
+  S_AXI_ARREADY <= new_read_access;
+
+  -- Store register address and write data 
+  Reg: process (LMB_Clk) is
+  begin
+    if LMB_Clk'event and LMB_Clk = '1' then
+      if LMB_Rst = '1' then
+        RegAddr   <= (others => '0');
+        RegWrData <= (others => '0');
+      elsif new_write_access = '1' then
+        RegAddr   <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
+        RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
+      elsif new_read_access = '1' then
+        RegAddr   <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
+      end if;
+    end if;
+  end process Reg;
+  
+  -- Handle write access.
+  WriteAccess: process (LMB_Clk) is
+  begin
+    if LMB_Clk'event and LMB_Clk = '1' then
+      if LMB_Rst = '1' then
+        ongoing_write <= '0';
+      elsif new_write_access = '1' then
+        ongoing_write <= '1';
+      elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
+        ongoing_write <= '0';
+      end if;
+      RegWr <= new_write_access;
+    end if;
+  end process WriteAccess;
+
+  S_AXI_BVALID <= ongoing_write;
+  S_AXI_BRESP  <= (others => '0');
+
+  -- Handle read access
+  ReadAccess: process (LMB_Clk) is
+  begin
+    if LMB_Clk'event and LMB_Clk = '1' then
+      if LMB_Rst = '1' then
+        ongoing_read   <= '0';
+        S_AXI_RVALID_i <= '0';
+      elsif new_read_access = '1' then
+        ongoing_read   <= '1';
+        S_AXI_RVALID_i <= '0';
+      elsif ongoing_read = '1' then
+        if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
+          ongoing_read   <= '0';
+          S_AXI_RVALID_i <= '0';
+        else
+          S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
+        end if;
+      end if;
+    end if;
+  end process ReadAccess;
+
+  S_AXI_RVALID <= S_AXI_RVALID_i;
+  S_AXI_RRESP  <= (others => '0');
+  
+  Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
+  begin
+    S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH)  <= (others=>'0');
+  end generate Not_All_Bits_Are_Used;
+
+  RegRdData_i <= RegRdData;             -- Swap to - downto
+  
+  S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
+  begin
+    S_AXI_RDATA_FDRE : MB_FDRE
+      generic map (
+        C_TARGET => C_TARGET)
+      port map (
+        Q  => S_AXI_RDATA(I),
+        C  => LMB_Clk,
+        CE => ongoing_read,
+        D  => RegRdData_i(I),
+        R  => LMB_Rst);
+  end generate S_AXI_RDATA_DFF;
+  
+end architecture IMP;
+
+
+-------------------------------------------------------------------------------
+-- lmb_mux.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        lmb_mux.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              lmb_mux.vhd
+--                pselct_mask.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+entity lmb_mux is
+  generic (
+    C_TARGET     : TARGET_FAMILY_TYPE;
+    C_BASEADDR   : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_MASK       : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK1      : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK2      : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK3      : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_LMB_AWIDTH : integer                   := 32;
+    C_LMB_DWIDTH : integer                   := 32;
+    C_ECC        : integer                   := 0;
+    C_NUM_LMB    : integer                   := 1;
+    C_LMB_PROTOCOL : integer                 := 0);
+  port (
+    LMB_Clk : in std_logic := '0';
+    LMB_Rst : in std_logic := '0';
+
+    -- LMB Bus 0
+    LMB0_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB0_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB0_AddrStrobe  : in  std_logic;
+    LMB0_ReadStrobe  : in  std_logic;
+    LMB0_WriteStrobe : in  std_logic;
+    LMB0_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl0_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl0_Ready        : out std_logic;
+    Sl0_Wait         : out std_logic;
+    Sl0_UE           : out std_logic;
+    Sl0_CE           : out std_logic;
+
+    -- LMB Bus 1
+    LMB1_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB1_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB1_AddrStrobe  : in  std_logic;
+    LMB1_ReadStrobe  : in  std_logic;
+    LMB1_WriteStrobe : in  std_logic;
+    LMB1_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl1_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl1_Ready        : out std_logic;
+    Sl1_Wait         : out std_logic;
+    Sl1_UE           : out std_logic;
+    Sl1_CE           : out std_logic;
+
+    -- LMB Bus 2
+    LMB2_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB2_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB2_AddrStrobe  : in  std_logic;
+    LMB2_ReadStrobe  : in  std_logic;
+    LMB2_WriteStrobe : in  std_logic;
+    LMB2_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl2_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl2_Ready        : out std_logic;
+    Sl2_Wait         : out std_logic;
+    Sl2_UE           : out std_logic;
+    Sl2_CE           : out std_logic;
+
+    -- LMB Bus 3
+    LMB3_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB3_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB3_AddrStrobe  : in  std_logic;
+    LMB3_ReadStrobe  : in  std_logic;
+    LMB3_WriteStrobe : in  std_logic;
+    LMB3_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl3_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl3_Ready        : out std_logic;
+    Sl3_Wait         : out std_logic;
+    Sl3_UE           : out std_logic;
+    Sl3_CE           : out std_logic;
+    
+    -- Muxed LMB Bus
+    LMB_ABus        : out std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB_WriteDBus   : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB_WriteECC    : out std_logic_vector(0 to 6);
+    LMB_AddrStrobe  : out std_logic;
+    LMB_ReadStrobe  : out std_logic;
+    LMB_WriteStrobe : out std_logic;
+    IsWordWrite     : out std_logic;
+    LMB_BE          : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl_DBus         : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl_Ready        : in  std_logic;
+    Sl_Wait         : in  std_logic;
+    Sl_UE           : in  std_logic;
+    Sl_CE           : in  std_logic;
+
+    lmb_select      : out std_logic);
+end entity lmb_mux;
+
+architecture imp of lmb_mux is
+
+  component pselect_mask
+    generic (
+      C_AW   : integer                   := 32;
+      C_BAR  : std_logic_vector(0 to 63) := X"0000000000000000";
+      C_MASK : std_logic_vector(0 to 63) := X"0000000000800000");
+    port (
+      A     : in  std_logic_vector(0 to C_AW - 1);
+      CS    : out std_logic;
+      Valid : in  std_logic);
+  end component;
+
+  component checkbit_handler is
+    generic (
+      C_TARGET   : TARGET_FAMILY_TYPE;
+      C_ENCODE   : boolean);
+    port (
+      DataIn     : in  std_logic_vector(0 to 31);
+      CheckIn    : in  std_logic_vector(0 to 6);
+      CheckOut   : out std_logic_vector(0 to 6);
+      Syndrome   : out std_logic_vector(0 to 6);
+      Enable_ECC : in  std_logic;
+      UE_Q       : in  std_logic;
+      CE_Q       : in  std_logic;
+      UE         : out std_logic;
+      CE         : out std_logic);
+  end component checkbit_handler;
+
+  signal one : std_logic;
+-------------------------------------------------------------------------------
+-- Begin architecture section
+-------------------------------------------------------------------------------
+begin  -- VHDL_RTL
+
+  LMB1_no: if (C_NUM_LMB < 2) generate
+    Sl1_DBus               <= (others => '0');
+    Sl1_Ready              <= '0';
+    Sl1_Wait               <= '0';
+    Sl1_UE                 <= '0';
+    Sl1_CE                 <= '0';
+  end generate LMB1_no;
+  
+  LMB2_no: if (C_NUM_LMB < 3) generate
+    Sl2_DBus               <= (others => '0');
+    Sl2_Ready              <= '0';
+    Sl2_Wait               <= '0';
+    Sl2_UE                 <= '0';
+    Sl2_CE                 <= '0';
+  end generate LMB2_no;
+
+  LMB3_no: if (C_NUM_LMB < 4) generate
+    Sl3_DBus               <= (others => '0');
+    Sl3_Ready              <= '0';
+    Sl3_Wait               <= '0';
+    Sl3_UE                 <= '0';
+    Sl3_CE                 <= '0';
+  end generate LMB3_no;
+    
+  one <= '1';
+
+  one_lmb: if (C_NUM_LMB = 1) generate
+  begin
+    
+    -----------------------------------------------------------------------------
+    -- Do the LMB address decoding
+    -----------------------------------------------------------------------------
+    pselect_mask_lmb : pselect_mask
+      generic map (
+        C_AW   => LMB_ABus'length,
+        C_BAR  => C_BASEADDR,
+        C_MASK => C_MASK)
+      port map (
+        A     => LMB0_ABus,
+        CS    => lmb_select,
+        Valid => one);
+
+    LMB_ABus        <= LMB0_ABus;
+    LMB_WriteDBus   <= LMB0_WriteDBus;
+    LMB_WriteECC    <= (others => '0');
+    LMB_AddrStrobe  <= LMB0_AddrStrobe;
+    LMB_ReadStrobe  <= LMB0_ReadStrobe;
+    LMB_WriteStrobe <= LMB0_WriteStrobe;
+    IsWordWrite     <= LMB0_WriteStrobe when (LMB0_BE = "1111") else '0';
+    LMB_BE          <= LMB0_BE;
+    Sl0_DBus        <= Sl_DBus;
+    Sl0_Ready       <= Sl_Ready;
+    Sl0_Wait        <= Sl_Wait;
+    Sl0_UE          <= Sl_UE;
+    Sl0_CE          <= Sl_CE;
+
+  end generate one_lmb;
+
+  more_than_one_lmb: if (C_NUM_LMB > 1) generate
+
+    type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 63);
+    constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
+
+    type ABus_vec_T  is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1); 
+    type DBus_vec_T  is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1); 
+    type ECC_vec_T   is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to 6); 
+    type BE_vec_T    is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
+  
+    signal LMB_ABus_vec          : ABus_vec_T;
+    signal LMB_ABus_vec_i        : ABus_vec_T;
+    signal LMB_ABus_vec_Q        : ABus_vec_T;
+    signal LMB_WriteDBus_vec     : DBus_vec_T;
+    signal LMB_WriteDBus_vec_i   : DBus_vec_T;
+    signal LMB_WriteDBus_vec_Q   : DBus_vec_T;
+    signal LMB_WriteECC_vec      : ECC_vec_T;
+    signal LMB_WriteECC_vec_i    : ECC_vec_T;
+    signal LMB_WriteECC_vec_Q    : ECC_vec_T;
+    signal LMB_AddrStrobe_vec    : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_AddrStrobe_vec_i  : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_AddrStrobe_vec_Q  : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_ReadStrobe_vec    : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_ReadStrobe_vec_i  : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_ReadStrobe_vec_Q  : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_WriteStrobe_vec   : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
+    signal IsWordWrite_vec       : std_logic_vector(0 to C_NUM_LMB-1);
+    signal IsWordWrite_vec_i     : std_logic_vector(0 to C_NUM_LMB-1);
+    signal IsWordWrite_vec_Q     : std_logic_vector(0 to C_NUM_LMB-1);
+    signal LMB_BE_vec            : BE_vec_T;
+    signal LMB_BE_vec_i          : BE_vec_T;
+    signal LMB_BE_vec_Q          : BE_vec_T;
+    signal Sl_DBus_vec           : DBus_vec_T;
+    signal Sl_Ready_vec          : std_logic_vector(0 to C_NUM_LMB-1);
+    signal Sl_Wait_vec           : std_logic_vector(0 to C_NUM_LMB-1);
+    signal Sl_UE_vec             : std_logic_vector(0 to C_NUM_LMB-1);
+    signal Sl_CE_vec             : std_logic_vector(0 to C_NUM_LMB-1);
+
+    signal wait_vec              : std_logic_vector(0 to C_NUM_LMB-1);
+    signal lmb_select_vec        : std_logic_vector(0 to C_NUM_LMB-1);
+    signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
+
+    signal ongoing     : natural range 0 to C_NUM_LMB-1;
+    signal ongoing_new : natural range 0 to C_NUM_LMB-1;
+    signal ongoing_Q   : natural range 0 to C_NUM_LMB-1;
+    signal ongoing_QQ  : natural range 0 to C_NUM_LMB-1;
+    signal ECC_ongoing : natural range 0 to C_NUM_LMB-1;
+
+  begin
+
+    LMB_ABus_vec(0)        <= LMB0_ABus;
+    LMB_WriteDBus_vec(0)   <= LMB0_WriteDBus;
+    LMB_AddrStrobe_vec(0)  <= LMB0_AddrStrobe;
+    LMB_ReadStrobe_vec(0)  <= LMB0_ReadStrobe;
+    LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
+    IsWordWrite_vec(0)     <= LMB0_WriteStrobe when (LMB0_BE = "1111") else '0';
+    LMB_BE_vec(0)          <= LMB0_BE;
+    Sl0_DBus               <= Sl_DBus_vec(0);
+    Sl0_Ready              <= Sl_Ready_vec(0);
+    Sl0_Wait               <= Sl_Wait_vec(0);
+    Sl0_UE                 <= Sl_UE_vec(0);
+    Sl0_CE                 <= Sl_CE_vec(0);
+
+    ECC_lmb0_yes: if (C_ECC = 1) generate
+      checkbit_handler_LMB0 : checkbit_handler
+        generic map (
+          C_TARGET   => C_TARGET,
+          C_ENCODE   => true)
+        port map (
+          DataIn     => LMB_WriteDBus_vec(0),
+          CheckIn    => (others => '0'),
+          CheckOut   => LMB_WriteECC_vec(0),
+          Syndrome   => open,
+          Enable_ECC => '1',
+          UE_Q       => '0',
+          CE_Q       => '0',
+          UE         => open,
+          CE         => open);
+    end generate ECC_lmb0_yes;
+
+    ECC_lmb0_no: if (C_ECC = 0) generate
+      LMB_WriteECC_vec(0) <= (others => '0');
+    end generate ECC_lmb0_no;
+
+    LMB_ABus_vec(1)        <= LMB1_ABus;
+    LMB_WriteDBus_vec(1)   <= LMB1_WriteDBus;
+    LMB_AddrStrobe_vec(1)  <= LMB1_AddrStrobe;
+    LMB_ReadStrobe_vec(1)  <= LMB1_ReadStrobe;
+    LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
+    IsWordWrite_vec(1)     <= LMB1_WriteStrobe when (LMB1_BE = "1111") else '0';
+    LMB_BE_vec(1)          <= LMB1_BE;
+    Sl1_DBus               <= Sl_DBus_vec(1);
+    Sl1_Ready              <= Sl_Ready_vec(1);
+    Sl1_Wait               <= Sl_Wait_vec(1);
+    Sl1_UE                 <= Sl_UE_vec(1);
+    Sl1_CE                 <= Sl_CE_vec(1);
+
+    ECC_lmb1_yes: if (C_ECC = 1) generate
+      checkbit_handler_LMB1 : checkbit_handler
+        generic map (
+          C_TARGET   => C_TARGET,
+          C_ENCODE   => true)
+        port map (
+          DataIn     => LMB_WriteDBus_vec(1),
+          CheckIn    => (others => '0'),
+          CheckOut   => LMB_WriteECC_vec(1),
+          Syndrome   => open,
+          Enable_ECC => '1',
+          UE_Q       => '0',
+          CE_Q       => '0',
+          UE         => open,
+          CE         => open);
+    end generate ECC_lmb1_yes;
+
+    ECC_lmb1_no: if (C_ECC = 0) generate
+      LMB_WriteECC_vec(1) <= (others => '0');
+    end generate ECC_lmb1_no;
+
+    LMB2_yes: if (C_NUM_LMB > 2) generate
+      LMB_ABus_vec(2)        <= LMB2_ABus;
+      LMB_WriteDBus_vec(2)   <= LMB2_WriteDBus;
+      LMB_AddrStrobe_vec(2)  <= LMB2_AddrStrobe;
+      LMB_ReadStrobe_vec(2)  <= LMB2_ReadStrobe;
+      LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
+      IsWordWrite_vec(2)     <= LMB2_WriteStrobe when (LMB2_BE = "1111") else '0';
+      LMB_BE_vec(2)          <= LMB2_BE;
+      Sl2_DBus               <= Sl_DBus_vec(2);
+      Sl2_Ready              <= Sl_Ready_vec(2);
+      Sl2_Wait               <= Sl_Wait_vec(2);
+      Sl2_UE                 <= Sl_UE_vec(2);
+      Sl2_CE                 <= Sl_CE_vec(2);
+
+      ECC_lmb2_yes: if (C_ECC = 1) generate
+        checkbit_handler_LMB2 : checkbit_handler
+          generic map (
+            C_TARGET   => C_TARGET,
+            C_ENCODE   => true)
+          port map (
+            DataIn     => LMB_WriteDBus_vec(2),
+            CheckIn    => (others => '0'),
+            CheckOut   => LMB_WriteECC_vec(2),
+            Syndrome   => open,
+            Enable_ECC => '1',
+            UE_Q       => '0',
+            CE_Q       => '0',
+            UE         => open,
+            CE         => open); 
+      end generate ECC_lmb2_yes;
+
+      ECC_lmb2_no: if (C_ECC = 0) generate
+        LMB_WriteECC_vec(2) <= (others => '0');
+      end generate ECC_lmb2_no;
+     
+    end generate LMB2_yes;
+
+    LMB3_yes: if (C_NUM_LMB > 3) generate
+      LMB_ABus_vec(3)        <= LMB3_ABus;
+      LMB_WriteDBus_vec(3)   <= LMB3_WriteDBus;
+      LMB_AddrStrobe_vec(3)  <= LMB3_AddrStrobe;
+      LMB_ReadStrobe_vec(3)  <= LMB3_ReadStrobe;
+      LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
+      IsWordWrite_vec(3)     <= LMB3_WriteStrobe when (LMB3_BE = "1111") else '0';
+      LMB_BE_vec(3)          <= LMB3_BE;
+      Sl3_DBus               <= Sl_DBus_vec(3);
+      Sl3_Ready              <= Sl_Ready_vec(3);
+      Sl3_Wait               <= Sl_Wait_vec(3);
+      Sl3_UE                 <= Sl_UE_vec(3);
+      Sl3_CE                 <= Sl_CE_vec(3);
+
+      ECC_lmb3_yes: if (C_ECC = 1) generate
+        checkbit_handler_LMB3 : checkbit_handler
+          generic map (
+            C_TARGET   => C_TARGET,
+            C_ENCODE   => true)
+          port map (
+            DataIn     => LMB_WriteDBus_vec(3),
+            CheckIn    => (others => '0'),
+            CheckOut   => LMB_WriteECC_vec(3),
+            Syndrome   => open,
+            Enable_ECC => '1',
+            UE_Q       => '0',
+            CE_Q       => '0',
+            UE         => open,
+            CE         => open);
+      end generate ECC_lmb3_yes;
+
+      ECC_lmb3_no: if (C_ECC = 0) generate
+        LMB_WriteECC_vec(3) <= (others => '0');
+      end generate ECC_lmb3_no;
+
+    end generate LMB3_yes;
+
+    lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
+    begin
+
+      -----------------------------------------------------------------------------
+      -- Do the LMB address decoding
+      -----------------------------------------------------------------------------
+      pselect_mask_lmb : pselect_mask
+        generic map (
+          C_AW   => LMB_ABus'length,
+          C_BAR  => C_BASEADDR,
+          C_MASK => C_Mask_Vec(I))
+        port map (
+          A     => LMB_ABus_vec(I),
+          CS    => lmb_select_vec(I),
+          Valid => one);
+
+      as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
+
+      remember_access : process (LMB_Clk) is
+      begin
+        if (LMB_Clk'event and LMB_Clk = '1') then
+          if (LMB_Rst = '1') then
+            LMB_ABus_vec_Q(I)        <= (others => '0');
+            LMB_WriteDBus_vec_Q(I)   <= (others => '0');
+            LMB_WriteECC_vec_Q(I)    <= (others => '0');
+            LMB_AddrStrobe_vec_Q(I)  <= '0';
+            LMB_ReadStrobe_vec_Q(I)  <= '0';
+            LMB_WriteStrobe_vec_Q(I) <= '0';
+            IsWordWrite_vec_Q(I)     <= '0';
+            LMB_BE_vec_Q(I)          <= (others => '0');
+          elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
+            LMB_ABus_vec_Q(I)        <= LMB_ABus_vec(I);
+            LMB_WriteDBus_vec_Q(I)   <= LMB_WriteDBus_vec(I);
+            LMB_WriteECC_vec_Q(I)    <= LMB_WriteECC_vec(I);
+            LMB_AddrStrobe_vec_Q(I)  <= LMB_AddrStrobe_vec(I);
+            LMB_ReadStrobe_vec_Q(I)  <= LMB_ReadStrobe_vec(I);
+            LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
+            IsWordWrite_vec_Q(I)     <= IsWordWrite_vec(I);
+            LMB_BE_vec_Q(I)          <= LMB_BE_vec(I);
+          end if;
+        end if;
+      end process remember_access;
+
+      wait_proc : process (LMB_Clk) is
+      begin
+        if (LMB_Clk'event and LMB_Clk = '1') then
+          if (LMB_Rst = '1') then
+            wait_vec(I) <= '0';
+          elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
+            wait_vec(I) <= '1';
+          elsif (wait_vec(I) = '1' and ongoing = I) then
+            wait_vec(I) <= '0';
+          end if;
+        end if;
+      end process wait_proc;
+
+      LMB_ABus_vec_i(I)        <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_ABus_vec(I);
+      LMB_WriteDBus_vec_i(I)   <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_WriteDBus_vec(I);
+      LMB_WriteECC_vec_i(I)    <= LMB_WriteECC_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_WriteECC_vec(I);
+      LMB_AddrStrobe_vec_i(I)  <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_AddrStrobe_vec(I);
+      LMB_ReadStrobe_vec_i(I)  <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_ReadStrobe_vec(I);
+      LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_WriteStrobe_vec(I);
+      IsWordWrite_vec_i(I)     <= IsWordWrite_vec_Q(I) when wait_vec(I) = '1' else
+                                  IsWordWrite_vec(I);
+      LMB_BE_vec_i(I)          <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
+                                  LMB_BE_vec(I);
+
+      -- Assign selected LMB from internal signals
+      Sl_DBus_vec(I)  <= Sl_DBus;
+      Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
+                        '0';
+      Sl_Wait_vec(I)  <= Sl_Wait when ongoing_Q = I else
+                         wait_vec(I);
+      Sl_UE_vec(I)    <= Sl_UE when ECC_ongoing = I else
+                        '0';
+      Sl_CE_vec(I)    <= Sl_CE when ECC_ongoing = I else
+                        '0';
+    end generate lmb_mux_generate;
+
+    OnGoing_Reg : process (LMB_Clk) is
+    begin 
+      if (LMB_Clk'event and LMB_Clk = '1') then
+        if (LMB_Rst = '1') then
+          ongoing_Q <= 0;
+        else
+          ongoing_Q <= ongoing;
+        end if;
+      end if;
+    end process OnGoing_Reg;
+
+    OnGoingQ_Reg : process (LMB_Clk) is
+    begin 
+      if (LMB_Clk'event and LMB_Clk = '1') then
+        if (LMB_Rst = '1') then
+          ongoing_QQ <= 0;
+        else
+          ongoing_QQ <= ongoing_Q;
+        end if;
+      end if;
+    end process OnGoingQ_Reg;
+
+    ECC_ongoing <= ongoing_QQ when C_LMB_PROTOCOL = 1 else ongoing_Q;
+
+    Arbit : process (as_and_lmb_select_vec, wait_vec) is
+      variable N : natural range 0 to C_NUM_LMB-1;
+    begin 
+      ongoing_new <= 0;
+      for N in 0 to C_NUM_LMB - 1 loop
+        if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
+          ongoing_new <= N;
+          exit;
+        end if;
+      end loop;
+    end process Arbit;
+  
+    ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
+               ongoing_new;
+
+    -- Assign selected LMB
+    LMB_ABus        <= LMB_ABus_vec_i(ongoing);
+    LMB_WriteDBus   <= LMB_WriteDBus_vec_i(ongoing);
+    LMB_WriteECC    <= LMB_WriteECC_vec_i(ongoing);
+    LMB_AddrStrobe  <= LMB_AddrStrobe_vec_i(ongoing);
+    LMB_ReadStrobe  <= LMB_ReadStrobe_vec_i(ongoing);
+    LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
+    IsWordWrite     <= IsWordWrite_vec_i(ongoing);
+    LMB_BE          <= LMB_BE_vec_i(ongoing);
+
+    lmb_select      <= lmb_select_vec(ongoing) or wait_vec(ongoing);
+    
+  end generate more_than_one_lmb;
+
+end imp;
+
+
+-------------------------------------------------------------------------------
+-- lmb_bram_if_cntlr.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2017] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+------------------------------------------------------------------------------
+-- Filename:        lmb_bram_if_cntlr.vhd
+--
+-- Description:
+--
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+--              lmb_bram_if_cntlr
+--                lmb_mux
+--                correct_one_bit
+--                xor18.vhd
+--                axi_interface
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.all;
+
+entity lmb_bram_if_cntlr is
+  generic (
+    C_FAMILY                   : string                    := "Virtex7";
+    C_HIGHADDR                 : std_logic_vector(0 to 63) := X"0000000000000000";
+    C_BASEADDR                 : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_MASK                     : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK1                    : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK2                    : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK3                    : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_LMB_AWIDTH               : integer                   := 32;
+    C_LMB_DWIDTH               : integer                   := 32;
+    C_ECC                      : integer                   := 0;
+    C_INTERCONNECT             : integer                   := 1;
+    C_FAULT_INJECT             : integer                   := 0;
+    C_CE_FAILING_REGISTERS     : integer                   := 0;
+    C_UE_FAILING_REGISTERS     : integer                   := 0;
+    C_ECC_STATUS_REGISTERS     : integer                   := 0;
+    C_ECC_ONOFF_REGISTER       : integer                   := 0;
+    C_ECC_ONOFF_RESET_VALUE    : integer                   := 1;
+    C_CE_COUNTER_WIDTH         : integer                   := 0;
+    C_WRITE_ACCESS             : integer                   := 2;
+    C_NUM_LMB                  : integer                   := 1;
+    C_LMB_PROTOCOL             : integer                   := 0;
+    -- BRAM generic
+    C_BRAM_AWIDTH              : integer                   := 32;
+    -- AXI generics
+    C_S_AXI_CTRL_BASEADDR      : std_logic_vector          := X"FFFF_FFFF";
+    C_S_AXI_CTRL_HIGHADDR      : std_logic_vector          := X"0000_0000";
+    C_S_AXI_CTRL_ADDR_WIDTH    : integer                   := 32;
+    C_S_AXI_CTRL_DATA_WIDTH    : integer                   := 32);
+  port (
+    LMB_Clk : in std_logic := '0';
+    LMB_Rst : in std_logic := '0';
+
+    -- LMB Bus
+    LMB_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB_AddrStrobe  : in  std_logic;
+    LMB_ReadStrobe  : in  std_logic;
+    LMB_WriteStrobe : in  std_logic;
+    LMB_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl_Ready        : out std_logic;
+    Sl_Wait         : out std_logic;
+    Sl_UE           : out std_logic;
+    Sl_CE           : out std_logic;
+
+    -- Supplementary LMB Bus 1
+    LMB1_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB1_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB1_AddrStrobe  : in  std_logic;
+    LMB1_ReadStrobe  : in  std_logic;
+    LMB1_WriteStrobe : in  std_logic;
+    LMB1_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl1_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl1_Ready        : out std_logic;
+    Sl1_Wait         : out std_logic;
+    Sl1_UE           : out std_logic;
+    Sl1_CE           : out std_logic;
+
+    -- Supplementary LMB Bus 2
+    LMB2_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB2_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB2_AddrStrobe  : in  std_logic;
+    LMB2_ReadStrobe  : in  std_logic;
+    LMB2_WriteStrobe : in  std_logic;
+    LMB2_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl2_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl2_Ready        : out std_logic;
+    Sl2_Wait         : out std_logic;
+    Sl2_UE           : out std_logic;
+    Sl2_CE           : out std_logic;
+
+    -- Supplementary LMB Bus 3
+    LMB3_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB3_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB3_AddrStrobe  : in  std_logic;
+    LMB3_ReadStrobe  : in  std_logic;
+    LMB3_WriteStrobe : in  std_logic;
+    LMB3_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl3_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl3_Ready        : out std_logic;
+    Sl3_Wait         : out std_logic;
+    Sl3_UE           : out std_logic;
+    Sl3_CE           : out std_logic;
+
+    -- ports to data memory block
+    BRAM_Rst_A  : out std_logic;
+    BRAM_Clk_A  : out std_logic;
+    BRAM_Addr_A : out std_logic_vector(0 to C_BRAM_AWIDTH-1);
+    BRAM_EN_A   : out std_logic;
+    BRAM_WEN_A  : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
+    BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
+    BRAM_Din_A  : in  std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
+
+    -- AXI Interface
+    S_AXI_CTRL_ACLK    : in  std_logic;
+    S_AXI_CTRL_ARESETN : in  std_logic;
+    S_AXI_CTRL_AWADDR  : in  std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
+    S_AXI_CTRL_AWVALID : in  std_logic;
+    S_AXI_CTRL_AWREADY : out std_logic;
+    S_AXI_CTRL_WDATA   : in  std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
+    S_AXI_CTRL_WSTRB   : in  std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
+    S_AXI_CTRL_WVALID  : in  std_logic;
+    S_AXI_CTRL_WREADY  : out std_logic;
+    S_AXI_CTRL_BRESP   : out std_logic_vector(1 downto 0);
+    S_AXI_CTRL_BVALID  : out std_logic;
+    S_AXI_CTRL_BREADY  : in  std_logic;
+    S_AXI_CTRL_ARADDR  : in  std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
+    S_AXI_CTRL_ARVALID : in  std_logic;
+    S_AXI_CTRL_ARREADY : out std_logic;
+    S_AXI_CTRL_RDATA   : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
+    S_AXI_CTRL_RRESP   : out std_logic_vector(1 downto 0);
+    S_AXI_CTRL_RVALID  : out std_logic;
+    S_AXI_CTRL_RREADY  : in  std_logic;
+
+    -- Interrupt and error signals
+    UE        : out std_logic;
+    CE        : out std_logic;
+    Interrupt : out std_logic);
+end lmb_bram_if_cntlr;
+
+library lmb_bram_if_cntlr_v4_0_19;
+use lmb_bram_if_cntlr_v4_0_19.lmb_bram_if_funcs.all;
+
+architecture imp of lmb_bram_if_cntlr is
+
+------------------------------------------------------------------------------
+-- component declarations
+------------------------------------------------------------------------------
+
+  component lmb_mux is
+  generic (
+    C_TARGET     : TARGET_FAMILY_TYPE;
+    C_BASEADDR   : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
+    C_MASK       : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK1      : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK2      : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_MASK3      : std_logic_vector(0 to 63) := X"0000000000800000";
+    C_LMB_AWIDTH : integer                   := 32;
+    C_LMB_DWIDTH : integer                   := 32;
+    C_ECC        : integer                   := 0;
+    C_NUM_LMB    : integer                   := 1;
+    C_LMB_PROTOCOL : integer                 := 0);
+  port (
+    LMB_Clk : in std_logic := '0';
+    LMB_Rst : in std_logic := '0';
+
+    -- LMB Bus 0
+    LMB0_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB0_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB0_AddrStrobe  : in  std_logic;
+    LMB0_ReadStrobe  : in  std_logic;
+    LMB0_WriteStrobe : in  std_logic;
+    LMB0_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl0_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl0_Ready        : out std_logic;
+    Sl0_Wait         : out std_logic;
+    Sl0_UE           : out std_logic;
+    Sl0_CE           : out std_logic;
+
+    -- LMB Bus 1
+    LMB1_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB1_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB1_AddrStrobe  : in  std_logic;
+    LMB1_ReadStrobe  : in  std_logic;
+    LMB1_WriteStrobe : in  std_logic;
+    LMB1_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl1_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl1_Ready        : out std_logic;
+    Sl1_Wait         : out std_logic;
+    Sl1_UE           : out std_logic;
+    Sl1_CE           : out std_logic;
+
+    -- LMB Bus 2
+    LMB2_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB2_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB2_AddrStrobe  : in  std_logic;
+    LMB2_ReadStrobe  : in  std_logic;
+    LMB2_WriteStrobe : in  std_logic;
+    LMB2_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl2_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl2_Ready        : out std_logic;
+    Sl2_Wait         : out std_logic;
+    Sl2_UE           : out std_logic;
+    Sl2_CE           : out std_logic;
+
+    -- LMB Bus 3
+    LMB3_ABus        : in  std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB3_WriteDBus   : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB3_AddrStrobe  : in  std_logic;
+    LMB3_ReadStrobe  : in  std_logic;
+    LMB3_WriteStrobe : in  std_logic;
+    LMB3_BE          : in  std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl3_DBus         : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl3_Ready        : out std_logic;
+    Sl3_Wait         : out std_logic;
+    Sl3_UE           : out std_logic;
+    Sl3_CE           : out std_logic;
+
+    -- Muxed LMB Bus
+    LMB_ABus        : out std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB_WriteDBus   : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB_WriteECC    : out std_logic_vector(0 to 6);
+    LMB_AddrStrobe  : out std_logic;
+    LMB_ReadStrobe  : out std_logic;
+    LMB_WriteStrobe : out std_logic;
+    IsWordWrite     : out std_logic;
+    LMB_BE          : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+    Sl_DBus         : in  std_logic_vector(0 to C_LMB_DWIDTH-1);
+    Sl_Ready        : in  std_logic;
+    Sl_Wait         : in  std_logic;
+    Sl_UE           : in  std_logic;
+    Sl_CE           : in  std_logic;
+
+    lmb_select       : out std_logic);
+  end component lmb_mux;
+
+  component axi_interface
+  generic (
+    C_TARGET           : TARGET_FAMILY_TYPE;
+    C_S_AXI_BASEADDR   : std_logic_vector := X"FFFF_FFFF";
+    C_S_AXI_HIGHADDR   : std_logic_vector := X"0000_0000";
+    C_S_AXI_ADDR_WIDTH : integer          := 32;
+    C_S_AXI_DATA_WIDTH : integer          := 32;
+    C_REGADDR_WIDTH    : integer          := 5;    -- Address bits including register offset.
+    C_DWIDTH           : integer          := 32);  -- Width of data bus.
+  port (
+    LMB_Clk       : in std_logic;
+    LMB_Rst       : in std_logic;
+    S_AXI_AWADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    S_AXI_AWVALID : in  std_logic;
+    S_AXI_AWREADY : out std_logic;
+    S_AXI_WDATA   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+    S_AXI_WSTRB   : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+    S_AXI_WVALID  : in  std_logic;
+    S_AXI_WREADY  : out std_logic;
+    S_AXI_BRESP   : out std_logic_vector(1 downto 0);
+    S_AXI_BVALID  : out std_logic;
+    S_AXI_BREADY  : in  std_logic;
+    S_AXI_ARADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    S_AXI_ARVALID : in  std_logic;
+    S_AXI_ARREADY : out std_logic;
+    S_AXI_RDATA   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+    S_AXI_RRESP   : out std_logic_vector(1 downto 0);
+    S_AXI_RVALID  : out std_logic;
+    S_AXI_RREADY  : in  std_logic;
+    RegWr         : out std_logic;
+    RegWrData     : out std_logic_vector(0 to C_DWIDTH - 1);
+    RegAddr       : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
+    RegRdData     : in  std_logic_vector(0 to C_DWIDTH - 1));
+  end component;
+
+  component checkbit_handler is
+    generic (
+      C_TARGET   : TARGET_FAMILY_TYPE;
+      C_ENCODE   : boolean);
+    port (
+      DataIn     : in  std_logic_vector(0 to 31);
+      CheckIn    : in  std_logic_vector(0 to 6);
+      CheckOut   : out std_logic_vector(0 to 6);
+      Syndrome   : out std_logic_vector(0 to 6);
+      Enable_ECC : in  std_logic;
+      UE_Q       : in  std_logic;
+      CE_Q       : in  std_logic;
+      UE         : out std_logic;
+      CE         : out std_logic);
+  end component checkbit_handler;
+
+  component Correct_One_Bit
+    generic (
+      C_TARGET      : TARGET_FAMILY_TYPE;
+      Correct_Value : std_logic_vector(0 to 6));
+    port (
+      DIn      : in  std_logic;
+      Syndrome : in  std_logic_vector(0 to 6);
+      DCorr    : out std_logic);
+  end component Correct_One_Bit;
+
+  constant C_TARGET   : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
+
+  constant C_HAS_FAULT_INJECT         : boolean := C_FAULT_INJECT = 1;
+  constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
+  constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
+  constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
+  constant C_HAS_ECC_ONOFF_REGISTER   : boolean := C_ECC_ONOFF_REGISTER = 1;
+  constant C_HAS_CE_COUNTER           : boolean := C_CE_COUNTER_WIDTH /= 0;
+
+  constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT  or
+                                     C_HAS_CE_FAILING_REGISTERS or
+                                     C_HAS_UE_FAILING_REGISTERS or
+                                     C_HAS_ECC_STATUS_REGISTERS or
+                                     C_HAS_ECC_ONOFF_REGISTER or
+                                     C_HAS_CE_COUNTER;
+
+  constant C_AXI : integer := 2;
+
+  constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
+
+  constant C_ECC_WIDTH : integer := 7;
+
+  -- Intermediate signals to handle multiple LMB ports
+  signal LMB_ABus_i        : std_logic_vector(0 to C_LMB_AWIDTH-1);
+  signal LMB_WriteDBus_i   : std_logic_vector(0 to C_LMB_DWIDTH-1);
+  signal LMB_WriteECC      : std_logic_vector(0 to 6);
+  signal LMB_AddrStrobe_i  : std_logic;
+  signal LMB_ReadStrobe_i  : std_logic;
+  signal LMB_WriteStrobe_i : std_logic;
+  signal LMB_BE_i          : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+  signal Sl_DBus_i         : std_logic_vector(0 to C_LMB_DWIDTH-1);
+  signal Sl_Ready_i        : std_logic;
+  signal Sl_Wait_i         : std_logic;
+  signal Sl_UE_i           : std_logic;
+  signal Sl_CE_i           : std_logic;
+
+  signal lmb_select       : std_logic;
+  signal lmb_as           : std_logic;
+
+  signal lmb_we : std_logic_vector(0 to 3);
+
+  signal Sl_Rdy : std_logic;
+
+  signal LMB_WrECC   : std_logic_vector(0 to C_ECC_WIDTH-1);
+  signal IsWordWrite : std_logic;
+
+  signal bram_din_a_i  : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
+
+begin
+
+  assert C_LMB_AWIDTH >= C_BRAM_AWIDTH
+    report "C_LMB_AWIDTH must be greater than or equal to C_BRAM_AWIDTH"
+    severity failure;
+
+  -----------------------------------------------------------------------------
+  -- Cleaning incoming data from BRAM from 'U' for simulation purpose
+  -- This is added since simulation model for BRAM will not initialize
+  -- undefined memory locations with zero.
+  -- Added as a work-around until this is fixed in the simulation model.
+  -----------------------------------------------------------------------------
+  -- Standard LMB protocol with RAM data read combinatorial through LMB controller 
+  BRAM_DIN_LMB_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+  begin
+
+    Cleaning_machine: process (BRAM_Din_A) is
+    begin  -- process Cleaning_machine
+      -- Default assignments
+      bram_din_a_i <= BRAM_Din_A;
+      -- pragma translate_off
+      bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
+      -- pragma translate_on
+
+    end process Cleaning_machine;
+
+  end generate BRAM_DIN_LMB_Protocol_0;
+
+  -- Timing optimized LMB protocol with RAM data read clocked in LMB controller
+  -- Only works with MicroBlaze 8-stage pipe and C_LMB_PROTOCOL set to 1 on MicroBlaze
+  BRAM_DIN_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+  begin
+
+    Cleaning_machine_DFF: process (LMB_Clk) is
+    begin  -- process Cleaning_machine
+      if LMB_Clk'event and LMB_Clk = '1' then
+        if LMB_Rst = '1' then
+          bram_din_a_i <= (others => '0');
+        else
+          -- Default assignments
+          bram_din_a_i <= BRAM_Din_A;
+          -- pragma translate_off
+          bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
+          -- pragma translate_on
+        end if;
+      end if;
+    end process Cleaning_machine_DFF;
+
+  end generate BRAM_DIN_LMB_Protocol_1;
+  
+  lmb_mux_I : lmb_mux
+    generic map (
+      C_TARGET     => C_TARGET,
+      C_BASEADDR   => C_BASEADDR,
+      C_MASK       => C_MASK,
+      C_MASK1      => C_MASK1,
+      C_MASK2      => C_MASK2,
+      C_MASK3      => C_MASK3,
+      C_LMB_AWIDTH => C_LMB_AWIDTH,
+      C_LMB_DWIDTH => C_LMB_DWIDTH,
+      C_ECC        => C_ECC,
+      C_NUM_LMB    => C_NUM_LMB,
+      C_LMB_PROTOCOL => C_LMB_PROTOCOL)
+    port map (
+      LMB_Clk          => LMB_Clk,
+      LMB_Rst          => LMB_Rst,
+      LMB0_ABus        => LMB_ABus,
+      LMB0_WriteDBus   => LMB_WriteDBus,
+      LMB0_AddrStrobe  => LMB_AddrStrobe,
+      LMB0_ReadStrobe  => LMB_ReadStrobe,
+      LMB0_WriteStrobe => LMB_WriteStrobe,
+      LMB0_BE          => LMB_BE,
+      Sl0_DBus         => Sl_DBus,
+      Sl0_Ready        => Sl_Ready,
+      Sl0_Wait         => Sl_Wait,
+      Sl0_UE           => Sl_UE,
+      Sl0_CE           => Sl_CE,
+      LMB1_ABus        => LMB1_ABus,
+      LMB1_WriteDBus   => LMB1_WriteDBus,
+      LMB1_AddrStrobe  => LMB1_AddrStrobe,
+      LMB1_ReadStrobe  => LMB1_ReadStrobe,
+      LMB1_WriteStrobe => LMB1_WriteStrobe,
+      LMB1_BE          => LMB1_BE,
+      Sl1_DBus         => Sl1_DBus,
+      Sl1_Ready        => Sl1_Ready,
+      Sl1_Wait         => Sl1_Wait,
+      Sl1_UE           => Sl1_UE,
+      Sl1_CE           => Sl1_CE,
+      LMB2_ABus        => LMB2_ABus,
+      LMB2_WriteDBus   => LMB2_WriteDBus,
+      LMB2_AddrStrobe  => LMB2_AddrStrobe,
+      LMB2_ReadStrobe  => LMB2_ReadStrobe,
+      LMB2_WriteStrobe => LMB2_WriteStrobe,
+      LMB2_BE          => LMB2_BE,
+      Sl2_DBus         => Sl2_DBus,
+      Sl2_Ready        => Sl2_Ready,
+      Sl2_Wait         => Sl2_Wait,
+      Sl2_UE           => Sl2_UE,
+      Sl2_CE           => Sl2_CE,
+      LMB3_ABus        => LMB3_ABus,
+      LMB3_WriteDBus   => LMB3_WriteDBus,
+      LMB3_AddrStrobe  => LMB3_AddrStrobe,
+      LMB3_ReadStrobe  => LMB3_ReadStrobe,
+      LMB3_WriteStrobe => LMB3_WriteStrobe,
+      LMB3_BE          => LMB3_BE,
+      Sl3_DBus         => Sl3_DBus,
+      Sl3_Ready        => Sl3_Ready,
+      Sl3_Wait         => Sl3_Wait,
+      Sl3_UE           => Sl3_UE,
+      Sl3_CE           => Sl3_CE,
+      LMB_ABus         => LMB_ABus_i,
+      LMB_WriteDBus    => LMB_WriteDBus_i,
+      LMB_WriteECC     => LMB_WriteECC,
+      LMB_AddrStrobe   => LMB_AddrStrobe_i,
+      LMB_ReadStrobe   => LMB_ReadStrobe_i,
+      LMB_WriteStrobe  => LMB_WriteStrobe_i,
+      IsWordWrite      => IsWordWrite,
+      LMB_BE           => LMB_BE_i,
+      Sl_DBus          => Sl_DBus_i,
+      Sl_Ready         => Sl_Ready_i,
+      Sl_Wait          => Sl_Wait_i,
+      Sl_UE            => Sl_UE_i,
+      Sl_CE            => Sl_CE_i,
+      lmb_select       => lmb_select);
+
+  BRAM_Rst_A  <= '0';
+  BRAM_Clk_A  <= LMB_Clk;
+
+  lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
+  lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
+  lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
+  lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
+
+
+  No_ECC : if (C_ECC = 0) generate
+
+  begin
+
+    BRAM_EN_A   <= LMB_AddrStrobe_i;
+    BRAM_WEN_A  <= lmb_we;
+    BRAM_Dout_A <= LMB_WriteDBus_i;
+    Sl_DBus_i   <= bram_din_a_i;
+    BRAM_Addr_A <= LMB_ABus_i(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1);
+
+    -- only used wen ECC enabled, tie to constant inactive
+    Sl_Wait_i   <= '0';
+    Sl_UE_i     <= '0';
+    Sl_CE_i     <= '0';
+    UE          <= '0';
+    CE          <= '0';
+    Interrupt   <= '0';
+
+    -----------------------------------------------------------------------------
+    -- Writes are pipelined in MB with 5 stage pipeline
+    -----------------------------------------------------------------------------
+    Ready_Handling : process (LMB_Clk) is
+    begin
+      if (LMB_Clk'event and LMB_Clk = '1') then
+        if (LMB_Rst = '1') then
+          Sl_Rdy <= '0';
+          lmb_as <= '0';
+        else
+          Sl_Rdy <= lmb_select;
+          lmb_as <= LMB_AddrStrobe_i;
+        end if;
+      end if;
+    end process Ready_Handling;
+
+    Sl_Ready_i <= Sl_Rdy and lmb_as;
+
+  end generate No_ECC;
+
+  ECC : if (C_ECC = 1) generate
+
+    constant NO_WRITES  : integer := 0;
+    constant ONLY_WORD  : integer := 1;
+    constant ALL_WRITES : integer := 2;
+
+    signal enable_ecc : std_logic;
+
+    -- On/Off Register
+    constant C_ECC_ONOFF         : natural := 31;
+    constant C_ECC_ONOFF_WIDTH   : natural := 1;
+    signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
+
+    -- Fault Inject Registers
+    signal FaultInjectData   : std_logic_vector(0 to C_LMB_DWIDTH-1);
+    signal FaultInjectECC    : std_logic_vector(32-C_ECC_WIDTH to 31);
+
+    -- Signals for read modify write operation when byte/half-word write
+    signal write_access           : std_logic;
+    signal full_word_write_access : std_logic;
+
+    signal RdModifyWr_Read        : std_logic;  -- Read cycle in read modify write sequence
+    signal RdModifyWr_Modify      : std_logic;  -- Modify cycle in read modify write sequence
+
+    signal RdModifyWr_Write       : std_logic;  -- Write cycle in read modify write sequence
+    signal LMB_ABus_Q             : std_logic_vector(0 to C_LMB_AWIDTH-1);
+    signal LMB_ABus_FFA           : std_logic_vector(0 to C_LMB_AWIDTH-1);
+
+    -- Read ECC
+    signal Syndrome          : std_logic_vector(0 to C_ECC_WIDTH-1);
+    signal CorrectedRdData   : std_logic_vector(0 to C_LMB_DWIDTH-1);
+    signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
+    signal CE_Q              : std_logic;
+    signal UE_Q              : std_logic;
+
+    signal Sl_Ready_ECC      : std_logic;    
+    
+    -- Enable and address same for both data and ECC BRAM
+    signal bram_en   : std_logic;
+    signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
+
+    subtype syndrome_bits is std_logic_vector(0 to 6);
+    type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
+    constant correct_data_table : correct_data_table_type := (
+      0 => "1100001",  1 => "1010001",  2 => "0110001",  3 => "1110001",
+      4 => "1001001",  5 => "0101001",  6 => "1101001",  7 => "0011001",
+      8 => "1011001",  9 => "0111001",  10 => "1111001",  11 => "1000101",
+      12 => "0100101",  13 => "1100101",  14 => "0010101",  15 => "1010101",
+      16 => "0110101",  17 => "1110101",  18 => "0001101",  19 => "1001101",
+      20 => "0101101",  21 => "1101101",  22 => "0011101",  23 => "1011101",
+      24 => "0111101",  25 => "1111101",  26 => "1000011",  27 => "0100011",
+      28 => "1100011",  29 => "0010011",  30 => "1010011",  31 => "0110011"
+      );
+
+    type bool_array is array (natural range 0 to 6) of boolean;
+    constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
+  begin
+
+    assert C_LMB_DWIDTH = 32 report "C_LMB_DWIDTH must be 32 when C_ECC = 1" severity failure;
+
+    -- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
+    bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
+               '0';
+
+    BRAM_EN_A <= bram_en;
+
+    -----------------------------------------------------------------------------
+    -- Writes are pipelined in MB with 5 stage pipeline
+    -----------------------------------------------------------------------------
+    Ready_Handling : process (LMB_Clk) is
+    begin
+      if (LMB_Clk'event and LMB_Clk = '1') then
+        if (LMB_Rst = '1') then
+          Sl_Rdy <= '0';
+          lmb_as <= '0';
+
+        else
+          -- Directly drive ready on valid read access or on valid word write access
+          -- otherwise drive ready when we have written the new data on a
+          -- readmodifywrite sequence
+          Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
+                        or RdModifyWr_Write;
+          lmb_as <= LMB_AddrStrobe_i;
+        end if;
+      end if;
+    end process Ready_Handling;
+
+    Sl_Ready_i <= Sl_Rdy;
+
+    Sl_Ready_ECC_LMB_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+    begin
+      -- ECC checking enable during access and when checking is turned on
+      enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
+      Sl_Ready_ECC <= Sl_Ready_i;
+    end generate Sl_Ready_ECC_LMB_Protocol_0;
+
+    Sl_Ready_ECC_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+    begin
+      Sl_Ready_ECC_p : process(LMB_Clk) is
+      begin
+        if LMB_Clk'event and LMB_Clk = '1' then
+          if LMB_Rst = '1' then
+            enable_ecc   <= '0';
+            Sl_Ready_ECC <= '0';
+          else
+            -- ECC checking enable during access and when checking is turned on
+            enable_ecc   <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
+            Sl_Ready_ECC <= Sl_Ready_i;
+          end if;
+        end if;
+      end process Sl_Ready_ECC_p;
+    end generate Sl_Ready_ECC_LMB_Protocol_1;
+    
+    Wait_Handling: process (LMB_Clk) is
+    begin  -- process Wait_Handling
+      if (LMB_Clk'event and LMB_Clk = '1') then
+        if (LMB_Rst = '1') then
+          Sl_Wait_i <= '0';
+        elsif (LMB_AddrStrobe_i = '1') then
+          Sl_Wait_i <= lmb_select;
+        elsif (Sl_Rdy = '1') then
+          Sl_Wait_i <= '0';
+        end if;
+      end if;
+    end process Wait_Handling;
+
+    -- Generate ECC bits for checking data read from BRAM
+    checkbit_handler_I1 : checkbit_handler
+      generic map (
+        C_TARGET   => C_TARGET,
+        C_ENCODE   => false)                 -- [boolean]
+      port map (
+        DataIn     => bram_din_a_i(0 to 31),   -- [in  std_logic_vector(0 to 31)]
+        CheckIn    => bram_din_a_i(33 to 39),  -- [in  std_logic_vector(0 to 6)]
+        CheckOut   => open,                    -- [out std_logic_vector(0 to 6)]
+        Syndrome   => Syndrome,                -- [out std_logic_vector(0 to 6)]
+        Enable_ECC => enable_ecc,              -- [in  std_logic]
+        UE_Q       => UE_Q,                    -- [in  std_logic]
+        CE_Q       => CE_Q,                    -- [in  std_logic]
+        UE         => Sl_UE_i,                 -- [out std_logic]
+        CE         => Sl_CE_i);                -- [out std_logic]
+
+    -- Discrete error signals
+    UE <= Sl_UE_i and Sl_Ready_ECC;
+    CE <= Sl_CE_i and Sl_Ready_ECC;
+
+    -- Correct Data
+    Gen_Correct_Data: for I in 0 to 31 generate
+      Correct_One_Bit_I : Correct_One_Bit
+        generic map (
+          C_TARGET      => C_TARGET,
+          Correct_Value => correct_data_table(I))
+        port map (
+          DIn           => bram_din_a_i(I),
+          Syndrome      => Syndrome,
+          DCorr         => CorrectedRdData(I));
+    end generate Gen_Correct_Data;
+
+    -- Drive corrected read data on LMB
+    Sl_DBus_i <= CorrectedRdData;
+
+    -- Remember address and writestrobe
+    AddressReg : process(LMB_Clk) is
+    begin
+      if (LMB_Clk'event and LMB_Clk = '1') then
+        if LMB_Rst = '1' then
+          LMB_ABus_Q             <= (others => '0');
+          write_access           <= '0';
+          full_word_write_access <= '0';
+        elsif LMB_AddrStrobe_i = '1' then
+          LMB_ABus_Q             <= LMB_ABus_i;
+          write_access           <= LMB_WriteStrobe_i;
+          full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
+        end if;
+      end if;
+    end process AddressReg;
+
+    bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
+                 LMB_ABus_i;
+
+    BRAM_Addr_A <= bram_addr(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1);
+
+    -- CE and UE generated when ready asserted, i.e. use sampled address
+    LMB_ABus_FFA_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+    begin
+      LMB_ABus_FFA <= LMB_ABus_Q;
+    end generate LMB_ABus_FFA_Protocol_0;
+
+    -- CE and UE generated one cycle after ready asserted, clock sampled address one extra time
+    -- to be valid the same time as data for sampling in First Failing Address register
+    LMB_ABus_FFA_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+    begin
+      LMB_ABus_FFA_p : process(LMB_Clk) is
+      begin
+        if LMB_Clk'event and LMB_Clk = '1' then
+          if LMB_Rst = '1' then
+            LMB_ABus_FFA <= (others => '0');
+          else
+            LMB_ABus_FFA <= LMB_ABus_Q;
+          end if;
+        end if;
+      end process LMB_ABus_FFA_p;
+    end generate LMB_ABus_FFA_LMB_Protocol_1;
+
+    Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
+      signal WrData  : std_logic_vector(0 to C_LMB_DWIDTH-1);
+      signal WrECC   : std_logic_vector(0 to C_ECC_WIDTH-1);
+    begin
+
+      DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
+        signal wrdata_i    : std_logic_vector(0 to C_LMB_DWIDTH-1);
+        signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
+        signal lmb_be_q    : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
+      begin
+
+        -- Remember correctable/uncorrectable error from read in read modify write
+        CorrReg : process(LMB_Clk) is
+        begin
+          if (LMB_Clk'event and LMB_Clk = '1') then
+            if RdModifyWr_Modify = '1' then   -- Remember error signals
+              CE_Q <= Sl_CE_i;
+              UE_Q <= Sl_UE_i;
+            elsif RdModifyWr_Write = '1' then   -- Keep the signals one more cycle
+              CE_Q <= CE_Q;
+              UE_Q <= UE_Q;
+            else
+              CE_Q <= '0';
+              UE_Q <= '0';
+            end if;
+          end if;
+        end process CorrReg;
+
+        RdModifyWr_LMB_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+          signal RdModifyWr_Modify_i    : std_logic;  -- Modify cycle in read modify write sequence
+        begin
+
+          -- Remember byte write enables one clock cycle to properly mux bytes to write,
+          -- with read data in read/modify write operation
+          -- Write in Read/Write always 1 cycle after Read
+          StoreLMB_WE : process(LMB_Clk) is
+          begin
+            if (LMB_Clk'event and LMB_Clk = '1') then
+              if (LMB_Rst = '1') then
+                 RdModifyWr_Modify_i  <= '0';
+                 RdModifyWr_Write     <= '0';
+                 CorrectedRdData_Q    <= (others => '0');
+               else
+                 RdModifyWr_Modify_i <= RdModifyWr_Read;
+                 RdModifyWr_Write    <= RdModifyWr_Modify;
+                 CorrectedRdData_Q   <= CorrectedRdData;
+              end if;
+            end if;
+          end process StoreLMB_WE;
+
+          RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
+
+          RdModifyWr_Read  <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
+                              '0';
+
+        end generate RdModifyWr_LMB_Protocol_0;
+
+
+        RdModifyWr_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+         signal RdModifyWr_Read_Q    : std_logic;  -- Read cycle in read modify write sequence gated by lmb_as
+         signal RdModifyWr_Read_Q_i  : std_logic;  -- Read cycle in read modify write sequence
+        begin
+        
+          StoreLMB_WE : process(LMB_Clk) is
+          begin
+            if (LMB_Clk'event and LMB_Clk = '1') then
+              if (LMB_Rst = '1') then
+                 RdModifyWr_Read_Q_i <= '0';
+                 RdModifyWr_Modify   <= '0';
+                 RdModifyWr_Write    <= '0';
+                 CorrectedRdData_Q   <= (others => '0');
+               else
+                 RdModifyWr_Read_Q_i <= RdModifyWr_Read;
+                 RdModifyWr_Modify   <= RdModifyWr_Read_Q;
+                 RdModifyWr_Write    <= RdModifyWr_Modify;
+                 CorrectedRdData_Q   <= CorrectedRdData;
+              end if;
+            end if;
+          end process StoreLMB_WE;
+
+          RdModifyWr_Read_Q <= RdModifyWr_Read_Q_i and lmb_as;
+
+          RdModifyWr_Read  <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
+                              '0';
+
+        end generate RdModifyWr_LMB_Protocol_1;
+
+        
+        -- Remember write data one cycle to be available after read has been completed in a
+        -- read/modify write operation
+        StoreWriteDBus : process(LMB_Clk) is
+        begin
+          if (LMB_Clk'event and LMB_Clk = '1') then
+            if (LMB_Rst = '1') then
+              WriteDBus_Q <= (others => '0');
+              lmb_be_q    <= (others => '0');
+            elsif (LMB_AddrStrobe_i = '1') then
+              WriteDBus_Q <= LMB_WriteDBus_i;
+              lmb_be_q    <= LMB_BE_i;
+            end if;
+          end if;
+        end process StoreWriteDBus;
+
+        wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
+
+        -- Select BRAM data to write from LMB on 32-bit word access or a mix of
+        -- read data and LMB write data for read/modify write operations
+        WrData(0 to 7)   <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
+                                                   (RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
+                            CorrectedRdData_Q(0 to 7);
+        WrData(8 to 15)  <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
+                                                    (RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
+                            CorrectedRdData_Q(8 to 15);
+        WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
+                                                     (RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
+                            CorrectedRdData_Q(16 to 23);
+        WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
+                                                     (RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
+                            CorrectedRdData_Q(24 to 31);
+
+        One_LMB: if (C_NUM_LMB = 1) generate
+        begin
+ 
+          -- Generate ECC bits for writing into BRAM
+          checkbit_handler_I2 : checkbit_handler
+            generic map (
+              C_TARGET   => C_TARGET,
+              C_ENCODE   => true)           -- [boolean]
+            port map (
+              DataIn     => WrData,         -- [in  std_logic_vector(0 to 31)]
+              CheckIn    => (others => '0'),-- [in  std_logic_vector(0 to 6)]
+              CheckOut   => WrECC,          -- [out std_logic_vector(0 to 6)]
+              Syndrome   => open,           -- [out std_logic_vector(0 to 6)]
+              Enable_ECC => '1',            -- [in  std_logic]
+              UE_Q       => '0',            -- [in  std_logic]
+              CE_Q       => '0',            -- [in  std_logic]
+              UE         => open,           -- [out std_logic]
+              CE         => open);          -- [out std_logic]
+
+        end generate One_LMB;
+
+        -- Timing QoR to move ECC generation before LMB source selection for
+        -- one cycle word write
+        Many_LMB: if (C_NUM_LMB > 1) generate
+          signal WrECC_i        : std_logic_vector(0 to C_ECC_WIDTH-1);
+          signal RdModifyWrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
+        begin
+          -- Only used for generating ECC for Read-Modify-Write
+          RdModifyWrData(0 to 7)   <= WriteDBus_Q(0 to 7) when lmb_be_q(0) = '1' else
+                                      CorrectedRdData_Q(0 to 7);
+          RdModifyWrData(8 to 15)  <= WriteDBus_Q(8 to 15) when lmb_be_q(1) = '1' else
+                                      CorrectedRdData_Q(8 to 15);
+          RdModifyWrData(16 to 23) <= WriteDBus_Q(16 to 23) when lmb_be_q(2) = '1' else
+                                      CorrectedRdData_Q(16 to 23);
+          RdModifyWrData(24 to 31) <= WriteDBus_Q(24 to 31) when lmb_be_q(3) = '1' else
+                                      CorrectedRdData_Q(24 to 31);
+          -- Generate ECC bits for writing into BRAM
+          checkbit_handler_I2 : checkbit_handler
+            generic map (
+              C_TARGET   => C_TARGET,
+              C_ENCODE   => true)           -- [boolean]
+            port map (
+              DataIn     => RdModifyWrData, -- [in  std_logic_vector(0 to 31)]
+              CheckIn    => (others => '0'),-- [in  std_logic_vector(0 to 6)]
+              CheckOut   => WrECC_i,        -- [out std_logic_vector(0 to 6)]
+              Syndrome   => open,           -- [out std_logic_vector(0 to 6)]
+              Enable_ECC => '1',            -- [in  std_logic]
+              UE_Q       => '0',            -- [in  std_logic]
+              CE_Q       => '0',            -- [in  std_logic]
+              UE         => open,           -- [out std_logic]
+              CE         => open);          -- [out std_logic]
+          
+          WrECC <= WrECC_i when RdModifyWr_Write = '1' else  -- from Read-Modify-Write above
+                   LMB_WriteECC;                             -- directly from lmb_mux pre generated ECC
+        end generate Many_LMB;
+
+      end generate DO_BYTE_HALFWORD_WRITES;
+
+      DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
+        RdModifyWr_Write  <= '0';
+        RdModifyWr_Read   <= '0';
+        RdModifyWr_Modify <= '0';
+        CorrectedRdData_Q <= (others => '0');
+        WrData            <= LMB_WriteDBus_i;
+        CE_Q              <= '0';
+        UE_Q              <= '0';
+      end generate DO_Only_Word_Writes;
+
+      -- Generate BRAM WEN, which will always be all 1's due to read modify write
+      -- for non 32-bit word access
+      WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
+      begin
+        if (RdModifyWr_Modify = '1') then
+          BRAM_WEN_A <= (others => '0');
+        elsif (RdModifyWr_Write = '1') then
+          if (UE_Q = '0') then
+            BRAM_WEN_A <= (others => '1');  -- byte or half word write, and not UE
+          else
+            BRAM_WEN_A <= (others => '0');
+          end if;
+        elsif (IsWordWrite = '1') then           -- word write
+          BRAM_WEN_A <= (others => lmb_select);
+        else
+          BRAM_WEN_A <= (others => '0');
+        end if;
+      end process WrDataSel;
+  
+      -- Drive BRAM write data and inject fault if applicable
+      BRAM_Dout_A(0 to 31)  <= WrData xor FaultInjectData;
+      BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
+
+    end generate Do_Writes;
+
+    No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
+      RdModifyWr_Write  <= '0';
+      RdModifyWr_Read   <= '0';
+      RdModifyWr_Modify <= '0';
+      CorrectedRdData_Q <= (others => '0');
+      FaultInjectData   <= (others => '0');
+      FaultInjectECC    <= (others => '0');
+      CE_Q              <= '0';
+      UE_Q              <= '0';
+      BRAM_WEN_A        <= (others => '0');
+      BRAM_Dout_A       <= (others => '0');
+    end generate No_Write_Accesses;
+
+    Has_AXI : if C_HAS_AXI generate
+
+      -- Register accesses
+      -- Register addresses use word address, i.e 2 LSB don't care
+      -- Don't decode MSB, i.e. mirroring of registers in address space of module
+      -- Don't decode unmapped addresses
+      -- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
+      -- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
+      -- Address registers occupy 2 words to accommodate 64-bit address
+      constant C_REGADDR_WIDTH     : integer          := 8;
+      constant C_ECC_StatusReg     : std_logic_vector := "00000000";  -- 0x000 ECC_STATUS
+      constant C_ECC_EnableIRQReg  : std_logic_vector := "00000001";  -- 0x004 ECC_EN_IRQ
+      constant C_ECC_OnOffReg      : std_logic_vector := "00000010";  -- 0x008 ECC_ONOFF
+      constant C_CE_CounterReg     : std_logic_vector := "00000011";  -- 0x00C CE_CNT
+      constant C_CE_FailingData    : std_logic_vector := "01000000";  -- 0x100 CE_FFD[31:0]
+      constant C_CE_FailingECC     : std_logic_vector := "01100000";  -- 0x180 CE_FFE
+      constant C_CE_FailingAddrLSH : std_logic_vector := "01110000";  -- 0x1C0 CE_FFA[31:0]
+      constant C_CE_FailingAddrMSH : std_logic_vector := "01110001";  -- 0x1C4 CE_FFA[C_LMB_AWIDTH-1:32]
+      constant C_UE_FailingData    : std_logic_vector := "10000000";  -- 0x200 UE_FFD[31:0]
+      constant C_UE_FailingECC     : std_logic_vector := "10100000";  -- 0x280 UE_FFE
+      constant C_UE_FailingAddrLSH : std_logic_vector := "10110000";  -- 0x2C0 UE_FFA[31:0]
+      constant C_UE_FailingAddrMSH : std_logic_vector := "10110001";  -- 0x2C4 UE_FFA[C_LMB_AWIDTH-1:32]
+      constant C_FaultInjectData   : std_logic_vector := "11000000";  -- 0x300 FI_D[31:0]
+      constant C_FaultInjectECC    : std_logic_vector := "11100000";  -- 0x380 FI_ECC
+
+      -- ECC Status register bit positions
+      constant C_ECC_STATUS_CE        : natural := 30;
+      constant C_ECC_STATUS_UE        : natural := 31;
+      constant C_ECC_STATUS_WIDTH     : natural := 2;
+      constant C_ECC_ENABLE_IRQ_CE    : natural := 30;
+      constant C_ECC_ENABLE_IRQ_UE    : natural := 31;
+      constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
+
+      -- Read and write data to internal registers
+      constant C_DWIDTH : integer := 32;
+      signal RegWrData  : std_logic_vector(0 to C_DWIDTH-1);
+      signal RegRdData  : std_logic_vector(0 to C_DWIDTH-1);
+      signal RegAddr    : std_logic_vector(0 to C_REGADDR_WIDTH-1);
+      signal RegWr      : std_logic;
+
+      -- Correctable Error First Failing Register
+      signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
+      signal CE_FailingAddrLSH : std_logic_vector(0 to 31);
+      signal CE_FailingAddrMSH : std_logic_vector(0 to 31);
+      signal CE_FailingData    : std_logic_vector(0 to C_LMB_DWIDTH-1);
+      signal CE_FailingECC     : std_logic_vector(32-C_ECC_WIDTH to 31);
+      -- Uncorrectable Error First Failing Register
+      signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
+      signal UE_FailingAddrLSH : std_logic_vector(0 to 31);
+      signal UE_FailingAddrMSH : std_logic_vector(0 to 31);
+      signal UE_FailingData    : std_logic_vector(0 to C_LMB_DWIDTH-1);
+      signal UE_FailingECC     : std_logic_vector(32-C_ECC_WIDTH to 31);
+      -- ECC Status and Control register
+      signal ECC_StatusReg     : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
+      signal ECC_EnableIRQReg  : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
+
+      -- Correctable Error Counter
+      signal CE_CounterReg     : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
+
+      signal sample_registers : std_logic;
+
+    begin
+
+      sample_registers_LMB_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+      begin
+        sample_registers <= lmb_as and not full_word_write_access;
+      end generate sample_registers_LMB_Protocol_0;
+
+      sample_registers_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+      begin
+        -- BRAM read data clocked UE, CE also one cycle later
+        sample_registers_dff : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              sample_registers <= '0';
+            else
+              sample_registers <= lmb_as and not full_word_write_access;
+            end if;
+          end if;
+        end process sample_registers_dff;
+      end generate sample_registers_LMB_Protocol_1;
+
+      -- Implement fault injection registers
+      Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
+      begin
+        FaultInjectDataReg : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              FaultInjectData <= (others => '0');
+              FaultInjectECC  <= (others => '0');
+            elsif RegWr = '1' and RegAddr = C_FaultInjectData then
+              FaultInjectData <= RegWrData;
+            elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
+              FaultInjectECC  <= RegWrData(FaultInjectECC'range);
+            elsif (Sl_Rdy = '1') and (write_access = '1') then  -- One shoot, clear after first LMB write
+              FaultInjectData <= (others => '0');
+              FaultInjectECC  <= (others => '0');
+            end if;
+          end if;
+        end process FaultInjectDataReg;
+      end generate Fault_Inject;
+
+      No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
+      begin
+        FaultInjectData <= (others => '0');
+        FaultInjectECC  <= (others => '0');
+      end generate No_Fault_Inject;
+
+      -- Implement Correctable Error First Failing Register
+      CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
+      begin
+        CE_FailingReg : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              CE_FailingAddress <= (others => '0');
+              CE_FailingData    <= (others => '0');
+              CE_FailingECC     <= (others => '0');
+            elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
+              CE_FailingAddress <= LMB_ABus_FFA;
+              CE_FailingData    <= bram_din_a_i(CE_FailingData'range);
+              CE_FailingECC     <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
+            end if;
+          end if;
+        end process CE_FailingReg;
+
+        CE_FailingAddrLSH <= CE_FailingAddress(C_LMB_AWIDTH-32 to C_LMB_AWIDTH-1);
+
+        Use_Extended_Address: if C_LMB_AWIDTH > 32 generate
+        begin
+          Assign_FailingAddress: process (CE_FailingAddress) is
+          begin
+            CE_FailingAddrMSH <= (others => '0');
+            for I in 0 to C_LMB_AWIDTH - 32 - 1 loop
+              CE_FailingAddrMSH(64 - C_LMB_AWIDTH + I) <= CE_FailingAddress(I);
+            end loop;
+          end process Assign_FailingAddress;
+        end generate Use_Extended_Address;
+
+        No_Extended_Address: if C_LMB_AWIDTH <= 32 generate
+        begin
+          CE_FailingAddrMSH <= (others => '0');
+        end generate No_Extended_Address;
+
+      end generate CE_Failing_Registers;
+
+      No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
+      begin
+        CE_FailingAddress <= (others => '0');
+        CE_FailingAddrLSH <= (others => '0');
+        CE_FailingAddrMSH <= (others => '0');
+        CE_FailingData    <= (others => '0');
+        CE_FailingECC     <= (others => '0');
+      end generate No_CE_Failing_Registers;
+
+      -- Implement Unorrectable Error First Failing Register
+      UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
+      begin
+        UE_FailingReg : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              UE_FailingAddress <= (others => '0');
+              UE_FailingData    <= (others => '0');
+              UE_FailingECC     <= (others => '0');
+            elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
+              UE_FailingAddress <= LMB_ABus_FFA;
+              UE_FailingData    <= bram_din_a_i(UE_FailingData'range);
+              UE_FailingECC     <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
+            end if;
+          end if;
+        end process UE_FailingReg;
+
+        UE_FailingAddrLSH <= UE_FailingAddress(C_LMB_AWIDTH-32 to C_LMB_AWIDTH-1);
+
+        Use_Extended_Address: if C_LMB_AWIDTH > 32 generate
+        begin
+          Assign_FailingAddress: process (UE_FailingAddress) is
+          begin
+            UE_FailingAddrMSH <= (others => '0');
+            for I in 0 to C_LMB_AWIDTH - 32 - 1 loop
+              UE_FailingAddrMSH(64 - C_LMB_AWIDTH + I) <= UE_FailingAddress(I);
+            end loop;
+          end process Assign_FailingAddress;
+        end generate Use_Extended_Address;
+
+        No_Extended_Address: if C_LMB_AWIDTH <= 32 generate
+        begin
+          UE_FailingAddrMSH <= (others => '0');
+        end generate No_Extended_Address;
+
+      end generate UE_Failing_Registers;
+
+      No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
+      begin
+        UE_FailingAddress <= (others => '0');
+        UE_FailingAddrLSH <= (others => '0');
+        UE_FailingAddrMSH <= (others => '0');
+        UE_FailingData    <= (others => '0');
+        UE_FailingECC     <= (others => '0');
+      end generate No_UE_Failing_Registers;
+
+      ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
+      begin
+
+        StatusReg : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              ECC_StatusReg <= (others => '0');
+            elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
+              -- CE Interrupt status bit
+              if RegWrData(C_ECC_STATUS_CE) = '1' then
+                ECC_StatusReg(C_ECC_STATUS_CE) <= '0';  -- Clear when write '1'
+              end if;
+              -- UE Interrupt status bit
+              if RegWrData(C_ECC_STATUS_UE) = '1' then
+                ECC_StatusReg(C_ECC_STATUS_UE) <= '0';  -- Clear when write '1'
+              end if;
+            else
+              if Sl_CE_i = '1' and sample_registers = '1' then
+                ECC_StatusReg(C_ECC_STATUS_CE) <= '1';  -- Set when CE occurs
+              end if;
+              if Sl_UE_i = '1' and sample_registers = '1' then
+                ECC_StatusReg(C_ECC_STATUS_UE) <= '1';  -- Set when UE occurs
+              end if;
+            end if;
+          end if;
+        end process StatusReg;
+
+        EnableIRQReg : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              ECC_EnableIRQReg <= (others => '0');
+            elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
+              -- CE Interrupt enable bit
+              ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
+              -- UE Interrupt enable bit
+              ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
+            end if;
+          end if;
+        end process EnableIRQReg;
+
+        Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
+                     (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
+
+      end generate ECC_Status_Registers;
+
+      No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
+      begin
+        ECC_EnableIRQReg <= (others => '0');
+        ECC_StatusReg    <= (others => '0');
+        Interrupt        <= '0';
+      end generate No_ECC_Status_Registers;
+
+      ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
+      begin
+
+        OnOffReg : process(LMB_Clk) is
+        begin
+          if LMB_Clk'event and LMB_Clk = '1' then
+            if LMB_Rst = '1' then
+              if C_ECC_ONOFF_RESET_VALUE = 0 then
+                 ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
+              else
+                 ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
+              end if;
+            elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
+              ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
+            end if;
+          end if;
+        end process OnOffReg;
+
+      end generate ECC_OnOff_Register;
+
+      No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
+      begin
+        ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
+      end generate No_ECC_OnOff_Register;
+
+      CE_Counter : if C_HAS_CE_COUNTER generate
+        -- One extra bit compare to CE_CounterReg to handle carry bit
+        signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
+      begin
+
+        CountReg : process(LMB_Clk) is
+        begin
+          if (LMB_Clk'event and LMB_Clk = '1') then
+            if (LMB_Rst = '1') then
+              CE_CounterReg <= (others => '0');
+            elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
+              CE_CounterReg <= RegWrData(CE_CounterReg'range);
+            elsif Sl_CE_i = '1' and
+                  sample_registers = '1' and
+                  CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
+              CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
+            end if;
+          end if;
+        end process CountReg;
+
+        CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
+
+      end generate CE_Counter;
+
+      No_CE_Counter : if not C_HAS_CE_COUNTER generate
+      begin
+        CE_CounterReg <= (others => '0');
+      end generate No_CE_Counter;
+
+      SelRegRdData : process (RegAddr,
+                              ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
+                              CE_FailingAddrLSH, CE_FailingAddrMSH, CE_FailingData, CE_FailingECC,
+                              UE_FailingAddrLSH, UE_FailingAddrMSH, UE_FailingData, UE_FailingECC)
+      begin
+        RegRdData <= (others => '0');
+
+        case RegAddr is
+          when C_ECC_StatusReg     => RegRdData(ECC_StatusReg'range)          <= ECC_StatusReg;
+          when C_ECC_EnableIRQReg  => RegRdData(ECC_EnableIRQReg'range)       <= ECC_EnableIRQReg;
+          when C_ECC_OnOffReg      => RegRdData(ECC_EnableCheckingReg'range)  <= ECC_EnableCheckingReg;
+          when C_CE_CounterReg     => RegRdData(CE_CounterReg'range)          <= CE_CounterReg;
+          when C_CE_FailingAddrLSH => RegRdData                               <= CE_FailingAddrLSH;
+          when C_CE_FailingAddrMSH => RegRdData                               <= CE_FailingAddrMSH;
+          when C_CE_FailingData    => RegRdData(CE_FailingData'range)         <= CE_FailingData;
+          when C_CE_FailingECC     => RegRdData(CE_FailingECC'range)          <= CE_FailingECC;
+          when C_UE_FailingAddrLSH => RegRdData                               <= UE_FailingAddrLSH;
+          when C_UE_FailingAddrMSH => RegRdData                               <= UE_FailingAddrMSH;
+          when C_UE_FailingData    => RegRdData(UE_FailingData'range)         <= UE_FailingData;
+          when C_UE_FailingECC     => RegRdData(UE_FailingECC'range)          <= UE_FailingECC;
+          when others              => RegRdData                               <= (others => '0');
+        end case;
+      end process SelRegRdData;
+
+      AXI : if C_HAS_AXI generate
+      begin
+        axi_I : axi_interface
+        generic map(
+          C_TARGET           => C_TARGET,
+          C_S_AXI_BASEADDR   => C_S_AXI_CTRL_BASEADDR,
+          C_S_AXI_HIGHADDR   => C_S_AXI_CTRL_HIGHADDR,
+          C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
+          C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
+          C_REGADDR_WIDTH    => C_REGADDR_WIDTH,
+          C_DWIDTH           => C_DWIDTH)
+        port map (
+          LMB_Clk       => LMB_Clk,
+          LMB_Rst       => LMB_Rst,
+          S_AXI_AWADDR  => S_AXI_CTRL_AWADDR,
+          S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
+          S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
+          S_AXI_WDATA   => S_AXI_CTRL_WDATA,
+          S_AXI_WSTRB   => S_AXI_CTRL_WSTRB,
+          S_AXI_WVALID  => S_AXI_CTRL_WVALID,
+          S_AXI_WREADY  => S_AXI_CTRL_WREADY,
+          S_AXI_BRESP   => S_AXI_CTRL_BRESP,
+          S_AXI_BVALID  => S_AXI_CTRL_BVALID,
+          S_AXI_BREADY  => S_AXI_CTRL_BREADY,
+          S_AXI_ARADDR  => S_AXI_CTRL_ARADDR,
+          S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
+          S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
+          S_AXI_RDATA   => S_AXI_CTRL_RDATA,
+          S_AXI_RRESP   => S_AXI_CTRL_RRESP,
+          S_AXI_RVALID  => S_AXI_CTRL_RVALID,
+          S_AXI_RREADY  => S_AXI_CTRL_RREADY,
+          RegWr         => RegWr,
+          RegWrData     => RegWrData,
+          RegAddr       => RegAddr,
+          RegRdData     => RegRdData);
+      end generate AXI;
+
+    end generate Has_AXI;
+
+    No_AXI : if not C_HAS_AXI generate
+    begin
+      FaultInjectData <= (others => '0');
+      FaultInjectECC  <= (others => '0');
+      Interrupt       <= '0';
+
+      ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
+    end generate No_AXI;
+
+  end generate ECC;
+
+  No_AXI_ECC : if not C_HAS_AXI generate
+  begin
+    S_AXI_CTRL_AWREADY <= '0';
+    S_AXI_CTRL_WREADY  <= '0';
+    S_AXI_CTRL_BRESP   <= (others => '0');
+    S_AXI_CTRL_BVALID  <= '0';
+    S_AXI_CTRL_ARREADY <= '0';
+    S_AXI_CTRL_RDATA   <= (others => '0');
+    S_AXI_CTRL_RRESP   <= (others => '0');
+    S_AXI_CTRL_RVALID  <= '0';
+  end generate No_AXI_ECC;
+
+end architecture imp;
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd
new file mode 100755
index 0000000..6b15c31
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd
@@ -0,0 +1,288 @@
+-------------------------------------------------------------------------------
+-- lmb_v10.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and 
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Filename:        lmb_v10.vhd
+--
+-- Description:     
+--                  
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   
+--              lmb_v10.vhd
+--
+-------------------------------------------------------------------------------
+-- Author:          rolandp
+--
+-- History:
+--  goran   2002-01-30    First Version
+--  paulo   2002-04-10    Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
+--  roland  2010-02-13    UE, CE and Wait signals added
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity lmb_v10 is
+
+  generic (
+    C_LMB_NUM_SLAVES     : integer := 4;
+    C_LMB_DWIDTH     : integer := 32;
+    C_LMB_AWIDTH     : integer := 32;
+    C_LMB_PROTOCOL   : integer := 0;
+    C_EXT_RESET_HIGH : integer := 1
+    );
+
+  port (
+    -- Global Ports
+    LMB_Clk : in  std_logic;
+    SYS_Rst : in  std_logic;
+    LMB_Rst : out std_logic;
+
+    -- LMB master signals
+    M_ABus        : in std_logic_vector(0 to C_LMB_AWIDTH-1);
+    M_ReadStrobe  : in std_logic;
+    M_WriteStrobe : in std_logic;
+    M_AddrStrobe  : in std_logic;
+    M_DBus        : in std_logic_vector(0 to C_LMB_DWIDTH-1);
+    M_BE          : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
+
+    -- LMB slave signals
+    Sl_DBus  : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
+    Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
+    Sl_Wait  : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
+    Sl_UE    : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
+    Sl_CE    : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
+    
+    -- LMB output signals
+    LMB_ABus        : out std_logic_vector(0 to C_LMB_AWIDTH-1);
+    LMB_ReadStrobe  : out std_logic;
+    LMB_WriteStrobe : out std_logic;
+    LMB_AddrStrobe  : out std_logic;
+    LMB_ReadDBus    : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB_WriteDBus   : out std_logic_vector(0 to C_LMB_DWIDTH-1);
+    LMB_Ready       : out std_logic;
+    LMB_Wait        : out std_logic;
+    LMB_UE          : out std_logic;
+    LMB_CE          : out std_logic;
+    LMB_BE          : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
+    );
+end entity lmb_v10;
+
+library unisim;
+use unisim.all;
+
+architecture IMP of lmb_v10 is
+
+  component FDS is
+    port(
+      Q : out std_logic;
+      D : in  std_logic;
+      C : in  std_logic;
+      S : in  std_logic);
+  end component FDS;
+
+  signal sys_rst_i    : std_logic;
+  signal Sl_Ready_i   : std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
+
+begin  -- architecture IMP
+
+  -----------------------------------------------------------------------------
+  -- Driving the reset signal
+  -----------------------------------------------------------------------------
+
+  SYS_RST_PROC : process (SYS_Rst) is
+    variable sys_rst_input : std_logic;
+  begin
+    if C_EXT_RESET_HIGH = 0 then
+      sys_rst_input := not SYS_Rst;
+    else
+      sys_rst_input := SYS_Rst;
+    end if;
+    sys_rst_i <= sys_rst_input;
+  end process SYS_RST_PROC;
+
+  POR_FF_I : FDS
+    port map (
+      Q => LMB_Rst,
+      D => '0',
+      C => LMB_Clk,
+      S => sys_rst_i);
+
+  -- Standard LMB protocol with RAM data read combinatorial through LMB controller 
+  Sl_Ready_LMB_Protocol_0 : if (C_LMB_PROTOCOL = 0) generate
+  begin
+    Sl_Ready_i <= Sl_Ready;
+  end generate Sl_Ready_LMB_Protocol_0;
+    
+  -- Timing optimized LMB protocol with RAM data read clocked in LMB controller
+  -- Sl_Ready needs to be clocked once to match clocked timing of DBus
+  -- Only works with MicroBlaze 8-stage pipe and C_LMB_PROTOCOL set to 1 on MicroBlaze
+  Sl_Ready_LMB_Protocol_1 : if (C_LMB_PROTOCOL = 1) generate
+  begin
+    -----------------------------------------------------------------------------
+    -- Provide clocked Sl_Ready
+    -----------------------------------------------------------------------------
+    Ready_DFF : process (LMB_Clk) is
+    begin
+      if LMB_Clk'event and LMB_Clk = '1' then
+        if SYS_Rst = '1' then
+          Sl_Ready_i <= (others => '0');
+        else
+          Sl_Ready_i <= Sl_Ready;
+        end if;
+      end if;
+    end process Ready_DFF;
+  end generate Sl_Ready_LMB_Protocol_1;
+  
+  -----------------------------------------------------------------------------
+  -- Drive all Master to Slave signals
+  -----------------------------------------------------------------------------
+  LMB_ABus        <= M_ABus;
+  LMB_ReadStrobe  <= M_ReadStrobe;
+  LMB_WriteStrobe <= M_WriteStrobe;
+  LMB_AddrStrobe  <= M_AddrStrobe;
+  LMB_BE          <= M_BE;
+  LMB_WriteDBus   <= M_DBus;
+
+  -----------------------------------------------------------------------------
+  -- Drive all the Slave to Master signals
+  -----------------------------------------------------------------------------
+  Ready_ORing : process (Sl_Ready) is
+    variable i : std_logic;
+  begin  -- process Ready_ORing
+    i := '0';
+    for S in Sl_Ready'range loop
+      i := i or Sl_Ready(S);
+    end loop;  -- S
+    LMB_Ready <= i;
+  end process Ready_ORing;
+
+  Wait_ORing : process (Sl_Wait) is
+    variable i : std_logic;
+  begin  -- process Wait_ORing
+    i := '0';
+    for S in Sl_Wait'range loop
+      i := i or Sl_Wait(S);
+    end loop;  -- S
+    LMB_Wait <= i;
+  end process Wait_ORing;
+
+  SI_UE_ORing : process (Sl_UE) is
+  variable i : std_logic;
+  begin  -- process UE_ORing
+    i := '0';
+    for S in Sl_UE'range loop
+      i := i or Sl_UE(S);
+    end loop;  -- S
+    LMB_UE <= i;
+  end process SI_UE_ORing;
+
+  SI_CE_ORing : process (Sl_CE) is
+  variable i : std_logic;
+  begin  -- process CE_ORing
+    i := '0';
+    for S in Sl_CE'range loop
+      i := i or Sl_CE(S);
+    end loop;  -- S
+    LMB_CE <= i;
+  end process SI_CE_ORing;
+
+  DBus_Oring : process (Sl_Ready_i, Sl_DBus) is
+    variable Res    : std_logic_vector(0 to C_LMB_DWIDTH-1);
+    variable Tmp    : std_logic_vector(Sl_DBus'range);
+    variable tmp_or : std_logic;
+  begin  -- process DBus_Oring
+    if (C_LMB_NUM_SLAVES = 1) then
+      LMB_ReadDBus <= Sl_DBus;
+    else
+      -- First gating all data signals with their resp. ready signal
+      for I in 0 to C_LMB_NUM_SLAVES-1 loop
+        for J in 0 to C_LMB_DWIDTH-1 loop
+          tmp(I*C_LMB_DWIDTH + J) := Sl_Ready_i(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
+        end loop;  -- J
+      end loop;  -- I
+      -- then oring the tmp signals together
+      for J in 0 to C_LMB_DWIDTH-1 loop
+        tmp_or := '0';
+        for I in 0 to C_LMB_NUM_SLAVES-1 loop
+          tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
+        end loop;  -- J
+        res(J) := tmp_or;
+      end loop;  -- I
+      LMB_ReadDBus <= Res;
+    end if;
+  end process DBus_Oring;
+
+end architecture IMP;
+
+
+
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd
new file mode 100755
index 0000000..3f647b4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd
@@ -0,0 +1,130122 @@
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diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd b/projects/U200/U200.ip_user_files/ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd
new file mode 100755
index 0000000..5102183
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd
@@ -0,0 +1,1646 @@
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- upcnt_n - entity/architecture pair
+-------------------------------------------------------------------------------
+--
+-- ************************************************************************
+-- ** DISCLAIMER OF LIABILITY                                            **
+-- **                                                                    **
+-- ** This file contains proprietary and confidential information of     **
+-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license       **
+-- ** from Xilinx, and may be used, copied and/or disclosed only         **
+-- ** pursuant to the terms of a valid license agreement with Xilinx.    **
+-- **                                                                    **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION              **
+-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER         **
+-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT                **
+-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,          **
+-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx      **
+-- ** does not warrant that functions included in the Materials will     **
+-- ** meet the requirements of Licensee, or that the operation of the    **
+-- ** Materials will be uninterrupted or error-free, or that defects     **
+-- ** in the Materials will be corrected. Furthermore, Xilinx does       **
+-- ** not warrant or make any representations regarding use, or the      **
+-- ** results of the use, of the Materials in terms of correctness,      **
+-- ** accuracy, reliability or otherwise.                                **
+-- **                                                                    **
+-- ** Xilinx products are not designed or intended to be fail-safe,      **
+-- ** or for use in any application requiring fail-safe performance,     **
+-- ** such as life-support or safety devices or systems, Class III       **
+-- ** medical devices, nuclear facilities, applications related to       **
+-- ** the deployment of airbags, or any other applications that could    **
+-- ** lead to death, personal injury or severe property or               **
+-- ** environmental damage (individually and collectively, "critical     **
+-- ** applications"). Customer assumes the sole risk and liability       **
+-- ** of any use of Xilinx products in critical applications,            **
+-- ** subject only to applicable laws and regulations governing          **
+-- ** limitations on product liability.                                  **
+-- **                                                                    **
+-- ** Copyright 2010 Xilinx, Inc.                                        **
+-- ** All rights reserved.                                               **
+-- **                                                                    **
+-- ** This disclaimer and copyright notice must be retained as part      **
+-- ** of this file at all times.                                         **
+-- ************************************************************************
+--
+-------------------------------------------------------------------------------
+-- Filename:        upcnt_n.vhd
+-- Version:         v4.00a
+-- Description:     Parameterizeable top level processor reset module.
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   This section should show the hierarchical structure of the
+--              designs.Separate lines with blank lines if necessary to improve
+--              readability.
+--
+--              proc_sys_reset.vhd
+--                  upcnt_n.vhd
+--                  lpf.vhd
+--                  sequence.vhd
+-------------------------------------------------------------------------------
+-- Author:      Kurt Conover
+-- History:
+--  Kurt Conover      11/07/01      -- First Release
+--
+-- ~~~~~~~
+--  SK          03/11/10
+-- ^^^^^^^
+-- 1. Updated the core so support the active low "Interconnect_aresetn" and
+--    "Peripheral_aresetn" signals.
+-- ^^^^^^^
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+-------------------------------------------------------------------------------
+-- Port Declaration
+-------------------------------------------------------------------------------
+-- Definition of Generics:
+--          C_SIZE    -- Number of bits in counter
+--                          
+--
+-- Definition of Ports:
+--          Data       -- parallel data input
+--          Cnt_en     -- count enable
+--          Load       -- Load Data
+--          Clr        -- reset
+--          Clk        -- Clock
+--          Qout       -- Count output
+--
+-------------------------------------------------------------------------------
+entity upcnt_n is
+   generic(
+           C_SIZE : Integer
+          );
+      
+	port(
+	     Data    : in  STD_LOGIC_VECTOR (C_SIZE-1 downto 0); 
+	     Cnt_en  : in  STD_LOGIC;                            
+	     Load    : in  STD_LOGIC;                            
+ 	     Clr     : in  STD_LOGIC;                            
+	     Clk     : in  STD_LOGIC;                            
+	     Qout    : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
+	    );
+		
+end upcnt_n;
+
+architecture imp of upcnt_n is
+
+constant CLEAR : std_logic := '0';
+
+signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
+
+begin
+   process(Clk)
+   begin
+	       
+      if (Clk'event) and Clk = '1' then
+          -- Clear output register
+         if (Clr = CLEAR) then
+            q_int <= (others => '0');
+	       -- Load in start value
+         elsif (Load = '1') then
+            q_int <= UNSIGNED(Data);
+	       -- If count enable is high
+         elsif Cnt_en = '1' then
+		      q_int <= q_int + 1;
+         end if;
+      end if;
+   end process;
+
+   Qout <= STD_LOGIC_VECTOR(q_int);
+
+end imp;
+  
+
+
+
+-------------------------------------------------------------------------------
+-- sequence - entity/architecture pair
+-------------------------------------------------------------------------------
+--
+-- ************************************************************************
+-- ** DISCLAIMER OF LIABILITY                                            **
+-- **                                                                    **
+-- ** This file contains proprietary and confidential information of     **
+-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license       **
+-- ** from Xilinx, and may be used, copied and/or disclosed only         **
+-- ** pursuant to the terms of a valid license agreement with Xilinx.    **
+-- **                                                                    **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION              **
+-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER         **
+-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT                **
+-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,          **
+-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx      **
+-- ** does not warrant that functions included in the Materials will     **
+-- ** meet the requirements of Licensee, or that the operation of the    **
+-- ** Materials will be uninterrupted or error-free, or that defects     **
+-- ** in the Materials will be corrected. Furthermore, Xilinx does       **
+-- ** not warrant or make any representations regarding use, or the      **
+-- ** results of the use, of the Materials in terms of correctness,      **
+-- ** accuracy, reliability or otherwise.                                **
+-- **                                                                    **
+-- ** Xilinx products are not designed or intended to be fail-safe,      **
+-- ** or for use in any application requiring fail-safe performance,     **
+-- ** such as life-support or safety devices or systems, Class III       **
+-- ** medical devices, nuclear facilities, applications related to       **
+-- ** the deployment of airbags, or any other applications that could    **
+-- ** lead to death, personal injury or severe property or               **
+-- ** environmental damage (individually and collectively, "critical     **
+-- ** applications"). Customer assumes the sole risk and liability       **
+-- ** of any use of Xilinx products in critical applications,            **
+-- ** subject only to applicable laws and regulations governing          **
+-- ** limitations on product liability.                                  **
+-- **                                                                    **
+-- ** Copyright 2012 Xilinx, Inc.                                        **
+-- ** All rights reserved.                                               **
+-- **                                                                    **
+-- ** This disclaimer and copyright notice must be retained as part      **
+-- ** of this file at all times.                                         **
+-- ************************************************************************
+--
+-------------------------------------------------------------------------------
+-- Filename:        proc_sys_reset.vhd
+-- Version:         v4.00a
+-- Description:     Parameterizeable top level processor reset module.
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   This section should show the hierarchical structure of the
+--              designs.Separate lines with blank lines if necessary to improve
+--              readability.
+--              -- proc_sys_reset.vhd
+--                 -- upcnt_n.vhd
+--                 -- lpf.vhd
+--                 -- sequence.vhd
+-------------------------------------------------------------------------------
+-- Filename:        sequence.vhd
+--
+-- Description:
+--                  This file control the sequencing coming out of a reset.
+--                  The sequencing is as follows:
+--                  Bus_Struct_Reset comes out of reset first.  Either when the
+--                     external or auxiliary reset goes inactive or 16 clocks
+--                     after a PPC Chip_Reset_Request, or 30 clocks after a PPC
+--                     System_Reset_Request.
+--                  Peripheral_Reset comes out of reset 16 clocks after
+--                     Bus_Struct_Reset.
+--                  The PPC resetcore, comes out of reset
+--                     16 clocks after Peripheral_Reset.
+--                  The PPC resetchip and resetsystem come out of reset
+--                     at the same time as Bus_Struct_Reset.
+-------------------------------------------------------------------------------
+-- Author:      Kurt Conover
+-- History:
+--  Kurt Conover      11/12/01      -- First Release
+--  LC Whittle	     10/11/2004	-- Update for NCSim
+--  rolandp          04/16/2007         -- v2.00a
+--
+-- ~~~~~~~
+--  SK          03/11/10
+-- ^^^^^^^
+-- 1. Updated the core so support the active low "Interconnect_aresetn" and
+--    "Peripheral_aresetn" signals.
+-- ^^^^^^^
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_com"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library unisim;
+use unisim.vcomponents.all;
+library proc_sys_reset_v5_0_13;
+
+-------------------------------------------------------------------------------
+-- Port Declaration
+-------------------------------------------------------------------------------
+-- Definition of Generics:
+--
+-- Definition of Ports:
+--          Lpf_reset            -- Low Pass Filtered in
+--          System_Reset_Req     -- System Reset Request
+--          Chip_Reset_Req       -- Chip Reset Request
+--          Slowest_Sync_Clk     -- Clock
+--          Bsr_out              -- Bus Structure Reset out
+--          Pr_out               -- Peripheral Reset out
+--          Core_out             -- Core reset out
+--          Chip_out             -- Chip reset out
+--          Sys_out              -- System reset out
+--          MB_out               -- MB reset out
+--
+-------------------------------------------------------------------------------
+entity sequence_psr is
+  port(
+    Lpf_reset         : in  std_logic;
+    -- System_Reset_Req  : in  std_logic;
+    -- Chip_Reset_Req    : in  std_logic;
+    Slowest_Sync_Clk  : in  std_logic;
+    Bsr_out           : out std_logic;
+    Pr_out            : out std_logic;
+    -- Core_out          : out std_logic;
+    -- Chip_out          : out std_logic;
+    -- Sys_out           : out std_logic;
+    MB_out            : out std_logic
+  );
+end sequence_psr;
+
+architecture imp of sequence_psr is
+
+constant CLEAR             : std_logic := '0';
+constant BSR_END_LPF_CHIP  : std_logic_vector(5 downto 0) := "001100";  -- 12
+constant BSR_END_SYS       : std_logic_vector(5 downto 0) := "011001";  -- 25
+constant PR_END_LPF_CHIP   : std_logic_vector(5 downto 0) := "011100";  -- 28
+constant PR_END_SYS        : std_logic_vector(5 downto 0) := "101001";  -- 41
+constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100";  -- 44
+constant CORE_END_SYS      : std_logic_vector(5 downto 0) := "111001";  -- 57
+constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
+constant CHIP_END_SYS      : std_logic_vector(5 downto 0) := BSR_END_SYS;
+constant SYS_END_LPF       : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
+constant SYS_END_SYS       : std_logic_vector(5 downto 0) := BSR_END_SYS;
+
+signal bsr                 : std_logic := '1';
+signal bsr_dec             : std_logic_vector(2 downto 0) := (others => '0');
+signal pr                  : std_logic := '1';
+signal pr_dec              : std_logic_vector(2 downto 0) := (others => '0');
+signal Core                : std_logic := '1';
+signal core_dec            : std_logic_vector(2 downto 0) := (others => '0');
+signal Chip                : std_logic := '0';
+signal chip_dec            : std_logic_vector(2 downto 0) := (others => '0');
+signal Sys                 : std_logic := '0';
+signal sys_dec             : std_logic_vector(2 downto 0) := (others => '0');
+signal chip_Reset_Req_d1   : std_logic := '0';  -- delayed Chip_Reset_Req
+signal chip_Reset_Req_d2   : std_logic := '0';  -- delayed Chip_Reset_Req
+signal chip_Reset_Req_d3   : std_logic := '0';  -- delayed Chip_Reset_Req
+signal system_Reset_Req_d1 : std_logic := '0';  -- delayed System_Reset_Req
+signal system_Reset_Req_d2 : std_logic := '0';  -- delayed System_Reset_Req
+signal system_Reset_Req_d3 : std_logic := '0';  -- delayed System_Reset_Req
+signal seq_cnt             : std_logic_vector(5 downto 0);
+signal seq_cnt_en          : std_logic := '0';
+signal seq_clr             : std_logic := '0';
+
+signal ris_edge            : std_logic := '0';
+signal sys_edge            : std_logic := '0';
+signal from_sys            : std_logic;
+
+-------------------------------------------------------------------------------
+-- Component Declarations
+-------------------------------------------------------------------------------
+
+begin
+
+   Pr_out   <= pr;
+   Bsr_out  <= bsr;
+   MB_out   <= core;
+   -- Core_out <= core;
+   -- Chip_out <= chip or sys;
+   -- Sys_out  <= sys;
+   
+-------------------------------------------------------------------------------
+-- This process remembers that the reset was caused be 
+-- System_Reset_Req
+-------------------------------------------------------------------------------
+  SYS_FROM_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      --if Lpf_reset='1' or system_reset_req_d3='1' then
+      if (Lpf_reset = '1') then
+        from_sys <= '1';
+      --elsif Chip_Reset_Req_d3='1' then
+      --  from_sys <= '0';
+      elsif (Core = '0') then
+        from_sys <='0';
+      end if;
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- This instantiates a counter to control the sequencing
+-------------------------------------------------------------------------------
+   SEQ_COUNTER : entity proc_sys_reset_v5_0_13.UPCNT_N
+   generic map (C_SIZE => 6)
+   port map(
+     Data     => "000000",
+     Cnt_en   => seq_cnt_en,
+     Load     => '0',
+     Clr      => seq_clr,
+     Clk      => Slowest_sync_clk,
+     Qout     => seq_cnt
+   );
+
+-------------------------------------------------------------------------------
+-- SEQ_CNT_EN_PROCESS
+-------------------------------------------------------------------------------
+--  This generates the reset pulse and the count enable to core reset counter
+--  count until all outputs are inactive
+-------------------------------------------------------------------------------
+  SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      if (Lpf_reset='1'           --or 
+          --System_Reset_Req_d3='1' or
+          --Chip_Reset_Req_d3='1'   or 
+	  --ris_edge = '1'
+	  ) then
+        seq_cnt_en <= '1';
+      elsif  (Core='0') then              -- Core always present and always last 
+        seq_cnt_en <= '0';
+      end if;
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- SEQ_CLR_PROCESS
+-------------------------------------------------------------------------------
+--  This generates the reset to the sequence counter
+--  Clear the counter on a rising edge of chip or system request or low pass
+--  filter output
+-------------------------------------------------------------------------------
+  SEQ_CLR_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      -- if  ris_edge = '1' or Lpf_reset = '1' then
+      if (Lpf_reset = '1') then
+        seq_clr <= '0';
+      else
+        seq_clr <= '1';
+      end if;
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- This process defines the Peripheral_Reset output signal
+-------------------------------------------------------------------------------
+  PR_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      --if  ris_edge = '1' or Lpf_reset = '1' then
+      if (Lpf_reset = '1') then
+        pr <= '1';
+      elsif (pr_dec(2) = '1') then
+        pr <= '0';
+      end if;
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- This process decodes the sequence counter for PR to use
+-------------------------------------------------------------------------------
+  PR_DECODE_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      if (
+          (seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')  
+	  or
+          (seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3)  and from_sys = '1')
+	  ) then
+         pr_dec(0) <= '1';
+      else
+         pr_dec(0) <= '0';
+      end if;
+      if (
+          (seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0') 
+          or
+          (seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
+	  )then
+         pr_dec(1) <= '1';
+      else
+         pr_dec(1) <= '0';
+      end if;
+      pr_dec(2) <= pr_dec(1) and pr_dec(0);
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- This process defines the Bus_Struct_Reset output signal
+-------------------------------------------------------------------------------
+  BSR_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      --if ris_edge = '1' or Lpf_reset = '1' then
+      if (Lpf_reset = '1') then
+        bsr <= '1';
+      elsif (bsr_dec(2) = '1') then
+        bsr <= '0';
+      end if;
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- This process decodes the sequence counter for BSR to use
+-------------------------------------------------------------------------------
+  BSR_DECODE_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      if (
+          (seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')  
+	  or
+          (seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
+	 )then
+         bsr_dec(0) <= '1';
+      else
+         bsr_dec(0) <= '0';
+      end if;
+      if (
+          (seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0') 
+	  or
+          (seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
+	  )then
+         bsr_dec(1) <= '1';
+      else
+         bsr_dec(1) <= '0';
+      end if;
+      bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
+    end if;
+  end process;
+
+
+-------------------------------------------------------------------------------
+-- This process defines the Peripheral_Reset output signal
+-------------------------------------------------------------------------------
+  CORE_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      -- if  ris_edge = '1' or Lpf_reset = '1' then
+      if (Lpf_reset = '1') then
+        core <= '1';
+      elsif (core_dec(2) = '1') then
+        core <= '0';
+      end if;
+    end if;
+  end process;
+
+-------------------------------------------------------------------------------
+-- This process decodes the sequence counter for PR to use
+-------------------------------------------------------------------------------
+  CORE_DECODE_PROCESS: process (Slowest_sync_clk)
+  begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      if (
+          (seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')  
+	  or
+          (seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
+	  )then
+         core_dec(0) <= '1';
+      else
+         core_dec(0) <= '0';
+      end if;
+      if (
+          (seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0') 
+	  or
+          (seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
+	  )then
+         core_dec(1) <= '1';
+      else
+         core_dec(1) <= '0';
+      end if;
+      core_dec(2) <= core_dec(1) and core_dec(0);
+    end if;
+  end process;
+
+---------------------------------------------------------------------------------
+---- This process defines the Chip output signal
+---------------------------------------------------------------------------------
+--  CHIP_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      -- if ris_edge = '1' or Lpf_reset = '1' then
+--      if Lpf_reset = '1' then
+--        chip <= '1';
+--      elsif chip_dec(2) = '1' then
+--        chip <= '0';
+--      end if;
+--    end if;
+--  end process;
+--
+---------------------------------------------------------------------------------
+---- This process decodes the sequence counter for Chip to use
+---- sys is overlapping the chip reset and thus no need to decode this here
+---------------------------------------------------------------------------------
+--  CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2))  then
+--         chip_dec(0) <= '1';
+--      else
+--         chip_dec(0) <= '0';
+--      end if;
+--      if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
+--         chip_dec(1) <= '1';
+--      else
+--         chip_dec(1) <= '0';
+--      end if;
+--      chip_dec(2) <= chip_dec(1) and chip_dec(0);
+--    end if;
+--  end process;
+  
+---------------------------------------------------------------------------------
+---- This process defines the Sys output signal
+---------------------------------------------------------------------------------
+--  SYS_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      if sys_edge = '1' or Lpf_reset = '1' then
+--        sys <= '1';
+--      elsif sys_dec(2) = '1' then
+--        sys <= '0';
+--      end if;
+--    end if;
+--  end process;
+--  
+---------------------------------------------------------------------------------
+---- This process decodes the sequence counter for Sys to use
+---------------------------------------------------------------------------------
+--  SYS_DECODE_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
+--         (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1')  then
+--        sys_dec(0) <= '1';
+--      else
+--        sys_dec(0) <= '0';
+--      end if;
+--      if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
+--         (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1')  then
+--        sys_dec(1) <= '1';
+--      else
+--        sys_dec(1) <= '0';
+--      end if;
+--      sys_dec(2) <= sys_dec(1) and sys_dec(0);
+--    end if;
+--  end process;
+--
+---------------------------------------------------------------------------------
+---- This process delays signals so the the edge can be detected and used
+---------------------------------------------------------------------------------
+--  DELAY_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      chip_reset_req_d1   <= Chip_Reset_Req  ;
+--      chip_reset_req_d2   <= chip_Reset_Req_d1  ;
+--      chip_reset_req_d3   <= chip_Reset_Req_d2  ;
+--      system_reset_req_d1 <= System_Reset_Req;
+--      system_reset_req_d2 <= system_Reset_Req_d1;
+--      system_reset_req_d3 <= system_Reset_Req_d2;
+--    end if;
+--  end process;
+
+-------------------------------------------------------------------------------
+-- This process creates a signal that goes high on the rising edge of either
+-- Chip_Reset_Req or System_Reset_Req
+-------------------------------------------------------------------------------
+--  RIS_EDGE_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      if (chip_reset_req_d3='0'   and chip_Reset_Req_d2= '1') -- rising edge
+--         or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
+--        ris_edge <= '1';
+--      else
+--        ris_edge <='0';
+--      end if;
+--    end if;
+--  end process;
+
+-------------------------------------------------------------------------------
+-- This process creates a signal that goes high on the rising edge of
+-- System_Reset_Req
+-------------------------------------------------------------------------------
+--  SYS_EDGE_PROCESS: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      if (system_reset_req_d3='0' and system_reset_req_d2='1') then
+--         sys_edge <= '1';
+--      else
+--         sys_edge <='0';
+--      end if;
+--    end if;
+--  end process;
+
+
+
+end architecture imp;
+
+
+
+
+-------------------------------------------------------------------------------
+-- lpf - entity/architecture pair
+-------------------------------------------------------------------------------
+--
+-- ************************************************************************
+-- ** DISCLAIMER OF LIABILITY                                            **
+-- **                                                                    **
+-- ** This file contains proprietary and confidential information of     **
+-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license       **
+-- ** from Xilinx, and may be used, copied and/or disclosed only         **
+-- ** pursuant to the terms of a valid license agreement with Xilinx.    **
+-- **                                                                    **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION              **
+-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER         **
+-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT                **
+-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,          **
+-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx      **
+-- ** does not warrant that functions included in the Materials will     **
+-- ** meet the requirements of Licensee, or that the operation of the    **
+-- ** Materials will be uninterrupted or error-free, or that defects     **
+-- ** in the Materials will be corrected. Furthermore, Xilinx does       **
+-- ** not warrant or make any representations regarding use, or the      **
+-- ** results of the use, of the Materials in terms of correctness,      **
+-- ** accuracy, reliability or otherwise.                                **
+-- **                                                                    **
+-- ** Xilinx products are not designed or intended to be fail-safe,      **
+-- ** or for use in any application requiring fail-safe performance,     **
+-- ** such as life-support or safety devices or systems, Class III       **
+-- ** medical devices, nuclear facilities, applications related to       **
+-- ** the deployment of airbags, or any other applications that could    **
+-- ** lead to death, personal injury or severe property or               **
+-- ** environmental damage (individually and collectively, "critical     **
+-- ** applications"). Customer assumes the sole risk and liability       **
+-- ** of any use of Xilinx products in critical applications,            **
+-- ** subject only to applicable laws and regulations governing          **
+-- ** limitations on product liability.                                  **
+-- **                                                                    **
+-- ** Copyright 2012 Xilinx, Inc.                                        **
+-- ** All rights reserved.                                               **
+-- **                                                                    **
+-- ** This disclaimer and copyright notice must be retained as part      **
+-- ** of this file at all times.                                         **
+-- ************************************************************************
+--
+-------------------------------------------------------------------------------
+-- Filename:        lpf.vhd
+-- Version:         v4.00a
+-- Description:     Parameterizeable top level processor reset module.
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   This section should show the hierarchical structure of the
+--              designs.Separate lines with blank lines if necessary to improve
+--              readability.
+--
+--              proc_sys_reset.vhd
+--                  upcnt_n.vhd
+--                  lpf.vhd
+--                  sequence.vhd
+-------------------------------------------------------------------------------
+-- Author:      Kurt Conover
+-- History:
+--  Kurt Conover      11/08/01      -- First Release
+--
+--  KC                02/25/2002    -- Added Dcm_locked as an input
+--                                  -- Added Power on reset srl_time_out
+--
+--  KC                08/26/2003    -- Added attribute statements for power on 
+--                                     reset SRL
+--
+-- ~~~~~~~
+--  SK          03/11/10
+-- ^^^^^^^
+-- 1. Updated the core so support the active low "Interconnect_aresetn" and
+--    "Peripheral_aresetn" signals.
+-- ^^^^^^^
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+    use IEEE.std_logic_1164.all;
+    use IEEE.std_logic_arith.all;
+library lib_cdc_v1_0_2;
+--use lib_cdc_v1_0_2.all;
+library Unisim; 
+    use Unisim.all; 
+-------------------------------------------------------------------------------
+-- Port Declaration
+-------------------------------------------------------------------------------
+-- Definition of Generics:
+--          C_EXT_RST_WIDTH       -- External Reset Low Pass Filter setting
+--          C_AUX_RST_WIDTH       -- Auxiliary Reset Low Pass Filter setting   
+--          C_EXT_RESET_HIGH      -- External Reset Active High or Active Low
+--          C_AUX_RESET_HIGH      -= Auxiliary Reset Active High or Active Low
+--
+-- Definition of Ports:
+--          Slowest_sync_clk       -- Clock 
+--          External_System_Reset  -- External Reset Input
+--          Auxiliary_System_Reset -- Auxiliary Reset Input
+--          Dcm_locked             -- DCM Locked, hold system in reset until 1
+--          Lpf_reset              -- Low Pass Filtered Output
+--
+-------------------------------------------------------------------------------
+entity lpf is
+   generic(
+           C_EXT_RST_WIDTH    : Integer;
+           C_AUX_RST_WIDTH    : Integer;
+           C_EXT_RESET_HIGH   : std_logic;
+           C_AUX_RESET_HIGH   : std_logic 
+          );
+      
+   port(
+        MB_Debug_Sys_Rst         : in  std_logic;
+        Dcm_locked               : in  std_logic;
+        External_System_Reset    : in  std_logic; 
+        Auxiliary_System_Reset   : in  std_logic;                         
+        Slowest_Sync_Clk         : in  std_logic; 
+        Lpf_reset                : out std_logic                          
+       );
+      
+end lpf;
+
+architecture imp of lpf is
+
+component SRL16 is 
+-- synthesis translate_off 
+  generic ( 
+        INIT : bit_vector ); 
+-- synthesis translate_on 
+  port (D    : in  std_logic; 
+        CLK  : in  std_logic; 
+        A0   : in  std_logic; 
+        A1   : in  std_logic; 
+        A2   : in  std_logic; 
+        A3   : in  std_logic; 
+        Q    : out std_logic); 
+end component SRL16; 
+
+
+constant CLEAR : std_logic := '0';
+
+signal exr_d1        : std_logic := '0'; -- delayed External_System_Reset
+signal exr_lpf       : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
+                             := (others => '0'); -- LPF DFF
+                             
+signal asr_d1        : std_logic := '0'; -- delayed Auxiliary_System_Reset
+signal asr_lpf       : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
+                             := (others => '0'); -- LPF DFF
+                             
+signal exr_and       : std_logic := '0'; -- varible input width "and" gate
+signal exr_nand      : std_logic := '0'; -- vaiable input width "and" gate
+                     
+signal asr_and       : std_logic := '0'; -- varible input width "and" gate
+signal asr_nand      : std_logic := '0'; -- vaiable input width "and" gate
+                     
+signal lpf_int       : std_logic := '0'; -- internal Lpf_reset
+signal lpf_exr       : std_logic := '0';
+signal lpf_asr       : std_logic := '0';
+                     
+signal srl_time_out  : std_logic;
+
+attribute INIT             : string;
+attribute INIT of POR_SRL_I: label is "FFFF";
+
+
+begin
+
+   Lpf_reset <= lpf_int;
+   
+-------------------------------------------------------------------------------
+-- Power On Reset Generation
+-------------------------------------------------------------------------------
+--  This generates a reset for the first 16 clocks after a power up
+-------------------------------------------------------------------------------
+  POR_SRL_I: SRL16 
+-- synthesis translate_off 
+    generic map ( 
+      INIT => X"FFFF") 
+-- synthesis translate_on 
+    port map ( 
+      D   => '0', 
+      CLK => Slowest_sync_clk, 
+      A0  => '1', 
+      A1  => '1', 
+      A2  => '1', 
+      A3  => '1', 
+      Q   => srl_time_out); 
+   
+-------------------------------------------------------------------------------
+-- LPF_OUTPUT_PROCESS
+-------------------------------------------------------------------------------
+--  This generates the reset pulse and the count enable to core reset counter
+--
+--ACTIVE_HIGH_LPF_EXT: if  (C_EXT_RESET_HIGH = '1') generate  
+--begin
+LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
+begin
+    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+       lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
+    end if;
+end process LPF_OUTPUT_PROCESS;
+--end generate ACTIVE_HIGH_LPF_EXT;
+
+--ACTIVE_LOW_LPF_EXT: if  (C_EXT_RESET_HIGH = '0') generate  
+--begin
+--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
+--   begin
+--      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--         lpf_int <= not (lpf_exr      or 
+--	                 lpf_asr      or 
+--			 srl_time_out)or 
+--			 not Dcm_locked;
+--      end if;
+--   end process;
+--end generate ACTIVE_LOW_LPF_EXT;
+
+EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
+begin
+   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      if exr_and = '1' then
+         lpf_exr <= '1';
+      elsif (exr_and = '0' and exr_nand = '1') then
+         lpf_exr <= '0';
+      end if;
+   end if;
+end process EXR_OUTPUT_PROCESS;
+
+ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
+begin
+   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+      if asr_and = '1' then
+         lpf_asr <= '1';
+      elsif (asr_and = '0' and asr_nand = '1') then
+         lpf_asr <= '0';
+      end if;
+   end if;
+end process ASR_OUTPUT_PROCESS;
+-------------------------------------------------------------------------------
+-- This If-generate selects an active high input for External System Reset 
+-------------------------------------------------------------------------------
+ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate  
+begin
+   -----------------------------------
+exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
+
+ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
+  generic map (
+    C_CDC_TYPE           => 1,
+    C_RESET_STATE        => 0,
+    C_SINGLE_BIT         => 1,
+    C_FLOP_INPUT         => 0,
+    C_VECTOR_WIDTH       => 2,
+    C_MTBF_STAGES        => 4
+            )
+  port map(
+    prmry_aclk            => '1',
+    prmry_resetn          => '1',--S_AXI_ARESETN,
+    prmry_in              => exr_d1,
+    prmry_ack             => open,
+    scndry_out            => exr_lpf(0),
+    scndry_aclk           => Slowest_Sync_Clk,
+    scndry_resetn         => '1', --S_AXIS_ARESETN,
+    prmry_vect_in         => "00",
+    scndry_vect_out       => open
+     );
+
+-----------------------------------
+end generate ACTIVE_HIGH_EXT;
+-------------------------------------------------------------------------------
+-- This If-generate selects an active low input for External System Reset 
+-------------------------------------------------------------------------------
+ACTIVE_LOW_EXT: if  (C_EXT_RESET_HIGH = '0') generate  
+begin
+exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
+   -------------------------------------
+
+ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
+  generic map (
+    C_CDC_TYPE           => 1,
+    C_RESET_STATE        => 0,
+    C_SINGLE_BIT         => 1,
+    C_FLOP_INPUT         => 0,
+    C_VECTOR_WIDTH       => 2,
+    C_MTBF_STAGES        => 4
+            )
+  port map(
+    prmry_aclk            => '1',
+    prmry_resetn          => '1',--S_AXI_ARESETN,
+    prmry_in              => exr_d1,
+    prmry_ack             => open,
+    scndry_out            => exr_lpf(0),
+    scndry_aclk           => Slowest_Sync_Clk,
+    scndry_resetn         => '1', --S_AXIS_ARESETN,
+    prmry_vect_in         => "00",
+    scndry_vect_out       => open
+     );
+-------------------------------------
+end generate ACTIVE_LOW_EXT;
+
+-------------------------------------------------------------------------------
+-- This If-generate selects an active high input for Auxiliary System Reset 
+-------------------------------------------------------------------------------
+ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate  
+begin
+asr_d1 <= Auxiliary_System_Reset;
+-------------------------------------
+
+ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
+  generic map (
+    C_CDC_TYPE           => 1,
+    C_RESET_STATE        => 0,
+    C_SINGLE_BIT         => 1,
+    C_FLOP_INPUT         => 0,
+    C_VECTOR_WIDTH       => 2,
+    C_MTBF_STAGES        => 4
+            )
+  port map(
+    prmry_aclk            => '1',
+    prmry_resetn          => '1',--S_AXI_ARESETN,
+    prmry_in              => asr_d1,
+    prmry_ack             => open,
+    scndry_out            => asr_lpf(0),
+    scndry_aclk           => Slowest_Sync_Clk,
+    scndry_resetn         => '1', --S_AXIS_ARESETN,
+    prmry_vect_in         => "00",
+    scndry_vect_out       => open
+     );
+   -------------------------------------
+end generate ACTIVE_HIGH_AUX;
+-------------------------------------------------------------------------------
+-- This If-generate selects an active low input for Auxiliary System Reset 
+-------------------------------------------------------------------------------
+ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate  
+begin
+   -------------------------------------
+asr_d1 <= not Auxiliary_System_Reset;
+
+ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
+  generic map (
+    C_CDC_TYPE           => 1,
+    C_RESET_STATE        => 0,
+    C_SINGLE_BIT         => 1,
+    C_FLOP_INPUT         => 0,
+    C_VECTOR_WIDTH       => 2,
+    C_MTBF_STAGES        => 4
+            )
+  port map(
+    prmry_aclk            => '1',
+    prmry_resetn          => '1',--S_AXI_ARESETN,
+    prmry_in              => asr_d1,
+    prmry_ack             => open,
+    scndry_out            => asr_lpf(0),
+    scndry_aclk           => Slowest_Sync_Clk,
+    scndry_resetn         => '1', --S_AXIS_ARESETN,
+    prmry_vect_in         => "00",
+    scndry_vect_out       => open
+     );
+   -------------------------------------
+end generate ACTIVE_LOW_AUX;
+
+-------------------------------------------------------------------------------
+-- This For-generate creates the low pass filter D-Flip Flops
+-------------------------------------------------------------------------------
+EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
+begin
+   ----------------------------------------
+   EXT_LPF_DFF : process (Slowest_Sync_Clk)
+   begin
+      if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
+         exr_lpf(i) <= exr_lpf(i-1);
+      end if;
+   end process;
+   ----------------------------------------
+end generate EXT_LPF;
+------------------------------------------------------------------------------------------
+-- Implement the 'AND' function on the for the LPF
+------------------------------------------------------------------------------------------
+EXT_LPF_AND : process (exr_lpf)
+Variable loop_and  : std_logic;
+Variable loop_nand : std_logic;
+Begin
+   loop_and  := '1';
+   loop_nand := '1';
+   for j in 0 to C_EXT_RST_WIDTH - 1 loop
+      loop_and  := loop_and and      exr_lpf(j);
+      loop_nand := loop_nand and not exr_lpf(j);
+   End loop;
+  
+   exr_and  <= loop_and;
+   exr_nand <= loop_nand;
+
+end process; 
+
+-------------------------------------------------------------------------------
+-- This For-generate creates the low pass filter D-Flip Flops
+-------------------------------------------------------------------------------
+AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
+begin
+   ----------------------------------------
+   AUX_LPF_DFF : process (Slowest_Sync_Clk)
+   begin
+      if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
+         asr_lpf(k) <= asr_lpf(k-1);
+      end if;
+   end process;
+   ----------------------------------------
+end generate AUX_LPF;
+------------------------------------------------------------------------------------------
+-- Implement the 'AND' function on the for the LPF
+------------------------------------------------------------------------------------------
+AUX_LPF_AND : process (asr_lpf)
+Variable aux_loop_and  : std_logic;
+Variable aux_loop_nand : std_logic;
+Begin
+   aux_loop_and  := '1';
+   aux_loop_nand := '1';
+   for m in 0 to C_AUX_RST_WIDTH - 1 loop
+      aux_loop_and  := aux_loop_and and      asr_lpf(m);
+      aux_loop_nand := aux_loop_nand and not asr_lpf(m);
+   End loop;
+  
+   asr_and  <= aux_loop_and;
+   asr_nand <= aux_loop_nand;
+
+end process; 
+
+end imp;
+  
+
+
+
+-------------------------------------------------------------------------------
+-- proc_sys_reset - entity/architecture pair
+-------------------------------------------------------------------------------
+--
+-- ************************************************************************
+-- ** DISCLAIMER OF LIABILITY                                            **
+-- **                                                                    **
+-- ** This file contains proprietary and confidential information of     **
+-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license       **
+-- ** from Xilinx, and may be used, copied and/or disclosed only         **
+-- ** pursuant to the terms of a valid license agreement with Xilinx.    **
+-- **                                                                    **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION              **
+-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER         **
+-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT                **
+-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,          **
+-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx      **
+-- ** does not warrant that functions included in the Materials will     **
+-- ** meet the requirements of Licensee, or that the operation of the    **
+-- ** Materials will be uninterrupted or error-free, or that defects     **
+-- ** in the Materials will be corrected. Furthermore, Xilinx does       **
+-- ** not warrant or make any representations regarding use, or the      **
+-- ** results of the use, of the Materials in terms of correctness,      **
+-- ** accuracy, reliability or otherwise.                                **
+-- **                                                                    **
+-- ** Xilinx products are not designed or intended to be fail-safe,      **
+-- ** or for use in any application requiring fail-safe performance,     **
+-- ** such as life-support or safety devices or systems, Class III       **
+-- ** medical devices, nuclear facilities, applications related to       **
+-- ** the deployment of airbags, or any other applications that could    **
+-- ** lead to death, personal injury or severe property or               **
+-- ** environmental damage (individually and collectively, "critical     **
+-- ** applications"). Customer assumes the sole risk and liability       **
+-- ** of any use of Xilinx products in critical applications,            **
+-- ** subject only to applicable laws and regulations governing          **
+-- ** limitations on product liability.                                  **
+-- **                                                                    **
+-- ** Copyright 2012 Xilinx, Inc.                                        **
+-- ** All rights reserved.                                               **
+-- **                                                                    **
+-- ** This disclaimer and copyright notice must be retained as part      **
+-- ** of this file at all times.                                         **
+-- ************************************************************************
+--
+-------------------------------------------------------------------------------
+-- Filename:        proc_sys_reset.vhd
+-- Version:         v4.00a
+-- Description:     Parameterizeable top level processor reset module.
+-- VHDL-Standard:   VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:   This section should show the hierarchical structure of the
+--              designs.Separate lines with blank lines if necessary to improve
+--              readability.
+--
+--              proc_sys_reset.vhd
+--                  upcnt_n.vhd
+--                  lpf.vhd
+--                  sequence.vhd
+-------------------------------------------------------------------------------
+-- Author:      rolandp
+-- History:
+--  kc           11/07/01      -- First version
+--
+--  kc           02/25/2002    -- Changed generic names C_EXT_RST_ACTIVE to
+--                                C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
+--                                C_AUX_RESET_HIGH to match generics used in
+--                                MicroBlaze.  Added the DCM Lock as an input
+--                                to keep reset active until after the Lock
+--                                is valid.
+-- lcw          10/11/2004  -- Updated for NCSim
+-- Ravi         09/14/2006  -- Added Attributes for synthesis
+-- rolandp      04/16/2007  -- version 2.00a
+-- ~~~~~~~
+--  SK          03/11/10
+-- ^^^^^^^
+-- 1. Updated the core so support the active low "Interconnect_aresetn" and
+--    "Peripheral_aresetn" signals.
+-- ^^^^^^^
+-- ~~~~~~~
+--  SK          05/12/11
+-- ^^^^^^^
+-- 1. Updated the core so remove the support for PPC related functionality.
+-- ^^^^^^^
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x"
+--      reset signals:                          "rst", "rst_n"
+--      generics:                               "C_*"
+--      user defined types:                     "*_TYPE"
+--      state machine next state:               "*_ns"
+--      state machine current state:            "*_cs"
+--      combinatorial signals:                  "*_cmb"
+--      pipelined or register delay signals:    "*_d#"
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce"
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin"
+--      ports:                                  - Names begin with Uppercase
+--      processes:                              "*_PROCESS"
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library ieee;
+    use ieee.std_logic_1164.all;
+library unisim;
+    use unisim.vcomponents.all;
+library proc_sys_reset_v5_0_13;
+    use proc_sys_reset_v5_0_13.all;
+
+-------------------------------------------------------------------------------
+-- Port Declaration
+-------------------------------------------------------------------------------
+-- Definition of Generics:
+--      C_EXT_RST_WIDTH       -- External Reset Low Pass Filter setting
+--      C_AUX_RST_WIDTH       -- Auxiliary Reset Low Pass Filter setting
+
+--      C_EXT_RESET_HIGH      -- External Reset Active High or Active Low
+--      C_AUX_RESET_HIGH      -= Auxiliary Reset Active High or Active Low
+
+--      C_NUM_BUS_RST         -- Number of Bus Structures reset to generate
+--      C_NUM_PERP_RST        -- Number of Peripheral resets to generate
+--
+--      C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
+--      C_NUM_PERP_ARESETN         -- No. of Active low reset to peripheral
+
+-- Definition of Ports:
+--      slowest_sync_clk       -- Clock
+--      ext_reset_in           -- External Reset Input
+--      aux_reset_in           -- Auxiliary Reset Input
+--      mb_debug_sys_rst       -- MDM Reset Input
+--      dcm_locked             -- DCM Locked, hold system in reset until 1
+--      mb_reset               -- MB core reset out
+--      bus_struct_reset       -- Bus structure reset out
+--      peripheral_reset       -- Peripheral reset out
+
+--      interconnect_aresetn   -- Interconnect Bus structure registered rst out
+--      peripheral_aresetn     -- Active Low Peripheral registered reset out
+-------------------------------------------------------------------------------
+
+entity proc_sys_reset is
+  generic (
+    C_FAMILY                 : string    := "virtex7";
+    C_EXT_RST_WIDTH          : integer   := 4;
+    C_AUX_RST_WIDTH          : integer   := 4;
+    C_EXT_RESET_HIGH         : std_logic := '0'; -- High active input
+    C_AUX_RESET_HIGH         : std_logic := '1'; -- High active input
+    C_NUM_BUS_RST            : integer   := 1;
+    C_NUM_PERP_RST           : integer   := 1;
+
+    C_NUM_INTERCONNECT_ARESETN : integer   := 1; -- 3/15/2010
+    C_NUM_PERP_ARESETN         : integer   := 1  -- 3/15/2010
+  );
+  port (
+    slowest_sync_clk     : in  std_logic;
+
+    ext_reset_in         : in  std_logic;
+    aux_reset_in         : in  std_logic;
+
+    -- from MDM
+    mb_debug_sys_rst     : in  std_logic;
+    -- DCM locked information
+    dcm_locked           : in  std_logic := '1';
+
+    -- -- from PPC
+    -- Core_Reset_Req_0     : in  std_logic;
+    -- Chip_Reset_Req_0     : in  std_logic;
+    -- System_Reset_Req_0   : in  std_logic;
+    -- Core_Reset_Req_1     : in  std_logic;
+    -- Chip_Reset_Req_1     : in  std_logic;
+    -- System_Reset_Req_1   : in  std_logic;
+
+    -- RstcPPCresetcore_0   : out std_logic := '0';
+    -- RstcPPCresetchip_0   : out std_logic := '0';
+    -- RstcPPCresetsys_0    : out std_logic := '0';
+    -- RstcPPCresetcore_1   : out std_logic := '0';
+    -- RstcPPCresetchip_1   : out std_logic := '0';
+    -- RstcPPCresetsys_1    : out std_logic := '0';
+
+    -- to Microblaze active high reset
+    mb_reset             : out std_logic;
+    -- active high resets
+    bus_struct_reset     : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
+                                                           := (others => '0');
+    peripheral_reset     : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
+                                                           := (others => '0');
+    -- active low resets
+    interconnect_aresetn : out
+                          std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
+                                                            := (others => '1');
+    peripheral_aresetn   : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
+                                                             := (others => '1')
+   );
+
+end entity proc_sys_reset;
+
+-------------------------------------------------------------------------------
+-- Architecture
+-------------------------------------------------------------------------------
+architecture imp of proc_sys_reset is
+
+-------------------------------------------------------------------------------
+-- Constant Declarations
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Signal and Type Declarations
+-- signal Core_Reset_Req_0_d1   : std_logic := '0';  -- delayed Core_Reset_Req
+-- signal Core_Reset_Req_0_d2   : std_logic := '0';  -- delayed Core_Reset_Req
+-- signal Core_Reset_Req_0_d3   : std_logic := '0';  -- delayed Core_Reset_Req
+-- signal Core_Reset_Req_1_d1   : std_logic := '0';  -- delayed Core_Reset_Req
+-- signal Core_Reset_Req_1_d2   : std_logic := '0';  -- delayed Core_Reset_Req
+-- signal Core_Reset_Req_1_d3   : std_logic := '0';  -- delayed Core_Reset_Req
+constant T : std_logic := C_EXT_RESET_HIGH;
+
+signal core_cnt_en_0         : std_logic := '0'; -- Core_Reset_Req_0 counter enable
+signal core_cnt_en_1         : std_logic := '0'; -- Core_Reset_Req_1 counter enable
+
+signal core_req_edge_0       : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
+signal core_req_edge_1       : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
+
+signal core_cnt_0            : std_logic_vector(3 downto 0); -- core counter output
+signal core_cnt_1            : std_logic_vector(3 downto 0); -- core counter output
+
+signal lpf_reset             : std_logic; -- Low pass filtered ext or aux
+
+--signal Chip_Reset_Req        : std_logic := '0';
+--signal System_Reset_Req      : std_logic := '0';
+
+signal Bsr_out   : std_logic;
+signal Pr_out    : std_logic;
+
+-- signal Core_out  : std_logic;
+-- signal Chip_out  : std_logic;
+-- signal Sys_out   : std_logic;
+signal MB_out    : std_logic := C_EXT_RESET_HIGH;
+signal MB_out1    : std_logic := C_EXT_RESET_HIGH;
+signal pr_outn : std_logic;
+signal bsr_outn : std_logic;
+
+-------------------------------------------------------------------------------
+-- Attributes to synthesis
+-------------------------------------------------------------------------------
+
+--attribute equivalent_register_removal: string;
+--attribute equivalent_register_removal of bus_struct_reset : signal is "no";
+--attribute equivalent_register_removal of peripheral_reset : signal is "no";
+
+--attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
+--attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
+
+begin
+-------------------------------------------------------------------------------
+
+-- ---------------------
+-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
+-- ---------------------
+-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
+-- begin
+--   mb_reset <= MB_out1;
+
+--  MB_Reset_PROCESS1: process (slowest_sync_clk)
+--  begin
+--    if (slowest_sync_clk'event and slowest_sync_clk = '1') then
+--      MB_out1 <= MB_out;
+--    end if;
+--  end process;
+
+  FDRE_inst : FDRE
+   generic map (
+      INIT => '1') -- Initial value of register ('0' or '1')  
+   port map (
+      Q => mb_reset,      -- Data output
+      C => slowest_sync_clk,      -- Clock input
+      CE => '1',    -- Clock enable input
+      R => '0',      -- Synchronous reset input
+      D => MB_out       -- Data input
+   );
+
+-- ----------------------------------------------------------------------------
+-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
+-- ----------------------------------------------------------------------------
+  BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
+
+  FDRE_BSR : FDRE
+   generic map (
+      INIT => '1') -- Initial value of register ('0' or '1')  
+   port map (
+      Q => bus_struct_reset(i),      -- Data output
+      C => slowest_sync_clk,      -- Clock input
+      CE => '1',    -- Clock enable input
+      R => '0',      -- Synchronous reset input
+      D => Bsr_out       -- Data input
+   );
+
+
+--    BSR_DFF : process (slowest_sync_clk)
+--    begin
+--      if (slowest_sync_clk'event and slowest_sync_clk = '1') then
+--        bus_struct_reset(i) <= Bsr_out;
+--      end if;
+--    end process;
+  end generate BSR_OUT_DFF;
+
+-- ---------------------------------------------------------------------------
+-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
+-- ---------------------------------------------------------------------------
+  bsr_outn <= not(Bsr_out);
+
+  ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
+  FDRE_BSR_N : FDRE
+   generic map (
+      INIT => '0') -- Initial value of register ('0' or '1')  
+   port map (
+      Q => interconnect_aresetn(i),      -- Data output
+      C => slowest_sync_clk,      -- Clock input
+      CE => '1',    -- Clock enable input
+      R => '0',      -- Synchronous reset input
+      D => bsr_outn       -- Data input
+   );
+--    BSR_DFF : process (slowest_sync_clk)
+--    begin
+--      if (slowest_sync_clk'event and slowest_sync_clk = '1') then
+--        interconnect_aresetn(i) <= not (Bsr_out);
+--      end if;
+--    end process;
+  end generate ACTIVE_LOW_BSR_OUT_DFF;
+-------------------------------------------------------------------------------
+
+-- ----------------------------------------------------------------------------
+-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
+-- ----------------------------------------------------------------------------
+  PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
+  FDRE_PER : FDRE
+   generic map (
+      INIT => '1') -- Initial value of register ('0' or '1')  
+   port map (
+      Q => peripheral_reset(i),      -- Data output
+      C => slowest_sync_clk,      -- Clock input
+      CE => '1',    -- Clock enable input
+      R => '0',      -- Synchronous reset input
+      D => Pr_out       -- Data input
+   );
+--    PR_DFF : process (slowest_sync_clk)
+--    begin
+--      if (slowest_sync_clk'event and slowest_sync_clk = '1') then
+--        peripheral_reset(i) <= Pr_out;
+--      end if;
+--    end process;
+  end generate PR_OUT_DFF;
+
+-- ----------------------------------------------------------------------------
+-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
+-- ---A-------------------------------------------------------------------------
+  pr_outn <= not(Pr_out);
+
+  ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
+  FDRE_PER_N : FDRE
+   generic map (
+      INIT => '0') -- Initial value of register ('0' or '1')  
+   port map (
+      Q => peripheral_aresetn(i),      -- Data output
+      C => slowest_sync_clk,      -- Clock input
+      CE => '1',    -- Clock enable input
+      R => '0',      -- Synchronous reset input
+      D => Pr_outn       -- Data input
+   );
+--    ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
+--    begin
+--      if (slowest_sync_clk'event and slowest_sync_clk = '1') then
+--        peripheral_aresetn(i) <= not(Pr_out);
+--      end if;
+--    end process;
+  end generate ACTIVE_LOW_PR_OUT_DFF;
+-------------------------------------------------------------------------------
+-- This process defines the RstcPPCreset and MB_Reset outputs
+-------------------------------------------------------------------------------
+  -- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
+  -- begin
+  --   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+  --     RstcPPCresetcore_0  <= not (core_cnt_0(3) and core_cnt_0(2) and
+  --                                 core_cnt_0(1) and core_cnt_0(0))
+  --                            or Core_out;
+  --     RstcPPCresetchip_0  <= Chip_out;
+  --     RstcPPCresetsys_0   <= Sys_out;
+  --   end if;
+  -- end process;
+
+  -- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
+  -- begin
+  --   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+  --     RstcPPCresetcore_1  <= not (core_cnt_1(3) and core_cnt_1(2) and
+  --                                 core_cnt_1(1) and core_cnt_1(0))
+  --                               or Core_out;
+  --     RstcPPCresetchip_1  <= Chip_out;
+  --     RstcPPCresetsys_1   <= Sys_out;
+  --   end if;
+  -- end process;
+
+-------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------
+---- This process delays signals so the the edge can be detected and used
+----  Double register to sync up with slowest_sync_clk
+---------------------------------------------------------------------------------
+--  DELAY_PROCESS_0: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      core_reset_req_0_d1   <= Core_Reset_Req_0;
+--      core_reset_req_0_d2   <= core_reset_req_0_d1;
+--      core_reset_req_0_d3   <= core_reset_req_0_d2;
+--    end if;
+--  end process;
+--
+--  DELAY_PROCESS_1: process (Slowest_sync_clk)
+--  begin
+--    if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+--      core_reset_req_1_d1   <= Core_Reset_Req_1;
+--      core_reset_req_1_d2   <= core_reset_req_1_d1;
+--      core_reset_req_1_d3   <= core_reset_req_1_d2;
+--    end if;
+--  end process;
+
+
+-- ** -- -------------------------------------------------------------------------------
+-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
+-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
+-- ** -- -------------------------------------------------------------------------------
+-- ** --   CORE_RESET_0 : entity proc_sys_reset_v5_0_13.UPCNT_N
+-- ** --   generic map (C_SIZE => 4)
+-- ** --   port map(
+-- ** --     Data     => "0000",                    -- in  STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
+-- ** --     Cnt_en   => core_cnt_en_0,             -- in  STD_LOGIC;                           
+-- ** --     Load     => '0',                       -- in  STD_LOGIC;                           
+-- ** --     Clr      => core_req_edge_0,           -- in  STD_LOGIC;                           
+-- ** --     Clk      => Slowest_sync_clk,          -- in  STD_LOGIC;                           
+-- ** --     Qout     => core_cnt_0                 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) 
+-- ** --   );
+-- ** -- 
+-- ** --   CORE_RESET_1 : entity proc_sys_reset_v5_0_13.UPCNT_N
+-- ** --   generic map (C_SIZE => 4)
+-- ** --   port map(
+-- ** --     Data     => "0000",                    -- in  STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
+-- ** --     Cnt_en   => core_cnt_en_1,             -- in  STD_LOGIC;                           
+-- ** --     Load     => '0',                       -- in  STD_LOGIC;                           
+-- ** --     Clr      => core_req_edge_1,           -- in  STD_LOGIC;                           
+-- ** --     Clk      => Slowest_sync_clk,          -- in  STD_LOGIC;                           
+-- ** --     Qout     => core_cnt_1                 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) 
+-- ** --   );
+-- ** -- 
+-- ** -- -------------------------------------------------------------------------------
+-- ** -- -- CORE_RESET_PROCESS
+-- ** -- -------------------------------------------------------------------------------
+-- ** -- --  This generates the reset pulse and the count enable to core reset counter
+-- ** -- --
+-- ** --   CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
+-- ** --   begin
+-- ** --      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+-- ** --        core_cnt_en_0   <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
+-- ** --                           --or not core_req_edge_0;
+-- ** --        --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
+-- ** --      end if;
+-- ** --   end process;
+-- ** -- 
+-- ** --   CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
+-- ** --   begin
+-- ** --     if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
+-- ** --       core_cnt_en_1   <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
+-- ** --                          --or not core_req_edge_1;
+-- ** --       --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
+-- ** --     end if;
+-- ** --   end process;
+
+-------------------------------------------------------------------------------
+-- This instantiates a low pass filter to filter both External and Auxiliary
+-- Reset Inputs.
+-------------------------------------------------------------------------------
+  EXT_LPF : entity proc_sys_reset_v5_0_13.LPF
+  generic map (
+    C_EXT_RST_WIDTH  => C_EXT_RST_WIDTH,
+    C_AUX_RST_WIDTH  => C_AUX_RST_WIDTH,
+    C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
+    C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
+  )
+  port map(
+    MB_Debug_Sys_Rst       => mb_debug_sys_rst,        --  in  std_logic
+    Dcm_locked             => dcm_locked,              --  in  std_logic
+    External_System_Reset  => ext_reset_in,            --  in  std_logic
+    Auxiliary_System_Reset => aux_reset_in,            --  in  std_logic
+    Slowest_Sync_Clk       => slowest_sync_clk,        --  in  std_logic
+    Lpf_reset              => lpf_reset                --  out std_logic
+  );
+
+-------------------------------------------------------------------------------
+-- This instantiates the sequencer
+--  This controls the time between resets becoming inactive
+-------------------------------------------------------------------------------
+
+  -- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
+
+  -- Chip_Reset_Req   <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
+
+  SEQ : entity proc_sys_reset_v5_0_13.SEQUENCE_PSR
+  --generic map (
+  --  C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
+  --)
+  port map(
+    Lpf_reset         => lpf_reset,                    -- in  std_logic
+    --System_Reset_Req  => '0', -- System_Reset_Req,     -- in  std_logic
+    --Chip_Reset_Req    => '0', -- Chip_Reset_Req,       -- in  std_logic
+    Slowest_Sync_Clk  => slowest_sync_clk,             -- in  std_logic
+    Bsr_out           => Bsr_out,                      -- out std_logic
+    Pr_out            => Pr_out,                       -- out std_logic
+    --Core_out          => open, -- Core_out,            -- out std_logic
+    --Chip_out          => open, -- Chip_out,            -- out std_logic
+    --Sys_out           => open, -- Sys_out,             -- out std_logic
+    MB_out            => MB_out);                      -- out std_logic
+
+end imp;
+
+--END_SINGLE_FILE_TAG
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/axi_infrastructure_header.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/axi_infrastructure_header.vh
new file mode 100755
index 0000000..d3d4a0e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/axi_infrastructure_header.vh
@@ -0,0 +1,138 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXI Infrastructure Modules
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+//
+// Tasks:
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+localparam G_AXI_AWADDR_INDEX   = 0;
+localparam G_AXI_AWADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_AWPROT_INDEX   = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
+localparam G_AXI_AWPROT_WIDTH   = 3;
+localparam G_AXI_AWSIZE_INDEX   = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
+localparam G_AXI_AWSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_AWBURST_INDEX  = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
+localparam G_AXI_AWBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_AWCACHE_INDEX  = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
+localparam G_AXI_AWCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWLEN_INDEX    = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
+localparam G_AXI_AWLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_AWLOCK_INDEX   = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
+localparam G_AXI_AWLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_AWID_INDEX     = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
+localparam G_AXI_AWID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_AWQOS_INDEX    = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
+localparam G_AXI_AWQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
+localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_AWUSER_INDEX   = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
+localparam G_AXI_AWUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
+localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
+localparam G_AXI_ARADDR_INDEX   = 0;
+localparam G_AXI_ARADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_ARPROT_INDEX   = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
+localparam G_AXI_ARPROT_WIDTH   = 3;
+localparam G_AXI_ARSIZE_INDEX   = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
+localparam G_AXI_ARSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_ARBURST_INDEX  = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
+localparam G_AXI_ARBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_ARCACHE_INDEX  = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
+localparam G_AXI_ARCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARLEN_INDEX    = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
+localparam G_AXI_ARLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_ARLOCK_INDEX   = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
+localparam G_AXI_ARLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_ARID_INDEX     = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
+localparam G_AXI_ARID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_ARQOS_INDEX    = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
+localparam G_AXI_ARQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
+localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_ARUSER_INDEX   = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
+localparam G_AXI_ARUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
+localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
+// Write channel widths
+localparam G_AXI_WDATA_INDEX    = 0;
+localparam G_AXI_WDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_WSTRB_INDEX    = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
+localparam G_AXI_WSTRB_WIDTH    = C_AXI_DATA_WIDTH / 8;
+localparam G_AXI_WLAST_INDEX    = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
+localparam G_AXI_WLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_WID_INDEX      = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
+localparam G_AXI_WID_WIDTH      = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_WUSER_INDEX    = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
+localparam G_AXI_WUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
+localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
+// Write Response channel Widths
+localparam G_AXI_BRESP_INDEX    = 0;
+localparam G_AXI_BRESP_WIDTH    = 2;
+localparam G_AXI_BID_INDEX      = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
+localparam G_AXI_BID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_BUSER_INDEX    = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
+localparam G_AXI_BUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
+localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
+// Read channel widths
+localparam G_AXI_RDATA_INDEX    = 0;
+localparam G_AXI_RDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_RRESP_INDEX    = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
+localparam G_AXI_RRESP_WIDTH    = 2;
+localparam G_AXI_RLAST_INDEX    = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
+localparam G_AXI_RLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_RID_INDEX      = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
+localparam G_AXI_RID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_RUSER_INDEX    = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
+localparam G_AXI_RUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
+localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/axidma_fifo.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/axidma_fifo.vh
new file mode 100755
index 0000000..8c12d3e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/axidma_fifo.vh
@@ -0,0 +1,1287 @@
+`ifndef AXIDMA_FIFO_VH
+`define AXIDMA_FIFO_VH
+`include "xdma_axi4mm_axi_bridge.vh"
+//-----------------------------------------------------------------------------
+// $Id: 
+//-----------------------------------------------------------------------------
+// axi_bridge.vh
+//-----------------------------------------------------------------------------
+// (c) Copyright 2010 - 2010 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and 
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:        axi_bridge.vh
+//
+// Description:     
+//                  
+// This file needs to be included in all modules so that all the modules can commonly 
+// reference state_transitions
+//                   
+//                  
+// VHDL-Standard:   VHDL'93
+//-----------------------------------------------------------------------------
+// Structure:   
+//              Include file
+//
+//-----------------------------------------------------------------------------
+// Revision:        v1.05.a
+// Date:            06/28/12
+//
+//-----------------------------------------------------------------------------
+
+
+
+   //signal arid_dependencySM_cs : arid_dependencySM_STATES;
+   //signal arid_dependencySM_ns : arid_dependencySM_STATES;
+   module xdma_v4_1_8_BufferMem
+   #(
+     parameter TCQ = 1,
+     parameter BUF_DATAWIDTH = 256,
+     parameter BUF_WE = BUF_DATAWIDTH/8,
+     parameter BUF_DEPTH = 512,
+     parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+     parameter NO_OUTPUT_REG = 1
+  ) 
+  (
+       input clkin,
+       input reset_n,
+       input wrEn,
+       input [BUF_DATAWIDTH-1:0] DataIn,
+       input [BUF_DATAWIDTH/8-1:0] EccIn,
+       input [BUF_PTR-1:0] AddrIn,
+       input [BUF_PTR-1:0] AddrOut,
+       input rdEn,
+       output [BUF_DATAWIDTH-1:0] DataOut,
+       output [BUF_DATAWIDTH/8-1:0] EccOut
+  );
+  reg [BUF_DATAWIDTH-1:0] DataMem [BUF_DEPTH-1:0];
+  reg [BUF_DATAWIDTH/8-1:0] EccMem [BUF_DEPTH-1:0];
+   `XLREG_XDMA(clkin, reset_n) begin
+       if (~reset_n) begin
+       end 
+       else if (wrEn) begin
+           DataMem[AddrIn] <= DataIn;
+           EccMem[AddrIn] <= EccIn;
+       end
+   end
+  //wire [BUF_DATAWIDTH-1:0] BuftoMem;
+  if(NO_OUTPUT_REG) begin: nooutput
+     assign DataOut = DataMem[AddrOut];
+     assign EccOut = EccMem[AddrOut];
+  end
+  else begin: outputStage
+     reg [BUF_DATAWIDTH-1:0] BufDout;
+     reg [BUF_DATAWIDTH/8-1:0] BufEccout;
+     `XSRREG_AXIMM(clkin, reset_n, BufDout, rdEn ?DataMem[AddrOut]: BufDout, {BUF_DATAWIDTH{1'b0}})
+     `XSRREG_AXIMM(clkin, reset_n, BufEccout, rdEn ?EccMem[AddrOut] : BufEccout, {(BUF_DATAWIDTH/8){1'b0}})
+     assign DataOut = BufDout;
+     assign EccOut = BufEccout;
+
+  end
+
+  endmodule // BufferMem
+
+  module xdma_v4_1_8_GenericFIFO1R2W
+    #(parameter BUF_DATAWIDTH = 256,
+      parameter BUF_WE = BUF_DATAWIDTH/8,
+      parameter BUF_DEPTH = 512,
+      parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+      parameter AE_THRESHOLD = BUF_DEPTH >> 2,
+      parameter AF_THRESHOLD = BUF_DEPTH - 2
+    )
+    (
+        input clkin,
+    input reset_n,
+    input sync_reset_n,
+    input WrEn0,
+    input WrEn1,
+        input [BUF_DATAWIDTH-1:0] DataIn0,
+        input [BUF_DATAWIDTH-1:0] DataIn1,
+        output [BUF_DATAWIDTH-1:0] DataOut,
+    input RdEn,
+    output almost_empty,
+    output almost_full,
+    output empty,
+    output full0,
+    output full1
+   );
+(* ram_style = "DISTRIBUTED" *)
+   reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0];
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtrp1;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr;
+   reg [BUF_PTR:0] FifoCntr;
+   reg almost_empty_ff;
+   reg almost_full_ff;
+   reg empty_ff;
+   reg full_ff0;
+   reg full_ff1;
+   assign RdDeQ = RdEn;
+   assign DataOut = MemArray[RdPtr];
+   assign almost_empty = almost_empty_ff;
+   assign almost_full = almost_full_ff;
+   assign empty = empty_ff;
+   assign full0 = full_ff0;
+   assign full1 = full_ff1;
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n) begin
+         WrPtr <= 'd0;
+         WrPtrp1 <= 'd1;
+    end
+        else if (WrEn0 && WrEn1) begin
+        WrPtr <= WrPtr + 'd2;
+        WrPtrp1 <= WrPtr + 'd3;
+        end
+        else if (WrEn0 || WrEn1) begin
+        WrPtr <= WrPtr + 'd1;
+        WrPtrp1 <= WrPtr + 'd2;
+       end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n) begin
+         RdPtr <= 'd0;
+    end
+        else if (RdEn) begin
+        RdPtr <= RdPtr + 'd1;
+        end
+    end
+
+   always @ (posedge clkin) begin
+    if (WrEn0 && WrEn1)
+    begin
+           MemArray[WrPtr] <= DataIn0;
+           MemArray[WrPtrp1] <= DataIn1;
+    end
+    else if (WrEn0)
+           MemArray[WrPtr] <= DataIn0;
+    else if (WrEn1)
+           MemArray[WrPtr] <= DataIn1;
+   end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n)
+         FifoCntr <= 'd0;
+    else if (WrEn0 && WrEn1 && ~RdDeQ)
+        FifoCntr <= FifoCntr +'d2;
+    else if (((WrEn0 || WrEn1) && ~RdDeQ) ||
+         ((WrEn0 && WrEn1) && RdDeQ))
+        FifoCntr <= FifoCntr +'d1;
+    else if (~(WrEn0 || WrEn1) && RdDeQ)
+        FifoCntr <= FifoCntr -'d1;
+        else
+        FifoCntr <= FifoCntr;
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n)
+        empty_ff <= 1'b1;
+    else if((FifoCntr==0) || ((FifoCntr==1) && RdEn))
+        empty_ff <= 1'b1;
+    else if(FifoCntr>0)
+        empty_ff <= 1'b0;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n)
+        almost_empty_ff <= 1'b1;
+    else if(FifoCntr>(AE_THRESHOLD))
+        almost_empty_ff <= 1'b0;
+    else if(FifoCntr<=(AE_THRESHOLD))
+        almost_empty_ff <= 1'b1;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n)
+        full_ff0 <= 1'b0;
+    else if ((FifoCntr==(BUF_DEPTH)) || 
+        ((FifoCntr==(BUF_DEPTH-1)) && (WrEn0 || WrEn1)) || 
+        ((FifoCntr==(BUF_DEPTH-2)) && (WrEn0 && WrEn1)))
+        full_ff0 <= 1'b1;
+    else if(FifoCntr<BUF_DEPTH)
+        full_ff0 <= 1'b0;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n)
+        full_ff1 <= 1'b0;
+    else if ((FifoCntr==(BUF_DEPTH-1)) || 
+        ((FifoCntr==(BUF_DEPTH-2)) && (WrEn0 || WrEn1)) || 
+        ((FifoCntr==(BUF_DEPTH-3)) && (WrEn0 && WrEn1)))
+        full_ff1 <= 1'b1;
+    else if(FifoCntr<BUF_DEPTH-1)
+        full_ff1 <= 1'b0;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n || ~sync_reset_n)
+        almost_full_ff <= 1'b0;
+    else if(FifoCntr>(AF_THRESHOLD))
+        almost_full_ff <= 1'b1;
+    else if(FifoCntr<=(AF_THRESHOLD)) 
+        almost_full_ff <= 1'b0;
+   end
+   endmodule
+  module xdma_v4_1_8_GenericFIFO
+    #(parameter BUF_DATAWIDTH = 256,
+      parameter BUF_WE = BUF_DATAWIDTH/8,
+      parameter BUF_DEPTH = 512,
+      parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+      parameter AE_THRESHOLD = BUF_DEPTH >> 2,
+      parameter AF_THRESHOLD = BUF_DEPTH - 2
+    )
+    (
+        input clkin,
+    input reset_n,
+    input sync_reset_n,
+        input [BUF_DATAWIDTH-1:0] DataIn,
+        output [BUF_DATAWIDTH-1:0] DataOut,
+    input WrEn,
+    input RdEn,
+    output almost_empty,
+    output almost_full,
+    output empty,
+    output full
+   );
+(* ram_style = "DISTRIBUTED" *)
+   reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0];
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr;
+   reg [BUF_PTR:0] FifoCntrWr;
+   reg [BUF_PTR:0] FifoCntrRd;
+   wire WriteQ, RdDeQ;
+   reg almost_empty_ff;
+   reg almost_full_ff;
+   reg empty_ff;
+   reg full_ff;
+   assign WriteQ = WrEn;
+   assign RdDeQ = RdEn;
+   assign DataOut = MemArray[RdPtr];
+   assign almost_empty = almost_empty_ff;
+   assign almost_full = almost_full_ff;
+   assign empty = empty_ff;
+   assign full = full_ff;
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n)
+         WrPtr <= 'd0;
+    else if  (~sync_reset_n)
+         WrPtr <= 'd0;
+        else if (WrEn) begin
+        WrPtr <= WrPtr + 'd1;
+        end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) 
+         RdPtr <= 'd0;
+        else if (~sync_reset_n) 
+         RdPtr <= 'd0;
+        else if (RdEn) begin
+        RdPtr <= RdPtr + 'd1;
+        end
+    end
+
+   always @ (posedge clkin) begin
+    if (WrEn)
+           MemArray[WrPtr] <= DataIn;
+   end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n)
+         FifoCntrWr <= 'd0;
+        else if (~sync_reset_n) 
+         FifoCntrWr <= 'd0;
+        else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin
+        FifoCntrWr <= FifoCntrWr;
+        end
+    else if (WrEn) begin
+        FifoCntrWr <= FifoCntrWr +'d1;
+    end
+        else begin
+        FifoCntrWr <= FifoCntrWr -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) 
+         FifoCntrRd <= 'd0;
+        else if (~sync_reset_n) 
+         FifoCntrRd <= 'd0;
+        else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin
+        FifoCntrRd <= FifoCntrRd;
+        end
+    else if (WriteQ) begin
+        FifoCntrRd <= FifoCntrRd +'d1;
+    end
+        else begin
+        FifoCntrRd <= FifoCntrRd -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n)
+        empty_ff <= 1'b1;
+        else if (~sync_reset_n)
+        empty_ff <= 1'b1;
+    else if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn))
+        empty_ff <= 1'b1;
+    else if(FifoCntrRd>0)
+        empty_ff <= 1'b0;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n)
+        almost_empty_ff <= 1'b1;
+        else if (~sync_reset_n)
+        almost_empty_ff <= 1'b1;
+    else if(FifoCntrRd>(AE_THRESHOLD))
+        almost_empty_ff <= 1'b0;
+    else if(FifoCntrRd<=(AE_THRESHOLD))
+        almost_empty_ff <= 1'b1;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n)
+        full_ff <= 1'b0;
+        else if (~sync_reset_n)
+        full_ff <= 1'b0;
+    else if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ))
+        full_ff <= 1'b1;
+    else if(FifoCntrWr<BUF_DEPTH)
+        full_ff <= 1'b0;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n)
+        almost_full_ff <= 1'b0;
+        else if (~sync_reset_n)
+        almost_full_ff <= 1'b0;
+    else if(FifoCntrWr>(AF_THRESHOLD))
+        almost_full_ff <= 1'b1;
+    else if(FifoCntrWr<=(AF_THRESHOLD)) 
+        almost_full_ff <= 1'b0;
+   end
+   endmodule
+
+  module xdma_v4_1_8_GenericFIFOAsyncNoHead
+    #(parameter BUF_DATAWIDTH = 256,
+      parameter BUF_WE = BUF_DATAWIDTH/8,
+      parameter BUF_DEPTH = 512,
+      parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1
+    )
+    (
+        input clkin,
+    input reset_n,
+    input clkout,
+    input reseto_n,
+        input [BUF_DATAWIDTH-1:0] DataIn,
+        output [BUF_DATAWIDTH-1:0] DataOut,
+    input WrEn,
+    input RdEn,
+    output almost_empty,
+    output almost_full,
+    output empty,
+    output full
+   );
+(* ram_style = "DISTRIBUTED" *)
+   reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0];
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr;
+   reg [BUF_PTR:0] FifoCntrWr;
+   reg [BUF_PTR:0] FifoCntrRd;
+   wire WriteQ, RdDeQ;
+   reg almost_empty_ff;
+   reg almost_full_ff;
+   reg empty_ff;
+   reg full_ff;
+   assign WriteQ = WrEn;
+   assign RdDeQ = RdEn;
+
+   assign DataOut = MemArray[RdPtr];
+
+   assign almost_empty = almost_empty_ff;
+   assign almost_full = almost_full_ff;
+   assign empty = empty_ff;
+   assign full = full_ff;
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         WrPtr <= 'd0;
+    end
+        else if (WrEn) begin
+        WrPtr <= WrPtr + 'd1;
+        end
+    end
+
+    `XLREG_XDMA(clkin, reset_n) begin
+         if (~reset_n) begin
+            RdPtr <= 'd0;
+    end else if (RdEn) begin
+          RdPtr <= RdPtr + 'd1;
+    end
+   end
+
+   always @ (posedge clkin) begin
+    if (WrEn)
+            MemArray[WrPtr] <= DataIn;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         FifoCntrWr <= 'd0;
+    end
+        else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin
+        FifoCntrWr <= FifoCntrWr;
+        end
+    else if (WrEn) begin
+        FifoCntrWr <= FifoCntrWr +'d1;
+    end
+        else begin
+        FifoCntrWr <= FifoCntrWr -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         FifoCntrRd <= 'd0;
+    end
+        else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin
+        FifoCntrRd <= FifoCntrRd;
+        end
+    else if (WriteQ) begin
+        FifoCntrRd <= FifoCntrRd +'d1;
+    end
+        else begin
+        FifoCntrRd <= FifoCntrRd -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+        almost_empty_ff <= 1'b1;
+        empty_ff <= 1'b1;
+    end
+    else begin
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin
+            empty_ff <= 1'b1;
+        end 
+        else if(FifoCntrRd>0) begin
+            empty_ff <= 1'b0;
+        end
+
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin
+            almost_empty_ff <= 1'b1;
+        end
+        else if(FifoCntrRd>(BUF_DEPTH>>2)) begin
+            almost_empty_ff <= 1'b0;
+        end
+        else if(FifoCntrRd<=(BUF_DEPTH>>2)) begin
+            almost_empty_ff <= 1'b1;
+        end
+    end
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+        almost_full_ff <= 1'b0;
+        full_ff <= 1'b0;
+    end
+    else begin
+        if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin
+            full_ff <= 1'b1;
+        end     
+        else if    (FifoCntrWr<BUF_DEPTH) begin
+            full_ff <= 1'b0;
+        end
+
+        if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if(FifoCntrWr>(BUF_DEPTH-2)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if(FifoCntrWr<=(BUF_DEPTH-2)) begin
+            almost_full_ff <= 1'b0;
+        end
+    end
+   end
+   endmodule
+
+  module xdma_v4_1_8_GenericFIFOAsync
+    #(parameter BUF_DATAWIDTH = 256,
+      parameter BUF_WE = BUF_DATAWIDTH/8,
+      parameter BUF_DEPTH = 512,
+      parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+      parameter AE_THRESHOLD = BUF_DEPTH >> 2,
+      parameter AF_THRESHOLD = BUF_DEPTH - 2
+    )
+    (
+        input clkin,
+    input reset_n,
+    input clkout,
+    input reseto_n,
+        input [BUF_DATAWIDTH-1:0] DataIn,
+        output [BUF_DATAWIDTH-1:0] DataOut,
+    input WrEn,
+    input RdEn,
+    output almost_empty,
+    output almost_full,
+    output empty,
+    output full
+   );
+
+(* ram_style = "DISTRIBUTED" *)
+   reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0];
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr;
+   reg [BUF_PTR:0] FifoCntrWr;
+   reg [BUF_PTR:0] FifoCntrRd;
+   wire WriteQ, RdDeQ;
+   reg almost_empty_ff;
+   reg almost_full_ff;
+   reg empty_ff;
+   reg full_ff;
+   assign WriteQ = WrEn;
+   assign RdDeQ = RdEn;
+
+   reg [BUF_DATAWIDTH-1:0] Head;
+
+   assign almost_empty = almost_empty_ff;
+   assign almost_full = almost_full_ff;
+   assign empty = empty_ff;
+   assign full = full_ff;
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         WrPtr <= 'd0;
+    end
+        else if (WrEn) begin
+        WrPtr <= WrPtr + 'd1;
+        end
+    end
+
+    `XLREG_XDMA(clkin, reset_n) begin
+           if (~reset_n) begin
+             RdPtr <= 'd0;
+    end
+           else if ((RdEn && (FifoCntrRd>1) ) ||
+         (WrEn && (FifoCntrRd==0) ) ||
+         (RdEn && WrEn && (FifoCntrRd==1)))begin
+               RdPtr <= RdPtr + 'd1;
+           end
+    end
+
+   always @(posedge clkin) begin
+    if (WrEn)
+            MemArray[WrPtr] <= DataIn;
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         FifoCntrWr <= 'd0;
+    end
+        else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin
+        FifoCntrWr <= FifoCntrWr;
+        end
+    else if (WrEn) begin
+        FifoCntrWr <= FifoCntrWr +'d1;
+    end
+        else begin
+        FifoCntrWr <= FifoCntrWr -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         FifoCntrRd <= 'd0;
+    end
+        else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin
+        FifoCntrRd <= FifoCntrRd;
+        end
+    else if (WriteQ) begin
+        FifoCntrRd <= FifoCntrRd +'d1;
+    end
+        else begin
+        FifoCntrRd <= FifoCntrRd -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+        almost_empty_ff <= 1'b1;
+        empty_ff <= 1'b1;
+    end
+    else begin
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin
+            empty_ff <= 1'b1;
+        end 
+        else if(FifoCntrRd>0) begin
+            empty_ff <= 1'b0;
+        end
+
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin
+            almost_empty_ff <= 1'b1;
+        end
+        else if(FifoCntrRd>(AE_THRESHOLD)) begin
+            almost_empty_ff <= 1'b0;
+        end
+        else if(FifoCntrRd<=(AE_THRESHOLD)) begin
+            almost_empty_ff <= 1'b1;
+        end
+    end
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+        almost_full_ff <= 1'b0;
+        full_ff <= 1'b0;
+    end
+    else begin
+        if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin
+            full_ff <= 1'b1;
+        end     
+        else if    (FifoCntrWr<BUF_DEPTH) begin
+            full_ff <= 1'b0;
+        end
+
+        if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if(FifoCntrWr>(AF_THRESHOLD)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if(FifoCntrWr<=(AF_THRESHOLD)) begin
+            almost_full_ff <= 1'b0;
+        end
+    end
+   end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+          if (~reset_n) begin
+        Head <= 1'b0;
+    end 
+    else begin
+        if ((WrEn && (FifoCntrRd == 0)) || (WrEn && RdEn && (FifoCntrRd == 1)))
+            Head <= DataIn;
+        else if (RdEn || (FifoCntrRd == 0))
+               Head <= MemArray[RdPtr];
+    end
+    end
+    assign DataOut = Head;
+
+   endmodule
+
+  module xdma_v4_1_8_GenericFIFOHead
+    #(parameter BUF_DATAWIDTH = 256,
+      parameter BUF_WE = BUF_DATAWIDTH/8,
+      parameter BUF_DEPTH = 512,
+      parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+      parameter AE_THRESHOLD = BUF_DEPTH >> 2,
+      parameter AF_THRESHOLD = BUF_DEPTH - 2
+    )
+    (
+        input clkin,
+    input reset_n,
+    input sync_reset_n,
+    input [BUF_DATAWIDTH-1:0] DataIn,
+    output [BUF_DATAWIDTH-1:0] DataOut,
+    input WrEn,
+    input WrAlloc,
+    input RdEn,
+    output almost_empty,
+    output almost_full,
+    output empty,
+    output full
+   );
+
+(* ram_style = "DISTRIBUTED" *)
+   reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0];
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr;
+   reg [BUF_PTR:0] FifoCntrWr;
+   reg [BUF_PTR:0] FifoCntrRd;
+   wire WriteQ, RdDeQ;
+   reg almost_empty_ff;
+   reg almost_full_ff;
+   reg empty_ff;
+   reg full_ff;
+   assign WriteQ = WrEn;
+   assign RdDeQ = RdEn;
+
+   reg [BUF_DATAWIDTH-1:0] Head;
+
+   assign almost_empty = almost_empty_ff;
+   assign almost_full = almost_full_ff;
+   assign empty = empty_ff;
+   assign full = full_ff;
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         WrPtr <= 'd0;
+    end
+        else if (~sync_reset_n)
+         WrPtr <= 'd0;
+        else if (WrEn) begin
+        WrPtr <= WrPtr + 'd1;
+        end
+    end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+           if (~reset_n) begin
+             RdPtr <= 'd0;
+    end
+        else if (~sync_reset_n)
+         RdPtr <= 'd0;
+           else if ((RdEn && (FifoCntrRd>1) ) ||
+         (WrEn && (FifoCntrRd==0) ) ||
+         (RdEn && WrEn && (FifoCntrRd==1)))begin
+               RdPtr <= RdPtr + 'd1;
+           end
+    end
+
+   always @(posedge clkin) begin
+    if (WrEn)
+            MemArray[WrPtr] <= DataIn;
+   end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         FifoCntrWr <= 'd0;
+    end
+    else if (~sync_reset_n)
+         FifoCntrWr <= 'd0;
+        else if ((WrAlloc & RdDeQ) | (~WrAlloc & ~RdDeQ))begin
+        FifoCntrWr <= FifoCntrWr;
+        end
+    else if (WrAlloc) begin
+        FifoCntrWr <= FifoCntrWr +'d1;
+    end
+        else begin
+        FifoCntrWr <= FifoCntrWr -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+         FifoCntrRd <= 'd0;
+    end
+        else if (~sync_reset_n)
+         FifoCntrRd <= 'd0;
+        else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin
+        FifoCntrRd <= FifoCntrRd;
+        end
+    else if (WriteQ) begin
+        FifoCntrRd <= FifoCntrRd +'d1;
+    end
+        else begin
+        FifoCntrRd <= FifoCntrRd -'d1;
+    end
+    end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+        almost_empty_ff <= 1'b1;
+        empty_ff <= 1'b1;
+    end
+        else if (~sync_reset_n) begin
+        almost_empty_ff <= 1'b1;
+        empty_ff <= 1'b1;
+    end
+    else begin
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin
+            empty_ff <= 1'b1;
+        end 
+        else if(FifoCntrRd>0) begin
+            empty_ff <= 1'b0;
+        end
+
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin
+            almost_empty_ff <= 1'b1;
+        end
+        else if(FifoCntrRd>(AE_THRESHOLD)) begin
+            almost_empty_ff <= 1'b0;
+        end
+        else if(FifoCntrRd<=(AE_THRESHOLD)) begin
+            almost_empty_ff <= 1'b1;
+        end
+    end
+   end
+   `XLREG_XDMA(clkin, reset_n) begin
+        if (~reset_n) begin
+        almost_full_ff <= 1'b0;
+        full_ff <= 1'b0;
+    end
+        else if (~sync_reset_n) begin
+        almost_full_ff <= 1'b0;
+        full_ff <= 1'b0;
+    end
+    else begin
+        if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin
+            full_ff <= 1'b1;
+        end     
+        else if    (FifoCntrWr<BUF_DEPTH) begin
+            full_ff <= 1'b0;
+        end
+
+        if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if((FifoCntrWr>AF_THRESHOLD) || ((FifoCntrWr == AF_THRESHOLD) && WriteQ)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if(FifoCntrWr<=(AF_THRESHOLD)) begin
+            almost_full_ff <= 1'b0;
+        end
+    end
+   end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+          if (~reset_n) begin
+        Head <= 1'b0;
+    end 
+    else if (~sync_reset_n) begin
+        Head <= 1'b0;
+    end
+    else begin
+        if ((WrEn && (FifoCntrRd == 0)) || (WrEn && RdEn && (FifoCntrRd == 1)))
+            Head <= DataIn;
+        else if (RdEn || (FifoCntrRd == 0))
+               Head <= MemArray[RdPtr];
+    end
+    end
+    assign DataOut = Head;
+
+   endmodule
+
+  module xdma_v4_1_8_GenericFIFOHead2
+    #(parameter BUF_DATAWIDTH = 256,
+      parameter BUF_WE = BUF_DATAWIDTH/8,
+      parameter BUF_DEPTH = 512,
+      parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+      parameter AE_THRESHOLD = BUF_DEPTH >> 2,
+      parameter AF_THRESHOLD = BUF_DEPTH - 2
+    )
+    (
+    input clkin,
+    input reset_n,
+    input sync_reset_n,
+    input [BUF_DATAWIDTH-1:0] DataIn,
+    output [BUF_DATAWIDTH-1:0] DataOut,
+    input WrEn,
+    input RdEn,
+    output almost_empty,
+    output almost_full,
+    output empty,
+    output full
+   );
+
+(* ram_style = "DISTRIBUTED" *)
+   reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0];
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr;
+(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr;
+   reg [BUF_PTR:0] FifoCntrWr;
+   reg [BUF_PTR:0] FifoCntrRd;
+   wire WriteQ, RdDeQ;
+   reg almost_empty_ff;
+   reg almost_full_ff;
+   reg empty_ff;
+   reg full_ff;
+   assign WriteQ = WrEn;
+   assign RdDeQ = RdEn;
+
+   reg [BUF_DATAWIDTH-1:0] Head;
+
+   assign almost_empty = almost_empty_ff;
+   assign almost_full = almost_full_ff;
+   assign empty = empty_ff;
+   assign full = full_ff;
+
+   `XLREG_XDMA (clkin, reset_n)
+    begin
+        if (~reset_n)
+            WrPtr <= 'd0;
+        else if (~sync_reset_n)
+            WrPtr <= 'd0;
+        else if (WrEn && (BUF_DEPTH > 1)) begin
+            WrPtr <= WrPtr + 'd1;
+        end
+    end
+
+   `XLREG_XDMA (clkin, reset_n)
+    begin
+        if (~reset_n)
+            RdPtr <= 'd0;
+        else if (~sync_reset_n) begin
+            RdPtr <= 'd0;
+        end
+        else if (BUF_DEPTH > 1)
+        begin
+            if ((RdEn && (FifoCntrRd>1) ) ||
+                (WrEn && (FifoCntrRd==0) ) ||
+                (RdEn && WrEn && (FifoCntrRd==1)))begin
+                   RdPtr <= RdPtr + 'd1;
+            end
+        end
+    end
+
+   always @(posedge clkin) begin
+    if (WrEn)
+            MemArray[WrPtr] <= DataIn;
+   end
+   
+   `XLREG_XDMA (clkin, reset_n)
+    begin
+        if (~reset_n) 
+            FifoCntrWr <= 'd0;
+        else if (~sync_reset_n)
+            FifoCntrWr <= 'd0;
+        else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin
+            FifoCntrWr <= FifoCntrWr;
+        end
+        else if (WrEn) begin
+            FifoCntrWr <= FifoCntrWr +'d1;
+        end
+        else begin
+            FifoCntrWr <= FifoCntrWr -'d1;
+        end
+    end
+   `XLREG_XDMA (clkin, reset_n)
+    begin
+        if (~reset_n) begin
+         FifoCntrRd <= 'd0;
+        end
+        else if (~sync_reset_n) begin
+         FifoCntrRd <= 'd0;
+        end
+        else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin
+        FifoCntrRd <= FifoCntrRd;
+        end
+    else if (WriteQ) begin
+        FifoCntrRd <= FifoCntrRd +'d1;
+    end
+        else begin
+        FifoCntrRd <= FifoCntrRd -'d1;
+    end
+    end
+   `XLREG_XDMA (clkin, reset_n)
+    begin
+        if (~reset_n) begin
+        almost_empty_ff <= 1'b1;
+        empty_ff <= 1'b1;
+    end
+       else if (~sync_reset_n) begin
+        almost_empty_ff <= 1'b1;
+        empty_ff <= 1'b1;
+    end
+    else begin
+        if(((FifoCntrRd==0) && ~WrEn) || ((FifoCntrRd==1) && RdEn && ~WrEn)) begin
+            empty_ff <= 1'b1;
+        end 
+        else  begin
+            empty_ff <= 1'b0;
+        end
+
+        if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn && ~WrEn)) begin
+            almost_empty_ff <= 1'b1;
+        end
+        else if(FifoCntrRd>(AE_THRESHOLD)) begin
+            almost_empty_ff <= 1'b0;
+        end
+        else if(FifoCntrRd<=(AE_THRESHOLD)) begin
+            almost_empty_ff <= 1'b1;
+        end
+    end
+   end
+
+   `XLREG_XDMA (clkin, reset_n)
+    begin
+        if (~reset_n) begin
+        almost_full_ff <= 1'b0;
+        full_ff <= 1'b0;
+    end
+        else if (~sync_reset_n) begin
+        almost_full_ff <= 1'b0;
+        full_ff <= 1'b0;
+    end
+    else begin
+        if(((FifoCntrWr==(BUF_DEPTH+1)) && (~RdEn || WriteQ)) || ((FifoCntrWr==BUF_DEPTH) && WriteQ && ~RdEn)) begin
+            full_ff <= 1'b1;
+        end     
+        else 
+        begin
+            full_ff <= 1'b0;
+        end
+
+        if((FifoCntrWr>(BUF_DEPTH)) || ((FifoCntrWr==BUF_DEPTH) && WriteQ)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if((FifoCntrWr>AF_THRESHOLD) || ((FifoCntrWr == AF_THRESHOLD) && WriteQ)) begin
+            almost_full_ff <= 1'b1;
+        end
+        else if(FifoCntrWr<=(AF_THRESHOLD)) begin
+            almost_full_ff <= 1'b0;
+        end
+    end
+   end
+
+   `XLREG_XDMA(clkin, reset_n) begin
+       if (~reset_n) begin
+           Head <= 1'b0;
+       end 
+       else if (~sync_reset_n) begin
+           Head <= 1'b0;
+       end 
+       else begin
+       if ((WrEn && (FifoCntrRd == 0)) || (WrEn && RdEn && (FifoCntrRd == 1)))
+           Head <= DataIn;
+       else if (RdEn || (FifoCntrRd == 0))
+           Head <= MemArray[RdPtr];
+    end
+    end
+    assign DataOut = Head;
+
+   endmodule
+
+/*
+module xdma_v4_1_8_GenericBRAMFIFOHead #(
+    parameter TCQ = 0,
+    parameter BUF_DATAWIDTH = 256,
+    parameter BUF_WE = BUF_DATAWIDTH/8,
+    parameter BUF_DEPTH = 512,
+    parameter BUF_PTR = (BUF_DEPTH <=2) ? 1:
+                           (BUF_DEPTH <=4)    ? 2:
+                           (BUF_DEPTH <=8)    ? 3:
+                           (BUF_DEPTH <=16)   ? 4:
+                           (BUF_DEPTH <=32)   ? 5:
+                           (BUF_DEPTH <=64)   ? 6:
+                           (BUF_DEPTH <=128)   ? 7:
+                           (BUF_DEPTH <=256)   ? 8:
+                           (BUF_DEPTH <=512)   ? 9:
+                   (BUF_DEPTH <=1024)   ? 10 : -1,
+      parameter AE_THRESHOLD = BUF_DEPTH >> 2,
+      parameter AF_THRESHOLD = BUF_DEPTH - 2
+    )
+    (
+        input                 clk,
+    input                rst,
+    input                srst,
+        input [BUF_DATAWIDTH-1:0]    DataIn,
+        output [BUF_DATAWIDTH-1:0]    DataOut,
+    input                WrEn,
+    input                RdEn,
+    output                almost_empty,
+    output                almost_full,
+    output                empty,
+    output                full
+   );
+
+(* ram_style = "BLOCK" *)
+reg [BUF_DATAWIDTH-1:0]    MemArray [BUF_DEPTH-1:0];
+
+reg [BUF_PTR-1:0]        WrPtr;
+reg [BUF_PTR-1:0]        WrPtr_nxt;
+
+reg [BUF_PTR-1:0]        RdPtr_nxt;
+reg [BUF_PTR-1:0]        RdPtr;
+
+reg [BUF_PTR:0]            FifoCntr_nxt;
+reg [BUF_PTR:0]            FifoCntr;
+
+reg                almost_empty_nxt;
+reg                almost_empty_ff;
+reg                almost_full_nxt;
+reg                almost_full_ff;
+reg                empty_nxt;
+reg                empty_ff;
+reg                full_nxt;
+reg                full_ff;
+
+wire [BUF_DATAWIDTH-1:0]        Head_nxt;
+reg [BUF_DATAWIDTH-1:0]        Head;
+
+assign almost_empty    = almost_empty_ff;
+assign almost_full    = almost_full_ff;
+assign empty        = empty_ff;
+assign full        = full_ff;
+
+always @(*) begin
+    WrPtr_nxt = WrPtr;
+    if (srst)
+        WrPtr_nxt = 'h0;
+    else if (WrEn)
+        WrPtr_nxt = WrPtr + 'd1;
+end
+`XSRREG_XDMA(clk, ~rst, WrPtr, WrPtr_nxt, 'h0)
+
+always @(*) begin
+    RdPtr_nxt = RdPtr;
+           if (srst) begin
+             RdPtr_nxt = 'h0;
+    end
+           else if ((RdEn && (FifoCntr > 1) ) ||
+         (WrEn && (FifoCntr == 0) ) ||
+         (RdEn && WrEn && (FifoCntr == 1)))begin
+               RdPtr_nxt = RdPtr + 'd1;
+           end
+    end
+`XSRREG_XDMA(clk, ~rst, RdPtr, RdPtr_nxt, 'h0)
+
+always @(posedge clk) begin
+    if (WrEn)
+            MemArray[WrPtr] <= DataIn;
+end
+
+always @(*) begin
+    FifoCntr_nxt = FifoCntr;
+        if (srst)
+        FifoCntr_nxt = 'd0;
+    else if ((RdEn & WrEn) | (~RdEn & ~WrEn)) 
+        FifoCntr_nxt = FifoCntr;
+    else if (WrEn) 
+        FifoCntr_nxt = FifoCntr +'d1;
+    else 
+        FifoCntr_nxt = FifoCntr -'d1;
+end
+`XSRREG_XDMA(clk, ~rst, FifoCntr, FifoCntr_nxt, 'h0)
+
+always @(*) begin
+    almost_empty_nxt    = almost_empty_ff;
+    empty_nxt        = empty_ff;
+
+        if (srst) begin
+        almost_empty_nxt= 1'b1;
+        empty_nxt    = 1'b1;
+    end
+    else begin
+        if((FifoCntr==0) || ((FifoCntr==1) && RdEn))
+            empty_nxt = 1'b1;
+        else if(FifoCntr > 0) 
+            empty_nxt = 1'b0;
+
+        if((FifoCntr==0) || ((FifoCntr==1) && RdEn))
+            almost_empty_nxt = 1'b1;
+        else if(FifoCntr > AE_THRESHOLD)
+            almost_empty_nxt = 1'b0;
+        else if(FifoCntr <= AE_THRESHOLD)
+            almost_empty_nxt = 1'b1;
+    end
+end
+`XSRREG_XDMA(clk, ~rst, almost_empty_ff, almost_empty_nxt, 'h0)
+`XSRREG_XDMA(clk, ~rst, empty_ff, empty_nxt, 'h0)
+
+
+always @(*) begin
+    full_nxt = full_ff;
+    almost_full_nxt = almost_full_ff;
+        if (srst) begin
+        almost_full_nxt    = 1'b0;
+        full_nxt     = 1'b0;
+    end
+    else begin
+        if((FifoCntr==(BUF_DEPTH)) || ((FifoCntr==(BUF_DEPTH-1)) && WrEn)) 
+            full_nxt = 1'b1;
+        else if    (FifoCntr<BUF_DEPTH) 
+            full_nxt = 1'b0;
+
+        if((FifoCntr==(BUF_DEPTH)) || ((FifoCntr==(BUF_DEPTH-1)) && WrEn))
+            almost_full_nxt = 1'b1;
+        else if(FifoCntr > AF_THRESHOLD) 
+            almost_full_nxt = 1'b1;
+        else if(FifoCntr <= AF_THRESHOLD) 
+            almost_full_nxt = 1'b0;
+    end
+end
+`XSRREG_XDMA(clk, ~rst, almost_full_ff, almost_full_nxt, 'h0)
+`XSRREG_XDMA(clk, ~rst, full_ff, full_nxt, 'h0)
+
+assign    Head_nxt =     (srst) ? 'h0 :
+            ((WrEn && (FifoCntr == 0)) || (WrEn && RdEn && (FifoCntr == 1))) ?  DataIn : 
+            (RdEn || (FifoCntr == 0)) ?  MemArray[RdPtr] :
+                Head;
+
+`XSRREG_XDMA(clk, ~rst, Head, Head_nxt, 'h0)
+assign DataOut = Head;
+
+endmodule
+*/
+`endif // AXI_BRIDGE_VH
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_defines.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_defines.svh
new file mode 100755
index 0000000..1199d24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_defines.svh
@@ -0,0 +1,387 @@
+`ifndef DMA_DEFINES_SVH
+`define DMA_DEFINES_SVH
+
+`include "dma_defines.vh"
+`include "pcie_dma_attr_defines.svh"
+
+// Interface Includes at bottom of file (use some structures defined in this file)
+
+`define IF_MI_CONVERSION_M \
+    always_comb begin \
+        ifc.wadr = wadr;\
+        ifc.wen  = wen;\
+        ifc.wpar = wpar;\
+        ifc.wdat = wdat;\
+        ifc.ren  = ren;\
+        ifc.radr = radr;\
+       rpar = ifc.rpar;\
+       rdat = ifc.rdat;\
+       rsbe = ifc.rsbe;\
+       rdbe = ifc.rdbe;\
+    end
+
+`define IF_MI_CONVERSION_S \
+    always_comb begin \
+        wadr = ifc.wadr;\
+        wen  = ifc.wen;\
+        wpar = ifc.wpar;\
+        wdat = ifc.wdat;\
+        ren  = ifc.ren;\
+        radr = ifc.radr;\
+        ifc.rpar = rpar;\
+        ifc.rdat = rdat;\
+        ifc.rsbe = rsbe;\
+        ifc.rdbe = rdbe;\
+    end
+
+typedef struct packed {
+   logic                  spl;
+    logic [`ADR_WIDTH-1:0] adr;
+    logic [`RID_WIDTH-1:0] rid;
+    logic [`LEN_WIDTH-1:0] byte_len;   // byte length
+    logic [`DID_WIDTH-1:0] did;
+        logic [7:0]            fnc;        // function
+} rrq_t;
+
+// Descriptor Sideband Info (Context RAM to DSC_CPLI_RAM)
+typedef struct packed {
+    logic                       wbi;     // Do writeback/interrupt on descriptor completion
+    logic                       wbi_chk; // Check status before writeback/interrupt
+    logic   [`QID_WIDTH-1:0]    qid;     // Q ID 
+    logic   [3:0]               qst;
+    logic   [7:0]               fnc;
+    logic   [15:0]              cidx;
+} dsc_sbi_t;  // 10 + 4 + 8 + 16 = 54
+
+typedef struct packed {
+    logic            sop;
+    logic            eop;
+    logic            wbk;
+    logic [4:0]      err;
+    logic [3:0]      errc;
+    //logic [`DAT_WIDTH/32-1:0] wen; // dword write enable
+    logic [`RID_WIDTH-1:0]    rid;
+    logic [`DID_WIDTH-1:0]    did;
+    logic [5:0]               lba;    // Last beat length adjustment (AXI ST C2H)
+    logic [`DAT_WIDTH/8-1:0]  par;
+    logic [`DAT_WIDTH-1:0]    dat;
+} rcp_t;
+
+typedef struct packed {
+   logic                   err;
+    logic [`ADR_WIDTH-1:0] adr;
+    logic [`RID_WIDTH-1:0] rid;
+    logic [`LEN_WIDTH-1:0] byte_len;   // byte length
+    logic [5:0]            aln;        // Source alignment
+    logic                  eop;
+    logic                  eod;
+    logic                  eor;
+} wrq_t;
+
+typedef struct packed {
+    logic    [`DAT_WIDTH/8-1:0]   par;
+    logic    [`DAT_WIDTH-1:0]     dat;
+} wpl_t;
+
+typedef struct packed {
+    logic    [`RID_WIDTH-1:0]  rid;
+    logic    [4:0]             err;
+} wcp_t;
+
+typedef struct packed {
+    logic [31:0]    dat;
+} wbrq_t;
+
+typedef struct packed {
+    logic [3:0]      be;    
+    logic            rd;
+    logic            wr;
+    logic [31:0]     dat;
+    logic [31:0]     adr;
+    logic [7:0]      func;
+} trq_t;
+
+typedef struct packed {
+    logic            vld;
+    logic [31:0]         dat;
+} tcp_t;
+
+typedef struct packed {
+    logic                     run;
+    logic                     c2h_wbk_ena;
+    logic                     noninc;
+    logic [`ADR_WIDTH-1:0]    cdc_wbk_adr;
+} creg_t;
+
+typedef struct packed {
+    logic    [63:0]        par;         // 136:73 Parity filled later
+    logic    [5:0]         seq1;        // 72:67  Sequence Num 1
+    logic    [5:0]         seq0;        // 66:61  Sequence Num 0
+    logic    [23:0]        tph;         // 60:45  TPH St Tag
+                                        // 44:43  TPH Ind Tag
+                                        // 42:39  TPH Type
+                                        // 38:37  TPH Present
+    logic                  disc;        // 36     Discontinue
+    logic    [3:0]         eop1_ptr;    // 35:32  EOP 1 Ptr
+    logic    [3:0]         eop0_ptr;    // 31:28  EOP 0 Ptr
+    logic                  eop1;        // 27     EOP 1
+    logic                  eop0;        // 26     EOP 0
+    logic    [1:0]         sop1_ptr;    // 25:24  SOP 1 Ptr
+    logic    [1:0]         sop0_ptr;    // 23:22  SOP 0 Ptr
+    logic                  sop1;        // 21     SOP 1
+    logic                  sop0;        // 20     SOP 0
+    logic    [3:0]         adr;         // 19:16  Address offset - Address aligned mode only
+    logic    [3:0]         lbe1;
+    logic    [3:0]         lbe0;
+    logic    [3:0]         fbe1;
+    logic    [3:0]         fbe0;
+} rq_usr_straddle_t;
+
+typedef struct packed {
+    logic    [76:0]        rsv;
+    logic    [31:0]        par;         // 59:28
+    logic    [3:0]        seq;        // 27:24
+    logic    [11:0]        tph;        // 23:12
+    logic            dis;        // 11
+    logic    [2:0]        adr;         // 10:8
+    logic    [3:0]         lbe;        // 7:4
+    logic    [3:0]         fbe;        // 3:0
+} rq_usr_nostraddle_t;
+
+typedef union packed {
+    rq_usr_straddle_t       rqu_str;
+    rq_usr_nostraddle_t      rqu_nstr;
+} rq_usr_t;
+
+typedef struct packed {
+    logic   [12:0]  pcie_mrrs;
+    logic   [12:0]  pcie_mps;
+    logic   [12:0]  axi_mrrs;
+    logic   [12:0]  axi_mps;
+} cfg_dma_t;
+
+typedef struct packed { 
+    logic            ecrc;
+    logic     [2:0]        attr;        
+    logic    [2:0]        tc;    
+    logic            rid_en;
+    logic    [15:0]        cpl_id;
+    logic    [7:0]        tag;
+    logic    [15:0]        req_id;
+    logic            poison;
+    logic    [3:0]        req;
+    logic    [10:0]        len;        
+    logic    [63:0]        adr;
+} rq_hdr_fields_t;
+
+typedef struct packed { 
+    logic    [23:0]        dw3_misc;
+    logic    [7:0]        tag;
+    logic    [16:0]        dw2_misc;
+    logic    [3:0]        req;
+    logic    [10:0]        len;        
+    logic    [63:0]        adr;
+} rq_hdr_compact_t;
+
+typedef struct packed { 
+    logic    [31:0]        dw3;
+    logic    [31:0]        dw2;
+    logic    [31:0]        dw1;
+    logic    [31:0]        dw0;
+} rq_hdr_dwords_t;
+
+typedef union packed {
+    rq_hdr_fields_t        rqh_f;
+    rq_hdr_compact_t      rqh_c;
+    rq_hdr_dwords_t      rqh_d;
+} rq_hdr_t;
+
+typedef struct packed { 
+    logic                    tlast;
+    logic    [`MULTQ_C2H_TUSER_WIDTH-1:0]    tuser;
+    logic    [`DAT_WIDTH/8-1:0]        tkeep;
+    logic    [`DAT_WIDTH/8-1:0]        tparity;
+    logic    [`DAT_WIDTH-1:0]        tdata;
+} dma_s_axis_t;
+
+typedef struct packed {
+    logic [`DID_WIDTH-1:0]            waddr;
+    logic [`DID_WIDTH-1:0]            raddr;
+    logic [`DAT_WIDTH/8-1:0]        wen;
+} dat_bram_cmd_t;
+
+typedef struct packed {
+    logic [`DAT_WIDTH-1:0]            dat;
+    logic [`DAT_WIDTH/8-1:0]        parity; // Even parity
+}dat_bram_dat_t;
+
+
+typedef struct packed {
+    
+    logic                    tlast;
+    logic    [`MULTQ_H2C_TUSER_WIDTH-1:0]    tuser;
+    logic    [`DAT_WIDTH/8-1:0]        tkeep;
+    logic    [`DAT_WIDTH/8-1:0]        tparity;
+    logic    [`DAT_WIDTH-1:0]        tdata;
+} dma_m_axis_t;
+
+
+// Descriptor Completion Memory Interface
+typedef struct packed {
+    logic    [`DAT_WIDTH-1:0]        rdat;
+    logic                    rbe;
+}dsc_cpl_bram_out_t;
+
+typedef struct packed {
+    logic                wen;
+    logic    [`DSC_DID_WIDTH-1:0]    waddr;
+    logic    [`DAT_WIDTH-1:0]        wdat;
+    logic    [`DSC_RID_WIDTH-1:0]    raddr;
+}dsc_cpl_bram_in_t;
+
+// XDMA Descriptor Memory Interface
+//typedef struct packed {    
+    //logic    [255:0]     rdat;
+    //logic                rbe;
+//}dsc_bram_out_t;      
+
+typedef struct packed {
+    logic                wen;
+    logic    [`DSC_DID_WIDTH-1:0]    waddr;
+    logic    [255:0]            wdat;
+    logic    [`DSC_RID_WIDTH-1:0]    raddr;
+}dsc_bram_in_t;
+
+
+//
+typedef struct packed {
+    logic    [7:0]            func;
+    //logic    [3:0]            be;
+} dma_axil_user_t;
+
+// Descriptor Completion
+typedef struct packed {
+    logic   [63:0]    wadr;
+    logic   [63:0]    radr;
+    logic   [27:0]    len;
+    logic             eop;
+    logic             cpl;
+    logic             stp;
+} dcp_t;
+
+// Descriptor In (user descriptors -> dma)
+typedef struct packed {
+    logic    [`QID_WIDTH-1:0] qid;    // Q ID 
+    logic    [1:0]            chn;    // Channel
+    logic    [3:0]            qst;    // Q status
+    logic    [2:0]            fmt;    // Format
+    logic    [255:0]          dsc;
+    logic    [3:0]            vld;
+} dma_dsc_in_t;
+
+// Descriptor In Credits (dma credits -> user)
+typedef struct packed {
+    logic                        vld;
+    logic    [8:0]               num;
+    logic    [`QID_WIDTH-1:0]    qid;
+} dma_dsc_in_crd_t;
+
+// Descriptor Out (dma descriptors -> user)
+typedef struct packed {
+    logic                       wbi;
+    logic                       wbi_chk;
+    logic    [15:0]             cidx;
+    logic    [`QID_WIDTH-1:0]   qid;    // Q ID
+    logic    [1:0]              chn;    // Channel
+    logic    [3:0]              qst;    // Q status
+    logic    [2:0]              siz;    // Format
+    logic                       dir;    // Direction
+    logic    [3:0]              vld;
+    logic    [255:0]            dsc;
+} dma_dsc_block_t;
+
+typedef struct packed {
+    logic                       wbi;
+    logic                       wbi_chk;
+    logic    [15:0]             cidx;
+    logic    [`QID_WIDTH-1:0]   qid;    // Q ID
+    logic    [1:0]              chn;    // Channel
+    logic    [3:0]              qst;    // Q status
+    logic    [2:0]              siz;    // Format
+    logic                       dir;    // Direction
+    logic    [255:0]            dsc;
+} dma_dsc_t;
+
+// Descriptor Out Credits (user credits -> dma)
+typedef struct packed {
+    logic                        vld;
+    logic    [8:0]               num;
+    logic    [`QID_WIDTH-1:0]    qid;
+    logic    [1:0]               chn;
+    logic                        clr;
+} dma_dsc_out_crd_t;
+
+
+// Interface Conversion
+
+`define PCIE_CC_TO_DMA_CC_IF(pcie_cc, dma_cc) \
+assign pcie_cc.axis_cc_tvalid =       dma_cc.tvalid; \
+assign pcie_cc.axis_cc_tdata  = 'h0 | dma_cc.tdata; \
+assign pcie_cc.axis_cc_tuser  = 'h0 | dma_cc.tuser; \
+assign pcie_cc.axis_cc_tkeep  = 'h0 | dma_cc.tkeep; \
+assign pcie_cc.axis_cc_tlast  =       dma_cc.tlast; \
+assign dma_cc.tready          = 'h0 | pcie_cc.axis_cc_tready; 
+
+`define PCIE_CQ_TO_DMA_CQ_IF(pcie_cq, dma_cq) \
+assign dma_cq.tvalid           =     | pcie_cq.axis_cq_tvalid; \
+assign dma_cq.tdata            = 'h0 | pcie_cq.axis_cq_tdata; \
+assign dma_cq.tuser            = 'h0 | pcie_cq.axis_cq_tuser; \
+assign dma_cq.tkeep            = 'h0 | pcie_cq.axis_cq_tkeep; \
+assign dma_cq.tlast            =     | pcie_cq.axis_cq_tlast; \
+assign pcie_cq.axis_cq_tready  = 'h0 | dma_cq.tready; 
+
+`define PCIE_RC_TO_DMA_RC_IF(pcie_rc, dma_rc) \
+assign dma_rc.tvalid           =     | pcie_rc.axis_rc_tvalid; \
+assign dma_rc.tdata            = 'h0 | pcie_rc.axis_rc_tdata; \
+assign dma_rc.tuser            = 'h0 | pcie_rc.axis_rc_tuser; \
+assign dma_rc.tkeep            = 'h0 | pcie_rc.axis_rc_tkeep; \
+assign dma_rc.tlast            =     | pcie_rc.axis_rc_tlast; \
+assign pcie_rc.axis_rc_tready  = 'h0 | dma_rc.tready; 
+
+`define PCIE_RQ_TO_DMA_RQ_IF(pcie_rq, dma_rq) \
+assign pcie_rq.axis_rq_tvalid =       dma_rq.tvalid; \
+assign pcie_rq.axis_rq_tdata  = 'h0 | dma_rq.tdata; \
+assign pcie_rq.axis_rq_tuser  = 'h0 | dma_rq.tuser; \
+assign pcie_rq.axis_rq_tkeep  = 'h0 | dma_rq.tkeep; \
+assign pcie_rq.axis_rq_tlast  =       dma_rq.tlast; \
+assign dma_rq.tready          = 'h0 | pcie_rq.axis_rq_tready; 
+
+`include "dma_pcie_axis_cc_if.svh"
+`include "dma_pcie_axis_cq_if.svh"
+`include "dma_pcie_axis_rc_if.svh"
+`include "dma_pcie_axis_rq_if.svh"
+//`include "dma_pcie_c2h_axis_if.svh"
+`include "dma_pcie_c2h_crdt_if.svh"
+`include "dma_pcie_dsc_in_if.svh"
+`include "dma_pcie_dsc_out_if.svh"
+`include "dma_pcie_fabric_input_if.svh"
+`include "dma_pcie_fabric_output_if.svh"
+`include "dma_pcie_gic_if.svh"
+//`include "dma_pcie_h2c_axis_if.svh"
+`include "dma_pcie_h2c_crdt_if.svh"
+`include "dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh"
+`include "dma_pcie_mi_2Bx2048_ram_if.svh"
+`include "dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx128_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx256_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx512_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh"
+`include "dma_pcie_mi_dsc_cpld_if.svh"
+`include "dma_pcie_mi_dsc_cpli_if.svh"
+`include "dma_pcie_misc_input_if.svh"
+`include "dma_pcie_misc_output_if.svh"
+`endif
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_defines.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_defines.vh
new file mode 100755
index 0000000..7323a0b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_defines.vh
@@ -0,0 +1,33 @@
+`ifndef DMA_DEFINES_VH
+`define DMA_DEFINES_VH
+
+`include "dma_soft_defines.vh"
+
+`define CPLI_WIDTH 80
+
+`define DAT_WIDTH 512
+`define ADR_WIDTH 64
+`define ALN_WIDTH 4	// Bits used for subbeat dword alignment 
+`define LEN_WIDTH 28
+`define RID_WIDTH 10 
+`define DID_WIDTH 10 
+`define QID_WIDTH 8	// Support for 128 H2C and 128 C2H queues
+`define DSC_RID_WIDTH 16
+`define DSC_DID_WIDTH 16
+
+`define H2C_TAR_ID 0
+`define C2H_TAR_ID 1
+`define IRQ_TAR_ID 2
+`define CFG_TAR_ID 3
+`define DSC_H2C_TAR_ID 4
+`define DSC_C2H_TAR_ID 5
+`define DSC_TAR_ID 6
+//`define MSIX_TAR_ID 8
+//`define PF1_MSIX_TAR_ID 9
+
+`define MSIX_PBA_OFFSET 12'hfe0
+
+`define MULTQ_C2H_TUSER_WIDTH   64
+`define MULTQ_H2C_TUSER_WIDTH   64 
+
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh
new file mode 100755
index 0000000..a1e6b25
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh
@@ -0,0 +1,35 @@
+`ifndef iF_AXIS_CC_PCIE_DMA_PORT_VS
+`define iF_AXIS_CC_PCIE_DMA_PORT_VS
+interface dma_pcie_axis_cc_if#(DATA_WIDTH = 512, USER_WIDTH = 81)();
+
+  wire [DATA_WIDTH-1:0]     tdata;
+  wire [USER_WIDTH-1:0]     tuser;
+  wire                      tlast;
+  wire [DATA_WIDTH/32-1:0]  tkeep;
+  wire                 tvalid;
+  wire                 tready;
+
+  modport s (
+    
+    input              tdata
+   ,input              tuser
+   ,input              tlast
+   ,input              tkeep
+   ,input              tvalid
+   ,output             tready
+
+  );
+
+  modport m (
+
+    output             tdata
+   ,output             tuser
+   ,output             tlast
+   ,output             tkeep
+   ,output             tvalid
+   ,input              tready
+
+  );
+  
+endinterface : dma_pcie_axis_cc_if
+`endif // iF_AXIS_CC_PCIE_PORT_VS
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh
new file mode 100755
index 0000000..f92954b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh
@@ -0,0 +1,35 @@
+`ifndef IF_AXIS_CQ_PCIE_DMA_PORT_SV
+`define IF_AXIS_CQ_PCIE_DMA_PORT_SV
+interface dma_pcie_axis_cq_if#(DATA_WIDTH = 512, USER_WIDTH = 183)();
+
+  wire [DATA_WIDTH-1:0]         tdata;
+  wire [USER_WIDTH-1:0]         tuser;
+  wire                          tlast;
+  wire [DATA_WIDTH/32-1:0]      tkeep;
+  wire                 tvalid;
+  wire [21:0]          tready;
+  
+  modport m (
+
+    output             tdata 
+   ,output             tuser 
+   ,output             tlast 
+   ,output             tkeep 
+   ,output             tvalid 
+   ,input              tready 
+  
+  );
+
+  modport s (
+
+    input              tdata 
+   ,input              tuser 
+   ,input              tlast 
+   ,input              tkeep 
+   ,input              tvalid 
+   ,output             tready 
+  
+  );
+
+endinterface : dma_pcie_axis_cq_if
+`endif // IF_AXIS_CQ_PCIE_DMA_PORT_SV
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh
new file mode 100755
index 0000000..20a2184
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh
@@ -0,0 +1,35 @@
+`ifndef IF_AXIS_RC_PCIE_DMA_PORT_VS
+`define IF_AXIS_RC_PCIE_DMA_PORT_VS
+interface dma_pcie_axis_rc_if#(DATA_WIDTH = 512, USER_WIDTH = 161)();
+
+  wire [DATA_WIDTH-1:0]         tdata;
+  wire                          tlast;
+  wire [USER_WIDTH-1:0]         tuser;
+  wire [DATA_WIDTH/32-1:0]      tkeep;
+  wire                          tvalid;
+  wire  [21:0]                  tready;
+
+  modport m (
+ 
+     output            tdata
+    ,output            tlast
+    ,output            tuser
+    ,output            tkeep
+    ,output            tvalid
+    ,input             tready
+
+  ); 
+
+  modport s (
+ 
+     input             tdata
+    ,input             tlast
+    ,input             tuser
+    ,input             tkeep
+    ,input             tvalid
+    ,output            tready
+
+  ); 
+
+endinterface : dma_pcie_axis_rc_if
+`endif // PCIE4_IF_AXIS_RC_PCIE_PORT
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh
new file mode 100755
index 0000000..bad7df2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh
@@ -0,0 +1,35 @@
+`ifndef IF_AXIS_RQ_PCIE_DMA_PORT_SV
+`define IF_AXIS_RQ_PCIE_DMA_PORT_SV
+interface dma_pcie_axis_rq_if#(DATA_WIDTH = 512, USER_WIDTH = 137)();
+
+  wire [DATA_WIDTH-1:0]    tdata;
+  wire                     tlast;
+  wire [USER_WIDTH-1:0]    tuser;
+  wire [DATA_WIDTH/32-1:0]   tkeep;
+  wire                 tvalid;
+  wire                 tready;
+
+  modport s (
+
+    input              tdata
+   ,input              tlast
+   ,input              tuser
+   ,input              tkeep
+   ,input              tvalid
+   ,output             tready
+
+  );
+
+  modport m (
+
+    output             tdata
+   ,output             tlast
+   ,output             tuser
+   ,output             tkeep
+   ,output             tvalid
+   ,input              tready
+
+  );
+
+endinterface : dma_pcie_axis_rq_if
+`endif // IF_AXIS_RQ_PCIE_DMA_PORT_SV
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh
new file mode 100755
index 0000000..17ae106
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh
@@ -0,0 +1,42 @@
+`ifndef IF_PCIE_DMA_C2H_CRDT_SV
+`define IF_PCIE_DMA_C2H_CRDT_SV
+interface dma_pcie_c2h_crdt_if #();
+    logic   [511:0]             tdata;
+    logic   [512/8-1:0]         tparity;
+    logic                       tlast;
+    logic   [512/8-1:0]         tkeep;
+    logic   [127:0]             tusr;
+    logic                       tvalid;
+    logic   [1:0]               tch;
+
+    logic                       crdt;
+    logic   [1:0]               crdt_ch;
+
+    modport m (
+        output                      tdata,
+        output                      tparity,
+        output                      tlast,
+        output                      tkeep,
+        output                      tusr,
+        output                      tvalid,
+        output                      tch,
+
+        input                       crdt,
+        input                       crdt_ch
+    );
+
+    modport s (
+        input                       tdata,
+        input                       tparity,
+        input                       tlast,
+        input                       tkeep,
+        input                       tusr,
+        input                       tvalid,
+        input                       tch,
+
+        output                      crdt,
+        output                      crdt_ch
+    );
+
+endinterface : dma_pcie_c2h_crdt_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh
new file mode 100755
index 0000000..edf83d7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh
@@ -0,0 +1,20 @@
+`ifndef IF_PCIE_DMA_DSC_IN_SV
+`define IF_PCIE_DMA_DSC_IN_SV
+`include "dma_defines.svh"
+
+interface dma_pcie_dsc_in_if();
+    dma_dsc_in_crd_t      crd;
+    dma_dsc_block_t       dsc;
+
+modport snk (
+input  dsc,
+output  crd
+);
+
+modport src (
+input dsc,
+output crd
+);
+
+endinterface : dma_pcie_dsc_in_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh
new file mode 100755
index 0000000..858c743
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh
@@ -0,0 +1,28 @@
+`ifndef DMA_PCIE_DSC_OUT_IF_SV
+`define DMA_PCIE_DSC_OUT_IF_SV
+`include "dma_defines.svh"
+
+interface dma_pcie_dsc_out_if();
+    dma_dsc_out_crd_t      crd;
+    dma_dsc_block_t        dsc;
+
+modport snk (
+    output       crd,
+    input        dsc
+);
+
+modport src (
+    input       crd,
+    output      dsc
+);
+
+modport outputs (
+    output       dsc
+);
+
+modport inputs (
+    input        crd
+);
+
+endinterface : dma_pcie_dsc_out_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_input_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_input_if.svh
new file mode 100755
index 0000000..099083d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_input_if.svh
@@ -0,0 +1,29 @@
+`ifndef IF_PCIE_DMA_FABRIC_INPUT_SV
+`define IF_PCIE_DMA_FABRIC_INPUT_SV
+interface dma_pcie_fabric_input_if();
+logic               usr_irq_clr;
+logic               usr_irq_set;
+logic   [4:0]       usr_irq_vec;
+logic   [7:0]       usr_irq_fnc;
+logic               flr_done_vld;
+logic   [7:0]       flr_done_fnc;
+
+modport s (
+input       usr_irq_clr,
+input       usr_irq_set,
+input       usr_irq_vec,
+input       usr_irq_fnc,
+input       flr_done_vld,
+input       flr_done_fnc
+);
+
+modport m (
+output       usr_irq_clr,
+output       usr_irq_set,
+output       usr_irq_vec,
+output       usr_irq_fnc,
+output       flr_done_vld,
+output       flr_done_fnc
+);
+endinterface : dma_pcie_fabric_input_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_output_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_output_if.svh
new file mode 100755
index 0000000..20c1727
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_output_if.svh
@@ -0,0 +1,64 @@
+`ifndef IF_PCIE_DMA_FABRIC_OUTPUT_SV
+`define IF_PCIE_DMA_FABRIC_OUTPUT_SV
+interface dma_pcie_fabric_output_if();
+logic            c2h_dsc_avail_inc_vld;
+logic  [1:0]     c2h_dsc_avail_inc_chn;
+logic  [7:0]     c2h_dsc_avail_inc_qid;
+logic  [1:0]     c2h_dsc_avail_inc_state;
+logic  [15:0]    c2h_dsc_avail_inc_num;
+logic            s_axis_c2h_tstat_vld;
+logic  [1:0]     s_axis_c2h_tstat_chn;
+logic  [4:0]     s_axis_c2h_tstat_qid;
+logic  [7:0]     s_axis_c2h_tstat;
+logic  [3:0][7:0]    c2h_sts;
+logic  [3:0][7:0]    h2c_sts;
+logic            flr_set;
+logic            flr_clr;
+logic  [7:0]     flr_fnc;
+logic  [4:0]     usr_irq_rvec;
+logic  [7:0]     usr_irq_rfnc;
+logic            usr_irq_fail;
+logic            usr_irq_sent;
+
+modport m (
+output  c2h_dsc_avail_inc_vld,
+output  c2h_dsc_avail_inc_chn,
+output  c2h_dsc_avail_inc_qid,
+output  c2h_dsc_avail_inc_state,
+output  c2h_dsc_avail_inc_num,
+output  s_axis_c2h_tstat_vld,
+output  s_axis_c2h_tstat_chn,
+output  s_axis_c2h_tstat_qid,
+output  s_axis_c2h_tstat,
+output  c2h_sts,
+output  h2c_sts,
+output  flr_set,
+output  flr_clr,
+output  flr_fnc,
+output  usr_irq_rvec,
+output  usr_irq_rfnc,
+output  usr_irq_fail,
+output  usr_irq_sent
+);
+modport s (
+input  c2h_dsc_avail_inc_vld,
+input  c2h_dsc_avail_inc_chn,
+input  c2h_dsc_avail_inc_qid,
+input  c2h_dsc_avail_inc_state,
+input  c2h_dsc_avail_inc_num,
+input  s_axis_c2h_tstat_vld,
+input  s_axis_c2h_tstat_chn,
+input  s_axis_c2h_tstat_qid,
+input  s_axis_c2h_tstat,
+input  c2h_sts,
+input  h2c_sts,
+input  flr_set,
+input  flr_clr,
+input  flr_fnc,
+input  usr_irq_rvec,
+input  usr_irq_rfnc,
+input  usr_irq_fail,
+input  usr_irq_sent
+);
+endinterface : dma_pcie_fabric_output_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_gic_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_gic_if.svh
new file mode 100755
index 0000000..0b425ef
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_gic_if.svh
@@ -0,0 +1,13 @@
+`ifndef IF_PCIE_DMA_GIC_SV
+`define IF_PCIE_DMA_GIC_SV
+interface dma_pcie_gic_if();
+    logic [6:0] interrupt;
+modport m (
+    output interrupt
+);
+modport s (
+    input interrupt
+);
+
+endinterface : dma_pcie_gic_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh
new file mode 100755
index 0000000..602c637
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh
@@ -0,0 +1,42 @@
+`ifndef IF_PCIE_DMA_H2C_CRDT_SV
+`define IF_PCIE_DMA_H2C_CRDT_SV
+interface dma_pcie_h2c_crdt_if #();
+    logic   [511:0]             tdata;
+    logic   [512/8-1:0]         tparity;
+    logic                       tlast;
+    logic   [512/8-1:0]         tkeep;
+    logic   [63:0]              tusr;
+    logic                       tvalid;
+    logic   [1:0]               tch;
+
+    logic                       crdt;
+    logic   [1:0]               crdt_ch;
+
+    modport m (
+        output                      tdata,
+        output                      tparity,
+        output                      tlast,
+        output                      tkeep,
+        output                      tusr,
+        output                      tvalid,
+        output                      tch,
+
+        input                       crdt,
+        input                       crdt_ch
+    );
+
+    modport s (
+        input                       tdata,
+        input                       tparity,
+        input                       tlast,
+        input                       tkeep,
+        input                       tusr,
+        input                       tvalid,
+        input                       tch,
+
+        output                      crdt,
+        output                      crdt_ch
+    );
+
+endinterface : dma_pcie_h2c_crdt_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh
new file mode 100755
index 0000000..7b7a560
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh
@@ -0,0 +1,43 @@
+`ifndef DMA_PCIE_MI_16BX2048_4BWE_RAM_IF_SV
+`define DMA_PCIE_MI_16BX2048_4BWE_RAM_IF_SV
+
+
+interface dma_pcie_mi_16Bx2048_4Bwe_ram_if();
+        logic   [11:0]  wadr; // 1024 H2C Qs, 1024 C2H Qs
+        logic    [3:0]  wen;
+        logic   [7:0]   wpar;
+        logic   [127:0]  wdat;  // 15:8 func, 3:0 = sts, 63:32 = produce index, 127:64 = base address
+        logic           ren;
+        logic   [11:0]   radr;
+        logic   [7:0]   rpar;
+        logic   [127:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh
new file mode 100755
index 0000000..44b2c5b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh
@@ -0,0 +1,40 @@
+`ifndef DMA_PCIE_MI_2BX2048_RAM_IF_SV
+`define DMA_PCIE_MI_2BX2048_RAM_IF_SV
+interface dma_pcie_mi_2Bx2048_ram_if();
+        logic   [11:0]  wadr;
+        logic           wen;
+        logic   [1:0]   wpar;
+        logic   [15:0]  wdat;
+        logic           ren;
+        logic   [11:0]  radr;
+        logic   [1:0]   rpar;
+        logic   [15:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh
new file mode 100755
index 0000000..8427aeb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh
@@ -0,0 +1,41 @@
+`ifndef DMA_PCIE_MI_4BX2048_4BWE_RAM_IF_SV
+`define DMA_PCIE_MI_4BX2048_4BWE_RAM_IF_SV
+
+interface dma_pcie_mi_4Bx2048_4Bwe_ram_if();
+        logic   [11:0]  wadr;
+        logic           wen;
+        logic   [7:0]   wpar;
+        logic   [31:0]  wdat;   // 31:16 = used credits.  15:0= consumer index
+        logic           ren;
+        logic   [11:0]  radr;
+        logic   [7:0]   rpar;
+        logic   [31:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh
new file mode 100755
index 0000000..c9eafff
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh
@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX1024_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX1024_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx1024_32Bwe_ram_if();
+                logic   [9:0]       wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [9:0]       radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh
new file mode 100755
index 0000000..3ad52dc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh
@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX128_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX128_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx128_32Bwe_ram_if();
+                logic   [6:0]       wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [6:0]       radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh
new file mode 100755
index 0000000..de18739
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh
@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX2048_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX2048_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx2048_32Bwe_ram_if();
+                logic   [10:0]      wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [10:0]      radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh
new file mode 100755
index 0000000..b947ffd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh
@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX256_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX256_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx256_32Bwe_ram_if();
+                logic   [8:0]       wadr;  // FIXME hack should be 8 bits
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [8:0]       radr;  // FIXME hack should be 8 bits
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh
new file mode 100755
index 0000000..69b39a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh
@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX512_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX512_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx512_32Bwe_ram_if();
+                logic   [8:0]       wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [8:0]       radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh
new file mode 100755
index 0000000..f1ecfdf
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh
@@ -0,0 +1,41 @@
+`ifndef DMA_PCIE_MI_8BX2048_4BWE_RAM_IF_SV
+`define DMA_PCIE_MI_8BX2048_4BWE_RAM_IF_SV
+
+interface dma_pcie_mi_8Bx2048_4Bwe_ram_if();
+        logic   [11:0]  wadr; // 1024 H2C Qs, 1024 C2H Qs
+        logic    [1:0]  wen;
+        logic   [7:0]   wpar;
+        logic   [63:0]  wdat;  // 63:0 writeback base address
+        logic           ren;
+        logic   [11:0]   radr;
+        logic   [7:0]   rpar;
+        logic   [127:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh
new file mode 100755
index 0000000..970ab49
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh
@@ -0,0 +1,71 @@
+`ifndef DMA_PCIE_MI_DSC_CPLD_IF_SV
+`define DMA_PCIE_MI_DSC_CPLD_IF_SV
+interface dma_pcie_mi_dsc_cpld_if();
+        logic   [9:0]   wadr; // 10 bits for MULTQ C2H
+        logic   [7:0]   wen;
+        logic   [63:0]  wpar;
+        logic   [511:0] wdat;
+        logic           ren;
+        logic   [9:0]   radr; // 10 bits for MULTQ C2H
+        logic   [63:0]  rpar;
+        logic   [511:0] rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+        modport s_outputs (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr
+        );
+
+        modport m_outputs (
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+
+        modport s_inputs (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr
+        );
+
+        modport m_inputs (
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+        );
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh
new file mode 100755
index 0000000..4a9cd1c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh
@@ -0,0 +1,41 @@
+`ifndef DMA_PCIE_MI_DSC_CPLI_IF_SV
+`define DMA_PCIE_MI_DSC_CPLI_IF_SV
+`include "dma_defines.vh"
+interface dma_pcie_mi_dsc_cpli_if();
+        logic   [9:0]   wadr;  // 10 bits for MULTQ C2H
+        logic   [7:0]   wen;
+        logic   [3:0]  wpar;
+        logic   [`CPLI_WIDTH-1:0] wdat;
+        logic           ren;
+        logic   [9:0]   radr;  // 10 bits for MULTQ C2H
+        logic   [3:0]  rpar;
+        logic   [`CPLI_WIDTH-1:0] rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_input_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_input_if.svh
new file mode 100755
index 0000000..edd0354
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_input_if.svh
@@ -0,0 +1,157 @@
+`ifndef IF_PCIE_DMA_MISC_INPUT_SV
+`define IF_PCIE_DMA_MISC_INPUT_SV
+
+interface dma_pcie_misc_input_if();
+logic          cfg_interrupt_msi_mask_update;
+logic          cfg_err_cor_out;
+logic          cfg_err_fatal_out;
+logic          cfg_err_nonfatal_out;
+logic          cfg_ext_read_received;
+logic          cfg_ext_write_received;
+logic          cfg_hot_reset_out;
+logic          cfg_interrupt_msi_enable;
+logic          cfg_interrupt_msi_fail;
+logic          cfg_interrupt_msi_sent;
+logic          cfg_interrupt_msix_fail;
+logic          cfg_interrupt_msix_sent;
+logic          cfg_interrupt_sent;
+logic          cfg_local_error;
+logic          cfg_mgmt_read_write_done;
+logic          cfg_msg_received;
+logic          cfg_msg_transmit_done;
+logic          cfg_per_function_update_done;
+logic          cfg_phy_link_down;
+logic          pcie_rq_seq_num_vld0;
+logic          pcie_rq_seq_num_vld1;
+logic   [15:0] cfg_function_status;
+logic   [15:0] cfg_per_func_status_data;
+logic   [3:0]  cfg_interrupt_msix_enable;
+logic   [3:0]  cfg_interrupt_msix_mask;
+logic   [1:0]  cfg_phy_link_status;
+logic   [251:0]cfg_vf_flr_in_process;
+logic   [2:0]  cfg_current_speed;
+logic   [2:0]  cfg_max_payload;
+logic   [2:0]  cfg_max_read_req;
+logic   [31:0] cfg_ext_write_data;
+logic   [31:0] cfg_mgmt_read_data;
+logic   [3:0]  cfg_ext_write_byte_enable;
+logic   [3:0]  cfg_flr_in_process;
+logic   [3:0]  cfg_negotiated_width;
+logic   [5:0]  pcie_cq_np_req_count;
+logic   [3:0]  pcie_rq_seq_num0;
+logic   [3:0]  pcie_rq_seq_num1;
+logic   [3:0]  pcie_tfc_nph_av;
+logic   [4:0]  cfg_msg_received_type;
+logic   [5:0]  cfg_interrupt_msix_vf_enable;
+logic   [5:0]  cfg_interrupt_msix_vf_mask;
+logic   [5:0]  cfg_ltssm_state;
+logic          cfg_pl_status_change;
+logic   [7:0]  cfg_ext_function_number;
+logic   [7:0]  cfg_msg_received_data;
+logic   [7:0]  cfg_fc_nph;
+logic   [9:0]  cfg_ext_register_number;
+
+modport s (
+input   cfg_interrupt_msi_mask_update,
+input   cfg_err_cor_out,
+input   cfg_err_fatal_out,
+input   cfg_err_nonfatal_out,
+input   cfg_ext_read_received,
+input   cfg_ext_write_received,
+input   cfg_hot_reset_out,
+input   cfg_interrupt_msi_enable,
+input   cfg_interrupt_msi_fail,
+input   cfg_interrupt_msi_sent,
+input   cfg_interrupt_msix_fail,
+input   cfg_interrupt_msix_sent,
+input   cfg_interrupt_sent,
+input   cfg_local_error,
+input   cfg_mgmt_read_write_done,
+input   cfg_msg_received,
+input   cfg_msg_transmit_done,
+input   cfg_per_function_update_done,
+input   cfg_phy_link_down,
+input   pcie_cq_np_req_count,
+input   pcie_rq_seq_num_vld0,
+input   pcie_rq_seq_num_vld1,
+input   cfg_function_status,
+input   cfg_per_func_status_data,
+input   cfg_interrupt_msix_enable,
+input   cfg_interrupt_msix_mask,
+input   cfg_phy_link_status,
+input   cfg_vf_flr_in_process,
+input   cfg_current_speed,
+input   cfg_max_payload,
+input   cfg_max_read_req,
+input   cfg_ext_write_data,
+input   cfg_mgmt_read_data,
+input   cfg_ext_write_byte_enable,
+input   cfg_flr_in_process,
+input   cfg_negotiated_width,
+input   pcie_rq_seq_num0,
+input   pcie_rq_seq_num1,
+input   pcie_tfc_nph_av,
+input   cfg_msg_received_type,
+input   cfg_interrupt_msix_vf_enable,
+input   cfg_interrupt_msix_vf_mask,
+input   cfg_ltssm_state,
+input   cfg_pl_status_change,
+input   cfg_ext_function_number,
+input   cfg_msg_received_data,
+input   cfg_fc_nph,
+input   cfg_ext_register_number
+);
+
+modport m (
+output   cfg_interrupt_msi_mask_update,
+output   cfg_err_cor_out,
+output   cfg_err_fatal_out,
+output   cfg_err_nonfatal_out,
+output   cfg_ext_read_received,
+output   cfg_ext_write_received,
+output   cfg_hot_reset_out,
+output   cfg_interrupt_msi_enable,
+output   cfg_interrupt_msi_fail,
+output   cfg_interrupt_msi_sent,
+output   cfg_interrupt_msix_fail,
+output   cfg_interrupt_msix_sent,
+output   cfg_interrupt_sent,
+output   cfg_local_error,
+output   cfg_mgmt_read_write_done,
+output   cfg_msg_received,
+output   cfg_msg_transmit_done,
+output   cfg_per_function_update_done,
+output   cfg_phy_link_down,
+output   pcie_cq_np_req_count,
+output   pcie_rq_seq_num_vld0,
+output   pcie_rq_seq_num_vld1,
+output   cfg_function_status,
+output   cfg_per_func_status_data,
+output   cfg_interrupt_msix_enable,
+output   cfg_interrupt_msix_mask,
+output   cfg_phy_link_status,
+output   cfg_vf_flr_in_process,
+output   cfg_current_speed,
+output   cfg_max_payload,
+output   cfg_max_read_req,
+output   cfg_ext_write_data,
+output   cfg_mgmt_read_data,
+output   cfg_ext_write_byte_enable,
+output   cfg_flr_in_process,
+output   cfg_negotiated_width,
+output   pcie_rq_seq_num0,
+output   pcie_rq_seq_num1,
+output   pcie_tfc_nph_av,
+output   cfg_msg_received_type,
+output   cfg_interrupt_msix_vf_enable,
+output   cfg_interrupt_msix_vf_mask,
+output   cfg_ltssm_state,
+output   cfg_pl_status_change,
+output   cfg_ext_function_number,
+output   cfg_msg_received_data,
+output   cfg_fc_nph,
+output   cfg_ext_register_number
+);
+endinterface : dma_pcie_misc_input_if
+
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_output_if.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_output_if.svh
new file mode 100755
index 0000000..4ed65b9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_output_if.svh
@@ -0,0 +1,158 @@
+`ifndef IF_PCIE_DMA_MISC_OUTPUT_SV
+`define IF_PCIE_DMA_MISC_OUTPUT_SV
+
+interface dma_pcie_misc_output_if();
+logic  [2:0]       cfg_fc_sel;
+logic  [1:0]       pcie_cq_np_req;
+logic  [18:0]      cfg_mgmt_addr;
+logic              cfg_mgmt_write;
+logic  [31:0]      cfg_mgmt_write_data;
+logic  [3:0]       cfg_mgmt_byte_enable;
+logic              cfg_mgmt_read;
+logic  [7:0]       cfg_mgmt_function_number;
+logic              cfg_mgmt_type1_cfg_reg_access;
+logic  [7:0]       cfg_ds_port_number;
+logic  [7:0]       cfg_ds_bus_number;
+logic  [4:0]       cfg_ds_device_number;
+logic  [2:0]       cfg_ds_function_number;
+logic  [2:0]       cfg_per_func_status_control;
+logic  [6:0]       cfg_per_function_number;
+logic              cfg_per_function_output_request;
+logic              cfg_per_function_logic_request;
+logic              cfg_msg_transmit;
+logic  [2:0]       cfg_msg_transmit_type;
+logic  [31:0]      cfg_msg_transmit_data;
+//logic  [15:0]      cfg_subsys_id;
+//logic  [15:0]      cfg_subsys_vend_id;
+//logic  [15:0]      cfg_vend_id;
+logic  [63:0]      cfg_dsn;
+logic              cfg_err_cor_in;
+logic              cfg_err_uncor_in;
+logic              cfg_link_training_enable;
+logic  [31:0]      cfg_ext_read_data;
+logic              cfg_ext_read_data_valid;
+logic  [3:0]       cfg_flr_done;
+logic              cfg_vf_flr_done;
+logic  [7:0]       cfg_vf_flr_func_num;
+logic              cfg_config_space_enable;
+logic              cfg_hot_reset_in;
+logic  [31:0]      cfg_interrupt_msi_int;
+logic  [31:0]      cfg_interrupt_msi_pending_status;
+logic              cfg_interrupt_msi_pending_status_data_enable;
+logic  [3:0]       cfg_interrupt_msi_pending_status_function_num;
+logic  [2:0]       cfg_interrupt_msi_attr;
+logic              cfg_interrupt_msi_tph_present;
+logic  [1:0]       cfg_interrupt_msi_tph_type;
+logic  [8:0]       cfg_interrupt_msi_tph_st_tag;
+logic  [3:0]       cfg_interrupt_msi_function_number;
+logic              cfg_interrupt_msix_int;
+logic  [31:0]      cfg_interrupt_msix_data;
+logic  [255:0]     cfg_interrupt_msix_address;
+logic  [3:0]       cfg_interrupt_int;
+logic  [3:0]       cfg_interrupt_pending;
+
+modport m (
+output      cfg_fc_sel,
+output      pcie_cq_np_req,
+output      cfg_mgmt_addr,
+output      cfg_mgmt_write,
+output      cfg_mgmt_write_data,
+output      cfg_mgmt_byte_enable,
+output      cfg_mgmt_read,
+output      cfg_mgmt_function_number,
+output      cfg_mgmt_type1_cfg_reg_access,
+output      cfg_ds_port_number,
+output      cfg_ds_bus_number,
+output      cfg_ds_device_number,
+output      cfg_ds_function_number,
+output      cfg_per_function_output_request,
+output      cfg_per_function_logic_request,
+output      cfg_per_func_status_control,
+output      cfg_per_function_number,
+output      cfg_msg_transmit,
+output      cfg_msg_transmit_type,
+output      cfg_msg_transmit_data,
+//output      cfg_rev_id,
+//output      cfg_subsys_id,
+//output      cfg_subsys_vend_id,
+//output      cfg_vend_id,
+output      cfg_dsn,
+output      cfg_err_cor_in,
+output      cfg_err_uncor_in,
+output      cfg_link_training_enable,
+output      cfg_ext_read_data,
+output      cfg_ext_read_data_valid,
+output      cfg_flr_done,
+output      cfg_vf_flr_done,
+output      cfg_vf_flr_func_num,
+output      cfg_config_space_enable,
+output      cfg_hot_reset_in,
+output      cfg_interrupt_msi_int,
+output      cfg_interrupt_msi_pending_status,
+output      cfg_interrupt_msi_pending_status_data_enable,
+output      cfg_interrupt_msi_pending_status_function_num,
+output      cfg_interrupt_msi_attr,
+output      cfg_interrupt_msi_tph_present,
+output      cfg_interrupt_msi_tph_type,
+output      cfg_interrupt_msi_tph_st_tag,
+output      cfg_interrupt_msi_function_number,
+output      cfg_interrupt_msix_int,
+output      cfg_interrupt_msix_data,
+output      cfg_interrupt_msix_address,
+output      cfg_interrupt_int,
+output      cfg_interrupt_pending
+);
+
+modport s (
+input      cfg_fc_sel,
+input      pcie_cq_np_req,
+input      cfg_mgmt_addr,
+input      cfg_mgmt_write,
+input      cfg_mgmt_write_data,
+input      cfg_mgmt_byte_enable,
+input      cfg_mgmt_read,
+input      cfg_mgmt_function_number,
+input      cfg_mgmt_type1_cfg_reg_access,
+input      cfg_ds_port_number,
+input      cfg_ds_bus_number,
+input      cfg_ds_device_number,
+input      cfg_ds_function_number,
+input      cfg_per_func_status_control,
+input      cfg_per_function_number,
+input      cfg_per_function_output_request,
+input      cfg_per_function_logic_request,
+input      cfg_msg_transmit,
+input      cfg_msg_transmit_type,
+input      cfg_msg_transmit_data,
+//input      cfg_rev_id,
+//input      cfg_subsys_id,
+//input      cfg_subsys_vend_id,
+//input      cfg_vend_id,
+input      cfg_dsn,
+input      cfg_err_cor_in,
+input      cfg_err_uncor_in,
+input      cfg_link_training_enable,
+input      cfg_ext_read_data,
+input      cfg_ext_read_data_valid,
+input      cfg_flr_done,
+input      cfg_vf_flr_done,
+input      cfg_vf_flr_func_num,
+input      cfg_config_space_enable,
+input      cfg_hot_reset_in,
+input      cfg_interrupt_msi_int,
+input      cfg_interrupt_msi_pending_status,
+input      cfg_interrupt_msi_pending_status_data_enable,
+input      cfg_interrupt_msi_pending_status_function_num,
+input      cfg_interrupt_msi_attr,
+input      cfg_interrupt_msi_tph_present,
+input      cfg_interrupt_msi_tph_type,
+input      cfg_interrupt_msi_tph_st_tag,
+input      cfg_interrupt_msi_function_number,
+input      cfg_interrupt_msix_int,
+input      cfg_interrupt_msix_data,
+input      cfg_interrupt_msix_address,
+input      cfg_interrupt_int,
+input      cfg_interrupt_pending
+);
+endinterface : dma_pcie_misc_output_if
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_soft_defines.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_soft_defines.vh
new file mode 100755
index 0000000..d91f492
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/dma_soft_defines.vh
@@ -0,0 +1,6 @@
+`ifndef DMA_SOFT_DEFINES_VH
+`define DMA_SOFT_DEFINES_VH
+
+`define SOFT_IP
+
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/pcie_dma_attr_defines.svh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/pcie_dma_attr_defines.svh
new file mode 100755
index 0000000..59df942
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/pcie_dma_attr_defines.svh
@@ -0,0 +1,162 @@
+`ifndef PCIE_DMA_ATTR_DEFINES_VH
+`define PCIE_DMA_ATTR_DEFINES_VH
+
+typedef struct packed {
+    logic  [255:213] unused;                       //255:213
+    logic           dis_pfch_evict_cache_fix;      //212      // If set, disable the prefetch eviction fix in cache
+    logic           dis_pfch_evict_lru_fix;        //211      // If set, disable the prefetch eviction fix in lru
+    logic           dis_crdt_coal_depth_fix;       //210      // If set, disable the credit coal fifo depth fix
+    logic           dis_timer_stall_fix;           //209      // If set, disable the mdma timer stall fix
+    logic  [3:0]    qinv_cnt_limit;                //208:205  // If qinv_limit_en is set, this is the limit of qinv from dsc engine through c2h st pfch_evt_fifo that is allowed.
+    logic           qinv_limit_en;                 //204      // If set, limit the number of qinvalidation in the pipe from dsc engine through C2H ST pfch_evt_fifo
+    logic           qinv_arb_stall;                //203      // If set, allow descriptor fetching to continue even if tm_dsc_sts is full.
+    logic           brdg_rro_en;                   //202      // If set, enable relaxed ordering for all bridge slave reads to pcie.
+    logic           mm_wbrq_ovf_fix_dis;           //201      // If set, disable fix to prevent qdma writeback fifo overflow in the MM engine.
+    logic           pcie_mrs_reg_en;               //200      // If set, pcie max read size used will be defined by register
+    logic           pcie_mpl_reg_en;               //199      // If set, pcie max payload used will be define by register
+    logic           bdg_mst_rw_rlx_dis;            //198      // If set, disable the fix to bypass r/w ordering based on attr[1]
+    logic           dis_wrb_prty_chk_fix;          //197      // If set, disable the fix to check WRB parity C2H WRB
+    logic           dis_h2c_sbe_dbe_err_fix;       //196      // If set, disable the fix to handle sbe/dbe on h2c-st
+    logic           dis_wrb_bad_cidx_chk_fix;      //195      // If set, disable the fix to check bad cidx update in C2H WRB
+    logic           dis_xdma_wcp_err_bsy_clr;      //194      // If set, disable fix to clear busy bit in event of wcp error.  Needed for surprise xdma  FLR.
+    logic           dis_acc_irq;                   //193      // If set, disable MM/H2C ST periodic interrupts in wb_acc mode
+    logic           dis_h2c_wrb_on_src_err_fix;    //192      // If set, disable the fix to send wrb on h2c src err
+    logic           sw_crdt_fix_dis;               //191      // If set, disable the sw_crdt fix in c2h_pfch_crdt
+    logic           fix_dbe_parity_dis;            //190      // If set, disable fix for EDT-985612, generate invalid parity on dbe at write interfaces
+    logic           pcie_rq_vf_flr_check_dis;      //189      // If set, flr for vfs will be assumed to be false in dma_pcie_req
+    logic           pcie_rq_pf_flr_check_dis;      //188      // If set, flr for pfs will be assumed to be false in dma_pcie_req
+    logic           mm_err_wbk_fix_dis;            //187      // If set, disable the fix for the write completion from the DMA Write Engine
+    logic           dis_c2h_ctxt_mgr_fix;          //186      // If set, disable the C2H fix for ctxt mgr, affects both wrb and pfch
+    logic           full_upd_fix_dis;              //185      // If set, disable the full_upd feature in the C2H-ST WRB
+    logic           slv_bresp_fix_dis;             //184      // If set, disable the fix for Slave Bresp (1: slv_wrq_commit; 0: slave_wcp_vld)
+    logic           wr_cmp_fix_dis;                //183      // If set, disable the fix for the write completion from the DMA Write Engine
+    logic           rcv_crd_chk_dis;               //182      // If set, disable dsc engine received credit check
+    logic           cfg_space_delay_en;            //181      // If set, enable Bridge register to control config space enable in the EP mode
+    logic  [31:0]   misc_cap;                      //180:149  // Misc capability registers, register accessible
+    logic           st_rx_msg_if_en;               //148      // If set, send vdm to the streaming i/f
+    logic           exp_rom_bar_to_axil;           //147      // If set, send hits to bar 6 (exp rom) to axi-lite
+    logic           pcie_rq_vf_bme_check_dis;      //146      // If set, bme for vfs will be assumed to be true.
+    logic           dsc_upd_ovf_dis;               //145      // If set, disable descriptor overflow detection.
+    logic           tm_dsc_sts_pidx_en;            //144      // If set, send out pidx instead of new descriptors available.
+    logic           dsc_ctxt_is_mm_en;             //143      // If set, the interface (st or mm) is determined by sw_ctxt.sts.is_mm instead of dsc_sz.
+    logic           trq_timeout_dat;               //142      // If set, return all 1 for tcp timeout data, else all 0
+    logic           trq_timeout_rsp;               //141      // If set, return all slv_err for tcp timeout response, else okay
+    logic           dsc_ctxt_err_on_rcp_ur_ca_dis; //140      // If set, the context error bit will not be set if a dsc fetch receives an ur_ca error including bme check failure
+    logic           cfg_mgmt_ep_wr_dis;            //139      // 1'b1: Disable CFG MGMT Write in EP and back to legacy; 1'b0: Enable
+    logic           axi_slv_brdge_range;           //138      // 1'b1: 16M, 1'b0: 256M 
+    logic           dsc_ctxt_err_on_rcp_flr_dis;   //137      // If set, the context error bit will be set if a dsc fetch receives an flr abort
+    logic           dma_rq_0len_dis;               //136      // If set, disble 0 length read support.
+    logic           ign_byp_irq_arm;               //135      // If set, in bypass mode ignore the irq arm bit
+    logic           dma_mm_linkdown_reset_dis;     //134      // If set, do not reset mm engine rrq, wrq fifos
+    logic           rsv_use_h2c_data_aln;          //133      // Reserved. Was: If set, H2C data to AXIS will be aligned and packed
+    logic           dma_rst_rc_rdy;                //132      // If set, assert rc_tready when dma in under reset.
+    logic           ign_pidx_upd_on_irq_arm;       //131      // If irq_arm bit is set by trq write, do not update the pidx
+    logic           use_stm_dsc_format;            //130      // Makes QDMA work on STM descriptor format
+    logic           dma_aximm_rsp_clr;             //129      // Clear aximm rsp count for channel when run bit is asserted.
+    logic           dsc_qinv_on_err_dis;           //128      // Invalidate queue on error disable
+    logic           xdma_drain_dat_en;             //127      // Enable draining of dat when run bit is not set for xdma.  Set to 1 for Evereset
+    logic           xdma_drain_dsc_en;             //126      // Enable draining of dsc when run bit is not set for xdma.  Set to 1 for Evereset
+    logic           disable_port_id_check;         //125      // Disable the port_id check
+    logic           wb_sts_all;                    //124      // All writeback check results from dsc engine are output to wb sts port
+    logic  [11:0]   brdg_slv_wr_pasid_offset;      //123:112  // Pasid index offset for bridge slave write requests if shared_rdwr_pasid_dis is set
+    logic           brdg_slv_shared_rdwr_pasid_dis;//111      // Enable different pasid for rd and writes from bridge slave.
+    logic           dsc_stall_irq_fl_dis ;//110               // Disable stall descriptor context if dsc engine has too many irqs to send.
+    logic           axi_parity_chk_dis   ;//109               // Disable AXI slave parity checks
+    logic  [7:0]    slv_fnc_msk          ;//108:101           // Mask for function bits received by aximm slave. Useful if number of functions supported needs less than 8 bits.  Upper bits can then be used for SMID
+    logic           dsc_rcp_evt_pri      ;//100               // Rcp events have priority for dsc context lookup
+    logic           fabric_reset_en      ;//99                // Enable reset from fabric // Not hooked up to reset yet
+    logic           rrq_disable_en       ;//98                // Block new read requests on RQ timeout or register write
+    logic           shared_rdwr_pasid_dis;//97                // Reads and writes for a qid/function will share the same pasid index.
+    logic  [11:0]   brdg_slv_pasid_offset;//96:85             // Pasid index offset for bridge slave requests
+    logic           fab_wb_dis           ;//84                // Send out mdma writeback check completions qid/cidx through the descriptor bypass output interface.
+    logic           axis_h2c_ext_cmp_en  ;//83                // Use external signal to indicating h2c stream packet is complete, for the purpose of issueing writeback and interrupts.
+    logic           axim_auser_mode      ;//82                // Everest only attribute, 1 will pass {vfg, vfg_off} instead of address[63:50]
+    logic           dma_bar_ext_en       ;//81                // Enable DMA bar aperture to extranal MM or external Lite interface.
+    logic  [4:0]    tcp_timeout_exp      ;//80:76             // Exponential timer for TRQ completion timeout;  2^exp,  0 = disabled
+    logic           brdg_slv_pasid_en    ;// 75               // Pasid_en below must also be set to enable pasid for the bridge slave
+    logic           system_id_ovr        ;// 74
+    logic  [15:0]   system_id            ;//73:58             // System ID csr[15:0]
+    logic           rq_flr_check_dis     ;// 57               // Disable RQ FLR check
+    logic           pasid_en             ;// 56               // Enable PASID
+    logic  [2:0]    vf_bar_num           ;//55:53             // Bar number of VFs
+    logic           pcie_rc_unmask_uc    ; //52               // Unmask unexpected completions coming out or dma_pcie_rc
+    logic           dsc_ecc_chk_dis      ; //51               // Disable ECC check
+    logic           mdma_one_err_wb_dis  ; //50               // If set, allow more writebacks for queue even if writeback with error was sent already
+    logic           mdma_dsc_wb_chk_all  ; //49               // Set wb_chk (if ctxt enabled) on all descriptors of fetch even if not last
+    logic           mdma_dsc_wb_imm_all  ; //48               //  Set wb_imm (if ctxt enabled) on all descriptors of fetch even if not last
+    logic           xdma_byp_eng_flr_done; //47               // Ignore xdma engines for flr_done
+    logic           mdma_eng_err_halt    ; //46               // Halt mdma mm engine on logging error in status reg
+    logic           mdma_sw_ctxt_clr_all ; //45               // Clear hw and crd ctxt if sw ctxt cleared
+    logic  [3:0][3:0]  xdma_c2h_axi_wr_cache;//44:41          // awcache for C2H writeback to AXI
+    logic  [3:0]       xdma_c2h_axi_wr_sec  ;//28             // awprot for C2H writeback to AXI
+    logic  [3:0][3:0]  xdma_h2c_axi_rd_cache;//23             // arcache for H2C writeback to AXI
+    logic  [3:0]       xdma_h2c_axi_rd_sec ;//8               // arprot for H2C writeback to AXI
+    logic          mgmt_flr_done_en     ;   //4               // flr_done needs mgmt ifc flr done bit
+    logic  [3:0]   mgmt_flr_done_src_dis;   //3:0             // Disable mgmt flr_done access per PF
+} attr_spare_t;
+
+// DMA PF Attributes
+typedef struct packed {
+    logic    [3:0]       ch_alloc;
+    logic    [1:0]       multq_chbits;
+    logic    [5:0]       multq_maxq;
+    logic    [2:0]       multq_bits;
+    logic    [5:0]       vfmaxq;
+    logic    [2:0]       multq_vfqbits;
+    logic    [7:0]       num_vfs;
+    logic    [7:0]       firstvf_offset;
+} attr_dma_pf_t;
+
+// DMA PCIeBAR to AXIBAR Attributes
+typedef struct packed {
+    logic    [63:12]     bar;
+    logic                sec;
+    logic    [3:0]       cache;
+    logic    [7:0]       len;
+    logic    [31:0]      bar_vf;
+    logic                sec_vf;
+    logic    [3:0]       cache_vf;
+    logic    [7:0]       len_vf;
+} attr_dma_pciebar2axibar_pf_t;
+
+// DMA AXIBAR to PCIeBAR Attributes
+typedef struct packed {
+    logic    [63:0]       base;
+    logic                 as;
+    logic    [7:0]        highaddr;
+    logic    [63:0]       bar;
+} attr_dma_axibar2pciebar_t;
+
+// DMA General Attributes 
+typedef struct packed {
+    logic    [63:0]       axi_slv_brdg_base_addr;
+    logic    [63:0]       axi_slv_multq_base_addr;
+    logic    [63:0]       axi_slv_xdma_base_addr;
+    logic                 enable;
+    logic                 bypass_msix;
+    logic    [2:0]        data_width;
+    logic                 metering_enable;
+    logic    [5:0]        mask50; 
+    logic                 root_port;
+    logic                 msi_rx_decode_en;
+    logic                 pcie_if_parity_check;
+    logic    [31:0]       slvlite_base0;
+    logic    [31:0]       slvlite_base1;
+    logic    [2:0]        barlite0;
+    logic    [2:0]        barlite1;
+    logic    [2:0]        axibar_num;
+    logic    [2:0]        pciebar_num;
+    logic    [3:0]        ch_en;
+    logic    [3:0][1:0]   ch_pfid;
+    logic    [3:0]        ch_multq;
+    logic    [3:0]        ch_stream;
+    logic    [3:0]        ch_c2h_axi_dsc;
+    logic    [3:0]        ch_h2c_axi_dsc;
+    logic    [3:0]        ch_multq_ll;
+    logic    [3:0][5:0]   ch_multq_max;
+    logic                 cq_rcfg_en;
+    logic                 rq_rcfg_en;
+    attr_spare_t          spare;
+} attr_dma_t;
+
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/pciedmacoredefines.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/pciedmacoredefines.vh
new file mode 100755
index 0000000..73acaf8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/pciedmacoredefines.vh
@@ -0,0 +1,453 @@
+/*****************************************************************************
+** (c) Copyright 2007-2013 Xilinx, Inc. All rights reserved.
+**
+** This file contains confidential and proprietary information
+** of Xilinx, Inc. and is protected under U.S. and
+** international copyright and other intellectual property
+** laws.
+**
+** DISCLAIMER
+** This disclaimer is not a license and does not grant any
+** rights to the materials distributed herewith. Except as
+** otherwise provided in a valid license issued to you by
+** Xilinx, and to the maximum extent permitted by applicable
+** law: (1) THESE MATERIALS ARE MADE AVAILABLE AS IS  AND
+** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+** (2) Xilinx shall not be liable (whether in contract or tort,
+** including negligence, or under any other theory of
+** liability) for any loss or damage of any kind or nature
+** related to, arising under or in connection with these
+** materials, including for any direct, or any indirect,
+** special, incidental, or consequential loss or damage
+** (including loss of data, profits, goodwill, or any type of
+** loss or damage suffered as a result of any action brought
+** by a third party) even if such damage or loss was
+** reasonably foreseeable or Xilinx had been advised of the
+** possibility of the same.
+**
+** CRITICAL APPLICATIONS
+** Xilinx products are not designed or intended to be fail-
+** safe, or for use in any application requiring fail-safe
+** performance, such as life-support or safety devices or
+** systems, Class III medical devices, nuclear facilities,
+** applications related to the deployment of airbags, or any
+** other applications that could lead to death, personal
+** injury, or severe property or environmental damage
+** (individually and collectively, ; Critical; 
+** Applications). Customer assumes the sole risk and
+** liability of any use of Xilinx products in Critical
+** Applications, subject only to applicable laws and
+** regulations governing limitations on product liability.
+**
+** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+** PART OF THIS FILE AT ALL TIMES.
+******************************************************************************
+**
+**  Project:PCI Express Gen4
+**  Author: Siva Prasad
+**  Date:$DateTime: 2014/08/05 13:55:49 $
+**  Description: PCIE core common defines and Macros
+**  Revision: $Revision: #22 $
+**  Changed By: $Author: dpan $
+**
+*****************************************************************************/
+`timescale 1ps/1ps
+
+`ifdef PCIEDMACOREDEFINES_VH
+`else
+    `define PCIEDMACOREDEFINES_VH
+// Default is asynchronous reset flops
+// X REG with async clear and sync load (reset), and enable
+`define XPLREG_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+`ifndef SYNC_FF \
+`XPLREG_ASYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+`else \
+`XPLREG_SYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+`endif
+
+
+`define XPLREG_SYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+always @(posedge clk)                                   \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) (en & clk) ? d : q;                         \
+`else                                                   \
+    q <= #(TCQ) en ? d : q;                                 \
+`endif                                                  \
+end
+
+`define XPLREG_ASYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+always @(posedge clk or negedge reset_n)                \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) (en & clk) ? d : q;                         \
+`else                                                   \
+    q <= #(TCQ) en ? d : q;                                 \
+`endif                                                  \
+end
+
+// X REG with async clear and sync load (reset)
+`define XPLREG(clk,reset_n,load,q,d,rstval,ldval)       \
+`ifndef SYNC_FF \
+`XPLREG_ASYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+`else \
+`XPLREG_SYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+`endif
+`define XPLREG_SYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+always @(posedge clk)                                   \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) clk ? d : q;                                \
+`else                                                   \
+    q <= #(TCQ)  d;                                         \
+`endif                                                  \
+end
+`define XPLREG_ASYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+always @(posedge clk or negedge reset_n)                \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) clk ? d : q;                                \
+`else                                                   \
+    q <= #(TCQ)  d;                                         \
+`endif                                                  \
+end
+
+`define XPREG(clk, reset_n, q,d,rstval)		\
+  `ifndef SYNC_FF                               \
+`XPREG_ASYNC(clk, reset_n, q,d,rstval)		\
+  `else                              \
+`XPREG_SYNC(clk, reset_n, q,d,rstval)		\
+  `endif                            
+`define XPREG_SYNC(clk, reset_n, q,d,rstval)		\
+    always @(posedge clk)	                \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+`define XPREG_ASYNC(clk, reset_n, q,d,rstval)		\
+    always @(posedge clk or negedge reset_n )	\
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+
+`define XPREG_EN(clk, reset_n, q, d, rstval, en)    \
+   `ifndef SYNC_FF                                  \
+`XPREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)    \
+   `else                                 \
+`XPREG_SYNC_EN(clk, reset_n, q, d, rstval, en)    \
+   `endif
+`define XPREG_SYNC_EN(clk, reset_n, q, d, rstval, en)    \
+    always @(posedge clk)	                    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) (en & clk) ? d : q;		    \
+	  `else					    \
+	    q <= #(TCQ) en ? d : q;			    \
+	  `endif				    \
+     end
+`define XPREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)    \
+    always @(posedge clk or negedge reset_n)	    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) (en & clk) ? d : q;		    \
+	  `else					    \
+	    q <= #(TCQ) en ? d : q;			    \
+	  `endif				    \
+     end
+
+`define XPREG_NORESET(clk,q,d)			    \
+    always @(posedge clk)			    \
+    begin					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) clk? d : q;			    \
+	  `else					    \
+	    q <= #(TCQ) d;				    \
+	  `endif				    \
+     end
+
+`define XARREG(clk, reset_n, q,d,rstval)	\
+`ifndef SYNC_FF                              \
+`XARREG_ASYNC(clk, reset_n, q,d,rstval)	\
+`else                             \
+`XARREG_SYNC(clk, reset_n, q,d,rstval)	\
+`endif
+`define XARREG_SYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk)	                \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+`define XARREG_ASYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk or negedge reset_n )	\
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+
+`define XARREG_EN(clk, reset_n, q, d, rstval, en)   \
+`ifndef SYNC_FF                                  \
+`XARREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)   \
+`else                                 \
+`XARREG_SYNC_EN(clk, reset_n, q, d, rstval, en)   \
+`endif
+`define XARREG_SYNC_EN(clk, reset_n, q, d, rstval, en)   \
+    always @(posedge clk)	                    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+`define XARREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)   \
+    always @(posedge clk or negedge reset_n)	    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+
+`define XSRREG(clk, reset_n, q,d,rstval)	\
+`ifndef SYNC_FF                              \
+`XSRREG_ASYNC(clk, reset_n, q,d,rstval)	\
+`else \
+`XSRREG_SYNC(clk, reset_n, q,d,rstval)	\
+`endif
+`define XSRREG_ASYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk or negedge reset_n)    \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+`define XSRREG_SYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk)	                \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+
+`define XSRREG_EN(clk, reset_n, q,d,rstval, en)     \
+`ifndef SYNC_FF \
+`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en)     \
+`else   \
+`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en)     \
+`endif
+`define XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en)     \
+    always @(posedge clk)	                    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+`define XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en)     \
+    always @(posedge clk or negedge reset_n)	    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+
+`define XLREG(clk, reset_n) \
+   `ifndef SYNC_FF \
+`XLREGS_ASYNC(clk, reset_n) \
+   `else \
+`XLREGS_SYNC(clk, reset_n) \
+   `endif
+`define XLREGS_SYNC(clk, reset_n) \
+      always @(posedge clk)
+`define XLREGS_ASYNC(clk, reset_n) \
+      always @(posedge clk or negedge reset_n)
+
+// Define for legacy FFs with arguments for edges
+`define XLREG_EDGE(clkedge,clk,rstedge,rst) \
+  `ifndef SYNC_FF \
+`XLREG_ASYNC_EDGE(clkedge,clk,rstedge,rst) \
+  `else \
+`XLREG_SYNC_EDGE(clkedge,clk,rstedge,rst) \
+  `endif
+`define XLREG_SYNC_EDGE(clkedge,clk,rstedge,rst) \
+    always @(clkedge clk)
+`define XLREG_ASYNC_EDGE(clkedge,clk,rstedge,rst) \
+    always @(clkedge clk or rstedge rst)
+
+// Define for legacy FFs with no reset and arguments for edges
+`define XLREG_EDGE_NORESET(clkedge,clk) \
+    always @(clkedge clk) \
+
+//General defines
+`define byte0    7:0
+`define byte1	15:8
+`define byte2	23:16
+`define byte3	31:24
+`define byte4	39:32
+`define byte5	47:40
+`define byte6	55:48
+`define byte7	63:56
+`define byte8	71:64
+`define byte9	79:72
+`define byte10	87:80
+`define byte11	95:88
+`define byte12 103:96
+`define byte13 111:104
+`define byte14 119:112
+`define byte15 127:120
+`define byte16 135:128
+`define byte17 143:136
+`define byte18 151:144
+`define byte19 159:152
+`define byte20 167:160
+`define byte21 175:168
+`define byte22 183:176
+`define byte23 191:184
+`define byte24 199:192
+`define byte25 207:200
+`define byte26 215:208
+`define byte27 223:216
+`define byte28 231:224
+`define byte29 239:232
+`define byte30 247:240
+`define byte31 255:248
+
+`define dw0b0    7:0
+`define dw0b1	15:8
+`define dw0b2	23:16
+`define dw0b3	31:24
+`define dw0b012	23:0
+`define dw0b123	31:8
+`define dw1b0	39:32
+`define dw1b1	47:40
+`define dw1b2	55:48
+`define dw1b3	63:56
+`define dw1b012	55:32
+`define dw1b123	63:40
+`define dw2b0	71:64
+`define dw2b1	79:72
+`define dw2b2	87:80
+`define dw2b3	95:88
+`define dw2b012	87:64
+`define dw2b123	95:72
+`define dw3b0 103:96
+`define dw3b1 111:104
+`define dw3b2 119:112
+`define dw3b3 127:120
+`define dw3b012 119:96
+`define dw3b123 127:104
+`define dw4b0 135:128
+`define dw4b1 143:136
+`define dw4b2 151:144
+`define dw4b3 159:152
+`define dw4b012 151:128
+`define dw4b123 159:136
+`define dw5b0 167:160
+`define dw5b1 175:168
+`define dw5b2 183:176
+`define dw5b3 191:184
+`define dw5b012 183:160
+`define dw5b123 191:168
+`define dw6b0 199:192
+`define dw6b1 207:200
+`define dw6b2 215:208
+`define dw6b3 223:216
+`define dw6b123 223:200
+`define dw6b012 215:192
+`define dw7b0 231:224
+`define dw7b1 239:232
+`define dw7b2 247:240
+`define dw7b3 255:248
+`define dw7b012 247:224
+`define dw7b123 255:232
+
+`define dw0  31:0
+`define dw1  63:32
+`define dw2  95:64
+`define dw3 127:96 
+`define dw4 159:128
+`define dw5 191:160
+`define dw6 223:192
+`define dw7 255:224
+
+`endif
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh
new file mode 100755
index 0000000..41a7a99
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh
@@ -0,0 +1,202 @@
+`ifndef AXI_BRIDGE_VH
+`define AXI_BRIDGE_VH
+`include "pciedmacoredefines.vh"
+//-----------------------------------------------------------------------------
+// $Id: 
+//-----------------------------------------------------------------------------
+// axi_bridge.vh
+//-----------------------------------------------------------------------------
+// (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and 
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:        axi_bridge.vh
+//
+// Description:     
+//                  
+// This file needs to be included in all modules so that all the modules can commonly 
+// reference state_transitions
+//                   
+//                  
+// VHDL-Standard:   VHDL'93
+//-----------------------------------------------------------------------------
+// Structure:   
+//              Include file
+//
+//-----------------------------------------------------------------------------
+// Revision:        v1.05.a
+// Date:            06/28/12
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+`define XSRREG_AXIMM(clk, reset_n, q,d,rstval)        \
+`ifdef SOFT_IP  \
+`XSRREG_SYNC (clk, reset_n, q,d,rstval) \
+`else   \
+`XSRREG_ASYNC (clk, reset_n, q,d,rstval)  \
+`endif 
+
+`define XSRREG_EN_AXIMM(clk, reset_n, q,d,rstval, en)     \
+`ifdef SOFT_IP \
+`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \
+`else \
+`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \
+`endif
+
+`define XSRREG_XDMA(clk, reset_n, q,d,rstval)        \
+`ifdef SOFT_IP  \
+`XSRREG_SYNC (clk, reset_n, q,d,rstval) \
+`else   \
+`XSRREG_ASYNC (clk, reset_n, q,d,rstval)  \
+`endif
+
+`define XSRREG_EN_XDMA(clk, reset_n, q,d,rstval, en)     \
+`ifdef SOFT_IP \
+`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \
+`else \
+`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \
+`endif
+
+`define XLREG_AXIMM(clk, reset_n) \
+`ifdef SOFT_IP \
+`XLREGS_SYNC(clk, reset_n) \
+`else \
+`XLREGS_ASYNC(clk, reset_n)  \
+`endif
+
+`define XLREG_XDMA(clk, reset_n) \
+`ifdef SOFT_IP \
+`XLREGS_SYNC(clk, reset_n) \
+`else \
+`XLREGS_ASYNC(clk, reset_n)  \
+`endif
+
+`define XNRREG_AXIMM(clk,q,d)                            \
+    always @(posedge clk)                            \
+    begin                                            \
+         `ifdef FOURVALCLKPROP                            \
+            q <= #(TCQ) clk? d : q;                            \
+          `else                                            \
+            q <= #(TCQ) d;                                    \
+          `endif                                    \
+     end
+
+`define XNRREG_EN_AXIMM(clk,q,d,en)     \
+    always @(posedge clk)                            \
+    begin                                            \
+         `ifdef FOURVALCLKPROP                            \
+            q <= #(TCQ) ((en & clk)  ? d : q);                    \
+          `else                                            \
+            q <= #(TCQ) (en ? d : q);                            \
+          `endif                                    \
+     end
+
+// AXI Defines
+`define SIZE64 0
+`define SIZE128 1
+`define SIZE256 2
+`define SIZE512 3
+`define CQ_USER_FBELO 0
+`define CQ_USER_FBEHI 3
+`define CQ_USER_LBELO 4
+`define CQ_USER_LBEHI 7
+`define CQ_USER_LBELO_512 8
+`define CQ_USER_LBEHI_512 11
+`define CQ_USER_BELO 8
+`define CQ_USER_BEHI (CQ_USER_BELO +31)
+`define CQ_USER_PARLO 53
+`define CQ_USER_PARLO_512 119
+`define CQ_USER_PARHI (CQ_USER_PARLO +31)
+`define AXIS_MEM_READ 4'h0
+`define AXIS_MEM_WRITE 4'h1
+`define AXIS_IO_READ 4'h2
+`define AXIS_IO_WRITE 4'h3
+`define AXIS_IO_WRITE 4'h3
+`define AXIS_FETCH_ADD 4'h4
+`define AXIS_UCOND_SWAP 4'h5
+`define AXIS_COMP_SWAP 4'h6
+`define AXIS_READ_LCK 4'h7
+`define AXIS_CFGRD_TYPE0 4'h8
+`define AXIS_CFGRD_TYPE1 4'h9
+`define AXIS_CFGWR_TYPE0 4'ha
+`define AXIS_CFGWR_TYPE1 4'hb
+`define AXIS_MSG_GEN 4'hc
+`define AXIS_MSG_VNDDEF 4'hd
+`define AXIS_MSG_ATS 4'he
+`define AXIS_RSVD 4'hf
+
+
+`define AXIMM_RRESP_OK 2'b00
+`define AXIMM_RRESP_EXOK 2'b01
+`define AXIMM_RRESP_SLVERR 2'b10
+`define AXIMM_RRESP_DECERR 2'b11
+//   typedef enum {IDLE_read_reqSM, CHECK_read_reqSM, SEND_REQ, WAIT_FOR_OPEN_SLOT} read_reqSM_STATES ;
+   // Add these to the State machines
+   //signal read_reqSM_cs : read_reqSM_STATES;
+   //signal read_reqSM_ns : read_reqSM_STATES;
+
+//   typedef enum {IDLE_read_dataSM,WAIT_FOR_CPLE, LOAD_READ_COUNTERE, FIRST_BRAM_READE, STR_DATAE, STR_DONEE, WAIT_SLOT_CLRE} read_dataSM_STATES ;
+   // Add This to the appropriate file
+   //signal read_dataSM_cs : read_dataSM_STATES;
+   //signal read_dataSM_ns : read_dataSM_STATES;
+   //signal read_dataSM_cs_d : read_dataSM_STATES;
+   
+//   typedef enum {IDLE_arid_dependencySM, FIND_HISTORY_MATCH, SET_DEPENDENCY, CLEAR_DEPENDENCY} arid_dependencySM_STATES ;
+//   typedef enum {IDLE_write_reqSM, CHECK_write_reqSM, CHECK2, ONE_REQ_ACTIVE, TWO_REQ_ACTIVE} write_reqSM_STATES ;
+
+
+//   typedef enum {IDLE_write_dataSM, FIRST_DATA_WORD, DATA_STREAM, DONE_write_dataSM, WAIT_TLP_START, WAIT_STR_DONE, FIRST_DATA_WORD_2, DATA_STREAM_2, DONE_2} write_dataSM_STATES ;
+
+//function integer clog2;
+//   input [0:7] value; // Input value
+//    begin : dummy
+//        reg [0:7] value_int;
+//        value_int = value;
+//        for (clog2 = 0; value_int > 0; clog2 = clog2 + 1)
+//            value_int = value_int >> 1;
+//   end
+//endfunction
+`endif // AXI_BRIDGE_VH
diff --git a/projects/U200/U200.ip_user_files/ipstatic/hdl/xdma_v4_1_vl_rfs.sv b/projects/U200/U200.ip_user_files/ipstatic/hdl/xdma_v4_1_vl_rfs.sv
new file mode 100755
index 0000000..038cbf5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/hdl/xdma_v4_1_vl_rfs.sv
@@ -0,0 +1,41208 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+g+3KGFUOAPivYzl0egix77lxvPLwN1envbT4RvDVdyK9d+cDBGIELtd1Yk9qvYWpCZZ5BWxvrSiy
+pyesh1vnFA==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+C4JkyzyA+NKuMrcmhNtbvCxPSIIMyxR/H/z4a5xi6vZf1N37AggITtS2vQPVi+l7U3oRB4pFJ3Rv
+bWjEu0jtf5lmoZzH/hyQSvnEOhSzsJflRFFHoeuLSFPtVirZvE4KIunEIUjz1tRY1GSUhs762YMy
+ABMPfMnk2qqZ3OwNXBc=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+uyRJcOoZYVE0e1hRddL8Gl4DdUrkQ2+eTgo3wH3S69Xu3ZQ+6omNUBT9MYQz7FfDriU/xrjOWzaM
+bVAFfpsWBV+byp8l0iA7rcgJRUHJ9deK45McjW74TeH1A80vxPv9SPhs8iT3KSgU7PswJWBEGgGE
+w4ZYubxICwjySVCVhuxw3CHFuEt5DCh8sz8JMQ50KdE0WB8DHOAt/5JXdzv6Yj0PiI8lvx3HWmph
+fYR9S7W4S6xVHduj7veEDyFz1tfiMM2lO78rpwrEgD12OMncrfjr3BKNGfZioHwywdB4efxfiVLD
+KTIoCY1fmReW0Wi49ruagRk02V4Hhpr0/uBopg==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+nzPtHu5RsFhjaWIJSp9j9gU+rwL1v+fbCDdcAWyRtcgFSUZ/iAdMU5yiAIqXSIfSMaMrO8LEyaZm
+3shJU7/OMS3hcCH0+fP9qoomveHa8RSmRqQLd4gC/xZNmafQ3c8UFIFsaZa1WsdZf5oq0EbWuEFY
+bX3Z8atRQOaowjsDgJRjP1BPuZYYL4y6fYf3G9chr7Xg3zHqgAm2gKsZe8fbwMhgbIPlOmMZV2fn
+1I6M1veYgxkPOLiBZI6jts6hphRlneiMjSsaqymtje0Eo5jYAy348REHz8aimPbYy8HacbnejvLh
+JanzEPx0K0tIMO/xfk7JkDzNAjKByehK3cnmEA==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+amUIqiymOx3BaX+Mtzv1KTF9dD12bhrI0thrIZmdg8z7G60bfNjCLZgZow5I0zYfwmUaJb5LFteI
+dadXQydbseV663jS+/qkMMnb3nd5aGmobwn9F6s1y4bskCBmPTKqgnkxqBndDz7AS3k1VxYNfDM4
+0yfoNw98GNYbjTzFj8I=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+DfQpizTrBDKRXQ/iySePFZExigvyPG9sRYwLEhk102L/r6SdroTqAnJ1hfG45ZXfwAoHkqfNn5q4
+EFVfhs3Rss2WtpSv2s7c3GH0yBn9LkEh4GWNmpqrVIfgUroX65kve9J7TwOmNjlhFVfZ+d8fQJl3
+XmpZo/uHccDSkAr4Q7/h9E0UjB+Rz217Z1QptIgsnPq1q+bP20UCod4yTY8RhHcN7g2CsbZ79dUy
+EFr+MZpmy6KIvSigOnQKb5r/qeaeMea4ca5D/+egGXP8AWtVdHVMzg9FymY61+WocMOYmGdXWqOf
+LUwO6mMwSoi2xxGBqsuAKO+dlUtRI8eWdsUbSw==
+
+`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+GE0QwSwgRaEa7M6DMe4Xn5ILAQUPTYT51/oxkvMwgyDlob8uVu7GLOkF+jG2PIKE7J4V6jOp2lPq
+wYepM6H9KARs6AS6OBcxrVa5CQAoruke+e1aVEbA3qCOZZAXsKuDNToLFOfTmkPctoKh2QV/haZK
+yXTQivNW87hKGT+FiuCEz/kNcUQtNQA5hecOiWN+27nNJ8jUSh6gEr6WkXowtrcuzNLvJPfM2bm5
+TWrXSDfhWXOWAwDtYMLLiUhzD77kkb89GsRQD+JcJW1dgeeVuTdF6ZDS/5xbdfGzmt7RxbMOEjqo
+zlVSZcFX+WSi+faoWHFlsx+olVlD/O5rjtb2DA==
+
+`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2020_08", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
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+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2344176)
+`pragma protect data_block
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+VZkHp5LSf+fEx7tAJaQUxjD0BcJpjjfoT7TEF4fQJ1rP54y04GpFg2mCZsb9ngJhIJX7
+`pragma protect end_protected
diff --git a/projects/U200/U200.ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v b/projects/U200/U200.ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v
new file mode 100755
index 0000000..73b8240
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v
@@ -0,0 +1,4522 @@
+/******************************************************************************
+-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+ *****************************************************************************
+ *
+ * Filename: blk_mem_gen_v8_4_4.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: Jan 11, 2006 Initial revision
+ *          Jun 11, 2007 Added independent register stages for 
+ *                       Port A and Port B (IP1_Jm/v2.5)
+ *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
+ *          Mar 13, 2008 Behavioral model optimizations
+ *          April 07, 2009  : Added support for Spartan-6 and Virtex-6
+ *                            features, including the following:
+ *                            (i)   error injection, detection and/or correction
+ *                            (ii) reset priority
+ *                            (iii)  special reset behavior
+ *    
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);
+
+  parameter INIT = 64'h0000000000000000;
+
+  input I0, I1, I2, I3, I4, I5;
+
+  output O;
+
+  reg O;
+  reg tmp;
+
+  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin
+ 
+    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;
+
+    if ( tmp == 0 || tmp == 1)
+
+        O = INIT[{I5, I4, I3, I2, I1, I0}];
+
+  end
+endmodule
+
+module beh_vlog_muxf7_v8_4 (O, I0, I1, S);
+
+    output O;
+    reg    O;
+
+    input  I0, I1, S;
+
+	always @(I0 or I1 or S) 
+	    if (S)
+		O = I1;
+	    else
+		O = I0;
+endmodule
+
+module beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);
+  parameter INIT = 0;
+localparam FLOP_DELAY = 100;
+    output Q;
+
+    input  C, CLR, D;
+
+    reg Q;
+
+    initial Q= 1'b0;
+
+    always @(posedge C )
+      if (CLR)
+	Q<= 1'b0;
+      else
+	Q<= #FLOP_DELAY D;
+
+
+endmodule
+
+module beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);
+
+  parameter INIT = 0;
+localparam FLOP_DELAY = 100;
+    output Q;
+    input  C, D, PRE;
+
+    reg Q;
+
+    initial Q= 1'b0;
+
+    always @(posedge C )
+      if (PRE)
+           Q <= 1'b1;
+      else
+	   Q <= #FLOP_DELAY D;
+
+endmodule
+
+module beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);
+
+  parameter INIT = 0;
+localparam FLOP_DELAY = 100;
+    output Q;
+    input  C, CE, CLR, D;
+
+    reg Q;
+
+    initial Q= 1'b0;
+    always @(posedge C )
+       if (CLR)
+           Q <= 1'b0;
+       else if (CE)
+	   Q <= #FLOP_DELAY D;
+
+endmodule
+
+module write_netlist_v8_4
+#(
+   parameter	     C_AXI_TYPE = 0
+ )
+ (
+    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
+    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
+    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c 
+  );
+
+    input S_ACLK;
+    input S_ARESETN;
+    input S_AXI_AWVALID;
+    input S_AXI_WVALID;
+    input S_AXI_BREADY;
+    input w_last_c;
+    input bready_timeout_c;
+    output aw_ready_r;
+    output S_AXI_WREADY;
+    output S_AXI_BVALID;
+    output S_AXI_WR_EN;
+    output addr_en_c;
+    output incr_addr_c;
+    output bvalid_c;
+ //-------------------------------------------------------------------------
+ //AXI LITE
+ //-------------------------------------------------------------------------
+generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
+  wire w_ready_r_7;
+  wire w_ready_c;
+  wire aw_ready_c;
+  wire NlwRenamedSignal_bvalid_c;
+  wire NlwRenamedSignal_incr_addr_c;
+  wire present_state_FSM_FFd3_13;
+  wire present_state_FSM_FFd2_14;
+  wire present_state_FSM_FFd1_15;
+  wire present_state_FSM_FFd4_16;
+  wire present_state_FSM_FFd4_In;
+  wire present_state_FSM_FFd3_In;
+  wire present_state_FSM_FFd2_In;
+  wire present_state_FSM_FFd1_In;
+  wire present_state_FSM_FFd4_In1_21;
+  wire [0:0] Mmux_aw_ready_c ; 
+begin
+  assign
+  S_AXI_WREADY = w_ready_r_7,
+  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
+  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
+  incr_addr_c = NlwRenamedSignal_incr_addr_c,
+  bvalid_c = NlwRenamedSignal_bvalid_c;
+
+  assign NlwRenamedSignal_incr_addr_c = 1'b0;
+
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  aw_ready_r_2 (
+      .C ( S_ACLK), 
+      .CLR ( S_ARESETN), 
+      .D ( aw_ready_c), 
+      .Q ( aw_ready_r)
+    );
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  w_ready_r (
+      .C ( S_ACLK), 
+      .CLR ( S_ARESETN), 
+      .D ( w_ready_c), 
+      .Q ( w_ready_r_7)
+    );
+  beh_vlog_ff_pre_v8_4  #(
+      .INIT (1'b1))
+  present_state_FSM_FFd4 (
+      .C ( S_ACLK), 
+      .D ( present_state_FSM_FFd4_In), 
+      .PRE ( S_ARESETN), 
+      .Q ( present_state_FSM_FFd4_16)
+    );
+ beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd3 (
+      .C ( S_ACLK), 
+      .CLR ( S_ARESETN), 
+      .D ( present_state_FSM_FFd3_In), 
+      .Q ( present_state_FSM_FFd3_13)
+    );
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd2 (
+      .C ( S_ACLK), 
+      .CLR ( S_ARESETN), 
+      .D ( present_state_FSM_FFd2_In), 
+      .Q ( present_state_FSM_FFd2_14)
+    );
+beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd1 (
+      .C ( S_ACLK), 
+      .CLR ( S_ARESETN), 
+      .D ( present_state_FSM_FFd1_In), 
+      .Q ( present_state_FSM_FFd1_15)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000055554440))
+  present_state_FSM_FFd3_In1 (
+      .I0 ( S_AXI_WVALID), 
+      .I1 ( S_AXI_AWVALID), 
+      .I2 ( present_state_FSM_FFd2_14), 
+      .I3 ( present_state_FSM_FFd4_16), 
+      .I4 ( present_state_FSM_FFd3_13), 
+      .I5 (1'b0), 
+      .O ( present_state_FSM_FFd3_In)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000088880800))
+  present_state_FSM_FFd2_In1 (
+      .I0 ( S_AXI_AWVALID), 
+      .I1 ( S_AXI_WVALID), 
+      .I2 ( bready_timeout_c), 
+      .I3 ( present_state_FSM_FFd2_14), 
+      .I4 ( present_state_FSM_FFd4_16), 
+      .I5 (1'b0), 
+      .O ( present_state_FSM_FFd2_In)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000AAAA2000))
+  Mmux_addr_en_c_0_1 (
+      .I0 ( S_AXI_AWVALID), 
+      .I1 ( bready_timeout_c), 
+      .I2 ( present_state_FSM_FFd2_14), 
+      .I3 ( S_AXI_WVALID), 
+      .I4 ( present_state_FSM_FFd4_16), 
+      .I5 (1'b0), 
+      .O ( addr_en_c)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'hF5F07570F5F05500))
+  Mmux_w_ready_c_0_1 (
+      .I0 ( S_AXI_WVALID), 
+      .I1 ( bready_timeout_c), 
+      .I2 ( S_AXI_AWVALID), 
+      .I3 ( present_state_FSM_FFd3_13), 
+      .I4 ( present_state_FSM_FFd4_16), 
+      .I5 ( present_state_FSM_FFd2_14), 
+      .O ( w_ready_c)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h88808880FFFF8880))
+  present_state_FSM_FFd1_In1 (
+      .I0 ( S_AXI_WVALID), 
+      .I1 ( bready_timeout_c), 
+      .I2 ( present_state_FSM_FFd3_13), 
+      .I3 ( present_state_FSM_FFd2_14), 
+      .I4 ( present_state_FSM_FFd1_15), 
+      .I5 ( S_AXI_BREADY), 
+      .O ( present_state_FSM_FFd1_In)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000000000A8))
+  Mmux_S_AXI_WR_EN_0_1 (
+      .I0 ( S_AXI_WVALID), 
+      .I1 ( present_state_FSM_FFd2_14), 
+      .I2 ( present_state_FSM_FFd3_13), 
+      .I3 (1'b0), 
+      .I4 (1'b0), 
+      .I5 (1'b0), 
+      .O ( NlwRenamedSignal_bvalid_c)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h2F0F27072F0F2200))
+  present_state_FSM_FFd4_In1 (
+      .I0 ( S_AXI_WVALID), 
+      .I1 ( bready_timeout_c), 
+      .I2 ( S_AXI_AWVALID), 
+      .I3 ( present_state_FSM_FFd3_13), 
+      .I4 ( present_state_FSM_FFd4_16), 
+      .I5 ( present_state_FSM_FFd2_14), 
+      .O ( present_state_FSM_FFd4_In1_21)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000000000F8))
+  present_state_FSM_FFd4_In2 ( 
+      .I0 ( present_state_FSM_FFd1_15), 
+      .I1 ( S_AXI_BREADY), 
+      .I2 ( present_state_FSM_FFd4_In1_21), 
+      .I3 (1'b0), 
+      .I4 (1'b0), 
+      .I5 (1'b0), 
+      .O ( present_state_FSM_FFd4_In)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h7535753575305500))
+  Mmux_aw_ready_c_0_1 ( 
+      .I0 ( S_AXI_AWVALID), 
+      .I1 ( bready_timeout_c), 
+      .I2 ( S_AXI_WVALID), 
+      .I3 ( present_state_FSM_FFd4_16), 
+      .I4 ( present_state_FSM_FFd3_13), 
+      .I5 ( present_state_FSM_FFd2_14), 
+      .O ( Mmux_aw_ready_c[0])
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000000000F8))
+  Mmux_aw_ready_c_0_2 (
+      .I0 ( present_state_FSM_FFd1_15), 
+      .I1 ( S_AXI_BREADY), 
+      .I2 ( Mmux_aw_ready_c[0]), 
+      .I3 (1'b0), 
+      .I4 (1'b0), 
+      .I5 (1'b0), 
+      .O ( aw_ready_c)
+    );
+end 
+end 
+endgenerate
+
+  //---------------------------------------------------------------------
+  // AXI FULL
+  //---------------------------------------------------------------------
+generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
+  wire w_ready_r_8; 
+  wire w_ready_c; 
+  wire aw_ready_c; 
+  wire NlwRenamedSig_OI_bvalid_c; 
+  wire present_state_FSM_FFd1_16; 
+  wire present_state_FSM_FFd4_17; 
+  wire present_state_FSM_FFd3_18; 
+  wire present_state_FSM_FFd2_19; 
+  wire present_state_FSM_FFd4_In; 
+  wire present_state_FSM_FFd3_In; 
+  wire present_state_FSM_FFd2_In; 
+  wire present_state_FSM_FFd1_In; 
+  wire present_state_FSM_FFd2_In1_24; 
+  wire present_state_FSM_FFd4_In1_25; 
+  wire N2; 
+  wire N4; 
+begin
+assign
+  S_AXI_WREADY = w_ready_r_8,
+  bvalid_c = NlwRenamedSig_OI_bvalid_c,
+  S_AXI_BVALID = 1'b0;
+
+beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  aw_ready_r_2
+    (
+      .C ( S_ACLK),
+      .CLR ( S_ARESETN),
+      .D ( aw_ready_c),
+      .Q ( aw_ready_r)
+    );
+beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  w_ready_r
+    (
+      .C ( S_ACLK),
+      .CLR ( S_ARESETN),
+      .D ( w_ready_c),
+      .Q ( w_ready_r_8)
+    );
+ beh_vlog_ff_pre_v8_4  #(
+      .INIT (1'b1))
+  present_state_FSM_FFd4
+    (
+      .C ( S_ACLK),
+      .D ( present_state_FSM_FFd4_In),
+      .PRE ( S_ARESETN),
+      .Q ( present_state_FSM_FFd4_17)
+    );
+beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd3
+    (
+      .C ( S_ACLK),
+      .CLR ( S_ARESETN),
+      .D ( present_state_FSM_FFd3_In),
+      .Q ( present_state_FSM_FFd3_18)
+    );
+beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd2
+    (
+      .C ( S_ACLK),
+      .CLR ( S_ARESETN),
+      .D ( present_state_FSM_FFd2_In),
+      .Q ( present_state_FSM_FFd2_19)
+    );
+ beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd1
+    (
+      .C ( S_ACLK),
+      .CLR ( S_ARESETN),
+      .D ( present_state_FSM_FFd1_In),
+      .Q ( present_state_FSM_FFd1_16)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000005540))
+  present_state_FSM_FFd3_In1
+    (
+      .I0 ( S_AXI_WVALID),
+      .I1 ( present_state_FSM_FFd4_17),
+      .I2 ( S_AXI_AWVALID),
+      .I3 ( present_state_FSM_FFd3_18),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( present_state_FSM_FFd3_In)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'hBF3FBB33AF0FAA00))
+  Mmux_aw_ready_c_0_2
+    (
+      .I0 ( S_AXI_BREADY),
+      .I1 ( bready_timeout_c),
+      .I2 ( S_AXI_AWVALID),
+      .I3 ( present_state_FSM_FFd1_16),
+      .I4 ( present_state_FSM_FFd4_17),
+      .I5 ( NlwRenamedSig_OI_bvalid_c),
+      .O ( aw_ready_c)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'hAAAAAAAA20000000))
+  Mmux_addr_en_c_0_1
+    (
+      .I0 ( S_AXI_AWVALID),
+      .I1 ( bready_timeout_c),
+      .I2 ( present_state_FSM_FFd2_19),
+      .I3 ( S_AXI_WVALID),
+      .I4 ( w_last_c),
+      .I5 ( present_state_FSM_FFd4_17),
+      .O ( addr_en_c)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000000000A8))
+  Mmux_S_AXI_WR_EN_0_1
+    (
+      .I0 ( S_AXI_WVALID),
+      .I1 ( present_state_FSM_FFd2_19),
+      .I2 ( present_state_FSM_FFd3_18),
+      .I3 (1'b0),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( S_AXI_WR_EN)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000002220))
+  Mmux_incr_addr_c_0_1
+    (
+      .I0 ( S_AXI_WVALID),
+      .I1 ( w_last_c),
+      .I2 ( present_state_FSM_FFd2_19),
+      .I3 ( present_state_FSM_FFd3_18),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( incr_addr_c)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000008880))
+  Mmux_aw_ready_c_0_11
+    (
+      .I0 ( S_AXI_WVALID),
+      .I1 ( w_last_c),
+      .I2 ( present_state_FSM_FFd2_19),
+      .I3 ( present_state_FSM_FFd3_18),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( NlwRenamedSig_OI_bvalid_c)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h000000000000D5C0))
+  present_state_FSM_FFd2_In1
+    (
+      .I0 ( w_last_c),
+      .I1 ( S_AXI_AWVALID),
+      .I2 ( present_state_FSM_FFd4_17),
+      .I3 ( present_state_FSM_FFd3_18),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( present_state_FSM_FFd2_In1_24)
+    );
+STATE_LOGIC_v8_4 #(
+      .INIT (64'hFFFFAAAA08AAAAAA))
+  present_state_FSM_FFd2_In2
+    (
+      .I0 ( present_state_FSM_FFd2_19),
+      .I1 ( S_AXI_AWVALID),
+      .I2 ( bready_timeout_c),
+      .I3 ( w_last_c),
+      .I4 ( S_AXI_WVALID),
+      .I5 ( present_state_FSM_FFd2_In1_24),
+      .O ( present_state_FSM_FFd2_In)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h00C0004000C00000))
+  present_state_FSM_FFd4_In1
+    (
+      .I0 ( S_AXI_AWVALID),
+      .I1 ( w_last_c),
+      .I2 ( S_AXI_WVALID),
+      .I3 ( bready_timeout_c),
+      .I4 ( present_state_FSM_FFd3_18),
+      .I5 ( present_state_FSM_FFd2_19),
+      .O ( present_state_FSM_FFd4_In1_25)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000FFFF88F8))
+  present_state_FSM_FFd4_In2
+    (
+      .I0 ( present_state_FSM_FFd1_16),
+      .I1 ( S_AXI_BREADY),
+      .I2 ( present_state_FSM_FFd4_17),
+      .I3 ( S_AXI_AWVALID),
+      .I4 ( present_state_FSM_FFd4_In1_25),
+      .I5 (1'b0),
+      .O ( present_state_FSM_FFd4_In)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000000007))
+  Mmux_w_ready_c_0_SW0
+    (
+      .I0 ( w_last_c),
+      .I1 ( S_AXI_WVALID),
+      .I2 (1'b0),
+      .I3 (1'b0),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( N2)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'hFABAFABAFAAAF000))
+  Mmux_w_ready_c_0_Q
+    (
+      .I0 ( N2),
+      .I1 ( bready_timeout_c),
+      .I2 ( S_AXI_AWVALID),
+      .I3 ( present_state_FSM_FFd4_17),
+      .I4 ( present_state_FSM_FFd3_18),
+      .I5 ( present_state_FSM_FFd2_19),
+      .O ( w_ready_c)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000000008))
+  Mmux_aw_ready_c_0_11_SW0
+    (
+      .I0 ( bready_timeout_c),
+      .I1 ( S_AXI_WVALID),
+      .I2 (1'b0),
+      .I3 (1'b0),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O ( N4)
+    );
+ STATE_LOGIC_v8_4 #(
+      .INIT (64'h88808880FFFF8880))
+  present_state_FSM_FFd1_In1
+    (
+      .I0 ( w_last_c),
+      .I1 ( N4),
+      .I2 ( present_state_FSM_FFd2_19),
+      .I3 ( present_state_FSM_FFd3_18),
+      .I4 ( present_state_FSM_FFd1_16),
+      .I5 ( S_AXI_BREADY),
+      .O ( present_state_FSM_FFd1_In)
+    );
+end
+end
+endgenerate
+endmodule
+
+
+module read_netlist_v8_4 #(
+      parameter C_AXI_TYPE                 = 1,
+      parameter C_ADDRB_WIDTH              = 12
+      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
+          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
+          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
+          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
+
+    input S_AXI_R_LAST_INT;
+    input S_ACLK;
+    input S_ARESETN;
+    input S_AXI_ARVALID;
+    input S_AXI_RREADY;
+    output S_AXI_INCR_ADDR;
+    output S_AXI_ADDR_EN;
+    output S_AXI_SINGLE_TRANS;
+    output S_AXI_MUX_SEL;
+    output S_AXI_R_LAST;
+    output S_AXI_ARREADY;
+    output S_AXI_RLAST;
+    output S_AXI_RVALID;
+    output S_AXI_RD_EN;
+    input [7:0] S_AXI_ARLEN;
+
+  wire present_state_FSM_FFd1_13 ; 
+  wire present_state_FSM_FFd2_14 ; 
+  wire gaxi_full_sm_outstanding_read_r_15 ; 
+  wire gaxi_full_sm_ar_ready_r_16 ; 
+  wire gaxi_full_sm_r_last_r_17 ; 
+  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; 
+  wire gaxi_full_sm_r_valid_c ; 
+  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; 
+  wire gaxi_full_sm_ar_ready_c ; 
+  wire gaxi_full_sm_outstanding_read_c ; 
+  wire NlwRenamedSig_OI_S_AXI_R_LAST ; 
+  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; 
+  wire present_state_FSM_FFd2_In ; 
+  wire present_state_FSM_FFd1_In ; 
+  wire Mmux_S_AXI_R_LAST13 ; 
+  wire N01 ; 
+  wire N2 ; 
+  wire Mmux_gaxi_full_sm_ar_ready_c11 ; 
+  wire N4 ; 
+  wire N8 ; 
+  wire N9 ; 
+  wire N10 ; 
+  wire N11 ; 
+  wire N12 ; 
+  wire N13 ; 
+  assign
+  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
+  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
+  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
+  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
+
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  gaxi_full_sm_outstanding_read_r (
+      .C (S_ACLK),
+      .CLR(S_ARESETN),
+      .D(gaxi_full_sm_outstanding_read_c),
+      .Q(gaxi_full_sm_outstanding_read_r_15)
+    );
+  beh_vlog_ff_ce_clr_v8_4 #(
+      .INIT (1'b0))
+  gaxi_full_sm_r_valid_r (
+      .C (S_ACLK),
+      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
+      .CLR (S_ARESETN),
+      .D (gaxi_full_sm_r_valid_c),
+      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
+    );
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  gaxi_full_sm_ar_ready_r (
+      .C (S_ACLK),
+      .CLR (S_ARESETN),
+      .D (gaxi_full_sm_ar_ready_c),
+      .Q (gaxi_full_sm_ar_ready_r_16)
+    );
+  beh_vlog_ff_ce_clr_v8_4 #(
+      .INIT(1'b0))
+  gaxi_full_sm_r_last_r (
+      .C (S_ACLK),
+      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
+      .CLR (S_ARESETN),
+      .D (NlwRenamedSig_OI_S_AXI_R_LAST),
+      .Q (gaxi_full_sm_r_last_r_17)
+    );
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd2 (
+      .C ( S_ACLK),
+      .CLR ( S_ARESETN),
+      .D ( present_state_FSM_FFd2_In),
+      .Q ( present_state_FSM_FFd2_14)
+    );
+  beh_vlog_ff_clr_v8_4 #(
+      .INIT (1'b0))
+  present_state_FSM_FFd1 (
+      .C (S_ACLK),
+      .CLR (S_ARESETN),
+      .D (present_state_FSM_FFd1_In),
+      .Q (present_state_FSM_FFd1_13)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h000000000000000B))
+  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
+      .I0 ( S_AXI_RREADY),
+      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I2 (1'b0),
+      .I3 (1'b0),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000000008))
+  Mmux_S_AXI_SINGLE_TRANS11 (
+      .I0 (S_AXI_ARVALID),
+      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I2 (1'b0),
+      .I3 (1'b0),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O (S_AXI_SINGLE_TRANS)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000000004))
+  Mmux_S_AXI_ADDR_EN11 (
+      .I0 (present_state_FSM_FFd1_13),
+      .I1 (S_AXI_ARVALID),
+      .I2 (1'b0),
+      .I3 (1'b0),
+      .I4 (1'b0),
+      .I5 (1'b0),
+      .O (S_AXI_ADDR_EN)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'hECEE2022EEEE2022))
+  present_state_FSM_FFd2_In1 (
+      .I0 ( S_AXI_ARVALID),
+      .I1 ( present_state_FSM_FFd1_13),
+      .I2 ( S_AXI_RREADY),
+      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I4 ( present_state_FSM_FFd2_14),
+      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .O ( present_state_FSM_FFd2_In)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000044440444))
+  Mmux_S_AXI_R_LAST131 (
+      .I0 ( present_state_FSM_FFd1_13),
+      .I1 ( S_AXI_ARVALID),
+      .I2 ( present_state_FSM_FFd2_14),
+      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I4 ( S_AXI_RREADY),
+      .I5 (1'b0),
+      .O ( Mmux_S_AXI_R_LAST13)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h4000FFFF40004000))
+  Mmux_S_AXI_INCR_ADDR11 (
+      .I0 ( S_AXI_R_LAST_INT),
+      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
+      .I2 ( present_state_FSM_FFd2_14),
+      .I3 ( present_state_FSM_FFd1_13),
+      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I5 ( Mmux_S_AXI_R_LAST13),
+      .O ( S_AXI_INCR_ADDR)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000000000FE))
+  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
+      .I0 ( S_AXI_ARLEN[2]),
+      .I1 ( S_AXI_ARLEN[1]),
+      .I2 ( S_AXI_ARLEN[0]),
+      .I3 ( 1'b0),
+      .I4 ( 1'b0),
+      .I5 ( 1'b0),
+      .O ( N01)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000000001))
+  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
+      .I0 ( S_AXI_ARLEN[7]),
+      .I1 ( S_AXI_ARLEN[6]),
+      .I2 ( S_AXI_ARLEN[5]),
+      .I3 ( S_AXI_ARLEN[4]),
+      .I4 ( S_AXI_ARLEN[3]),
+      .I5 ( N01),
+      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000000007))
+  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
+      .I0 ( S_AXI_ARVALID),
+      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I2 ( 1'b0),
+      .I3 ( 1'b0),
+      .I4 ( 1'b0),
+      .I5 ( 1'b0),
+      .O ( N2)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0020000002200200))
+  Mmux_gaxi_full_sm_outstanding_read_c1 (
+      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I1 ( S_AXI_RREADY),
+      .I2 ( present_state_FSM_FFd1_13),
+      .I3 ( present_state_FSM_FFd2_14),
+      .I4 ( gaxi_full_sm_outstanding_read_r_15),
+      .I5 ( N2),
+      .O ( gaxi_full_sm_outstanding_read_c)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000000004555))
+  Mmux_gaxi_full_sm_ar_ready_c12 (
+      .I0 ( S_AXI_ARVALID),
+      .I1 ( S_AXI_RREADY),
+      .I2 ( present_state_FSM_FFd2_14),
+      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I4 ( 1'b0),
+      .I5 ( 1'b0),
+      .O ( Mmux_gaxi_full_sm_ar_ready_c11)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000000000EF))
+  Mmux_S_AXI_R_LAST11_SW0 (
+      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I1 ( S_AXI_RREADY),
+      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I3 ( 1'b0),
+      .I4 ( 1'b0),
+      .I5 ( 1'b0),
+      .O ( N4)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'hFCAAFC0A00AA000A))
+  Mmux_S_AXI_R_LAST11 (
+      .I0 ( S_AXI_ARVALID),
+      .I1 ( gaxi_full_sm_outstanding_read_r_15),
+      .I2 ( present_state_FSM_FFd2_14),
+      .I3 ( present_state_FSM_FFd1_13),
+      .I4 ( N4),
+      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
+      .O ( gaxi_full_sm_r_valid_c)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000AAAAAA08))
+  S_AXI_MUX_SEL1 (
+      .I0 (present_state_FSM_FFd1_13),
+      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I2 (S_AXI_RREADY),
+      .I3 (present_state_FSM_FFd2_14),
+      .I4 (gaxi_full_sm_outstanding_read_r_15),
+      .I5 (1'b0),
+      .O (S_AXI_MUX_SEL)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'hF3F3F755A2A2A200))
+  Mmux_S_AXI_RD_EN11 (
+      .I0 ( present_state_FSM_FFd1_13),
+      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I2 ( S_AXI_RREADY),
+      .I3 ( gaxi_full_sm_outstanding_read_r_15),
+      .I4 ( present_state_FSM_FFd2_14),
+      .I5 ( S_AXI_ARVALID),
+      .O ( S_AXI_RD_EN)
+    );
+  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (
+      .I0 ( N8),
+      .I1 ( N9),
+      .S ( present_state_FSM_FFd1_13),
+      .O ( present_state_FSM_FFd1_In)
+    );
+
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h000000005410F4F0))
+  present_state_FSM_FFd1_In3_F (
+      .I0 ( S_AXI_RREADY),
+      .I1 ( present_state_FSM_FFd2_14),
+      .I2 ( S_AXI_ARVALID),
+      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I5 ( 1'b0),
+      .O ( N8)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000072FF7272))
+  present_state_FSM_FFd1_In3_G (
+      .I0 ( present_state_FSM_FFd2_14),
+      .I1 ( S_AXI_R_LAST_INT),
+      .I2 ( gaxi_full_sm_outstanding_read_r_15),
+      .I3 ( S_AXI_RREADY),
+      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I5 ( 1'b0),
+      .O ( N9)
+    );
+  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (
+      .I0 ( N10),
+      .I1 ( N11),
+      .S ( present_state_FSM_FFd1_13),
+      .O ( gaxi_full_sm_ar_ready_c)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000FFFF88A8))
+  Mmux_gaxi_full_sm_ar_ready_c14_F (
+      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I1 ( S_AXI_RREADY),
+      .I2 ( present_state_FSM_FFd2_14),
+      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
+      .I5 ( 1'b0),
+      .O ( N10)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h000000008D008D8D))
+  Mmux_gaxi_full_sm_ar_ready_c14_G (
+      .I0 ( present_state_FSM_FFd2_14),
+      .I1 ( S_AXI_R_LAST_INT),
+      .I2 ( gaxi_full_sm_outstanding_read_r_15),
+      .I3 ( S_AXI_RREADY),
+      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I5 ( 1'b0),
+      .O ( N11)
+    );
+  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (
+      .I0 ( N12),
+      .I1 ( N13),
+      .S ( present_state_FSM_FFd1_13),
+      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h0000000088088888))
+  Mmux_S_AXI_R_LAST1_F (
+      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
+      .I1 ( S_AXI_ARVALID),
+      .I2 ( present_state_FSM_FFd2_14),
+      .I3 ( S_AXI_RREADY),
+      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I5 ( 1'b0),
+      .O ( N12)
+    );
+  STATE_LOGIC_v8_4 #(
+      .INIT (64'h00000000E400E4E4))
+  Mmux_S_AXI_R_LAST1_G (
+      .I0 ( present_state_FSM_FFd2_14),
+      .I1 ( gaxi_full_sm_outstanding_read_r_15),
+      .I2 ( S_AXI_R_LAST_INT),
+      .I3 ( S_AXI_RREADY),
+      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
+      .I5 ( 1'b0),
+      .O ( N13)
+    );
+
+endmodule
+
+
+module blk_mem_axi_write_wrapper_beh_v8_4
+  # (
+    // AXI Interface related parameters start here
+    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface
+    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;
+    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
+    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
+    parameter C_WRITE_DEPTH_A            = 0,
+    parameter C_AXI_AWADDR_WIDTH         = 32,
+    parameter C_ADDRA_WIDTH 	         = 12,
+    parameter C_AXI_WDATA_WIDTH          = 32,
+    parameter C_HAS_AXI_ID               = 0,
+    parameter C_AXI_ID_WIDTH             = 4,
+    // AXI OUTSTANDING WRITES
+    parameter C_AXI_OS_WR                = 2
+    )
+    (
+     // AXI Global Signals
+    input S_ACLK,  
+    input S_ARESETN,
+    // AXI Full/Lite Slave Write Channel (write side)
+    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
+    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
+    input [8-1:0] S_AXI_AWLEN,
+    input [2:0] S_AXI_AWSIZE,
+    input [1:0] S_AXI_AWBURST,
+    input  S_AXI_AWVALID,
+    output S_AXI_AWREADY,
+    input  S_AXI_WVALID,
+    output S_AXI_WREADY, 
+    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
+    output S_AXI_BVALID,
+    input  S_AXI_BREADY,
+    // Signals for BMG interface
+    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
+    output S_AXI_WR_EN
+    );
+
+  localparam FLOP_DELAY  = 100;  // 100 ps
+
+   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
+                       ((C_AXI_WDATA_WIDTH==16)?1:
+                       ((C_AXI_WDATA_WIDTH==32)?2:
+                       ((C_AXI_WDATA_WIDTH==64)?3:
+                       ((C_AXI_WDATA_WIDTH==128)?4:
+                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));
+
+
+
+
+  wire bvalid_c                 ;
+  reg bready_timeout_c          = 0;
+  wire [1:0] bvalid_rd_cnt_c;
+  reg bvalid_r         	= 0;
+  reg [2:0] bvalid_count_r = 0;
+  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
+        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
+  reg [1:0] bvalid_wr_cnt_r = 0;
+  reg [1:0] bvalid_rd_cnt_r = 0;
+  wire w_last_c                 ;
+  wire addr_en_c                ;
+  wire incr_addr_c              ;
+  wire aw_ready_r 	        ;
+  wire dec_alen_c               ;
+  reg bvalid_d1_c = 0;
+  reg [7:0] awlen_cntr_r = 0;
+  reg [7:0] awlen_int = 0;
+  reg [1:0] awburst_int = 0;
+
+  integer total_bytes              = 0;
+  integer wrap_boundary            = 0;
+  integer wrap_base_addr           = 0;
+  integer num_of_bytes_c           = 0;
+  integer num_of_bytes_r           = 0;
+  // Array to store BIDs
+  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
+  wire S_AXI_BVALID_axi_wr_fsm;
+
+  //-------------------------------------
+  //AXI WRITE FSM COMPONENT INSTANTIATION
+  //-------------------------------------
+ write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
+      (
+      .S_ACLK(S_ACLK),
+      .S_ARESETN(S_ARESETN),
+      .S_AXI_AWVALID(S_AXI_AWVALID),
+      .aw_ready_r(aw_ready_r),
+      .S_AXI_WVALID(S_AXI_WVALID),
+      .S_AXI_WREADY(S_AXI_WREADY),
+      .S_AXI_BREADY(S_AXI_BREADY),
+      .S_AXI_WR_EN(S_AXI_WR_EN),
+      .w_last_c(w_last_c),
+      .bready_timeout_c(bready_timeout_c),
+      .addr_en_c(addr_en_c),
+      .incr_addr_c(incr_addr_c),
+      .bvalid_c(bvalid_c),
+      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) 
+	  );   
+  
+   
+   //Wrap Address boundary calculation 
+   always@(*) begin
+    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
+    total_bytes    = (num_of_bytes_r)*(awlen_int+1);
+    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
+    wrap_boundary  = wrap_base_addr+total_bytes;
+  end
+  
+  //-------------------------------------------------------------------------
+  // BMG address generation
+  //-------------------------------------------------------------------------
+   always @(posedge S_ACLK or S_ARESETN) begin
+         if (S_ARESETN == 1'b1) begin
+           awaddr_reg       <= 0;
+	   num_of_bytes_r   <= 0;
+	   awburst_int      <= 0; 
+	 end else begin
+           if (addr_en_c == 1'b1) begin
+              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;
+	      num_of_bytes_r   <= num_of_bytes_c;
+	      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
+	   end else if (incr_addr_c == 1'b1) begin
+	      if (awburst_int == 2'b10) begin
+		if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
+		  awaddr_reg  <= wrap_base_addr;
+		end else begin
+		  awaddr_reg <= awaddr_reg + num_of_bytes_r;
+		end
+	      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
+		awaddr_reg   <= awaddr_reg + num_of_bytes_r;
+	      end
+           end
+         end
+   end
+  
+    
+   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
+			  	       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
+
+  //-------------------------------------------------------------------------
+  // AXI wlast generation
+  //-------------------------------------------------------------------------
+    always @(posedge S_ACLK or S_ARESETN) begin
+        if (S_ARESETN == 1'b1) begin
+          awlen_cntr_r      <= 0;
+	  awlen_int       <= 0;
+	  end else begin
+          if (addr_en_c == 1'b1) begin
+	    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
+	    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
+	    end else if (dec_alen_c == 1'b1) begin
+            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;
+          end
+        end
+    end
+
+    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
+    
+    assign dec_alen_c        =  (incr_addr_c | w_last_c);
+
+   //-------------------------------------------------------------------------
+   // Generation of bvalid counter for outstanding transactions  
+   //-------------------------------------------------------------------------
+    always @(posedge S_ACLK or S_ARESETN) begin
+      if (S_ARESETN == 1'b1) begin
+	bvalid_count_r             <= 0;
+	end else begin
+	// bvalid_count_r generation
+	if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
+	  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;
+	  end else if (bvalid_c == 1'b1) begin  
+	  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;
+	  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
+	  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;
+	end
+      end
+    end
+
+    //-------------------------------------------------------------------------
+    // Generation of bvalid when BID is used 
+    //-------------------------------------------------------------------------
+    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
+      always @(posedge S_ACLK or S_ARESETN) begin
+        if (S_ARESETN == 1'b1) begin
+          bvalid_r                   <=  0;
+          bvalid_d1_c                <=  0;
+	end else begin
+         // Delay the generation o bvalid_r for generation for BID 
+         bvalid_d1_c  <= bvalid_c;
+         
+         //external bvalid signal generation
+         if (bvalid_d1_c == 1'b1) begin
+           bvalid_r                <=   #FLOP_DELAY 1'b1 ;
+	 end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
+           bvalid_r                <=   #FLOP_DELAY 0 ;
+         end
+        end
+      end
+    end
+    endgenerate
+      
+   //-------------------------------------------------------------------------
+   // Generation of bvalid when BID is not used 
+   //-------------------------------------------------------------------------
+   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
+    always @(posedge S_ACLK or S_ARESETN) begin
+        if (S_ARESETN == 1'b1) begin
+          bvalid_r                   <=  0;
+	end else begin
+         //external bvalid signal generation
+         if (bvalid_c == 1'b1) begin
+           bvalid_r                <=   #FLOP_DELAY 1'b1 ;
+	 end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
+           bvalid_r                <=   #FLOP_DELAY 0 ;
+         end
+       end
+    end
+    end
+   endgenerate
+    
+    //-------------------------------------------------------------------------
+    // Generation of Bready timeout
+    //-------------------------------------------------------------------------
+    always @(bvalid_count_r) begin
+    	// bready_timeout_c generation
+	if(bvalid_count_r == C_AXI_OS_WR-1) begin
+	  bready_timeout_c        <=   1'b1;
+	end else begin
+	  bready_timeout_c        <=   1'b0;
+	end
+    end
+    
+    //-------------------------------------------------------------------------
+    // Generation of BID 
+    //-------------------------------------------------------------------------
+    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
+
+    always @(posedge S_ACLK or S_ARESETN) begin
+        if (S_ARESETN == 1'b1) begin
+            bvalid_wr_cnt_r   <= 0;
+            bvalid_rd_cnt_r   <= 0;
+	end else begin
+          // STORE AWID IN AN ARRAY
+          if(bvalid_c == 1'b1) begin
+            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;
+          end
+	  // generate BID FROM AWID ARRAY
+	  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
+	  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];
+        end       
+    end
+    
+    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
+    
+    //-------------------------------------------------------------------------
+    // Storing AWID for generation of BID
+    //-------------------------------------------------------------------------
+    always @(posedge S_ACLK or S_ARESETN) begin
+      if(S_ARESETN == 1'b1) begin
+	axi_bid_array[0] = 0;
+	axi_bid_array[1] = 0;
+	axi_bid_array[2] = 0;
+	axi_bid_array[3] = 0;
+	end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
+	axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
+      end
+    end
+  
+  end
+  endgenerate
+
+  assign S_AXI_BVALID   =  bvalid_r;
+  assign S_AXI_AWREADY  =  aw_ready_r;
+
+  endmodule
+
+module blk_mem_axi_read_wrapper_beh_v8_4
+# (
+    //// AXI Interface related parameters start here
+    parameter  C_INTERFACE_TYPE           = 0,
+    parameter  C_AXI_TYPE                 = 0,
+    parameter  C_AXI_SLAVE_TYPE           = 0,
+    parameter  C_MEMORY_TYPE              = 0,
+    parameter  C_WRITE_WIDTH_A            = 4,
+    parameter  C_WRITE_DEPTH_A            = 32,
+    parameter  C_ADDRA_WIDTH              = 12,
+    parameter  C_AXI_PIPELINE_STAGES      = 0,
+    parameter  C_AXI_ARADDR_WIDTH         = 12,
+    parameter  C_HAS_AXI_ID               = 0,
+    parameter  C_AXI_ID_WIDTH             = 4,
+    parameter  C_ADDRB_WIDTH              = 12
+    )
+   (
+
+    //// AXI Global Signals
+    input S_ACLK,
+    input S_ARESETN,
+    //// AXI Full/Lite Slave Read (Read side)
+    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
+    input [7:0] S_AXI_ARLEN,
+    input [2:0] S_AXI_ARSIZE,
+    input [1:0] S_AXI_ARBURST,
+    input S_AXI_ARVALID,
+    output S_AXI_ARREADY,
+    output S_AXI_RLAST, 
+    output S_AXI_RVALID,
+    input S_AXI_RREADY,
+    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
+    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
+    //// AXI Full/Lite Read Address Signals to BRAM
+    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
+    output S_AXI_RD_EN
+    );
+
+  localparam FLOP_DELAY  = 100;  // 100 ps
+  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
+                       ((C_WRITE_WIDTH_A==16)?1:
+                       ((C_WRITE_WIDTH_A==32)?2:
+                       ((C_WRITE_WIDTH_A==64)?3:
+                       ((C_WRITE_WIDTH_A==128)?4:
+                       ((C_WRITE_WIDTH_A==256)?5:0))))));
+
+
+
+  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
+  wire addr_en_c; 
+  wire rd_en_c; 
+  wire incr_addr_c; 
+  wire single_trans_c; 
+  wire dec_alen_c; 
+  wire mux_sel_c; 
+  wire r_last_c; 
+  wire r_last_int_c; 
+  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; 
+
+  reg [7:0] arlen_int_r=0; 
+  reg [7:0] arlen_cntr=8'h01; 
+  reg [1:0] arburst_int_c=0; 
+  reg [1:0] arburst_int_r=0; 
+  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
+        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
+  integer num_of_bytes_c           = 0;
+  integer total_bytes              = 0;
+  integer num_of_bytes_r           = 0;
+  integer wrap_base_addr_r         = 0;
+  integer wrap_boundary_r          = 0;
+
+  reg [7:0] arlen_int_c=0;                  
+  integer total_bytes_c            = 0;
+  integer wrap_base_addr_c         = 0;
+  integer wrap_boundary_c          = 0;
+
+  assign dec_alen_c        = incr_addr_c | r_last_int_c;
+
+
+  read_netlist_v8_4
+  #(.C_AXI_TYPE      (1),
+    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) 
+    axi_read_fsm (
+    .S_AXI_INCR_ADDR(incr_addr_c),
+    .S_AXI_ADDR_EN(addr_en_c),
+    .S_AXI_SINGLE_TRANS(single_trans_c),
+    .S_AXI_MUX_SEL(mux_sel_c),
+    .S_AXI_R_LAST(r_last_c),
+    .S_AXI_R_LAST_INT(r_last_int_c),
+
+    //// AXI Global Signals
+    .S_ACLK(S_ACLK),
+    .S_ARESETN(S_ARESETN),
+    //// AXI Full/Lite Slave Read (Read side)
+    .S_AXI_ARLEN(S_AXI_ARLEN),
+    .S_AXI_ARVALID(S_AXI_ARVALID),
+    .S_AXI_ARREADY(S_AXI_ARREADY),
+    .S_AXI_RLAST(S_AXI_RLAST),
+    .S_AXI_RVALID(S_AXI_RVALID),
+    .S_AXI_RREADY(S_AXI_RREADY),
+    //// AXI Full/Lite Read Address Signals to BRAM
+    .S_AXI_RD_EN(rd_en_c)
+      );
+
+   always@(*) begin
+     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
+     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);
+     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
+     wrap_boundary_r  = wrap_base_addr_r+total_bytes;
+
+     //////// combinatorial from interface
+     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
+     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);
+     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
+     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;
+     
+     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  
+   end
+
+  ////-------------------------------------------------------------------------
+  //// BMG address generation
+  ////-------------------------------------------------------------------------
+   always @(posedge S_ACLK or S_ARESETN) begin
+     if (S_ARESETN == 1'b1) begin
+        araddr_reg 	<= 0;
+   	arburst_int_r   <= 0;
+	num_of_bytes_r  <= 0;
+     end else begin
+        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
+	      arburst_int_r    <= arburst_int_c;
+	      num_of_bytes_r   <= num_of_bytes_c;
+	      if (arburst_int_c == 2'b10) begin
+		    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
+		      araddr_reg <= wrap_base_addr_c;
+		    end else begin
+		      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
+		    end
+	      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
+		    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
+	      end
+
+        end else if (addr_en_c == 1'b1) begin
+              araddr_reg       <= S_AXI_ARADDR;
+	      num_of_bytes_r   <= num_of_bytes_c;
+	      arburst_int_r    <= arburst_int_c;
+	    end else if (incr_addr_c == 1'b1) begin
+	      if (arburst_int_r == 2'b10) begin
+	     	if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
+	     	  araddr_reg <= wrap_base_addr_r;
+	     	end else begin
+	     	  araddr_reg <= araddr_reg + num_of_bytes_r;
+	     	end
+	      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
+		      araddr_reg   <= araddr_reg + num_of_bytes_r;
+	      end
+         end
+         end
+   end
+
+assign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
+  
+
+ ////-----------------------------------------------------------------------
+    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM
+ ////-----------------------------------------------------------------------
+    always @(posedge S_ACLK or S_ARESETN) begin
+        if (S_ARESETN == 1'b1) begin
+          arlen_cntr        <= 8'h01;
+	    arlen_int_r     <= 0;
+	end else begin
+          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
+	    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
+            arlen_cntr      <= S_AXI_ARLEN - 1'b1;
+	  end else if (addr_en_c == 1'b1) begin
+	    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
+	    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
+	  end else if (dec_alen_c == 1'b1) begin
+            arlen_cntr      <= arlen_cntr - 1'b1 ;
+          end
+	  else begin
+	        arlen_cntr      <= arlen_cntr;
+	  end
+     end
+   end
+
+    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
+
+
+    ////------------------------------------------------------------------------
+    //// AXI FULL FSM
+    //// Mux Selection of ARADDR
+    //// ARADDR is driven out from the read fsm based on the mux_sel_c
+    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is
+    //// given out to BRAM
+    ////------------------------------------------------------------------------
+	assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
+    
+    ////------------------------------------------------------------------------
+    //// Assign output signals  - AXI FULL FSM
+    ////------------------------------------------------------------------------
+    assign S_AXI_RD_EN = rd_en_c;
+
+    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
+      always @(posedge S_ACLK or S_ARESETN) begin
+        if (S_ARESETN == 1'b1) begin
+          S_AXI_RID <= 0;
+          ar_id_r   <= 0;
+	end else begin
+          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
+             S_AXI_RID <= S_AXI_ARID;
+             ar_id_r <= S_AXI_ARID;
+          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
+	     ar_id_r <= S_AXI_ARID;
+          end else if (rd_en_c == 1'b1) begin
+             S_AXI_RID <= ar_id_r;
+          end
+        end
+     end 
+     end 
+   endgenerate 
+
+endmodule
+
+module blk_mem_axi_regs_fwd_v8_4
+  #(parameter C_DATA_WIDTH = 8
+   )(
+    input   ACLK,
+    input   ARESET,
+    input   S_VALID,
+    output  S_READY,
+    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+    output  M_VALID,
+    input   M_READY,
+    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
+    );
+
+    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;
+    wire S_READY_I;
+    reg  M_VALID_I;
+    reg  [1:0] ARESET_D;
+
+      //assign local signal to its output signal
+      assign S_READY = S_READY_I;
+      assign M_VALID = M_VALID_I;
+
+   always @(posedge ACLK) begin
+	  ARESET_D <= {ARESET_D[0], ARESET};
+	end
+      
+      //Save payload data whenever we have a transaction on the slave side
+   always @(posedge ACLK or ARESET) begin
+        if (ARESET == 1'b1) begin
+  	    STORAGE_DATA <= 0;
+	end else begin
+	  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
+  	    STORAGE_DATA <= S_PAYLOAD_DATA;
+  	  end
+  	end
+     end
+
+   always @(posedge ACLK) begin
+     M_PAYLOAD_DATA = STORAGE_DATA;
+   end
+      
+      //M_Valid set to high when we have a completed transfer on slave side
+      //Is removed on a M_READY except if we have a new transfer on the slave side
+       
+   always @(posedge ACLK or ARESET_D) begin
+	if (ARESET_D != 2'b00) begin
+  	    M_VALID_I <= 1'b0;
+	end else begin
+	  if (S_VALID == 1'b1) begin
+	    //Always set M_VALID_I when slave side is valid
+            M_VALID_I <= 1'b1;
+	  end else if (M_READY == 1'b1 ) begin
+	    //Clear (or keep) when no slave side is valid but master side is ready
+	    M_VALID_I <= 1'b0;
+	  end
+	end
+      end
+
+      //Slave Ready is either when Master side drives M_READY or we have space in our storage data
+      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
+
+  endmodule
+
+//*****************************************************************************
+// Output Register Stage module
+//
+// This module builds the output register stages of the memory. This module is 
+// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is
+// declared/implemented further down in this file.
+//*****************************************************************************
+module blk_mem_gen_v8_4_4_output_stage
+  #(parameter C_FAMILY              = "virtex7",
+    parameter C_XDEVICEFAMILY       = "virtex7",
+    parameter C_RST_TYPE            = "SYNC",
+    parameter C_HAS_RST             = 0,
+    parameter C_RSTRAM              = 0,
+    parameter C_RST_PRIORITY        = "CE",
+    parameter C_INIT_VAL            = "0",
+    parameter C_HAS_EN              = 0,
+    parameter C_HAS_REGCE           = 0,
+    parameter C_DATA_WIDTH          = 32,
+    parameter C_ADDRB_WIDTH         = 10,
+    parameter C_HAS_MEM_OUTPUT_REGS = 0,
+    parameter C_USE_SOFTECC         = 0,
+    parameter C_USE_ECC             = 0,
+    parameter NUM_STAGES            = 1,
+	parameter C_EN_ECC_PIPE         = 0,
+    parameter FLOP_DELAY            = 100
+  )
+  (
+   input                         CLK,
+   input                         RST,
+   input                         EN,
+   input                         REGCE,
+   input      [C_DATA_WIDTH-1:0] DIN_I,
+   output reg [C_DATA_WIDTH-1:0] DOUT,
+   input                         SBITERR_IN_I,
+   input                         DBITERR_IN_I,
+   output reg                    SBITERR,
+   output reg                    DBITERR,
+   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,
+   input                         ECCPIPECE,    
+   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC
+);
+
+//******************************
+// Port and Generic Definitions
+//******************************
+  //////////////////////////////////////////////////////////////////////////
+  // Generic Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
+  //                           options are available - "spartan3", "spartan6", 
+  //                           "virtex4", "virtex5", "virtex6" and "virtex6l".
+  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous
+  // C_HAS_RST               : Determines the presence of the RST port
+  // C_RSTRAM                : Determines if special reset behavior is used
+  // C_RST_PRIORITY          : Determines the priority between CE and SR
+  // C_INIT_VAL              : Initialization value
+  // C_HAS_EN                : Determines the presence of the EN port
+  // C_HAS_REGCE             : Determines the presence of the REGCE port
+  // C_DATA_WIDTH            : Memory write/read width
+  // C_ADDRB_WIDTH           : Width of the ADDRB input port
+  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output 
+  //                           of the RAM primitive
+  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or
+  //                           not. Only applicable Spartan-6
+  // C_USE_ECC               : Determines if the ECC feature is used or
+  //                           not. Only applicable for V5 and V6
+  // NUM_STAGES              : Determines the number of output stages
+  // FLOP_DELAY              : Constant delay for register assignments
+  //////////////////////////////////////////////////////////////////////////
+  // Port Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // CLK    : Clock to synchronize all read and write operations
+  // RST    : Reset input to reset memory outputs to a user-defined 
+  //           reset state
+  // EN     : Enable all read and write operations
+  // REGCE  : Register Clock Enable to control each pipeline output
+  //           register stages
+  // DIN    : Data input to the Output stage.
+  // DOUT   : Final Data output
+  // SBITERR_IN    : SBITERR input signal to the Output stage.
+  // SBITERR       : Final SBITERR Output signal.
+  // DBITERR_IN    : DBITERR input signal to the Output stage.
+  // DBITERR       : Final DBITERR Output signal.
+  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.
+  // RDADDRECC     : Final RDADDRECC Output signal.
+  //////////////////////////////////////////////////////////////////////////
+
+//  Fix for CR-509792
+
+  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
+  
+  // Declare the pipeline registers 
+  // (includes mem output reg, mux pipeline stages, and mux output reg)
+  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
+  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
+  reg [REG_STAGES-1:0] sbiterr_regs;
+  reg [REG_STAGES-1:0] dbiterr_regs;
+
+  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;
+  reg [C_DATA_WIDTH-1:0]            init_val ;
+
+  //*********************************************
+  // Wire off optional inputs based on parameters
+  //*********************************************
+  wire                              en_i;
+  wire                              regce_i;
+  wire                              rst_i;
+  
+  // Internal signals
+  reg [C_DATA_WIDTH-1:0]     DIN;
+  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;
+  reg                        SBITERR_IN;
+  reg                        DBITERR_IN;
+
+
+  // Internal enable for output registers is tied to user EN or '1' depending
+  // on parameters
+  assign   en_i    = (C_HAS_EN==0 || EN);
+
+  // Internal register enable for output registers is tied to user REGCE, EN or
+  // '1' depending on parameters
+  // For V4 ECC, REGCE is always 1
+  // Virtex-4 ECC Not Yet Supported
+  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||
+                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
+  
+  //Internal SRR is tied to user RST or '0' depending on parameters
+  assign   rst_i   = (C_HAS_RST==1) && RST;
+
+  //****************************************************
+  // Power on: load up the output registers and latches
+  //****************************************************
+  initial begin
+    if (!($sscanf(init_str, "%h", init_val))) begin
+      init_val = 0;
+    end
+    DOUT = init_val;
+    RDADDRECC = 0;
+    SBITERR = 1'b0;
+    DBITERR = 1'b0;
+	DIN     = {(C_DATA_WIDTH){1'b0}};
+    RDADDRECC_IN = 0;
+    SBITERR_IN = 0;
+	DBITERR_IN = 0;
+	// This will be one wider than need, but 0 is an error
+    out_regs = {(REG_STAGES+1){init_val}};
+    rdaddrecc_regs = 0;
+    sbiterr_regs = {(REG_STAGES+1){1'b0}};
+    dbiterr_regs = {(REG_STAGES+1){1'b0}};
+  end
+
+ //***********************************************
+ // NUM_STAGES = 0 (No output registers. RAM only)
+ //***********************************************
+  generate if (NUM_STAGES == 0) begin : zero_stages
+    always @* begin
+      DOUT = DIN;
+      RDADDRECC = RDADDRECC_IN;
+      SBITERR = SBITERR_IN;
+      DBITERR = DBITERR_IN;
+    end
+  end
+  endgenerate
+
+  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
+    always @* begin
+      DIN = DIN_I;
+	  SBITERR_IN = SBITERR_IN_I;
+      DBITERR_IN = DBITERR_IN_I;
+      RDADDRECC_IN = RDADDRECC_IN_I;
+    end
+  end
+  endgenerate
+
+  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
+    always @(posedge CLK) begin
+      if(ECCPIPECE == 1) begin
+	    DIN <= #FLOP_DELAY DIN_I;
+        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
+        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
+        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
+      end
+	end
+  end
+  endgenerate
+
+
+  //***********************************************
+  // NUM_STAGES = 1 
+  // (Mem Output Reg only or Mux Output Reg only)
+  //***********************************************
+
+  // Possible valid combinations: 
+  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
+  //   +-----------------------------------------+
+  //   |   C_RSTRAM_*   |  Reset Behavior        |
+  //   +----------------+------------------------+
+  //   |       0        |   Normal Behavior      |
+  //   +----------------+------------------------+
+  //   |       1        |  Special Behavior      |
+  //   +----------------+------------------------+
+  //
+  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.
+  // Special = EN gates reset, as in the case of S3ADSP.
+
+  generate if (NUM_STAGES == 1 && 
+                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
+                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
+  begin : one_stages_norm
+
+      always @(posedge CLK) begin
+        if (C_RST_PRIORITY == "CE") begin //REGCE has priority
+          if (regce_i && rst_i) begin
+            DOUT    <= #FLOP_DELAY init_val;
+            RDADDRECC <= #FLOP_DELAY 0;
+            SBITERR <= #FLOP_DELAY 1'b0;
+            DBITERR <= #FLOP_DELAY 1'b0;
+          end else if (regce_i) begin
+            DOUT    <= #FLOP_DELAY DIN;
+            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
+            SBITERR <= #FLOP_DELAY SBITERR_IN;
+            DBITERR <= #FLOP_DELAY DBITERR_IN;
+          end //Output signal assignments
+        end else begin             //RST has priority
+          if (rst_i) begin
+            DOUT    <= #FLOP_DELAY init_val;
+            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
+            SBITERR <= #FLOP_DELAY 1'b0;
+            DBITERR <= #FLOP_DELAY 1'b0;
+          end else if (regce_i) begin
+            DOUT    <= #FLOP_DELAY DIN;
+            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
+            SBITERR <= #FLOP_DELAY SBITERR_IN;
+            DBITERR <= #FLOP_DELAY DBITERR_IN;
+          end //Output signal assignments
+        end //end Priority conditions
+    end //end RST Type conditions
+  end //end one_stages_norm generate statement
+  endgenerate
+
+  // Special Reset Behavior for S3ADSP
+  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
+  begin : one_stage_splbhv
+    always @(posedge CLK) begin
+      if (en_i && rst_i) begin
+        DOUT <= #FLOP_DELAY init_val;
+      end else if (regce_i && !rst_i) begin
+        DOUT <= #FLOP_DELAY DIN;
+      end //Output signal assignments
+    end  //end CLK
+  end //end one_stage_splbhv generate statement
+  endgenerate
+
+ //************************************************************
+ // NUM_STAGES > 1 
+ // Mem Output Reg + Mux Output Reg
+ //              or 
+ // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
+ //              or 
+ // Mux Pipeline Stages (>0) + Mux Output Reg
+ //*************************************************************
+ generate if (NUM_STAGES > 1) begin : multi_stage
+       //Asynchronous Reset
+      always @(posedge CLK) begin
+        if (C_RST_PRIORITY == "CE") begin  //REGCE has priority
+          if (regce_i && rst_i) begin
+            DOUT    <= #FLOP_DELAY init_val;
+            RDADDRECC <= #FLOP_DELAY 0;
+            SBITERR <= #FLOP_DELAY 1'b0;
+            DBITERR <= #FLOP_DELAY 1'b0;
+          end else if (regce_i) begin
+            DOUT    <= #FLOP_DELAY
+                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
+            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
+            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
+            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
+          end //Output signal assignments
+        end else begin                     //RST has priority
+          if (rst_i) begin
+            DOUT    <= #FLOP_DELAY init_val;
+            RDADDRECC <= #FLOP_DELAY 0;
+            SBITERR <= #FLOP_DELAY 1'b0;
+            DBITERR <= #FLOP_DELAY 1'b0;
+          end else if (regce_i) begin
+            DOUT    <= #FLOP_DELAY
+                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
+            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
+            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
+            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
+          end //Output signal assignments
+        end   //end Priority conditions
+         // Shift the data through the output stages
+         if (en_i) begin
+           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
+           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
+           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
+           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
+         end
+      end  //end CLK
+  end //end multi_stage generate statement
+  endgenerate
+endmodule
+
+module blk_mem_gen_v8_4_4_softecc_output_reg_stage
+  #(parameter C_DATA_WIDTH          = 32,
+    parameter C_ADDRB_WIDTH         = 10,
+    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
+    parameter C_USE_SOFTECC         = 0,
+    parameter FLOP_DELAY            = 100
+  )
+  (
+   input                         CLK,
+   input      [C_DATA_WIDTH-1:0] DIN,
+   output reg [C_DATA_WIDTH-1:0] DOUT,
+   input                         SBITERR_IN,
+   input                         DBITERR_IN,
+   output reg                    SBITERR,
+   output reg                    DBITERR,
+   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,
+   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC
+);
+
+//******************************
+// Port and Generic Definitions
+//******************************
+  //////////////////////////////////////////////////////////////////////////
+  // Generic Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // C_DATA_WIDTH                  : Memory write/read width
+  // C_ADDRB_WIDTH                 : Width of the ADDRB input port
+  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output 
+  //                                 of the RAM primitive
+  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or
+  //                                 not. Only applicable Spartan-6
+  // FLOP_DELAY                    : Constant delay for register assignments
+  //////////////////////////////////////////////////////////////////////////
+  // Port Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // CLK    : Clock to synchronize all read and write operations
+  // DIN    : Data input to the Output stage.
+  // DOUT   : Final Data output
+  // SBITERR_IN    : SBITERR input signal to the Output stage.
+  // SBITERR       : Final SBITERR Output signal.
+  // DBITERR_IN    : DBITERR input signal to the Output stage.
+  // DBITERR       : Final DBITERR Output signal.
+  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.
+  // RDADDRECC     : Final RDADDRECC Output signal.
+  //////////////////////////////////////////////////////////////////////////
+
+  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;
+  reg                              sbiterr_i    = 0;
+  reg                              dbiterr_i    = 0;
+  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;
+
+ //***********************************************
+ // NO OUTPUT REGISTERS.
+ //***********************************************
+  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
+    always @* begin
+      DOUT = DIN;
+      RDADDRECC = RDADDRECC_IN;
+      SBITERR = SBITERR_IN;
+      DBITERR = DBITERR_IN;
+    end
+  end
+  endgenerate
+
+ //***********************************************
+ // WITH OUTPUT REGISTERS.
+ //***********************************************
+  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
+      always @(posedge CLK) begin
+      dout_i <= #FLOP_DELAY DIN;
+      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
+      sbiterr_i <= #FLOP_DELAY SBITERR_IN;
+      dbiterr_i <= #FLOP_DELAY DBITERR_IN;
+      end
+
+      always @* begin
+      DOUT = dout_i;
+      RDADDRECC = rdaddrecc_i;
+      SBITERR = sbiterr_i;
+      DBITERR = dbiterr_i;
+      end //end always
+      end //end in_or_out_stage generate statement
+ endgenerate
+
+endmodule
+
+
+//*****************************************************************************
+// Main Memory module
+//
+// This module is the top-level behavioral model and this implements the RAM 
+//*****************************************************************************
+module blk_mem_gen_v8_4_4_mem_module
+  #(parameter C_CORENAME                = "blk_mem_gen_v8_4_4",
+    parameter C_FAMILY                  = "virtex7",
+    parameter C_XDEVICEFAMILY           = "virtex7",
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_USE_BRAM_BLOCK          = 0,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_INIT_FILE               = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL               = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL               = "",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
+    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_SOFTECC             = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter FLOP_DELAY                = 100,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+	parameter C_EN_ECC_PIPE             = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0
+  )
+  (input                       CLKA,
+   input                       RSTA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input                       RSTB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   input                       INJECTSBITERR,
+   input                       INJECTDBITERR,
+   input                       ECCPIPECE,
+   input                       SLEEP,
+   output                      SBITERR,
+   output                      DBITERR,
+   output [C_ADDRB_WIDTH-1:0]  RDADDRECC
+  );
+//******************************
+// Port and Generic Definitions
+//******************************
+  //////////////////////////////////////////////////////////////////////////
+  // Generic Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // C_CORENAME              : Instance name of the Block Memory Generator core
+  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
+  //                           options are available - "spartan3", "spartan6", 
+  //                           "virtex4", "virtex5", "virtex6" and "virtex6l".
+  // C_MEM_TYPE              : Designates memory type.
+  //                           It can be
+  //                           0 - Single Port Memory
+  //                           1 - Simple Dual Port Memory
+  //                           2 - True Dual Port Memory
+  //                           3 - Single Port Read Only Memory
+  //                           4 - Dual Port Read Only Memory
+  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)
+  // C_ALGORITHM             : Designates the algorithm method used
+  //                           for constructing the memory.
+  //                           It can be Fixed_Primitives, Minimum_Area or 
+  //                           Low_Power
+  // C_PRIM_TYPE             : Designates the user selected primitive used to 
+  //                           construct the memory.
+  //
+  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to
+  //                           initialize memory contents.
+  // C_INIT_FILE_NAME        : Memory initialization file name.
+  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining
+  //                           initialization space with default data
+  // C_DEFAULT_DATA          : Default value of all memory locations
+  //                           not initialized by the memory
+  //                           initialization file.
+  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous
+  // C_HAS_RSTA              : Determines the presence of the RSTA port
+  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for 
+  //                           Port A.
+  // C_RSTRAM_A              : Determines if special reset behavior is used for
+  //                           Port A
+  // C_INITA_VAL             : The initialization value for Port A
+  // C_HAS_ENA               : Determines the presence of the ENA port
+  // C_HAS_REGCEA            : Determines the presence of the REGCEA port
+  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.
+  // C_WEA_WIDTH             : The width of the WEA port
+  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be
+  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.
+  // C_WRITE_WIDTH_A         : Memory write width for Port A.
+  // C_READ_WIDTH_A          : Memory read width for Port A.
+  // C_WRITE_DEPTH_A         : Memory write depth for Port A.
+  // C_READ_DEPTH_A          : Memory read depth for Port A.
+  // C_ADDRA_WIDTH           : Width of the ADDRA input port
+  // C_HAS_RSTB              : Determines the presence of the RSTB port
+  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for 
+  //                           Port B.
+  // C_RSTRAM_B              : Determines if special reset behavior is used for
+  //                           Port B
+  // C_INITB_VAL             : The initialization value for Port B
+  // C_HAS_ENB               : Determines the presence of the ENB port
+  // C_HAS_REGCEB            : Determines the presence of the REGCEB port
+  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.
+  // C_WEB_WIDTH             : The width of the WEB port
+  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be
+  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.
+  // C_WRITE_WIDTH_B         : Memory write width for Port B.
+  // C_READ_WIDTH_B          : Memory read width for Port B.
+  // C_WRITE_DEPTH_B         : Memory write depth for Port B.
+  // C_READ_DEPTH_B          : Memory read depth for Port B.
+  // C_ADDRB_WIDTH           : Width of the ADDRB input port
+  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output 
+  //                           of the RAM primitive for Port A.
+  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output 
+  //                           of the RAM primitive for Port B.
+  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
+  //                           of the MUX for Port A.
+  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
+  //                           of the MUX for Port B.
+  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in 
+  //                           between the muxes.
+  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or
+  //                           not. Only applicable Spartan-6
+  // C_USE_ECC               : Determines if the ECC feature is used or
+  //                           not. Only applicable for V5 and V6
+  // C_HAS_INJECTERR         : Determines if the error injection pins
+  //                           are present or not. If the ECC feature
+  //                           is not used, this value is defaulted to
+  //                           0, else the following are the allowed 
+  //                           values:
+  //                         0 : No INJECTSBITERR or INJECTDBITERR pins
+  //                         1 : Only INJECTSBITERR pin exists
+  //                         2 : Only INJECTDBITERR pin exists
+  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist
+  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision
+  //                           warnings. It can be "ALL", "NONE", 
+  //                           "Warnings_Only" or "Generate_X_Only".
+  // C_COMMON_CLK            : Determins if the core has a single CLK input.
+  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
+  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range 
+  //                           warnings
+  //////////////////////////////////////////////////////////////////////////
+  // Port Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // CLKA    : Clock to synchronize all read and write operations of Port A.
+  // RSTA    : Reset input to reset memory outputs to a user-defined 
+  //           reset state for Port A.
+  // ENA     : Enable all read and write operations of Port A.
+  // REGCEA  : Register Clock Enable to control each pipeline output
+  //           register stages for Port A.
+  // WEA     : Write Enable to enable all write operations of Port A.
+  // ADDRA   : Address of Port A.
+  // DINA    : Data input of Port A.
+  // DOUTA   : Data output of Port A.
+  // CLKB    : Clock to synchronize all read and write operations of Port B.
+  // RSTB    : Reset input to reset memory outputs to a user-defined 
+  //           reset state for Port B.
+  // ENB     : Enable all read and write operations of Port B.
+  // REGCEB  : Register Clock Enable to control each pipeline output
+  //           register stages for Port B.
+  // WEB     : Write Enable to enable all write operations of Port B.
+  // ADDRB   : Address of Port B.
+  // DINB    : Data input of Port B.
+  // DOUTB   : Data output of Port B.
+  // INJECTSBITERR : Single Bit ECC Error Injection Pin.
+  // INJECTDBITERR : Double Bit ECC Error Injection Pin.
+  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been
+  //                 detected and corrected.
+  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been
+  //                 detected.
+  // RDADDRECC     : Read Address Output signal indicating address at which an
+  //                 ECC error has occurred.
+  //////////////////////////////////////////////////////////////////////////
+
+
+// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_4_4" and it is
+// only used by this module to print warning messages. It is neither passed 
+// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template
+// coregen generates
+  
+  //***************************************************************************
+  // constants for the core behavior
+  //***************************************************************************
+  // file handles for logging
+  //--------------------------------------------------
+  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range
+  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection
+  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors
+
+  // other constants
+  //--------------------------------------------------
+  localparam COLL_DELAY         = 100;  // 100 ps
+
+  // locally derived parameters to determine memory shape
+  //-----------------------------------------------------
+
+  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); 
+
+  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
+             C_WRITE_WIDTH_A : C_READ_WIDTH_A;
+  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
+             C_WRITE_WIDTH_B : C_READ_WIDTH_B;
+  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
+             MIN_WIDTH_A : MIN_WIDTH_B;
+
+  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
+             C_WRITE_DEPTH_A : C_READ_DEPTH_A;
+  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
+             C_WRITE_DEPTH_B : C_READ_DEPTH_B;
+  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
+             MAX_DEPTH_A : MAX_DEPTH_B;
+
+
+  // locally derived parameters to assist memory access
+  //----------------------------------------------------
+  // Calculate the width ratios of each port with respect to the narrowest
+  // port
+  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
+  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;
+  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
+  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;
+
+  // To modify the LSBs of the 'wider' data to the actual
+  // address value
+  //----------------------------------------------------
+  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;
+  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;
+  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;
+  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;
+
+  // If byte writes aren't being used, make sure BYTE_SIZE is not
+  // wider than the memory elements to avoid compilation warnings
+  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
+
+  // The memory
+  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];
+  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];
+  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
+  // ECC error arrays
+  reg                      sbiterr_arr [0:MAX_DEPTH-1];
+  reg                      dbiterr_arr [0:MAX_DEPTH-1];
+
+  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];
+  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];
+  // Memory output 'latches'
+  reg [C_READ_WIDTH_A-1:0] memory_out_a;
+  reg [C_READ_WIDTH_B-1:0] memory_out_b;
+
+  // ECC error inputs and outputs from output_stage module:
+  reg                      sbiterr_in;
+  wire                     sbiterr_sdp;
+  reg                      dbiterr_in;
+  wire                     dbiterr_sdp;
+
+  wire [C_READ_WIDTH_B-1:0]            dout_i;
+  wire                     dbiterr_i;
+  wire                     sbiterr_i;
+  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;
+
+  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;
+  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;
+
+  // Reset values
+  reg [C_READ_WIDTH_A-1:0] inita_val;
+  reg [C_READ_WIDTH_B-1:0] initb_val;
+
+  // Collision detect
+  reg                      is_collision;
+  reg                      is_collision_a, is_collision_delay_a;
+  reg                      is_collision_b, is_collision_delay_b;
+
+  // Temporary variables for initialization
+  //---------------------------------------
+  integer                  status;
+  integer                  initfile;
+  integer                  meminitfile;
+  // data input buffer
+  reg [C_WRITE_WIDTH_A-1:0]    mif_data;
+  reg [C_WRITE_WIDTH_A-1:0]    mem_data;
+  // string values in hex
+  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;
+  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;
+  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;
+  // initialization filename
+  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;
+  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;
+
+
+  //Constants used to calculate the effective address widths for each of the 
+  //four ports. 
+  integer cnt = 1;
+  integer write_addr_a_width, read_addr_a_width;
+  integer write_addr_b_width, read_addr_b_width;
+
+    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY=="virtexuplushbm"?"virtex7":(C_FAMILY=="zynquplusrfsoc"?"virtex7":(C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))))));
+
+  // Internal configuration parameters
+  //---------------------------------------------
+  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
+  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
+  localparam HAS_A_WRITE = (!IS_ROM);
+  localparam HAS_B_WRITE = (C_MEM_TYPE==2);
+  localparam HAS_A_READ  = (C_MEM_TYPE!=1);
+  localparam HAS_B_READ  = (!SINGLE_PORT);
+  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);
+
+  // Calculate the mux pipeline register stages for Port A and Port B
+  //------------------------------------------------------------------
+  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
+                             C_MUX_PIPELINE_STAGES : 0;
+  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
+                             C_MUX_PIPELINE_STAGES : 0;
+  
+  // Calculate total number of register stages in the core
+  // -----------------------------------------------------
+  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
+
+  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
+
+  wire                   ena_i;
+  wire                   enb_i;
+  wire                   reseta_i;
+  wire                   resetb_i;
+  wire [C_WEA_WIDTH-1:0] wea_i;
+  wire [C_WEB_WIDTH-1:0] web_i;
+  wire                   rea_i;
+  wire                   reb_i;
+  wire                   rsta_outp_stage;
+  wire                   rstb_outp_stage;
+  // ECC SBITERR/DBITERR Outputs
+  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.
+  //  For Virtex-5, these outputs will be tied to 0.
+   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
+   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
+   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
+
+
+  // This effectively wires off optional inputs
+  assign ena_i = (C_HAS_ENA==0) || ENA;
+  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
+  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and
+  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
+  // write operation depends on both enable and write enable. So, the below code
+  // which is actually doing the write operation only on enable ignoring the wea
+  // is removed to be in consistent with RTL.
+  // To Fix CR855535 (The fix to this CR is reverted to match RTL)
+  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
+  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
+  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
+  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;
+  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;
+
+  // These signals reset the memory latches
+
+  assign reseta_i = 
+     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
+      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
+
+  assign resetb_i = 
+     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
+      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
+
+  // Tasks to access the memory
+  //---------------------------
+  //**************
+  // write_a
+  //**************
+  task write_a
+    (input  reg [C_ADDRA_WIDTH-1:0]   addr,
+     input  reg [C_WEA_WIDTH-1:0]     byte_en,
+     input  reg [C_WRITE_WIDTH_A-1:0] data,
+     input  inj_sbiterr,
+     input  inj_dbiterr);
+    reg [C_WRITE_WIDTH_A-1:0] current_contents;
+    reg [C_ADDRA_WIDTH-1:0] address;
+    integer i;
+    begin
+      // Shift the address by the ratio
+      address = (addr/WRITE_ADDR_A_DIV);
+      if (address >= C_WRITE_DEPTH_A) begin
+        if (!C_DISABLE_WARN_BHV_RANGE) begin
+          $fdisplay(ADDRFILE,
+                    "%0s WARNING: Address %0h is outside range for A Write",
+                    C_CORENAME, addr);
+        end
+
+      // valid address
+      end else begin
+
+        // Combine w/ byte writes
+        if (C_USE_BYTE_WEA) begin
+
+          // Get the current memory contents
+          if (WRITE_WIDTH_RATIO_A == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            current_contents = memory[address];
+          end else begin
+            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
+              current_contents[MIN_WIDTH*i+:MIN_WIDTH]
+                = memory[address*WRITE_WIDTH_RATIO_A + i];
+            end
+          end
+
+          // Apply incoming bytes
+          if (C_WEA_WIDTH == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            if (byte_en[0]) begin
+              current_contents = data;
+            end
+          end else begin
+            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
+              if (byte_en[i]) begin
+                current_contents[BYTE_SIZE*i+:BYTE_SIZE]
+                  = data[BYTE_SIZE*i+:BYTE_SIZE];
+              end
+            end
+          end
+
+        // No byte-writes, overwrite the whole word
+        end else begin
+          current_contents = data;
+        end
+
+        // Insert double bit errors:
+        if (C_USE_ECC == 1) begin
+          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
+// Modified for Implementing CR_859399            
+            current_contents[0] = !(current_contents[30]);
+            current_contents[1] = !(current_contents[62]);
+            
+            /*current_contents[0] = !(current_contents[0]);
+            current_contents[1] = !(current_contents[1]);*/
+          end
+        end
+    
+        // Insert softecc double bit errors:
+        if (C_USE_SOFTECC == 1) begin
+          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
+            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
+            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
+            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
+            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
+          end
+        end
+    
+        // Write data to memory
+        if (WRITE_WIDTH_RATIO_A == 1) begin
+          // Workaround for IUS 5.5 part-select issue
+          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
+        end else begin
+          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
+            memory[address*WRITE_WIDTH_RATIO_A + i]
+              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];
+          end
+        end
+
+        // Store the address at which error is injected:
+        if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
+          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || 
+            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
+          begin
+            sbiterr_arr[addr] = 1;
+          end else begin
+            sbiterr_arr[addr] = 0;
+          end
+  
+          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
+            dbiterr_arr[addr] = 1;
+          end else begin
+            dbiterr_arr[addr] = 0;
+          end
+        end
+
+        // Store the address at which softecc error is injected:
+        if (C_USE_SOFTECC == 1) begin
+          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || 
+            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
+          begin
+            softecc_sbiterr_arr[addr] = 1;
+          end else begin
+            softecc_sbiterr_arr[addr] = 0;
+          end
+  
+          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
+            softecc_dbiterr_arr[addr] = 1;
+          end else begin
+            softecc_dbiterr_arr[addr] = 0;
+          end
+        end
+
+      end
+    end
+  endtask
+
+  //**************
+  // write_b
+  //**************
+  task write_b
+    (input  reg [C_ADDRB_WIDTH-1:0]   addr,
+     input  reg [C_WEB_WIDTH-1:0]     byte_en,
+     input  reg [C_WRITE_WIDTH_B-1:0] data);
+    reg [C_WRITE_WIDTH_B-1:0] current_contents;
+    reg [C_ADDRB_WIDTH-1:0]   address;
+    integer i;
+    begin
+      // Shift the address by the ratio
+      address = (addr/WRITE_ADDR_B_DIV);
+      if (address >= C_WRITE_DEPTH_B) begin
+        if (!C_DISABLE_WARN_BHV_RANGE) begin
+          $fdisplay(ADDRFILE,
+                    "%0s WARNING: Address %0h is outside range for B Write",
+                    C_CORENAME, addr);
+        end
+
+      // valid address
+      end else begin
+
+        // Combine w/ byte writes
+        if (C_USE_BYTE_WEB) begin
+
+          // Get the current memory contents
+          if (WRITE_WIDTH_RATIO_B == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            current_contents = memory[address];
+          end else begin
+            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
+              current_contents[MIN_WIDTH*i+:MIN_WIDTH]
+                = memory[address*WRITE_WIDTH_RATIO_B + i];
+            end
+          end
+
+          // Apply incoming bytes
+          if (C_WEB_WIDTH == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            if (byte_en[0]) begin
+              current_contents = data;
+            end
+          end else begin
+            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
+              if (byte_en[i]) begin
+                current_contents[BYTE_SIZE*i+:BYTE_SIZE]
+                  = data[BYTE_SIZE*i+:BYTE_SIZE];
+              end
+            end
+          end
+
+        // No byte-writes, overwrite the whole word
+        end else begin
+          current_contents = data;
+        end
+
+        // Write data to memory
+        if (WRITE_WIDTH_RATIO_B == 1) begin
+          // Workaround for IUS 5.5 part-select issue
+          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
+        end else begin
+          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
+            memory[address*WRITE_WIDTH_RATIO_B + i]
+              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];
+          end
+        end
+      end
+    end
+  endtask
+
+  //**************
+  // read_a
+  //**************
+  task read_a
+    (input reg [C_ADDRA_WIDTH-1:0] addr,
+     input reg reset);
+    reg [C_ADDRA_WIDTH-1:0] address;
+    integer i;
+  begin
+
+    if (reset) begin
+      memory_out_a <= #FLOP_DELAY inita_val;
+    end else begin
+      // Shift the address by the ratio
+      address = (addr/READ_ADDR_A_DIV);
+      if (address >= C_READ_DEPTH_A) begin
+        if (!C_DISABLE_WARN_BHV_RANGE) begin
+          $fdisplay(ADDRFILE,
+                    "%0s WARNING: Address %0h is outside range for A Read",
+                    C_CORENAME, addr);
+        end
+        memory_out_a <= #FLOP_DELAY 'bX;
+      // valid address
+      end else begin
+        if (READ_WIDTH_RATIO_A==1) begin
+          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
+        end else begin
+          // Increment through the 'partial' words in the memory
+          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
+            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
+              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
+          end
+        end //end READ_WIDTH_RATIO_A==1 loop
+
+      end //end valid address loop
+    end //end reset-data assignment loops
+  end
+  endtask
+
+  //**************
+  // read_b
+  //**************
+  task read_b
+    (input reg [C_ADDRB_WIDTH-1:0] addr,
+     input reg reset);
+    reg [C_ADDRB_WIDTH-1:0] address;
+    integer i;
+    begin
+
+    if (reset) begin
+      memory_out_b <= #FLOP_DELAY initb_val;
+      sbiterr_in   <= #FLOP_DELAY 1'b0;
+      dbiterr_in   <= #FLOP_DELAY 1'b0;
+      rdaddrecc_in <= #FLOP_DELAY 0;
+    end else begin
+      // Shift the address
+      address = (addr/READ_ADDR_B_DIV);
+      if (address >= C_READ_DEPTH_B) begin
+        if (!C_DISABLE_WARN_BHV_RANGE) begin
+          $fdisplay(ADDRFILE,
+                    "%0s WARNING: Address %0h is outside range for B Read",
+                    C_CORENAME, addr);
+        end
+        memory_out_b <= #FLOP_DELAY 'bX;
+        sbiterr_in <= #FLOP_DELAY 1'bX;
+        dbiterr_in <= #FLOP_DELAY 1'bX;
+        rdaddrecc_in <= #FLOP_DELAY 'bX;
+        // valid address
+      end else begin
+        if (READ_WIDTH_RATIO_B==1) begin
+          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
+        end else begin
+          // Increment through the 'partial' words in the memory
+          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
+            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
+              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
+          end
+        end
+
+        if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
+          rdaddrecc_in <= #FLOP_DELAY addr;
+          if (sbiterr_arr[addr] == 1) begin
+            sbiterr_in <= #FLOP_DELAY 1'b1;
+          end else begin
+            sbiterr_in <= #FLOP_DELAY 1'b0;
+          end
+
+          if (dbiterr_arr[addr] == 1) begin
+            dbiterr_in <= #FLOP_DELAY 1'b1;
+          end else begin
+            dbiterr_in <= #FLOP_DELAY 1'b0;
+          end
+
+         end else  if (C_USE_SOFTECC == 1) begin
+          rdaddrecc_in <= #FLOP_DELAY addr;
+          if (softecc_sbiterr_arr[addr] == 1) begin
+            sbiterr_in <= #FLOP_DELAY 1'b1;
+          end else begin
+            sbiterr_in <= #FLOP_DELAY 1'b0;
+          end
+
+          if (softecc_dbiterr_arr[addr] == 1) begin
+            dbiterr_in <= #FLOP_DELAY 1'b1;
+          end else begin
+            dbiterr_in <= #FLOP_DELAY 1'b0;
+          end
+        end else begin
+          rdaddrecc_in <= #FLOP_DELAY 0;
+          dbiterr_in <= #FLOP_DELAY 1'b0;
+          sbiterr_in <= #FLOP_DELAY 1'b0;
+        end //end SOFTECC Loop
+      end //end Valid address loop
+    end //end reset-data assignment loops
+  end
+  endtask
+
+  //**************
+  // reset_a
+  //**************
+  task reset_a (input reg reset);
+  begin
+    if (reset) memory_out_a <= #FLOP_DELAY inita_val;
+  end
+  endtask
+
+  //**************
+  // reset_b
+  //**************
+  task reset_b (input reg reset);
+  begin
+    if (reset) memory_out_b <= #FLOP_DELAY initb_val;
+  end
+  endtask
+
+  //**************
+  // init_memory
+  //**************
+  task init_memory;
+    integer i, j, addr_step;
+    integer status;
+    reg [C_WRITE_WIDTH_A-1:0] default_data;
+    begin
+      default_data = 0;
+
+      //Display output message indicating that the behavioral model is being 
+      //initialized
+      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
+
+      // Convert the default to hex
+      if (C_USE_DEFAULT_DATA) begin
+        if (default_data_str == "") begin
+         $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
+          $finish;
+        end else begin
+          status = $sscanf(default_data_str, "%h", default_data);
+          if (status == 0) begin
+            $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
+                                "from C_DEFAULT_DATA: %0s"},
+                      C_CORENAME, C_DEFAULT_DATA);
+            $finish;
+          end
+        end
+      end
+
+      // Step by WRITE_ADDR_A_DIV through the memory via the
+      // Port A write interface to hit every location once
+      addr_step = WRITE_ADDR_A_DIV;
+
+      // 'write' to every location with default (or 0)
+      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
+        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
+      end
+
+      // Get specialized data from the MIF file
+      if (C_LOAD_INIT_FILE) begin
+        if (init_file_str == "") begin
+          $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
+                    C_CORENAME);
+          $finish;
+        end else begin
+          initfile = $fopen(init_file_str, "r");
+          if (initfile == 0) begin
+            $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
+                                "C_INIT_FILE_NAME: %0s!"},
+                      C_CORENAME, init_file_str);
+            $finish;
+          end else begin
+            // loop through the mif file, loading in the data
+            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
+              status = $fscanf(initfile, "%b", mif_data);
+              if (status > 0) begin
+                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
+              end
+            end
+            $fclose(initfile);
+          end //initfile
+        end //init_file_str
+      end //C_LOAD_INIT_FILE
+
+
+      if (C_USE_BRAM_BLOCK) begin
+            // Get specialized data from the MIF file
+            if (C_INIT_FILE != "NONE") begin
+              if (mem_init_file_str == "") begin
+                $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
+                          C_CORENAME);
+                $finish;
+              end else begin
+                meminitfile = $fopen(mem_init_file_str, "r");
+                if (meminitfile == 0) begin
+                  $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
+                                      "C_INIT_FILE: %0s!"},
+                            C_CORENAME, mem_init_file_str);
+                  $finish;
+                end else begin
+                  // loop through the mif file, loading in the data
+                    $readmemh(mem_init_file_str, memory );
+                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
+                      end 
+                  $fclose(meminitfile);
+                end //meminitfile
+              end //mem_init_file_str
+            end //C_INIT_FILE
+      end //C_USE_BRAM_BLOCK
+
+      //Display output message indicating that the behavioral model is done 
+      //initializing
+      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) 
+          $display(" Block Memory Generator data initialization complete.");
+    end
+  endtask
+
+  //**************
+  // log2roundup
+  //**************
+  function integer log2roundup (input integer data_value);
+      integer width;
+      integer cnt;
+      begin
+         width = 0;
+
+         if (data_value > 1) begin
+            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
+               width = width + 1;
+            end //loop
+         end //if
+
+         log2roundup = width;
+
+      end //log2roundup
+   endfunction
+
+
+  //*******************
+  // collision_check
+  //*******************
+  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
+                                    input integer iswrite_a,
+                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,
+                                    input integer iswrite_b);
+    reg c_aw_bw, c_aw_br, c_ar_bw;
+    integer scaled_addra_to_waddrb_width;
+    integer scaled_addrb_to_waddrb_width;
+    integer scaled_addra_to_waddra_width;
+    integer scaled_addrb_to_waddra_width;
+    integer scaled_addra_to_raddrb_width;
+    integer scaled_addrb_to_raddrb_width;
+    integer scaled_addra_to_raddra_width;
+    integer scaled_addrb_to_raddra_width;
+
+
+
+    begin
+
+    c_aw_bw = 0;
+    c_aw_br = 0;
+    c_ar_bw = 0;
+
+    //If write_addr_b_width is smaller, scale both addresses to that width for 
+    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
+    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
+    //scale it down to write_addr_b_width. Once both are scaled to 
+    //write_addr_b_width, compare.
+    scaled_addra_to_waddrb_width  = ((addr_a)/
+                                        2**(C_ADDRA_WIDTH-write_addr_b_width));
+    scaled_addrb_to_waddrb_width  = ((addr_b)/
+                                        2**(C_ADDRB_WIDTH-write_addr_b_width));
+
+    //If write_addr_a_width is smaller, scale both addresses to that width for 
+    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
+    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
+    //scale it down to write_addr_a_width. Once both are scaled to 
+    //write_addr_a_width, compare.
+    scaled_addra_to_waddra_width  = ((addr_a)/
+                                        2**(C_ADDRA_WIDTH-write_addr_a_width));
+    scaled_addrb_to_waddra_width  = ((addr_b)/
+                                        2**(C_ADDRB_WIDTH-write_addr_a_width));
+
+    //If read_addr_b_width is smaller, scale both addresses to that width for 
+    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
+    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
+    //scale it down to read_addr_b_width. Once both are scaled to 
+    //read_addr_b_width, compare.
+    scaled_addra_to_raddrb_width  = ((addr_a)/
+                                         2**(C_ADDRA_WIDTH-read_addr_b_width));
+    scaled_addrb_to_raddrb_width  = ((addr_b)/
+                                         2**(C_ADDRB_WIDTH-read_addr_b_width));
+
+    //If read_addr_a_width is smaller, scale both addresses to that width for 
+    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
+    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
+    //scale it down to read_addr_a_width. Once both are scaled to 
+    //read_addr_a_width, compare.
+    scaled_addra_to_raddra_width  = ((addr_a)/
+                                         2**(C_ADDRA_WIDTH-read_addr_a_width));
+    scaled_addrb_to_raddra_width  = ((addr_b)/
+                                         2**(C_ADDRB_WIDTH-read_addr_a_width));
+
+    //Look for a write-write collision. In order for a write-write
+    //collision to exist, both ports must have a write transaction.
+    if (iswrite_a && iswrite_b) begin
+      if (write_addr_a_width > write_addr_b_width) begin
+        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
+          c_aw_bw = 1;
+        end else begin
+          c_aw_bw = 0;
+        end
+      end else begin
+        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
+          c_aw_bw = 1;
+        end else begin
+          c_aw_bw = 0;
+        end
+      end //width
+    end //iswrite_a and iswrite_b
+
+    //If the B port is reading (which means it is enabled - so could be
+    //a TX_WRITE or TX_READ), then check for a write-read collision).
+    //This could happen whether or not a write-write collision exists due
+    //to asymmetric write/read ports.
+    if (iswrite_a) begin
+      if (write_addr_a_width > read_addr_b_width) begin
+        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
+          c_aw_br = 1;
+        end else begin
+          c_aw_br = 0;
+        end
+    end else begin
+        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
+          c_aw_br = 1;
+        end else begin
+          c_aw_br = 0;
+        end
+      end //width
+    end //iswrite_a
+
+    //If the A port is reading (which means it is enabled - so could be
+    //  a TX_WRITE or TX_READ), then check for a write-read collision).
+    //This could happen whether or not a write-write collision exists due
+    //  to asymmetric write/read ports.
+    if (iswrite_b) begin
+      if (read_addr_a_width > write_addr_b_width) begin
+        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
+          c_ar_bw = 1;
+        end else begin
+          c_ar_bw = 0;
+        end
+      end else begin
+        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
+          c_ar_bw = 1;
+        end else begin
+          c_ar_bw = 0;
+        end
+      end //width
+    end //iswrite_b
+
+
+
+      collision_check = c_aw_bw | c_aw_br | c_ar_bw;
+
+    end
+  endfunction
+
+  //*******************************
+  // power on values
+  //*******************************
+  initial begin
+    // Load up the memory
+    init_memory;
+    // Load up the output registers and latches
+    if ($sscanf(inita_str, "%h", inita_val)) begin
+      memory_out_a = inita_val;
+    end else begin
+      memory_out_a = 0;
+    end
+    if ($sscanf(initb_str, "%h", initb_val)) begin
+      memory_out_b = initb_val;
+    end else begin
+      memory_out_b = 0;
+    end
+
+    sbiterr_in   = 1'b0;
+    dbiterr_in   = 1'b0;
+    rdaddrecc_in = 0;
+
+    // Determine the effective address widths for each of the 4 ports
+    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
+    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
+    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
+    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
+
+    $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
+
+  end
+
+  //***************************************************************************
+  // These are the main blocks which schedule read and write operations
+  // Note that the reset priority feature at the latch stage is only supported
+  // for Spartan-6. For other families, the default priority at the latch stage
+  // is "CE"
+  //***************************************************************************
+      // Synchronous clocks: schedule port operations with respect to
+      // both write operating modes
+  generate
+    if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
+                    "WRITE_FIRST")) begin : com_clk_sched_wf_wf
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        
+        if (rea_i) read_a(ADDRA, reseta_i);
+ 
+       //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+      end
+    end
+    else 
+    if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
+                    "WRITE_FIRST")) begin : com_clk_sched_rf_wf
+      always @(posedge CLKA) begin
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        //Read B
+         if (reb_i) read_b(ADDRB, resetb_i);
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+      end
+    end
+    else 
+    if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
+                    "READ_FIRST")) begin : com_clk_sched_wf_rf
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+      end
+    end
+    else 
+    if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
+                    "READ_FIRST")) begin : com_clk_sched_rf_rf
+      always @(posedge CLKA) begin
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+      end
+    end
+    else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
+                    "NO_CHANGE")) begin : com_clk_sched_wf_nc
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+      end
+    end
+    else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
+                    "NO_CHANGE")) begin : com_clk_sched_rf_nc
+      always @(posedge CLKA) begin
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+      end
+    end
+    else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
+                    "WRITE_FIRST")) begin : com_clk_sched_nc_wf
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        //Read A
+          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+      end
+    end
+    else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == 
+                    "READ_FIRST")) begin : com_clk_sched_nc_rf
+      always @(posedge CLKA) begin
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+        //Read A
+          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+      end
+    end
+    else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
+                    "NO_CHANGE")) begin : com_clk_sched_nc_nc
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        //Read A
+          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
+      end
+    end
+    else if(C_COMMON_CLK) begin: com_clk_sched_default
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+      end
+    end
+  endgenerate
+
+      // Asynchronous clocks: port operation is independent
+  generate
+    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Read A
+          if (rea_i) read_a(ADDRA, reseta_i);
+      end
+    end
+    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
+      always @(posedge CLKA) begin
+        //Read A
+        if (rea_i) read_a(ADDRA, reseta_i);
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+      end
+    end
+    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
+      always @(posedge CLKA) begin
+        //Write A
+        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
+        //Read A
+         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
+      end
+    end
+  endgenerate
+
+  generate 
+    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
+      always @(posedge CLKB) begin
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+      end
+    end
+    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
+      always @(posedge CLKB) begin
+        //Read B
+          if (reb_i) read_b(ADDRB, resetb_i);
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+      end
+    end
+    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
+      always @(posedge CLKB) begin
+        //Write B
+        if (web_i) write_b(ADDRB, web_i, DINB);
+        //Read B
+          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
+      end
+    end
+  endgenerate
+
+  
+  //***************************************************************
+  //  Instantiate the variable depth output register stage module
+  //***************************************************************
+  // Port A
+  
+  assign rsta_outp_stage = RSTA & (~SLEEP);
+
+  blk_mem_gen_v8_4_4_output_stage
+    #(.C_FAMILY                 (C_FAMILY),
+      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),
+      .C_RST_TYPE               ("SYNC"),
+      .C_HAS_RST                (C_HAS_RSTA),
+      .C_RSTRAM                 (C_RSTRAM_A),
+      .C_RST_PRIORITY           (C_RST_PRIORITY_A),
+      .C_INIT_VAL               (C_INITA_VAL),
+      .C_HAS_EN                 (C_HAS_ENA),
+      .C_HAS_REGCE              (C_HAS_REGCEA),
+      .C_DATA_WIDTH             (C_READ_WIDTH_A),
+      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),
+      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),
+      .C_USE_SOFTECC            (C_USE_SOFTECC),
+      .C_USE_ECC                (C_USE_ECC),
+      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),
+	  .C_EN_ECC_PIPE            (0),
+      .FLOP_DELAY               (FLOP_DELAY))
+      reg_a
+        (.CLK         (CLKA),
+         .RST         (rsta_outp_stage),//(RSTA),
+         .EN          (ENA),
+         .REGCE       (REGCEA),
+         .DIN_I       (memory_out_a),
+         .DOUT        (DOUTA),
+         .SBITERR_IN_I  (1'b0),
+         .DBITERR_IN_I  (1'b0),
+         .SBITERR     (),
+         .DBITERR     (),
+         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
+		 .ECCPIPECE (1'b0),
+         .RDADDRECC   ()
+        );
+
+  assign rstb_outp_stage = RSTB & (~SLEEP);
+
+  // Port B 
+  blk_mem_gen_v8_4_4_output_stage
+    #(.C_FAMILY                 (C_FAMILY),
+      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),
+      .C_RST_TYPE               ("SYNC"),
+      .C_HAS_RST                (C_HAS_RSTB),
+      .C_RSTRAM                 (C_RSTRAM_B),
+      .C_RST_PRIORITY           (C_RST_PRIORITY_B),
+      .C_INIT_VAL               (C_INITB_VAL),
+      .C_HAS_EN                 (C_HAS_ENB),
+      .C_HAS_REGCE              (C_HAS_REGCEB),
+      .C_DATA_WIDTH             (C_READ_WIDTH_B),
+      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),
+      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),
+      .C_USE_SOFTECC            (C_USE_SOFTECC),
+      .C_USE_ECC                (C_USE_ECC),
+      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),
+      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),
+      .FLOP_DELAY               (FLOP_DELAY))
+      reg_b
+        (.CLK         (CLKB),
+         .RST         (rstb_outp_stage),//(RSTB),
+         .EN          (ENB),
+         .REGCE       (REGCEB),
+         .DIN_I       (memory_out_b),
+         .DOUT        (dout_i),
+         .SBITERR_IN_I  (sbiterr_in),
+         .DBITERR_IN_I  (dbiterr_in),
+         .SBITERR     (sbiterr_i),
+         .DBITERR     (dbiterr_i),
+         .RDADDRECC_IN_I (rdaddrecc_in),
+         .ECCPIPECE   (ECCPIPECE),
+         .RDADDRECC   (rdaddrecc_i)
+        );
+
+  //***************************************************************
+  //  Instantiate the Input and Output register stages
+  //***************************************************************
+blk_mem_gen_v8_4_4_softecc_output_reg_stage
+    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),
+      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),
+      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),
+      .C_USE_SOFTECC                (C_USE_SOFTECC),
+      .FLOP_DELAY                   (FLOP_DELAY))
+  has_softecc_output_reg_stage
+      (.CLK       (CLKB),
+      .DIN        (dout_i),
+      .DOUT        (DOUTB),
+      .SBITERR_IN        (sbiterr_i),
+      .DBITERR_IN        (dbiterr_i),
+      .SBITERR        (sbiterr_sdp),
+      .DBITERR        (dbiterr_sdp),
+      .RDADDRECC_IN        (rdaddrecc_i),
+      .RDADDRECC        (rdaddrecc_sdp)
+);
+
+  //****************************************************
+  // Synchronous collision checks
+  //****************************************************
+// CR 780544 : To make verilog model's collison warnings in consistant with
+// vhdl model, the non-blocking assignments are replaced with blocking 
+// assignments.
+  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
+    always @(posedge CLKA) begin
+      // Possible collision if both are enabled and the addresses match
+      if (ena_i && enb_i) begin
+        if (wea_i || web_i) begin
+          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
+        end else begin
+          is_collision = 0;
+        end
+      end else begin
+          is_collision = 0;
+      end
+
+      // If the write port is in READ_FIRST mode, there is no collision
+      if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
+        is_collision = 0;
+      end
+      if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
+        is_collision = 0;
+      end
+
+      // Only flag if one of the accesses is a write
+      if (is_collision && (wea_i || web_i)) begin
+        $fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B %0s address: %0h\n",
+                wea_i ? "write" : "read", ADDRA,
+                web_i ? "write" : "read", ADDRB);
+      end
+    end
+
+  //****************************************************
+  // Asynchronous collision checks
+  //****************************************************
+  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
+
+    // Delay A and B addresses in order to mimic setup/hold times
+    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;
+    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;
+    wire                      #COLL_DELAY ena_delay   = ena_i;
+    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;
+    wire [0:0]                #COLL_DELAY web_delay   = web_i;
+    wire                      #COLL_DELAY enb_delay   = enb_i;
+
+    // Do the checks w/rt A
+    always @(posedge CLKA) begin
+      // Possible collision if both are enabled and the addresses match
+      if (ena_i && enb_i) begin
+        if (wea_i || web_i) begin
+          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
+        end else begin
+          is_collision_a = 0;
+        end
+      end else begin
+        is_collision_a = 0;
+      end
+
+      if (ena_i && enb_delay) begin
+        if(wea_i || web_delay) begin
+          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
+                                                                    web_delay);
+        end else begin
+          is_collision_delay_a = 0;
+        end
+      end else begin
+        is_collision_delay_a = 0;
+      end
+
+      // Only flag if B access is a write
+      if (is_collision_a && web_i) begin
+        $fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n",
+                wea_i ? "write" : "read", ADDRA, ADDRB);
+
+      end else if (is_collision_delay_a && web_delay) begin
+        $fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n",
+                wea_i ? "write" : "read", ADDRA, addrb_delay);
+      end
+
+    end
+
+    // Do the checks w/rt B
+    always @(posedge CLKB) begin
+
+      // Possible collision if both are enabled and the addresses match
+      if (ena_i && enb_i) begin
+        if (wea_i || web_i) begin
+          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
+        end else begin
+          is_collision_b = 0;
+        end
+      end else begin
+        is_collision_b = 0;
+      end
+
+      if (ena_delay && enb_i) begin
+        if (wea_delay || web_i) begin
+          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
+                                                                        web_i);
+        end else begin
+          is_collision_delay_b = 0;
+        end
+      end else begin
+        is_collision_delay_b = 0;
+      end
+
+
+      // Only flag if A access is a write
+      if (is_collision_b && wea_i) begin
+        $fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n",
+                ADDRA, web_i ? "write" : "read", ADDRB);
+
+      end else if (is_collision_delay_b && wea_delay) begin
+        $fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n",
+                addra_delay, web_i ? "write" : "read", ADDRB);
+      end
+
+    end
+  end
+  endgenerate
+
+endmodule
+//*****************************************************************************
+// Top module wraps Input register and Memory module
+//
+// This module is the top-level behavioral model and this implements the memory 
+// module and the input registers
+//*****************************************************************************
+module blk_mem_gen_v8_4_4
+  #(parameter C_CORENAME                = "blk_mem_gen_v8_4_4",
+    parameter C_FAMILY                  = "virtex7",
+    parameter C_XDEVICEFAMILY           = "virtex7",
+    parameter C_ELABORATION_DIR         = "",
+    parameter C_INTERFACE_TYPE          = 0,
+    parameter C_USE_BRAM_BLOCK          = 0,
+    parameter C_CTRL_ECC_ALGO           = "NONE",
+    parameter C_ENABLE_32BIT_ADDRESS    = 0,
+    parameter C_AXI_TYPE                = 0,
+    parameter C_AXI_SLAVE_TYPE          = 0,
+    parameter C_HAS_AXI_ID              = 0,
+    parameter C_AXI_ID_WIDTH            = 4,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_INIT_FILE               = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    //parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL               = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL               = "",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
+    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_SOFTECC             = 0,
+    parameter C_READ_LATENCY_A          = 1,
+    parameter C_READ_LATENCY_B          = 1,
+    parameter C_USE_ECC                 = 0,
+	parameter C_EN_ECC_PIPE             = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+	parameter C_EN_SLEEP_PIN            = 0,
+    parameter C_USE_URAM                = 0,
+    parameter C_EN_RDADDRA_CHG          = 0,
+    parameter C_EN_RDADDRB_CHG          = 0,
+    parameter C_EN_DEEPSLEEP_PIN        = 0,
+    parameter C_EN_SHUTDOWN_PIN         = 0,
+	parameter C_EN_SAFETY_CKT           = 0,
+	parameter C_COUNT_36K_BRAM          = "",
+	parameter C_COUNT_18K_BRAM          = "",
+	parameter C_EST_POWER_SUMMARY       = "",
+	parameter C_DISABLE_WARN_BHV_RANGE  = 0
+	
+  )
+  (input                       clka,
+   input                       rsta,
+   input                       ena,
+   input                       regcea,
+   input [C_WEA_WIDTH-1:0]     wea,
+   input [C_ADDRA_WIDTH-1:0]   addra,
+   input [C_WRITE_WIDTH_A-1:0] dina,
+   output [C_READ_WIDTH_A-1:0] douta,
+   input                       clkb,
+   input                       rstb,
+   input                       enb,
+   input                       regceb,
+   input [C_WEB_WIDTH-1:0]     web,
+   input [C_ADDRB_WIDTH-1:0]   addrb,
+   input [C_WRITE_WIDTH_B-1:0] dinb,
+   output [C_READ_WIDTH_B-1:0] doutb,
+   input                       injectsbiterr,
+   input                       injectdbiterr,
+   output                      sbiterr,
+   output                      dbiterr,
+   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,
+   input                       eccpipece,
+   input                       sleep,
+   input                       deepsleep,
+   input                       shutdown,
+   output                      rsta_busy, 
+   output                      rstb_busy, 
+   //AXI BMG Input and Output Port Declarations
+ 
+   //AXI Global Signals
+   input                         s_aclk,
+   input                         s_aresetn,
+ 
+   //AXI                        Full/lite slave write (write side)
+   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,
+   input  [31:0]                 s_axi_awaddr,
+   input  [7:0]                  s_axi_awlen,
+   input  [2:0]                  s_axi_awsize,
+   input  [1:0]                  s_axi_awburst,
+   input                         s_axi_awvalid,
+   output                        s_axi_awready,
+   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,
+   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,
+   input                         s_axi_wlast,
+   input                         s_axi_wvalid,
+   output                        s_axi_wready,
+   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,
+   output [1:0]                  s_axi_bresp,
+   output                        s_axi_bvalid,
+   input                         s_axi_bready,
+ 
+   //AXI                        Full/lite slave read (write side)
+   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,
+   input  [31:0]                 s_axi_araddr,
+   input  [7:0]                  s_axi_arlen,
+   input  [2:0]                  s_axi_arsize,
+   input  [1:0]                  s_axi_arburst,
+   input                         s_axi_arvalid,
+   output                        s_axi_arready,
+   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,
+   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,
+   output [1:0]                  s_axi_rresp,
+   output                        s_axi_rlast,
+   output                        s_axi_rvalid,
+   input                         s_axi_rready,
+ 
+   //AXI                        Full/lite sideband signals
+   input                         s_axi_injectsbiterr,
+   input                         s_axi_injectdbiterr,
+   output                        s_axi_sbiterr,
+   output                        s_axi_dbiterr,
+   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc 
+ 
+  );
+//******************************
+// Port and Generic Definitions
+//******************************
+  //////////////////////////////////////////////////////////////////////////
+  // Generic Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // C_CORENAME              : Instance name of the Block Memory Generator core
+  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
+  //                           options are available - "spartan3", "spartan6", 
+  //                           "virtex4", "virtex5", "virtex6" and "virtex6l".
+  // C_MEM_TYPE              : Designates memory type.
+  //                           It can be
+  //                           0 - Single Port Memory
+  //                           1 - Simple Dual Port Memory
+  //                           2 - True Dual Port Memory
+  //                           3 - Single Port Read Only Memory
+  //                           4 - Dual Port Read Only Memory
+  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)
+  // C_ALGORITHM             : Designates the algorithm method used
+  //                           for constructing the memory.
+  //                           It can be Fixed_Primitives, Minimum_Area or 
+  //                           Low_Power
+  // C_PRIM_TYPE             : Designates the user selected primitive used to 
+  //                           construct the memory.
+  //
+  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to
+  //                           initialize memory contents.
+  // C_INIT_FILE_NAME        : Memory initialization file name.
+  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining
+  //                           initialization space with default data
+  // C_DEFAULT_DATA          : Default value of all memory locations
+  //                           not initialized by the memory
+  //                           initialization file.
+  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous
+  // C_HAS_RSTA              : Determines the presence of the RSTA port
+  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for 
+  //                           Port A.
+  // C_RSTRAM_A              : Determines if special reset behavior is used for
+  //                           Port A
+  // C_INITA_VAL             : The initialization value for Port A
+  // C_HAS_ENA               : Determines the presence of the ENA port
+  // C_HAS_REGCEA            : Determines the presence of the REGCEA port
+  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.
+  // C_WEA_WIDTH             : The width of the WEA port
+  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be
+  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.
+  // C_WRITE_WIDTH_A         : Memory write width for Port A.
+  // C_READ_WIDTH_A          : Memory read width for Port A.
+  // C_WRITE_DEPTH_A         : Memory write depth for Port A.
+  // C_READ_DEPTH_A          : Memory read depth for Port A.
+  // C_ADDRA_WIDTH           : Width of the ADDRA input port
+  // C_HAS_RSTB              : Determines the presence of the RSTB port
+  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for 
+  //                           Port B.
+  // C_RSTRAM_B              : Determines if special reset behavior is used for
+  //                           Port B
+  // C_INITB_VAL             : The initialization value for Port B
+  // C_HAS_ENB               : Determines the presence of the ENB port
+  // C_HAS_REGCEB            : Determines the presence of the REGCEB port
+  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.
+  // C_WEB_WIDTH             : The width of the WEB port
+  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be
+  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.
+  // C_WRITE_WIDTH_B         : Memory write width for Port B.
+  // C_READ_WIDTH_B          : Memory read width for Port B.
+  // C_WRITE_DEPTH_B         : Memory write depth for Port B.
+  // C_READ_DEPTH_B          : Memory read depth for Port B.
+  // C_ADDRB_WIDTH           : Width of the ADDRB input port
+  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output 
+  //                           of the RAM primitive for Port A.
+  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output 
+  //                           of the RAM primitive for Port B.
+  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
+  //                           of the MUX for Port A.
+  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
+  //                           of the MUX for Port B.
+  // C_HAS_SOFTECC_INPUT_REGS_A  : 
+  // C_HAS_SOFTECC_OUTPUT_REGS_B : 
+  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in 
+  //                           between the muxes.
+  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or
+  //                           not. Only applicable Spartan-6
+  // C_USE_ECC               : Determines if the ECC feature is used or
+  //                           not. Only applicable for V5 and V6
+  // C_HAS_INJECTERR         : Determines if the error injection pins
+  //                           are present or not. If the ECC feature
+  //                           is not used, this value is defaulted to
+  //                           0, else the following are the allowed 
+  //                           values:
+  //                         0 : No INJECTSBITERR or INJECTDBITERR pins
+  //                         1 : Only INJECTSBITERR pin exists
+  //                         2 : Only INJECTDBITERR pin exists
+  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist
+  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision
+  //                           warnings. It can be "ALL", "NONE", 
+  //                           "Warnings_Only" or "Generate_X_Only".
+  // C_COMMON_CLK            : Determins if the core has a single CLK input.
+  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
+  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range 
+  //                           warnings
+  //////////////////////////////////////////////////////////////////////////
+  // Port Definitions
+  //////////////////////////////////////////////////////////////////////////
+  // CLKA    : Clock to synchronize all read and write operations of Port A.
+  // RSTA    : Reset input to reset memory outputs to a user-defined 
+  //           reset state for Port A.
+  // ENA     : Enable all read and write operations of Port A.
+  // REGCEA  : Register Clock Enable to control each pipeline output
+  //           register stages for Port A.
+  // WEA     : Write Enable to enable all write operations of Port A.
+  // ADDRA   : Address of Port A.
+  // DINA    : Data input of Port A.
+  // DOUTA   : Data output of Port A.
+  // CLKB    : Clock to synchronize all read and write operations of Port B.
+  // RSTB    : Reset input to reset memory outputs to a user-defined 
+  //           reset state for Port B.
+  // ENB     : Enable all read and write operations of Port B.
+  // REGCEB  : Register Clock Enable to control each pipeline output
+  //           register stages for Port B.
+  // WEB     : Write Enable to enable all write operations of Port B.
+  // ADDRB   : Address of Port B.
+  // DINB    : Data input of Port B.
+  // DOUTB   : Data output of Port B.
+  // INJECTSBITERR : Single Bit ECC Error Injection Pin.
+  // INJECTDBITERR : Double Bit ECC Error Injection Pin.
+  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been
+  //                 detected and corrected.
+  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been
+  //                 detected.
+  // RDADDRECC     : Read Address Output signal indicating address at which an
+  //                 ECC error has occurred.
+  //////////////////////////////////////////////////////////////////////////
+
+  wire SBITERR;
+  wire DBITERR;
+  wire S_AXI_AWREADY;
+  wire S_AXI_WREADY;
+  wire S_AXI_BVALID;
+  wire S_AXI_ARREADY;
+  wire S_AXI_RLAST;
+  wire S_AXI_RVALID;
+  wire S_AXI_SBITERR;
+  wire S_AXI_DBITERR;
+
+  wire [C_WEA_WIDTH-1:0]       WEA              = wea;
+  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;
+  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;
+  wire [C_READ_WIDTH_A-1:0]    DOUTA;
+  wire [C_WEB_WIDTH-1:0]       WEB              = web;
+  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;
+  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;
+  wire [C_READ_WIDTH_B-1:0]    DOUTB;
+  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;
+  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;
+  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;
+  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;
+  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;
+  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;
+  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;
+  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;
+  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;
+  wire [1:0]                   S_AXI_BRESP;
+  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;
+  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;
+  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;
+  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;
+  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;
+  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;
+  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;
+  wire [1:0]                   S_AXI_RRESP;
+  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;
+  // Added to fix the simulation warning #CR731605
+  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;
+  wire                         ECCPIPECE;
+  wire                         SLEEP;
+  reg                          RSTA_BUSY = 0;
+  reg                          RSTB_BUSY = 0;
+  // Declaration of internal signals to avoid warnings #927399
+  wire                         CLKA;
+  wire                         RSTA;
+  wire                         ENA;
+  wire                         REGCEA;
+  wire                         CLKB;
+  wire                         RSTB;
+  wire                         ENB;
+  wire                         REGCEB;
+  wire                         INJECTSBITERR;
+  wire                         INJECTDBITERR;
+  wire                         S_ACLK;
+  wire                         S_ARESETN;
+  wire                         S_AXI_AWVALID;
+  wire                         S_AXI_WLAST;
+  wire                         S_AXI_WVALID;
+  wire                         S_AXI_BREADY;
+  wire                         S_AXI_ARVALID;
+  wire                         S_AXI_RREADY;
+  wire                         S_AXI_INJECTSBITERR;
+  wire                         S_AXI_INJECTDBITERR;
+
+  assign CLKA                 = clka;
+  assign RSTA                 = rsta;
+  assign ENA                  = ena;
+  assign REGCEA               = regcea;
+  assign CLKB                 = clkb;
+  assign RSTB                 = rstb;
+  assign ENB                  = enb;
+  assign REGCEB               = regceb;
+  assign INJECTSBITERR        = injectsbiterr;
+  assign INJECTDBITERR        = injectdbiterr;
+  assign ECCPIPECE            = eccpipece;
+  assign SLEEP                = sleep;
+  assign sbiterr              = SBITERR;
+  assign dbiterr              = DBITERR;
+  assign S_ACLK               = s_aclk;
+  assign S_ARESETN            = s_aresetn;
+  assign S_AXI_AWVALID        = s_axi_awvalid;
+  assign s_axi_awready        = S_AXI_AWREADY;
+  assign S_AXI_WLAST          = s_axi_wlast;
+  assign S_AXI_WVALID         = s_axi_wvalid;
+  assign s_axi_wready         = S_AXI_WREADY;
+  assign s_axi_bvalid         = S_AXI_BVALID;
+  assign S_AXI_BREADY         = s_axi_bready;
+  assign S_AXI_ARVALID        = s_axi_arvalid;
+  assign s_axi_arready        = S_AXI_ARREADY;
+  assign s_axi_rlast          = S_AXI_RLAST;
+  assign s_axi_rvalid         = S_AXI_RVALID;
+  assign S_AXI_RREADY         = s_axi_rready;
+  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;
+  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;
+  assign s_axi_sbiterr        = S_AXI_SBITERR;
+  assign s_axi_dbiterr        = S_AXI_DBITERR;
+
+  assign rsta_busy            = RSTA_BUSY;
+  assign rstb_busy            = RSTB_BUSY;
+
+  assign doutb            = DOUTB;
+  assign douta            = DOUTA;
+  assign rdaddrecc        = RDADDRECC;
+  assign s_axi_bid        = S_AXI_BID;
+  assign s_axi_bresp      = S_AXI_BRESP;
+  assign s_axi_rid        = S_AXI_RID;
+  assign s_axi_rdata      = S_AXI_RDATA;
+  assign s_axi_rresp      = S_AXI_RRESP;
+  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;
+
+  localparam FLOP_DELAY  = 100;  // 100 ps
+
+   reg                       injectsbiterr_in;
+   reg                       injectdbiterr_in;
+   reg                       rsta_in;
+   reg                       ena_in;
+   reg                       regcea_in;
+   reg [C_WEA_WIDTH-1:0]     wea_in;
+   reg [C_ADDRA_WIDTH-1:0]   addra_in;
+   reg [C_WRITE_WIDTH_A-1:0] dina_in;
+
+  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
+  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
+  wire s_axi_wr_en_c;
+  wire s_axi_rd_en_c;
+  wire s_aresetn_a_c;
+  wire [7:0] s_axi_arlen_c ;
+
+
+  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
+  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
+  wire [1:0] s_axi_rresp_c;
+  wire s_axi_rlast_c;
+  wire s_axi_rvalid_c;
+  wire s_axi_rready_c;
+  wire regceb_c;
+
+  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
+  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
+  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
+
+// Safety logic related signals
+
+  reg [4:0] RSTA_SHFT_REG = 0;
+  reg POR_A = 0; 
+  reg [4:0] RSTB_SHFT_REG = 0;
+  reg POR_B = 0;
+ 
+  reg ENA_dly = 0;
+  reg ENA_dly_D = 0;
+
+  reg ENB_dly = 0;
+  reg ENB_dly_D = 0;
+
+  wire RSTA_I_SAFE;
+  wire RSTB_I_SAFE;
+
+  wire ENA_I_SAFE;
+  wire ENB_I_SAFE;
+  
+  reg ram_rstram_a_busy = 0;
+  reg ram_rstreg_a_busy = 0;
+  reg ram_rstram_b_busy = 0;
+  reg ram_rstreg_b_busy = 0;
+
+  reg ENA_dly_reg = 0;
+  reg ENB_dly_reg = 0;
+ 
+  reg ENA_dly_reg_D = 0;
+  reg ENB_dly_reg_D = 0;
+
+  //**************
+  // log2roundup
+  //**************
+  function integer log2roundup (input integer data_value);
+      integer width;
+      integer cnt;
+      begin
+         width = 0;
+
+         if (data_value > 1) begin
+            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
+               width = width + 1;
+            end //loop
+         end //if
+
+         log2roundup = width;
+
+      end //log2roundup
+   endfunction
+
+  //**************
+  // log2int
+  //**************
+  function integer log2int (input integer data_value);
+      integer width;
+      integer cnt;
+      begin
+         width = 0;
+		 cnt= data_value;
+
+            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
+               width = width + 1;
+            end //loop
+
+         log2int = width;
+
+      end //log2int
+   endfunction
+
+ //**************************************************************************
+ // FUNCTION : divroundup
+ // Returns the ceiling value of the division
+ // Data_value - the quantity to be divided, dividend
+ // Divisor - the value to divide the data_value by
+ //**************************************************************************
+  function integer divroundup (input integer data_value,input integer divisor);
+      integer div;
+      begin
+    div   = data_value/divisor;
+         if ((data_value % divisor) != 0) begin
+      div = div+1;
+         end //if
+         divroundup = div;
+         end //if
+   endfunction
+
+  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
+  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
+  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;
+ 
+  //Data Width        Number of LSB address bits to be discarded
+  //1 to 16                      1
+  //17 to 32                     2
+  //33 to 64                     3
+  //65 to 128                    4
+  //129 to 256                   5
+  //257 to 512                   6
+  //513 to 1024                  7
+  // The following two constants determine this.
+
+  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
+  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
+  localparam C_AXI_OS_WR = 2;
+
+ //***********************************************
+ // INPUT REGISTERS.
+ //***********************************************
+  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
+      always @* begin
+      injectsbiterr_in = INJECTSBITERR;
+      injectdbiterr_in = INJECTDBITERR;
+      rsta_in    = RSTA;
+      ena_in     = ENA;
+      regcea_in  = REGCEA;
+      wea_in     = WEA;
+      addra_in   = ADDRA;
+      dina_in    = DINA;
+      end //end always
+      end //end no_softecc_input_reg_stage
+ endgenerate
+
+  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
+      always @(posedge CLKA) begin
+      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
+      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
+      rsta_in     <= #FLOP_DELAY RSTA;
+      ena_in     <= #FLOP_DELAY ENA;
+      regcea_in  <= #FLOP_DELAY REGCEA;
+      wea_in     <= #FLOP_DELAY WEA;
+      addra_in   <= #FLOP_DELAY ADDRA;
+      dina_in    <= #FLOP_DELAY DINA;
+      end //end always
+      end //end input_reg_stages generate statement
+ endgenerate
+
+  //**************************************************************************
+  // NO SAFETY LOGIC
+  //**************************************************************************
+
+   generate 
+     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
+       assign ENA_I_SAFE     = ena_in;
+       assign ENB_I_SAFE     = ENB;
+       assign RSTA_I_SAFE    = rsta_in;
+       assign RSTB_I_SAFE    = RSTB;
+     end
+   endgenerate
+
+  //***************************************************************************
+  // SAFETY LOGIC
+  // Power-ON Reset Generation
+  //***************************************************************************
+  generate 
+    if (C_EN_SAFETY_CKT == 1) begin
+      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
+      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
+      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
+      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; 
+ 
+      assign RSTA_I_SAFE = rsta_in | POR_A;  
+      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
+    end
+  endgenerate
+
+  //-----------------------------------------------------------------------------
+  //  -- RSTA/B_BUSY Generation
+  //-----------------------------------------------------------------------------
+
+  generate 
+    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
+      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
+      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
+    end
+  endgenerate
+  
+  generate 
+    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
+      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
+      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
+    end
+  endgenerate
+
+  generate 
+    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
+      always @(*) RSTB_BUSY = 1'b0;
+    end
+  endgenerate
+
+  generate 
+    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG
+      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
+      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
+    end
+  endgenerate
+    
+  generate 
+    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  
+      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
+      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
+    end
+  endgenerate
+
+  //-----------------------------------------------------------------------------
+  //  -- ENA/ENB Generation
+  //-----------------------------------------------------------------------------
+  
+  generate 
+    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    
+      always @(posedge clka) begin
+        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;
+        ENA_dly_D <= #FLOP_DELAY ENA_dly;
+      end
+      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
+    end
+  endgenerate
+
+  generate 
+    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
+      always @(posedge clka) begin
+        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;
+        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
+      end
+      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
+    end
+  endgenerate
+
+  generate 
+    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
+      assign ENB_I_SAFE = 1'b0;
+    end
+  endgenerate
+
+  generate 
+    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
+      always @(posedge clkb) begin : PROC_ENB_GEN
+        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;
+        ENB_dly_D <= #FLOP_DELAY ENB_dly;
+      end
+      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
+    end
+  endgenerate
+  
+  generate 
+    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
+      always @(posedge clkb) begin : PROC_ENB_GEN
+        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;
+        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;
+      end
+      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
+    end
+  endgenerate
+
+  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
+blk_mem_gen_v8_4_4_mem_module
+  #(.C_CORENAME                        (C_CORENAME),
+    .C_FAMILY                          (C_FAMILY),
+    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                        (C_MEM_TYPE),
+    .C_BYTE_SIZE                       (C_BYTE_SIZE),
+    .C_ALGORITHM                       (C_ALGORITHM),
+    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),
+    .C_PRIM_TYPE                       (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),
+    .C_INIT_FILE                       (C_INIT_FILE),
+    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),
+    .C_RST_TYPE                        ("SYNC"),
+    .C_HAS_RSTA                        (C_HAS_RSTA),
+    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                        (C_RSTRAM_A),
+    .C_INITA_VAL                       (C_INITA_VAL),
+    .C_HAS_ENA                         (C_HAS_ENA),
+    .C_HAS_REGCEA                      (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH                       (C_WEA_WIDTH),
+    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                        (C_HAS_RSTB),
+    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                        (C_RSTRAM_B),
+    .C_INITB_VAL                       (C_INITB_VAL),
+    .C_HAS_ENB                         (C_HAS_ENB),
+    .C_HAS_REGCEB                      (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH                       (C_WEB_WIDTH),
+    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),
+    .C_USE_SOFTECC                     (C_USE_SOFTECC),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK                      (C_COMMON_CLK),
+    .FLOP_DELAY                        (FLOP_DELAY),
+    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),
+ .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),
+    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))
+    blk_mem_gen_v8_4_4_inst
+   (.CLKA            (CLKA),
+   .RSTA             (RSTA_I_SAFE),//(rsta_in),
+   .ENA              (ENA_I_SAFE),//(ena_in),
+   .REGCEA           (regcea_in),
+   .WEA              (wea_in),
+   .ADDRA            (addra_in),
+   .DINA             (dina_in),
+   .DOUTA            (DOUTA),
+   .CLKB             (CLKB),
+   .RSTB             (RSTB_I_SAFE),//(RSTB),
+   .ENB              (ENB_I_SAFE),//(ENB),
+   .REGCEB           (REGCEB),
+   .WEB              (WEB),
+   .ADDRB            (ADDRB),
+   .DINB             (DINB),
+   .DOUTB            (DOUTB),
+   .INJECTSBITERR    (injectsbiterr_in),
+   .INJECTDBITERR    (injectdbiterr_in),
+   .ECCPIPECE        (ECCPIPECE),
+   .SLEEP            (SLEEP),
+   .SBITERR          (SBITERR),
+   .DBITERR          (DBITERR),
+   .RDADDRECC        (RDADDRECC)
+  );
+ end
+ endgenerate
+
+  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
+
+  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
+  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
+
+  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
+  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
+ // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
+ // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
+  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;
+  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;
+
+  // Data Width        Number of LSB address bits to be discarded
+  //  1 to 16                      1
+  //  17 to 32                     2
+  //  33 to 64                     3
+  //  65 to 128                    4
+  //  129 to 256                   5
+  //  257 to 512                   6
+  //  513 to 1024                  7
+  // The following two constants determine this.
+
+  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
+  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));
+  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
+  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
+
+  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
+  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
+  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
+  
+  assign msb_zero_i = 0;
+  assign lsb_zero_i = 0;
+  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
+
+blk_mem_gen_v8_4_4_mem_module
+  #(.C_CORENAME                        (C_CORENAME),
+    .C_FAMILY                          (C_FAMILY),
+    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                        (C_MEM_TYPE),
+    .C_BYTE_SIZE                       (C_BYTE_SIZE),
+    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),
+    .C_ALGORITHM                       (C_ALGORITHM),
+    .C_PRIM_TYPE                       (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),
+    .C_INIT_FILE                       (C_INIT_FILE),
+    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),
+    .C_RST_TYPE                        ("SYNC"),
+    .C_HAS_RSTA                        (C_HAS_RSTA),
+    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                        (C_RSTRAM_A),
+    .C_INITA_VAL                       (C_INITA_VAL),
+    .C_HAS_ENA                         (C_HAS_ENA),
+    .C_HAS_REGCEA                      (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH                       (C_WEA_WIDTH),
+    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),
+    .C_HAS_RSTB                        (C_HAS_RSTB),
+    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                        (C_RSTRAM_B),
+    .C_INITB_VAL                       (C_INITB_VAL),
+    .C_HAS_ENB                         (C_HAS_ENB),
+    .C_HAS_REGCEB                      (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH                       (C_WEB_WIDTH),
+    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),
+    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),
+    .C_USE_SOFTECC                     (C_USE_SOFTECC),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK                      (C_COMMON_CLK),
+    .FLOP_DELAY                        (FLOP_DELAY),
+    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),
+ .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),
+    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))
+    blk_mem_gen_v8_4_4_inst
+   (.CLKA            (CLKA),
+   .RSTA             (RSTA_I_SAFE),//(rsta_in),
+   .ENA              (ENA_I_SAFE),//(ena_in),
+   .REGCEA           (regcea_in),
+   .WEA              (wea_in),
+   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
+   .DINA             (dina_in),
+   .DOUTA            (DOUTA),
+   .CLKB             (CLKB),
+   .RSTB             (RSTB_I_SAFE),//(RSTB),
+   .ENB              (ENB_I_SAFE),//(ENB),
+   .REGCEB           (REGCEB),
+   .WEB              (WEB),
+   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
+   .DINB             (DINB),
+   .DOUTB            (DOUTB),
+   .INJECTSBITERR    (injectsbiterr_in),
+   .INJECTDBITERR    (injectdbiterr_in),
+   .ECCPIPECE        (ECCPIPECE),
+   .SLEEP            (SLEEP),
+   .SBITERR          (SBITERR),
+   .DBITERR          (DBITERR),
+   .RDADDRECC        (rdaddrecc_i)
+  );
+ end
+ endgenerate
+
+  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
+      assign S_AXI_RDATA    = s_axi_rdata_c;
+      assign S_AXI_RLAST    = s_axi_rlast_c;
+      assign S_AXI_RVALID   = s_axi_rvalid_c;
+      assign S_AXI_RID      = s_axi_rid_c;
+      assign S_AXI_RRESP    = s_axi_rresp_c;
+      assign s_axi_rready_c = S_AXI_RREADY;
+ end
+ endgenerate
+
+     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
+        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
+ end
+     endgenerate
+
+     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
+        assign regceb_c = REGCEB;
+ end
+     endgenerate
+
+     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
+        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
+        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
+        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
+        assign S_AXI_RRESP     = m_axi_payload_c[2:1];
+        assign S_AXI_RLAST     = m_axi_payload_c[0];
+ end
+     endgenerate
+
+     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
+        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
+        assign S_AXI_RDATA     = s_axi_rdata_c;
+        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
+        assign S_AXI_RRESP     = m_axi_payload_c[2:1];
+        assign S_AXI_RLAST     = m_axi_payload_c[0];
+ end
+     endgenerate
+
+  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
+
+    blk_mem_axi_regs_fwd_v8_4
+      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))
+    axi_regs_inst (
+        .ACLK           (S_ACLK), 
+        .ARESET         (s_aresetn_a_c),
+        .S_VALID        (s_axi_rvalid_c), 
+        .S_READY        (s_axi_rready_c),
+        .S_PAYLOAD_DATA (s_axi_payload_c),
+        .M_VALID        (S_AXI_RVALID),
+        .M_READY        (S_AXI_RREADY),
+        .M_PAYLOAD_DATA (m_axi_payload_c)
+    );
+ end
+ endgenerate
+
+  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
+
+assign s_aresetn_a_c = !S_ARESETN;
+assign S_AXI_BRESP = 2'b00;
+assign s_axi_rresp_c = 2'b00;
+assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
+
+  blk_mem_axi_write_wrapper_beh_v8_4
+    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),
+      .C_AXI_TYPE                 (C_AXI_TYPE),
+      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),
+      .C_MEMORY_TYPE              (C_MEM_TYPE),
+      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),
+      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
+      .C_HAS_AXI_ID               (C_HAS_AXI_ID),
+      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),
+      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),
+      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),
+      .C_AXI_OS_WR                (C_AXI_OS_WR))
+  axi_wr_fsm (
+      // AXI Global Signals
+      .S_ACLK                     (S_ACLK),
+      .S_ARESETN                  (s_aresetn_a_c),
+      // AXI Full/Lite Slave Write interface
+      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
+      .S_AXI_AWLEN                (S_AXI_AWLEN),
+      .S_AXI_AWID                 (S_AXI_AWID),
+      .S_AXI_AWSIZE               (S_AXI_AWSIZE),
+      .S_AXI_AWBURST              (S_AXI_AWBURST),
+      .S_AXI_AWVALID              (S_AXI_AWVALID),
+      .S_AXI_AWREADY              (S_AXI_AWREADY),
+      .S_AXI_WVALID               (S_AXI_WVALID),
+      .S_AXI_WREADY               (S_AXI_WREADY),
+      .S_AXI_BVALID               (S_AXI_BVALID),
+      .S_AXI_BREADY               (S_AXI_BREADY),
+      .S_AXI_BID                  (S_AXI_BID),
+      // Signals for BRAM interfac(
+      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),
+      .S_AXI_WR_EN                (s_axi_wr_en_c)
+      );
+
+  blk_mem_axi_read_wrapper_beh_v8_4
+  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), 
+    .C_AXI_TYPE		          (C_AXI_TYPE), 
+    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), 
+    .C_MEMORY_TYPE                (C_MEM_TYPE), 
+    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), 
+    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), 
+    .C_AXI_PIPELINE_STAGES        (1), 
+    .C_AXI_ARADDR_WIDTH	          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), 
+    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), 
+    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), 
+    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) 
+  axi_rd_sm(
+    //AXI Global Signals
+    .S_ACLK                       (S_ACLK), 
+    .S_ARESETN                    (s_aresetn_a_c),
+    //AXI Full/Lite Read Side
+    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
+    .S_AXI_ARLEN                  (s_axi_arlen_c),
+    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),
+    .S_AXI_ARBURST                (S_AXI_ARBURST),
+    .S_AXI_ARVALID                (S_AXI_ARVALID),
+    .S_AXI_ARREADY                (S_AXI_ARREADY),
+    .S_AXI_RLAST                  (s_axi_rlast_c),
+    .S_AXI_RVALID                 (s_axi_rvalid_c),
+    .S_AXI_RREADY                 (s_axi_rready_c),
+    .S_AXI_ARID                   (S_AXI_ARID),
+    .S_AXI_RID                    (s_axi_rid_c),
+    //AXI Full/Lite Read FSM Outputs
+    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),
+    .S_AXI_RD_EN                  (s_axi_rd_en_c)
+  );
+
+blk_mem_gen_v8_4_4_mem_module
+  #(.C_CORENAME                        (C_CORENAME),
+    .C_FAMILY                          (C_FAMILY),
+    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                        (C_MEM_TYPE),
+    .C_BYTE_SIZE                       (C_BYTE_SIZE),
+    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),
+    .C_ALGORITHM                       (C_ALGORITHM),
+    .C_PRIM_TYPE                       (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),
+    .C_INIT_FILE                       (C_INIT_FILE),
+    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),
+    .C_RST_TYPE                        ("SYNC"),
+    .C_HAS_RSTA                        (C_HAS_RSTA),
+    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                        (C_RSTRAM_A),
+    .C_INITA_VAL                       (C_INITA_VAL),
+    .C_HAS_ENA                         (1),
+    .C_HAS_REGCEA                      (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA                    (1),
+    .C_WEA_WIDTH                       (C_WEA_WIDTH),
+    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                        (C_HAS_RSTB),
+    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                        (C_RSTRAM_B),
+    .C_INITB_VAL                       (C_INITB_VAL),
+    .C_HAS_ENB                         (1),
+    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_USE_BYTE_WEB                    (1),
+    .C_WEB_WIDTH                       (C_WEB_WIDTH),
+    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A           (0),
+    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A           (0),
+    .C_HAS_MUX_OUTPUT_REGS_B           (0),
+    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),
+    .C_USE_SOFTECC                     (C_USE_SOFTECC),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK                      (C_COMMON_CLK),
+    .FLOP_DELAY                        (FLOP_DELAY),
+    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),
+	.C_EN_ECC_PIPE                     (0),
+    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))
+    blk_mem_gen_v8_4_4_inst
+   (.CLKA            (S_ACLK),
+   .RSTA             (s_aresetn_a_c),
+   .ENA              (s_axi_wr_en_c),
+   .REGCEA           (regcea_in),
+   .WEA              (S_AXI_WSTRB),
+   .ADDRA            (s_axi_awaddr_out_c),
+   .DINA             (S_AXI_WDATA),
+   .DOUTA            (DOUTA),
+   .CLKB             (S_ACLK),
+   .RSTB             (s_aresetn_a_c),
+   .ENB              (s_axi_rd_en_c),
+   .REGCEB           (regceb_c),
+   .WEB              (WEB_parameterized),
+   .ADDRB            (s_axi_araddr_out_c),
+   .DINB             (DINB),
+   .DOUTB            (s_axi_rdata_c),
+   .INJECTSBITERR    (injectsbiterr_in),
+   .INJECTDBITERR    (injectdbiterr_in),
+   .SBITERR          (SBITERR),
+   .DBITERR          (DBITERR),
+   .ECCPIPECE        (1'b0),
+   .SLEEP            (1'b0),
+   .RDADDRECC        (RDADDRECC)
+  );
+ end
+ endgenerate
+endmodule
+
+
+
diff --git a/projects/U200/U200.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v b/projects/U200/U200.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v
new file mode 100755
index 0000000..e5067fe
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v
@@ -0,0 +1,10519 @@
+/*
+ *******************************************************************************
+ *
+ * FIFO Generator - Verilog Behavioral Model
+ *
+ *******************************************************************************
+ *
+ * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
+ *
+ * This file contains confidential and proprietary information
+ * of Xilinx, Inc. and is protected under U.S. and
+ * international copyright and other intellectual property
+ * laws.
+ *
+ * DISCLAIMER
+ * This disclaimer is not a license and does not grant any
+ * rights to the materials distributed herewith. Except as
+ * otherwise provided in a valid license issued to you by
+ * Xilinx, and to the maximum extent permitted by applicable
+ * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ * (2) Xilinx shall not be liable (whether in contract or tort,
+ * including negligence, or under any other theory of
+ * liability) for any loss or damage of any kind or nature
+ * related to, arising under or in connection with these
+ * materials, including for any direct, or any indirect,
+ * special, incidental, or consequential loss or damage
+ * (including loss of data, profits, goodwill, or any type of
+ * loss or damage suffered as a result of any action brought
+ * by a third party) even if such damage or loss was
+ * reasonably foreseeable or Xilinx had been advised of the
+ * possibility of the same.
+ *
+ * CRITICAL APPLICATIONS
+ * Xilinx products are not designed or intended to be fail-
+ * safe, or for use in any application requiring fail-safe
+ * performance, such as life-support or safety devices or
+ * systems, Class III medical devices, nuclear facilities,
+ * applications related to the deployment of airbags, or any
+ * other applications that could lead to death, personal
+ * injury, or severe property or environmental damage
+ * (individually and collectively, "Critical
+ * Applications"). Customer assumes the sole risk and
+ * liability of any use of Xilinx products in Critical
+ * Applications, subject only to applicable laws and
+ * regulations governing limitations on product liability.
+ *
+ * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ * PART OF THIS FILE AT ALL TIMES.
+ *
+ *******************************************************************************
+ *******************************************************************************
+ *
+ * Filename: fifo_generator_vlog_beh.v
+ *
+ * Author     : Xilinx
+ *
+ *******************************************************************************
+ * Structure:
+ * 
+ * fifo_generator_vlog_beh.v
+ *    |
+ *    +-fifo_generator_v13_2_5_bhv_ver_as
+ *    |
+ *    +-fifo_generator_v13_2_5_bhv_ver_ss
+ *    |
+ *    +-fifo_generator_v13_2_5_bhv_ver_preload0
+ * 
+ *******************************************************************************
+ * Description:
+ *
+ * The Verilog behavioral model for the FIFO Generator.
+ *
+ *   The behavioral model has three parts:
+ *      - The behavioral model for independent clocks FIFOs (_as)
+ *      - The behavioral model for common clock FIFOs (_ss)
+ *      - The "preload logic" block which implements First-word Fall-through
+ * 
+ *******************************************************************************
+ * Description:
+ *  The verilog behavioral model for the FIFO generator core.
+ *
+ *******************************************************************************
+ */
+
+`timescale 1ps/1ps
+`ifndef TCQ
+ `define TCQ 100
+`endif
+
+
+/*******************************************************************************
+ * Declaration of top-level module
+ ******************************************************************************/
+module fifo_generator_vlog_beh
+  #(
+    //-----------------------------------------------------------------------
+    // Generic Declarations
+    //-----------------------------------------------------------------------
+    parameter C_COMMON_CLOCK                 = 0,
+    parameter C_COUNT_TYPE                   = 0,
+    parameter C_DATA_COUNT_WIDTH             = 2,
+    parameter C_DEFAULT_VALUE                = "",
+    parameter C_DIN_WIDTH                    = 8,
+    parameter C_DOUT_RST_VAL                 = "",
+    parameter C_DOUT_WIDTH                   = 8,
+    parameter C_ENABLE_RLOCS                 = 0,
+    parameter C_FAMILY                       = "",
+    parameter C_FULL_FLAGS_RST_VAL           = 1,
+    parameter C_HAS_ALMOST_EMPTY             = 0,
+    parameter C_HAS_ALMOST_FULL              = 0,
+    parameter C_HAS_BACKUP                   = 0,
+    parameter C_HAS_DATA_COUNT               = 0,
+    parameter C_HAS_INT_CLK                  = 0,
+    parameter C_HAS_MEMINIT_FILE             = 0,
+    parameter C_HAS_OVERFLOW                 = 0,
+    parameter C_HAS_RD_DATA_COUNT            = 0,
+    parameter C_HAS_RD_RST                   = 0,
+    parameter C_HAS_RST                      = 1,
+    parameter C_HAS_SRST                     = 0,
+    parameter C_HAS_UNDERFLOW                = 0,
+    parameter C_HAS_VALID                    = 0,
+    parameter C_HAS_WR_ACK                   = 0,
+    parameter C_HAS_WR_DATA_COUNT            = 0,
+    parameter C_HAS_WR_RST                   = 0,
+    parameter C_IMPLEMENTATION_TYPE          = 0,
+    parameter C_INIT_WR_PNTR_VAL             = 0,
+    parameter C_MEMORY_TYPE                  = 1,
+    parameter C_MIF_FILE_NAME                = "",
+    parameter C_OPTIMIZATION_MODE            = 0,
+    parameter C_OVERFLOW_LOW                 = 0,
+    parameter C_EN_SAFETY_CKT                = 0,
+    parameter C_PRELOAD_LATENCY              = 1,
+    parameter C_PRELOAD_REGS                 = 0,
+    parameter C_PRIM_FIFO_TYPE               = "4kx4",
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter C_PROG_EMPTY_TYPE              = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter C_PROG_FULL_TYPE               = 0,
+    parameter C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter C_RD_DEPTH                     = 256,
+    parameter C_RD_FREQ                      = 1,
+    parameter C_RD_PNTR_WIDTH                = 8,
+    parameter C_UNDERFLOW_LOW                = 0,
+    parameter C_USE_DOUT_RST                 = 0,
+    parameter C_USE_ECC                      = 0,
+    parameter C_USE_EMBEDDED_REG             = 0,
+    parameter C_USE_PIPELINE_REG             = 0,
+    parameter C_POWER_SAVING_MODE            = 0,
+    parameter C_USE_FIFO16_FLAGS             = 0,
+    parameter C_USE_FWFT_DATA_COUNT          = 0,
+    parameter C_VALID_LOW                    = 0,
+    parameter C_WR_ACK_LOW                   = 0,
+    parameter C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter C_WR_DEPTH                     = 256,
+    parameter C_WR_FREQ                      = 1,
+    parameter C_WR_PNTR_WIDTH                = 8,
+    parameter C_WR_RESPONSE_LATENCY          = 1,
+    parameter C_MSGON_VAL                    = 1,
+    parameter C_ENABLE_RST_SYNC              = 1,
+    parameter C_ERROR_INJECTION_TYPE         = 0,
+    parameter C_SYNCHRONIZER_STAGE           = 2,
+
+    // AXI Interface related parameters start here
+    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
+    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
+    parameter C_HAS_AXI_WR_CHANNEL           = 0,
+    parameter C_HAS_AXI_RD_CHANNEL           = 0,
+    parameter C_HAS_SLAVE_CE                 = 0,
+    parameter C_HAS_MASTER_CE                = 0,
+    parameter C_ADD_NGC_CONSTRAINT           = 0,
+    parameter C_USE_COMMON_UNDERFLOW         = 0,
+    parameter C_USE_COMMON_OVERFLOW          = 0,
+    parameter C_USE_DEFAULT_SETTINGS         = 0,
+
+    // AXI Full/Lite
+    parameter C_AXI_ID_WIDTH                 = 0,
+    parameter C_AXI_ADDR_WIDTH               = 0,
+    parameter C_AXI_DATA_WIDTH               = 0,
+    parameter C_AXI_LEN_WIDTH                = 8,
+    parameter C_AXI_LOCK_WIDTH               = 2,
+    parameter C_HAS_AXI_ID                   = 0,
+    parameter C_HAS_AXI_AWUSER               = 0,
+    parameter C_HAS_AXI_WUSER                = 0,
+    parameter C_HAS_AXI_BUSER                = 0,
+    parameter C_HAS_AXI_ARUSER               = 0,
+    parameter C_HAS_AXI_RUSER                = 0,
+    parameter C_AXI_ARUSER_WIDTH             = 0,
+    parameter C_AXI_AWUSER_WIDTH             = 0,
+    parameter C_AXI_WUSER_WIDTH              = 0,
+    parameter C_AXI_BUSER_WIDTH              = 0,
+    parameter C_AXI_RUSER_WIDTH              = 0,
+
+    // AXI Streaming
+    parameter C_HAS_AXIS_TDATA               = 0,
+    parameter C_HAS_AXIS_TID                 = 0,
+    parameter C_HAS_AXIS_TDEST               = 0,
+    parameter C_HAS_AXIS_TUSER               = 0,
+    parameter C_HAS_AXIS_TREADY              = 0,
+    parameter C_HAS_AXIS_TLAST               = 0,
+    parameter C_HAS_AXIS_TSTRB               = 0,
+    parameter C_HAS_AXIS_TKEEP               = 0,
+    parameter C_AXIS_TDATA_WIDTH             = 1,
+    parameter C_AXIS_TID_WIDTH               = 1,
+    parameter C_AXIS_TDEST_WIDTH             = 1,
+    parameter C_AXIS_TUSER_WIDTH             = 1,
+    parameter C_AXIS_TSTRB_WIDTH             = 1,
+    parameter C_AXIS_TKEEP_WIDTH             = 1,
+
+    // AXI Channel Type
+    // WACH --> Write Address Channel
+    // WDCH --> Write Data Channel
+    // WRCH --> Write Response Channel
+    // RACH --> Read Address Channel
+    // RDCH --> Read Data Channel
+    // AXIS --> AXI Streaming
+    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
+    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+
+    // AXI Implementation Type
+    // 1 = Common Clock Block RAM FIFO
+    // 2 = Common Clock Distributed RAM FIFO
+    // 11 = Independent Clock Block RAM FIFO
+    // 12 = Independent Clock Distributed RAM FIFO
+    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,
+
+    // AXI FIFO Type
+    // 0 = Data FIFO
+    // 1 = Packet FIFO
+    // 2 = Low Latency Sync FIFO
+    // 3 = Low Latency Async FIFO
+    parameter C_APPLICATION_TYPE_WACH        = 0,
+    parameter C_APPLICATION_TYPE_WDCH        = 0,
+    parameter C_APPLICATION_TYPE_WRCH        = 0,
+    parameter C_APPLICATION_TYPE_RACH        = 0,
+    parameter C_APPLICATION_TYPE_RDCH        = 0,
+    parameter C_APPLICATION_TYPE_AXIS        = 0,
+
+    // AXI Built-in FIFO Primitive Type
+    // 512x36, 1kx18, 2kx9, 4kx4, etc
+    parameter C_PRIM_FIFO_TYPE_WACH          = "512x36",
+    parameter C_PRIM_FIFO_TYPE_WDCH          = "512x36",
+    parameter C_PRIM_FIFO_TYPE_WRCH          = "512x36",
+    parameter C_PRIM_FIFO_TYPE_RACH          = "512x36",
+    parameter C_PRIM_FIFO_TYPE_RDCH          = "512x36",
+    parameter C_PRIM_FIFO_TYPE_AXIS          = "512x36",
+
+    // Enable ECC
+    // 0 = ECC disabled
+    // 1 = ECC enabled
+    parameter C_USE_ECC_WACH                 = 0,
+    parameter C_USE_ECC_WDCH                 = 0,
+    parameter C_USE_ECC_WRCH                 = 0,
+    parameter C_USE_ECC_RACH                 = 0,
+    parameter C_USE_ECC_RDCH                 = 0,
+    parameter C_USE_ECC_AXIS                 = 0,
+
+    // ECC Error Injection Type
+    // 0 = No Error Injection
+    // 1 = Single Bit Error Injection
+    // 2 = Double Bit Error Injection
+    // 3 = Single Bit and Double Bit Error Injection
+    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,
+
+    // Input Data Width
+    // Accumulation of all AXI input signal's width
+    parameter C_DIN_WIDTH_WACH               = 1,
+    parameter C_DIN_WIDTH_WDCH               = 1,
+    parameter C_DIN_WIDTH_WRCH               = 1,
+    parameter C_DIN_WIDTH_RACH               = 1,
+    parameter C_DIN_WIDTH_RDCH               = 1,
+    parameter C_DIN_WIDTH_AXIS               = 1,
+
+    parameter C_WR_DEPTH_WACH                = 16,
+    parameter C_WR_DEPTH_WDCH                = 16,
+    parameter C_WR_DEPTH_WRCH                = 16,
+    parameter C_WR_DEPTH_RACH                = 16,
+    parameter C_WR_DEPTH_RDCH                = 16,
+    parameter C_WR_DEPTH_AXIS                = 16,
+
+    parameter C_WR_PNTR_WIDTH_WACH           = 4,
+    parameter C_WR_PNTR_WIDTH_WDCH           = 4,
+    parameter C_WR_PNTR_WIDTH_WRCH           = 4,
+    parameter C_WR_PNTR_WIDTH_RACH           = 4,
+    parameter C_WR_PNTR_WIDTH_RDCH           = 4,
+    parameter C_WR_PNTR_WIDTH_AXIS           = 4,
+
+    parameter C_HAS_DATA_COUNTS_WACH         = 0,
+    parameter C_HAS_DATA_COUNTS_WDCH         = 0,
+    parameter C_HAS_DATA_COUNTS_WRCH         = 0,
+    parameter C_HAS_DATA_COUNTS_RACH         = 0,
+    parameter C_HAS_DATA_COUNTS_RDCH         = 0,
+    parameter C_HAS_DATA_COUNTS_AXIS         = 0,
+
+    parameter C_HAS_PROG_FLAGS_WACH          = 0,
+    parameter C_HAS_PROG_FLAGS_WDCH          = 0,
+    parameter C_HAS_PROG_FLAGS_WRCH          = 0,
+    parameter C_HAS_PROG_FLAGS_RACH          = 0,
+    parameter C_HAS_PROG_FLAGS_RDCH          = 0,
+    parameter C_HAS_PROG_FLAGS_AXIS          = 0,
+
+    parameter C_PROG_FULL_TYPE_WACH          = 0,
+    parameter C_PROG_FULL_TYPE_WDCH          = 0,
+    parameter C_PROG_FULL_TYPE_WRCH          = 0,
+    parameter C_PROG_FULL_TYPE_RACH          = 0,
+    parameter C_PROG_FULL_TYPE_RDCH          = 0,
+    parameter C_PROG_FULL_TYPE_AXIS          = 0,
+
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,
+
+    parameter C_PROG_EMPTY_TYPE_WACH         = 0,
+    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,
+    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,
+    parameter C_PROG_EMPTY_TYPE_RACH         = 0,
+    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,
+    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,
+
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,
+
+    parameter C_REG_SLICE_MODE_WACH          = 0,
+    parameter C_REG_SLICE_MODE_WDCH          = 0,
+    parameter C_REG_SLICE_MODE_WRCH          = 0,
+    parameter C_REG_SLICE_MODE_RACH          = 0,
+    parameter C_REG_SLICE_MODE_RDCH          = 0,
+    parameter C_REG_SLICE_MODE_AXIS          = 0
+
+    )
+
+   (
+    //------------------------------------------------------------------------------
+    // Input and Output Declarations
+    //------------------------------------------------------------------------------
+
+    // Conventional FIFO Interface Signals
+    input                               backup,
+    input                               backup_marker,
+    input                               clk,
+    input                               rst,
+    input                               srst,
+    input                               wr_clk,
+    input                               wr_rst,
+    input                               rd_clk,
+    input                               rd_rst,
+    input [C_DIN_WIDTH-1:0]             din,
+    input                               wr_en,
+    input                               rd_en,
+    // Optional inputs
+    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,
+    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,
+    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,
+    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,
+    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,
+    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,
+    input                               int_clk,
+    input                               injectdbiterr,
+    input                               injectsbiterr,
+    input                               sleep,
+
+    output [C_DOUT_WIDTH-1:0]           dout,
+    output                              full,
+    output                              almost_full,
+    output                              wr_ack,
+    output                              overflow,
+    output                              empty,
+    output                              almost_empty,
+    output                              valid,
+    output                              underflow,
+    output [C_DATA_COUNT_WIDTH-1:0]     data_count,
+    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,
+    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,
+    output                              prog_full,
+    output                              prog_empty,
+    output                              sbiterr,
+    output                              dbiterr,
+    output                              wr_rst_busy,
+    output                              rd_rst_busy,
+
+
+    // AXI Global Signal
+    input                               m_aclk,
+    input                               s_aclk,
+    input                               s_aresetn,
+    input                               s_aclk_en,
+    input                               m_aclk_en,
+    
+    // AXI Full/Lite Slave Write Channel (write side)
+    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,
+    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,
+    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,
+    input [3-1:0]                       s_axi_awsize,
+    input [2-1:0]                       s_axi_awburst,
+    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,
+    input [4-1:0]                       s_axi_awcache,
+    input [3-1:0]                       s_axi_awprot,
+    input [4-1:0]                       s_axi_awqos,
+    input [4-1:0]                       s_axi_awregion,
+    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,
+    input                               s_axi_awvalid,
+    output                              s_axi_awready,
+    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,
+    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,
+    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,
+    input                               s_axi_wlast,
+    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,
+    input                               s_axi_wvalid,
+    output                              s_axi_wready,
+    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,
+    output [2-1:0]                      s_axi_bresp,
+    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,
+    output                              s_axi_bvalid,
+    input                               s_axi_bready,
+    
+    // AXI Full/Lite Master Write Channel (read side)
+    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,
+    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,
+    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,
+    output [3-1:0]                      m_axi_awsize,
+    output [2-1:0]                      m_axi_awburst,
+    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,
+    output [4-1:0]                      m_axi_awcache,
+    output [3-1:0]                      m_axi_awprot,
+    output [4-1:0]                      m_axi_awqos,
+    output [4-1:0]                      m_axi_awregion,
+    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,
+    output                              m_axi_awvalid,
+    input                               m_axi_awready,
+    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,
+    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,
+    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,
+    output                              m_axi_wlast,
+    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,
+    output                              m_axi_wvalid,
+    input                               m_axi_wready,
+    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,
+    input [2-1:0]                       m_axi_bresp,
+    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,
+    input                               m_axi_bvalid,
+    output                              m_axi_bready,
+    
+    
+    // AXI Full/Lite Slave Read Channel (write side)
+    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,
+    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, 
+    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,
+    input [3-1:0]                       s_axi_arsize,
+    input [2-1:0]                       s_axi_arburst,
+    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,
+    input [4-1:0]                       s_axi_arcache,
+    input [3-1:0]                       s_axi_arprot,
+    input [4-1:0]                       s_axi_arqos,
+    input [4-1:0]                       s_axi_arregion,
+    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,
+    input                               s_axi_arvalid,
+    output                              s_axi_arready,
+    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       
+    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, 
+    output [2-1:0]                      s_axi_rresp,
+    output                              s_axi_rlast,
+    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,
+    output                              s_axi_rvalid,
+    input                               s_axi_rready,
+    
+    
+    
+    // AXI Full/Lite Master Read Channel (read side)
+    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        
+    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  
+    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,
+    output [3-1:0]                      m_axi_arsize,
+    output [2-1:0]                      m_axi_arburst,
+    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,
+    output [4-1:0]                      m_axi_arcache,
+    output [3-1:0]                      m_axi_arprot,
+    output [4-1:0]                      m_axi_arqos,
+    output [4-1:0]                      m_axi_arregion,
+    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,
+    output                              m_axi_arvalid,
+    input                               m_axi_arready,
+    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        
+    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  
+    input [2-1:0]                       m_axi_rresp,
+    input                               m_axi_rlast,
+    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,
+    input                               m_axi_rvalid,
+    output                              m_axi_rready,
+    
+    
+    // AXI Streaming Slave Signals (Write side)
+    input                               s_axis_tvalid,
+    output                              s_axis_tready,
+    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,
+    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,
+    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,
+    input                               s_axis_tlast,
+    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,
+    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,
+    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,
+    
+    // AXI Streaming Master Signals (Read side)
+    output                              m_axis_tvalid,
+    input                               m_axis_tready,
+    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,
+    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,
+    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,
+    output                              m_axis_tlast,
+    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,
+    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,
+    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,
+    
+           
+    
+    
+    // AXI Full/Lite Write Address Channel signals
+    input                               axi_aw_injectsbiterr,
+    input                               axi_aw_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,
+    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,
+    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,
+    output                              axi_aw_sbiterr,
+    output                              axi_aw_dbiterr,
+    output                              axi_aw_overflow,
+    output                              axi_aw_underflow,
+    output                              axi_aw_prog_full,
+    output                              axi_aw_prog_empty,
+    
+    
+    // AXI Full/Lite Write Data Channel signals
+    input                               axi_w_injectsbiterr,
+    input                               axi_w_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,
+    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,
+    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,
+    output                              axi_w_sbiterr,
+    output                              axi_w_dbiterr,
+    output                              axi_w_overflow,
+    output                              axi_w_underflow,
+    output                              axi_w_prog_full,
+    output                              axi_w_prog_empty,
+    
+    
+    // AXI Full/Lite Write Response Channel signals
+    input                               axi_b_injectsbiterr,
+    input                               axi_b_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,
+    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,
+    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,
+    output                              axi_b_sbiterr,
+    output                              axi_b_dbiterr,
+    output                              axi_b_overflow,
+    output                              axi_b_underflow,
+    output                              axi_b_prog_full,
+    output                              axi_b_prog_empty,
+    
+    
+    
+    // AXI Full/Lite Read Address Channel signals
+    input                               axi_ar_injectsbiterr,
+    input                               axi_ar_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,
+    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,
+    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,
+    output                              axi_ar_sbiterr,
+    output                              axi_ar_dbiterr,
+    output                              axi_ar_overflow,
+    output                              axi_ar_underflow,
+    output                              axi_ar_prog_full,
+    output                              axi_ar_prog_empty,
+
+    
+    // AXI Full/Lite Read Data Channel Signals
+    input                               axi_r_injectsbiterr,
+    input                               axi_r_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,
+    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,
+    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,
+    output                              axi_r_sbiterr,
+    output                              axi_r_dbiterr,
+    output                              axi_r_overflow,
+    output                              axi_r_underflow,
+    output                              axi_r_prog_full,
+    output                              axi_r_prog_empty,
+
+    
+    // AXI Streaming FIFO Related Signals
+    input                               axis_injectsbiterr,
+    input                               axis_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,
+    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,
+    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,
+    output                              axis_sbiterr,
+    output                              axis_dbiterr,
+    output                              axis_overflow,
+    output                              axis_underflow,
+    output                              axis_prog_full,
+    output                              axis_prog_empty
+
+    );
+
+    wire                              BACKUP;
+    wire                              BACKUP_MARKER;
+    wire                              CLK;
+    wire                              RST;
+    wire                              SRST;
+    wire                              WR_CLK;
+    wire                              WR_RST;
+    wire                              RD_CLK;
+    wire                              RD_RST;
+    wire [C_DIN_WIDTH-1:0]            DIN;
+    wire                              WR_EN;
+    wire                              RD_EN;
+    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;
+    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;
+    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;
+    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;
+    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;
+    wire                              INT_CLK;
+    wire                              INJECTDBITERR;
+    wire                              INJECTSBITERR;
+    wire                              SLEEP;
+    wire [C_DOUT_WIDTH-1:0]           DOUT;
+    wire                              FULL;
+    wire                              ALMOST_FULL;
+    wire                              WR_ACK;
+    wire                              OVERFLOW;
+    wire                              EMPTY;
+    wire                              ALMOST_EMPTY;
+    wire                              VALID;
+    wire                              UNDERFLOW;
+    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;
+    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;
+    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;
+    wire                              PROG_FULL;
+    wire                              PROG_EMPTY;
+    wire                              SBITERR;
+    wire                              DBITERR;
+    wire                              WR_RST_BUSY;
+    wire                              RD_RST_BUSY;
+    wire                              M_ACLK;
+    wire                              S_ACLK;
+    wire                              S_ARESETN;
+    wire                              S_ACLK_EN;
+    wire                              M_ACLK_EN;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;
+    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;
+    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;
+    wire [3-1:0]                      S_AXI_AWSIZE;
+    wire [2-1:0]                      S_AXI_AWBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;
+    wire [4-1:0]                      S_AXI_AWCACHE;
+    wire [3-1:0]                      S_AXI_AWPROT;
+    wire [4-1:0]                      S_AXI_AWQOS;
+    wire [4-1:0]                      S_AXI_AWREGION;
+    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;
+    wire                              S_AXI_AWVALID;
+    wire                              S_AXI_AWREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;
+    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;
+    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;
+    wire                              S_AXI_WLAST;
+    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;
+    wire                              S_AXI_WVALID;
+    wire                              S_AXI_WREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;
+    wire [2-1:0]                      S_AXI_BRESP;
+    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;
+    wire                              S_AXI_BVALID;
+    wire                              S_AXI_BREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;
+    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;
+    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;
+    wire [3-1:0]                      M_AXI_AWSIZE;
+    wire [2-1:0]                      M_AXI_AWBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;
+    wire [4-1:0]                      M_AXI_AWCACHE;
+    wire [3-1:0]                      M_AXI_AWPROT;
+    wire [4-1:0]                      M_AXI_AWQOS;
+    wire [4-1:0]                      M_AXI_AWREGION;
+    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;
+    wire                              M_AXI_AWVALID;
+    wire                              M_AXI_AWREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;
+    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;
+    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;
+    wire                              M_AXI_WLAST;
+    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;
+    wire                              M_AXI_WVALID;
+    wire                              M_AXI_WREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;
+    wire [2-1:0]                      M_AXI_BRESP;
+    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;
+    wire                              M_AXI_BVALID;
+    wire                              M_AXI_BREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;
+    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; 
+    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;
+    wire [3-1:0]                      S_AXI_ARSIZE;
+    wire [2-1:0]                      S_AXI_ARBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;
+    wire [4-1:0]                      S_AXI_ARCACHE;
+    wire [3-1:0]                      S_AXI_ARPROT;
+    wire [4-1:0]                      S_AXI_ARQOS;
+    wire [4-1:0]                      S_AXI_ARREGION;
+    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;
+    wire                              S_AXI_ARVALID;
+    wire                              S_AXI_ARREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       
+    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; 
+    wire [2-1:0]                      S_AXI_RRESP;
+    wire                              S_AXI_RLAST;
+    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;
+    wire                              S_AXI_RVALID;
+    wire                              S_AXI_RREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        
+    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  
+    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;
+    wire [3-1:0]                      M_AXI_ARSIZE;
+    wire [2-1:0]                      M_AXI_ARBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;
+    wire [4-1:0]                      M_AXI_ARCACHE;
+    wire [3-1:0]                      M_AXI_ARPROT;
+    wire [4-1:0]                      M_AXI_ARQOS;
+    wire [4-1:0]                      M_AXI_ARREGION;
+    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;
+    wire                              M_AXI_ARVALID;
+    wire                              M_AXI_ARREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        
+    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  
+    wire [2-1:0]                      M_AXI_RRESP;
+    wire                              M_AXI_RLAST;
+    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;
+    wire                              M_AXI_RVALID;
+    wire                              M_AXI_RREADY;
+    wire                              S_AXIS_TVALID;
+    wire                              S_AXIS_TREADY;
+    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;
+    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;
+    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;
+    wire                              S_AXIS_TLAST;
+    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;
+    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;
+    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;
+    wire                              M_AXIS_TVALID;
+    wire                              M_AXIS_TREADY;
+    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;
+    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;
+    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;
+    wire                              M_AXIS_TLAST;
+    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;
+    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;
+    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;
+    wire                              AXI_AW_INJECTSBITERR;
+    wire                              AXI_AW_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;
+    wire                              AXI_AW_SBITERR;
+    wire                              AXI_AW_DBITERR;
+    wire                              AXI_AW_OVERFLOW;
+    wire                              AXI_AW_UNDERFLOW;
+    wire                              AXI_AW_PROG_FULL;
+    wire                              AXI_AW_PROG_EMPTY;
+    wire                              AXI_W_INJECTSBITERR;
+    wire                              AXI_W_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;
+    wire                              AXI_W_SBITERR;
+    wire                              AXI_W_DBITERR;
+    wire                              AXI_W_OVERFLOW;
+    wire                              AXI_W_UNDERFLOW;
+    wire                              AXI_W_PROG_FULL;
+    wire                              AXI_W_PROG_EMPTY;
+    wire                              AXI_B_INJECTSBITERR;
+    wire                              AXI_B_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;
+    wire                              AXI_B_SBITERR;
+    wire                              AXI_B_DBITERR;
+    wire                              AXI_B_OVERFLOW;
+    wire                              AXI_B_UNDERFLOW;
+    wire                              AXI_B_PROG_FULL;
+    wire                              AXI_B_PROG_EMPTY;
+    wire                              AXI_AR_INJECTSBITERR;
+    wire                              AXI_AR_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;
+    wire                              AXI_AR_SBITERR;
+    wire                              AXI_AR_DBITERR;
+    wire                              AXI_AR_OVERFLOW;
+    wire                              AXI_AR_UNDERFLOW;
+    wire                              AXI_AR_PROG_FULL;
+    wire                              AXI_AR_PROG_EMPTY;
+    wire                              AXI_R_INJECTSBITERR;
+    wire                              AXI_R_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;
+    wire                              AXI_R_SBITERR;
+    wire                              AXI_R_DBITERR;
+    wire                              AXI_R_OVERFLOW;
+    wire                              AXI_R_UNDERFLOW;
+    wire                              AXI_R_PROG_FULL;
+    wire                              AXI_R_PROG_EMPTY;
+    wire                              AXIS_INJECTSBITERR;
+    wire                              AXIS_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;
+    wire                              AXIS_SBITERR;
+    wire                              AXIS_DBITERR;
+    wire                              AXIS_OVERFLOW;
+    wire                              AXIS_UNDERFLOW;
+    wire                              AXIS_PROG_FULL;
+    wire                              AXIS_PROG_EMPTY;
+    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;
+    wire                              wr_rst_int;
+    wire                              rd_rst_int;
+    wire                              wr_rst_busy_o;
+    wire                              wr_rst_busy_ntve;
+    wire                              wr_rst_busy_axis;
+    wire                              wr_rst_busy_wach;
+    wire                              wr_rst_busy_wdch;
+    wire                              wr_rst_busy_wrch;
+    wire                              wr_rst_busy_rach;
+    wire                              wr_rst_busy_rdch;
+
+
+
+  function integer find_log2;
+    input integer int_val;
+    integer i,j;
+    begin
+      i = 1;
+      j = 0;
+      for (i = 1; i < int_val; i = i*2) begin
+        j = j + 1;
+      end
+      find_log2 = j;
+    end
+  endfunction
+
+
+
+
+    // Conventional FIFO Interface Signals
+    assign BACKUP                 = backup;
+    assign BACKUP_MARKER          = backup_marker;
+    assign CLK                    = clk;
+    assign RST                    = rst;
+    assign SRST                   = srst;
+    assign WR_CLK                 = wr_clk;
+    assign WR_RST                 = wr_rst;
+    assign RD_CLK                 = rd_clk;
+    assign RD_RST                 = rd_rst;
+    assign WR_EN                  = wr_en;
+    assign RD_EN                  = rd_en;
+    assign INT_CLK                = int_clk;
+    assign INJECTDBITERR          = injectdbiterr;
+    assign INJECTSBITERR          = injectsbiterr;
+    assign SLEEP                  = sleep;
+    assign full                   = FULL;
+    assign almost_full            = ALMOST_FULL;
+    assign wr_ack                 = WR_ACK;
+    assign overflow               = OVERFLOW;
+    assign empty                  = EMPTY;
+    assign almost_empty           = ALMOST_EMPTY;
+    assign valid                  = VALID;
+    assign underflow              = UNDERFLOW;
+    assign prog_full              = PROG_FULL;
+    assign prog_empty             = PROG_EMPTY;
+    assign sbiterr                = SBITERR;
+    assign dbiterr                = DBITERR;
+//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;
+    assign wr_rst_busy            = wr_rst_busy_o;
+    assign rd_rst_busy            = RD_RST_BUSY;
+    assign M_ACLK                 = m_aclk;
+    assign S_ACLK                 = s_aclk;
+    assign S_ARESETN              = s_aresetn;
+    assign S_ACLK_EN              = s_aclk_en;
+    assign M_ACLK_EN              = m_aclk_en;
+    assign S_AXI_AWVALID          = s_axi_awvalid;
+    assign s_axi_awready          = S_AXI_AWREADY;
+    assign S_AXI_WLAST            = s_axi_wlast;
+    assign S_AXI_WVALID           = s_axi_wvalid;
+    assign s_axi_wready           = S_AXI_WREADY;
+    assign s_axi_bvalid           = S_AXI_BVALID;
+    assign S_AXI_BREADY           = s_axi_bready;
+    assign m_axi_awvalid          = M_AXI_AWVALID;
+    assign M_AXI_AWREADY          = m_axi_awready;
+    assign m_axi_wlast            = M_AXI_WLAST;
+    assign m_axi_wvalid           = M_AXI_WVALID;
+    assign M_AXI_WREADY           = m_axi_wready;
+    assign M_AXI_BVALID           = m_axi_bvalid;
+    assign m_axi_bready           = M_AXI_BREADY;
+    assign S_AXI_ARVALID          = s_axi_arvalid;
+    assign s_axi_arready          = S_AXI_ARREADY;
+    assign s_axi_rlast            = S_AXI_RLAST;
+    assign s_axi_rvalid           = S_AXI_RVALID;
+    assign S_AXI_RREADY           = s_axi_rready;
+    assign m_axi_arvalid          = M_AXI_ARVALID;
+    assign M_AXI_ARREADY          = m_axi_arready;
+    assign M_AXI_RLAST            = m_axi_rlast;
+    assign M_AXI_RVALID           = m_axi_rvalid;
+    assign m_axi_rready           = M_AXI_RREADY;
+    assign S_AXIS_TVALID          = s_axis_tvalid;
+    assign s_axis_tready          = S_AXIS_TREADY;
+    assign S_AXIS_TLAST           = s_axis_tlast;
+    assign m_axis_tvalid          = M_AXIS_TVALID;
+    assign M_AXIS_TREADY          = m_axis_tready;
+    assign m_axis_tlast           = M_AXIS_TLAST;
+    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;
+    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;
+    assign axi_aw_sbiterr         = AXI_AW_SBITERR;
+    assign axi_aw_dbiterr         = AXI_AW_DBITERR;
+    assign axi_aw_overflow        = AXI_AW_OVERFLOW;
+    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;
+    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;
+    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;
+    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;
+    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;
+    assign axi_w_sbiterr          = AXI_W_SBITERR;
+    assign axi_w_dbiterr          = AXI_W_DBITERR;
+    assign axi_w_overflow         = AXI_W_OVERFLOW;
+    assign axi_w_underflow        = AXI_W_UNDERFLOW;
+    assign axi_w_prog_full        = AXI_W_PROG_FULL;
+    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;
+    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;
+    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;
+    assign axi_b_sbiterr          = AXI_B_SBITERR;
+    assign axi_b_dbiterr          = AXI_B_DBITERR;
+    assign axi_b_overflow         = AXI_B_OVERFLOW;
+    assign axi_b_underflow        = AXI_B_UNDERFLOW;
+    assign axi_b_prog_full        = AXI_B_PROG_FULL;
+    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;
+    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;
+    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;
+    assign axi_ar_sbiterr         = AXI_AR_SBITERR;
+    assign axi_ar_dbiterr         = AXI_AR_DBITERR;
+    assign axi_ar_overflow        = AXI_AR_OVERFLOW;
+    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;
+    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;
+    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;
+    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;
+    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;
+    assign axi_r_sbiterr          = AXI_R_SBITERR;
+    assign axi_r_dbiterr          = AXI_R_DBITERR;
+    assign axi_r_overflow         = AXI_R_OVERFLOW;
+    assign axi_r_underflow        = AXI_R_UNDERFLOW;
+    assign axi_r_prog_full        = AXI_R_PROG_FULL;
+    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;
+    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;
+    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;
+    assign axis_sbiterr           = AXIS_SBITERR;
+    assign axis_dbiterr           = AXIS_DBITERR;
+    assign axis_overflow          = AXIS_OVERFLOW;
+    assign axis_underflow         = AXIS_UNDERFLOW;
+    assign axis_prog_full         = AXIS_PROG_FULL;
+    assign axis_prog_empty        = AXIS_PROG_EMPTY;
+
+
+    assign DIN                       = din;
+    assign PROG_EMPTY_THRESH         = prog_empty_thresh;
+    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;
+    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;
+    assign PROG_FULL_THRESH          = prog_full_thresh;
+    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;
+    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;
+    assign dout                      = DOUT;
+    assign data_count                = DATA_COUNT;
+    assign rd_data_count             = RD_DATA_COUNT;
+    assign wr_data_count             = WR_DATA_COUNT;
+    assign S_AXI_AWID                = s_axi_awid;
+    assign S_AXI_AWADDR              = s_axi_awaddr;
+    assign S_AXI_AWLEN               = s_axi_awlen;
+    assign S_AXI_AWSIZE              = s_axi_awsize;
+    assign S_AXI_AWBURST             = s_axi_awburst;
+    assign S_AXI_AWLOCK              = s_axi_awlock;
+    assign S_AXI_AWCACHE             = s_axi_awcache;
+    assign S_AXI_AWPROT              = s_axi_awprot;
+    assign S_AXI_AWQOS               = s_axi_awqos;
+    assign S_AXI_AWREGION            = s_axi_awregion;
+    assign S_AXI_AWUSER              = s_axi_awuser;
+    assign S_AXI_WID                 = s_axi_wid;
+    assign S_AXI_WDATA               = s_axi_wdata;
+    assign S_AXI_WSTRB               = s_axi_wstrb;
+    assign S_AXI_WUSER               = s_axi_wuser;
+    assign s_axi_bid                 = S_AXI_BID;
+    assign s_axi_bresp               = S_AXI_BRESP;
+    assign s_axi_buser               = S_AXI_BUSER;
+    assign m_axi_awid                = M_AXI_AWID;
+    assign m_axi_awaddr              = M_AXI_AWADDR;
+    assign m_axi_awlen               = M_AXI_AWLEN;
+    assign m_axi_awsize              = M_AXI_AWSIZE;
+    assign m_axi_awburst             = M_AXI_AWBURST;
+    assign m_axi_awlock              = M_AXI_AWLOCK;
+    assign m_axi_awcache             = M_AXI_AWCACHE;
+    assign m_axi_awprot              = M_AXI_AWPROT;
+    assign m_axi_awqos               = M_AXI_AWQOS;
+    assign m_axi_awregion            = M_AXI_AWREGION;
+    assign m_axi_awuser              = M_AXI_AWUSER;
+    assign m_axi_wid                 = M_AXI_WID;
+    assign m_axi_wdata               = M_AXI_WDATA;
+    assign m_axi_wstrb               = M_AXI_WSTRB;
+    assign m_axi_wuser               = M_AXI_WUSER;
+    assign M_AXI_BID                 = m_axi_bid;
+    assign M_AXI_BRESP               = m_axi_bresp;
+    assign M_AXI_BUSER               = m_axi_buser;
+    assign S_AXI_ARID                = s_axi_arid;
+    assign S_AXI_ARADDR              = s_axi_araddr; 
+    assign S_AXI_ARLEN               = s_axi_arlen;
+    assign S_AXI_ARSIZE              = s_axi_arsize;
+    assign S_AXI_ARBURST             = s_axi_arburst;
+    assign S_AXI_ARLOCK              = s_axi_arlock;
+    assign S_AXI_ARCACHE             = s_axi_arcache;
+    assign S_AXI_ARPROT              = s_axi_arprot;
+    assign S_AXI_ARQOS               = s_axi_arqos;
+    assign S_AXI_ARREGION            = s_axi_arregion;
+    assign S_AXI_ARUSER              = s_axi_aruser;
+    assign s_axi_rid                 = S_AXI_RID;
+    assign s_axi_rdata               = S_AXI_RDATA;
+    assign s_axi_rresp               = S_AXI_RRESP;
+    assign s_axi_ruser               = S_AXI_RUSER;
+    assign m_axi_arid                = M_AXI_ARID;        
+    assign m_axi_araddr              = M_AXI_ARADDR;  
+    assign m_axi_arlen               = M_AXI_ARLEN;
+    assign m_axi_arsize              = M_AXI_ARSIZE;
+    assign m_axi_arburst             = M_AXI_ARBURST;
+    assign m_axi_arlock              = M_AXI_ARLOCK;
+    assign m_axi_arcache             = M_AXI_ARCACHE;
+    assign m_axi_arprot              = M_AXI_ARPROT;
+    assign m_axi_arqos               = M_AXI_ARQOS;
+    assign m_axi_arregion            = M_AXI_ARREGION;
+    assign m_axi_aruser              = M_AXI_ARUSER;
+    assign M_AXI_RID                 = m_axi_rid;        
+    assign M_AXI_RDATA               = m_axi_rdata;  
+    assign M_AXI_RRESP               = m_axi_rresp;
+    assign M_AXI_RUSER               = m_axi_ruser;
+    assign S_AXIS_TDATA              = s_axis_tdata;
+    assign S_AXIS_TSTRB              = s_axis_tstrb;
+    assign S_AXIS_TKEEP              = s_axis_tkeep;
+    assign S_AXIS_TID                = s_axis_tid;
+    assign S_AXIS_TDEST              = s_axis_tdest;
+    assign S_AXIS_TUSER              = s_axis_tuser;
+    assign m_axis_tdata              = M_AXIS_TDATA;
+    assign m_axis_tstrb              = M_AXIS_TSTRB;
+    assign m_axis_tkeep              = M_AXIS_TKEEP;
+    assign m_axis_tid                = M_AXIS_TID;
+    assign m_axis_tdest              = M_AXIS_TDEST;
+    assign m_axis_tuser              = M_AXIS_TUSER;
+    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;
+    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;
+    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;
+    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;
+    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;
+    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;
+    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;
+    assign axi_w_data_count          = AXI_W_DATA_COUNT;
+    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;
+    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;
+    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;
+    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;
+    assign axi_b_data_count          = AXI_B_DATA_COUNT;
+    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;
+    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;
+    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;
+    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;
+    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;
+    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;
+    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;
+    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;
+    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;
+    assign axi_r_data_count          = AXI_R_DATA_COUNT;
+    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;
+    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;
+    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;
+    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;
+    assign axis_data_count           = AXIS_DATA_COUNT;
+    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;
+    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;
+
+
+  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_COMMON_CLOCK 		(C_COMMON_CLOCK),
+        .C_INTERFACE_TYPE 		(C_INTERFACE_TYPE),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DATA_COUNT_WIDTH		(C_DATA_COUNT_WIDTH),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_DIN_WIDTH			(C_DIN_WIDTH),
+        .C_DOUT_RST_VAL			(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
+        .C_DOUT_WIDTH			(C_DOUT_WIDTH),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_FAMILY			(C_FAMILY),
+        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),
+        .C_HAS_ALMOST_EMPTY		(C_HAS_ALMOST_EMPTY),
+        .C_HAS_ALMOST_FULL		(C_HAS_ALMOST_FULL),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_DATA_COUNT		(C_HAS_DATA_COUNT),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_HAS_RD_DATA_COUNT		(C_HAS_RD_DATA_COUNT),
+        .C_HAS_RD_RST			(C_HAS_RD_RST),
+        .C_HAS_RST			(C_HAS_RST),
+        .C_HAS_SRST			(C_HAS_SRST),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_HAS_VALID			(C_HAS_VALID),
+        .C_HAS_WR_ACK			(C_HAS_WR_ACK),
+        .C_HAS_WR_DATA_COUNT		(C_HAS_WR_DATA_COUNT),
+        .C_HAS_WR_RST			(C_HAS_WR_RST),
+        .C_IMPLEMENTATION_TYPE		(C_IMPLEMENTATION_TYPE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_MEMORY_TYPE			(C_MEMORY_TYPE),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+        .C_PRELOAD_LATENCY		(C_PRELOAD_LATENCY),
+        .C_PRELOAD_REGS			(C_PRELOAD_REGS),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL),
+        .C_PROG_EMPTY_THRESH_NEGATE_VAL	(C_PROG_EMPTY_THRESH_NEGATE_VAL),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL),
+        .C_PROG_FULL_THRESH_NEGATE_VAL	(C_PROG_FULL_THRESH_NEGATE_VAL),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE),
+        .C_RD_DATA_COUNT_WIDTH		(C_RD_DATA_COUNT_WIDTH),
+        .C_RD_DEPTH			(C_RD_DEPTH),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_RD_PNTR_WIDTH		(C_RD_PNTR_WIDTH),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),
+        .C_USE_ECC                      (C_USE_ECC),
+        .C_USE_EMBEDDED_REG		(C_USE_EMBEDDED_REG),
+        .C_EN_SAFETY_CKT		(C_EN_SAFETY_CKT),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_USE_FWFT_DATA_COUNT		(C_USE_FWFT_DATA_COUNT),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_DATA_COUNT_WIDTH),
+        .C_WR_DEPTH			(C_WR_DEPTH),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),
+        .C_AXI_TYPE                     (C_AXI_TYPE),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)
+      )
+    fifo_generator_v13_2_5_conv_dut
+      (
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .CLK                      (CLK),
+        .RST                      (RST),
+        .SRST                     (SRST),
+        .WR_CLK                   (WR_CLK),
+        .WR_RST                   (WR_RST),
+        .RD_CLK                   (RD_CLK),
+        .RD_RST                   (RD_RST),
+        .DIN                      (DIN),
+        .WR_EN                    (WR_EN),
+        .RD_EN                    (RD_EN),
+        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
+        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
+        .PROG_FULL_THRESH         (PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
+        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
+        .INT_CLK                  (INT_CLK),
+        .INJECTDBITERR            (INJECTDBITERR), 
+        .INJECTSBITERR            (INJECTSBITERR),
+  
+        .DOUT                     (DOUT),
+        .FULL                     (FULL),
+        .ALMOST_FULL              (ALMOST_FULL),
+        .WR_ACK                   (WR_ACK),
+        .OVERFLOW                 (OVERFLOW),
+        .EMPTY                    (EMPTY),
+        .ALMOST_EMPTY             (ALMOST_EMPTY),
+        .VALID                    (VALID),
+        .UNDERFLOW                (UNDERFLOW),
+        .DATA_COUNT               (DATA_COUNT),
+        .RD_DATA_COUNT            (RD_DATA_COUNT),
+        .WR_DATA_COUNT            (wr_data_count_in),
+        .PROG_FULL                (PROG_FULL),
+        .PROG_EMPTY               (PROG_EMPTY),
+        .SBITERR                  (SBITERR),
+        .DBITERR                  (DBITERR),
+        .wr_rst_busy_o            (wr_rst_busy_o),
+        .wr_rst_busy              (wr_rst_busy_i),
+        .rd_rst_busy              (rd_rst_busy),
+        .wr_rst_i_out             (wr_rst_int),
+        .rd_rst_i_out             (rd_rst_int)
+       );
+  end endgenerate
+
+
+
+  localparam IS_8SERIES         = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
+  localparam C_AXI_SIZE_WIDTH   = 3;
+  localparam C_AXI_BURST_WIDTH  = 2;
+  localparam C_AXI_CACHE_WIDTH  = 4;
+  localparam C_AXI_PROT_WIDTH   = 3;
+  localparam C_AXI_QOS_WIDTH    = 4;
+  localparam C_AXI_REGION_WIDTH = 4;
+  localparam C_AXI_BRESP_WIDTH  = 2;
+  localparam C_AXI_RRESP_WIDTH  = 2;
+
+  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;
+  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
+  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
+  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
+  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
+  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
+  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
+  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); 
+  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); 
+
+
+  function [LOG_DEPTH_AXIS-1:0] bin2gray;
+      input [LOG_DEPTH_AXIS-1:0] x;
+      begin
+         bin2gray = x ^ (x>>1);
+      end
+   endfunction
+
+  function [LOG_DEPTH_AXIS-1:0] gray2bin;
+      input [LOG_DEPTH_AXIS-1:0] x;
+      integer                i;
+      begin
+         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
+         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
+            gray2bin[i] =  gray2bin[i+1] ^ x[i];
+         end
+      end
+   endfunction
+
+wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
+wire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;
+wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;
+reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
+reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
+reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
+reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
+wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
+wire [LOG_WR_DEPTH : 0] r_inv_pad;
+wire [LOG_WR_DEPTH-1 : 0] d_cnt;
+reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
+reg adj_w_cnt_rd_pad_0 = 0;
+reg r_inv_pad_0 = 0;
+
+
+   genvar l;
+
+   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
+     fifo_generator_v13_2_5_sync_stage
+       #(
+         .C_WIDTH  (LOG_WR_DEPTH)
+        )
+     rd_stg_inst
+        (
+         .RST      (rd_rst_int), 
+         .CLK      (RD_CLK), 
+         .DIN      (w_q[l-1]), 
+         .DOUT     (w_q[l])
+        );
+   end endgenerate // gpkt_cnt_sync_stage
+
+
+
+      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
+    assign wr_eop_ad = WR_EN & !(FULL);
+    assign rd_eop_ad = RD_EN & !(EMPTY);
+
+
+  always @ (posedge wr_rst_int or posedge WR_CLK)
+    begin
+      if (wr_rst_int)
+        w_cnt    <= 1'b0;
+      else if (wr_eop_ad)
+        w_cnt    <= w_cnt + 1;
+    end
+
+  always @ (posedge wr_rst_int or posedge WR_CLK)
+    begin
+      if (wr_rst_int)
+        w_cnt_gc    <= 1'b0;
+      else 
+        w_cnt_gc    <= bin2gray(w_cnt);
+    end
+
+
+    assign  w_q[0]  = w_cnt_gc;
+    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];
+
+
+
+  always @ (posedge rd_rst_int or posedge RD_CLK)
+    begin
+      if (rd_rst_int)
+        w_cnt_rd    <= 1'b0;
+      else 
+        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);
+    end
+
+  always @ (posedge rd_rst_int or posedge RD_CLK)
+    begin
+      if (rd_rst_int)
+        r_cnt    <= 1'b0;
+      else if (rd_eop_ad)
+        r_cnt    <= r_cnt + 1;
+    end
+
+
+  // Take the difference of write and read packet count
+  // Logic is similar to rd_pe_as
+   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
+   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;
+   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;
+   assign r_inv_pad[0]                       = r_inv_pad_0;
+
+
+  always @ ( rd_eop_ad )
+    begin
+      if (!rd_eop_ad) begin
+        adj_w_cnt_rd_pad_0    <= 1'b1;
+        r_inv_pad_0           <= 1'b1;
+      end else begin 
+        adj_w_cnt_rd_pad_0    <= 1'b0;
+        r_inv_pad_0           <= 1'b0;
+      end	
+    end
+
+  always @ (posedge rd_rst_int or posedge RD_CLK)
+    begin
+      if (rd_rst_int)
+        d_cnt_pad    <= 1'b0;
+      else 
+        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;
+    end
+
+   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
+   assign  WR_DATA_COUNT = d_cnt;
+
+  end endgenerate // fifo_ic_adapter
+
+      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
+   assign  WR_DATA_COUNT = wr_data_count_in;
+
+  end endgenerate // fifo_icn_adapter
+
+
+
+  wire                          inverted_reset = ~S_ARESETN;
+  wire                          axi_rs_rst;
+  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;
+  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;
+  wire                          axis_full         ;
+  wire                          axis_almost_full  ;
+  wire                          axis_empty        ;
+  wire                          axis_s_axis_tready;
+  wire                          axis_m_axis_tvalid;
+  wire                          axis_wr_en        ;
+  wire                          axis_rd_en        ;
+  wire                          axis_we           ;
+  wire                          axis_re           ;
+  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
+  reg                           axis_pkt_read = 1'b0;
+  wire                          axis_rd_rst;
+  wire                          axis_wr_rst;
+
+  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
+               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
+      reg                           rst_d1 = 0        ;
+      reg                           rst_d2 = 0        ;
+      reg [3:0]                    axi_rst = 4'h0     ;
+      always @ (posedge inverted_reset or posedge S_ACLK) begin
+        if (inverted_reset) begin
+          rst_d1         <= 1'b1;
+          rst_d2         <= 1'b1;
+          axi_rst        <= 4'hf;
+        end else begin
+          rst_d1         <= #`TCQ 1'b0;
+          rst_d2         <= #`TCQ rst_d1;
+          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};
+        end
+      end
+
+      assign axi_rs_rst = axi_rst[3];//rst_d2;
+  end endgenerate // gaxi_rs_rst
+
+  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
+
+    // Write protection when almost full or prog_full is high
+    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : 
+                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
+                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
+    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;
+    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_FAMILY			(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),
+        .C_MEMORY_TYPE			((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE		((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
+        .C_PRELOAD_REGS			(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY		(0), // always FWFT for AXI
+        .C_DIN_WIDTH			(C_DIN_WIDTH_AXIS),
+        .C_WR_DEPTH			(C_WR_DEPTH_AXIS),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH_AXIS),
+        .C_DOUT_WIDTH			(C_DIN_WIDTH_AXIS),
+        .C_RD_DEPTH			(C_WR_DEPTH_AXIS),
+        .C_RD_PNTR_WIDTH		(C_WR_PNTR_WIDTH_AXIS),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE_AXIS),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE_AXIS),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
+        .C_USE_ECC                      (C_USE_ECC_AXIS),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),
+        .C_HAS_ALMOST_EMPTY		(0),
+        .C_HAS_ALMOST_FULL		(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+        .C_USE_EMBEDDED_REG		(C_USE_EMBEDDED_REG),
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST			(0),
+        .C_HAS_RD_RST			(0),
+        .C_HAS_RST			(1),
+        .C_HAS_SRST			(0),
+        .C_DOUT_RST_VAL			(0),
+
+        .C_HAS_VALID			(0),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK			(0),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT		((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_AXIS + 1),
+        .C_HAS_RD_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_AXIS + 1),
+        .C_USE_FWFT_DATA_COUNT		(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_AXIS + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_2_5_axis_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (axis_wr_en),
+        .RD_EN                    (axis_rd_en),
+        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
+        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
+        .INJECTDBITERR            (AXIS_INJECTDBITERR), 
+        .INJECTSBITERR            (AXIS_INJECTSBITERR),
+  
+        .DIN                      (axis_din),
+        .DOUT                     (axis_dout),
+        .FULL                     (axis_full),
+        .EMPTY                    (axis_empty),
+        .ALMOST_FULL              (axis_almost_full),
+        .PROG_FULL                (AXIS_PROG_FULL),
+        .ALMOST_EMPTY             (),
+        .PROG_EMPTY               (AXIS_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (AXIS_OVERFLOW),
+        .VALID                    (),
+        .UNDERFLOW                (AXIS_UNDERFLOW),
+        .DATA_COUNT               (axis_dc),
+        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),
+        .SBITERR                  (AXIS_SBITERR),
+        .DBITERR                  (AXIS_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_axis),
+        .rd_rst_busy              (rd_rst_busy_axis),
+        .wr_rst_i_out             (axis_wr_rst),
+        .rd_rst_i_out             (axis_rd_rst),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
+    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
+    assign S_AXIS_TREADY         = axis_s_axis_tready;
+    assign M_AXIS_TVALID         = axis_m_axis_tvalid;
+
+  end endgenerate // axi_streaming
+
+  wire axis_wr_eop;
+  reg  axis_wr_eop_d1 = 1'b0;
+  wire axis_rd_eop;
+  integer  axis_pkt_cnt;
+
+  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
+    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
+    assign axis_rd_eop = axis_rd_en & axis_dout[0];
+
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_pkt_read    <= 1'b0;
+      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
+        axis_pkt_read    <= 1'b0;
+      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
+        axis_pkt_read    <= 1'b1;
+    end
+
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_wr_eop_d1    <= 1'b0;
+      else
+        axis_wr_eop_d1   <= axis_wr_eop;
+    end
+
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_pkt_cnt    <= 0;
+      else if (axis_wr_eop_d1 && ~axis_rd_eop)
+        axis_pkt_cnt    <= axis_pkt_cnt + 1;
+      else if (axis_rd_eop && ~axis_wr_eop_d1)
+        axis_pkt_cnt    <= axis_pkt_cnt - 1;
+    end
+  end endgenerate // gaxis_pkt_fifo_cc
+
+
+reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
+wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
+wire axis_rd_has_rst;
+wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
+wire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
+wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
+wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;
+reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
+reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
+reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
+wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
+wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
+wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
+reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
+reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
+reg rpkt_inv_pad_0 = 0;
+wire axis_af_rd ;
+
+generate if (C_HAS_RST == 1) begin : rst_blk_has
+  assign axis_rd_has_rst = axis_rd_rst;
+end endgenerate //rst_blk_has
+
+generate if (C_HAS_RST == 0) begin :rst_blk_no
+  assign axis_rd_has_rst = 1'b0;
+end endgenerate //rst_blk_no
+
+   genvar i;
+
+   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
+     fifo_generator_v13_2_5_sync_stage
+       #(
+         .C_WIDTH  (LOG_DEPTH_AXIS)
+        )
+     rd_stg_inst
+        (
+         .RST      (axis_rd_has_rst), 
+         .CLK      (M_ACLK), 
+         .DIN      (wpkt_q[i-1]), 
+         .DOUT     (wpkt_q[i])
+        );
+ 
+     fifo_generator_v13_2_5_sync_stage
+       #(
+         .C_WIDTH  (1)
+        )
+     wr_stg_inst
+        (
+         .RST      (axis_rd_has_rst), 
+         .CLK      (M_ACLK), 
+         .DIN      (axis_af_q[i-1]), 
+         .DOUT     (axis_af_q[i])
+        );
+   end endgenerate // gpkt_cnt_sync_stage
+
+
+  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
+    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
+    assign axis_rd_eop = axis_rd_en & axis_dout[0];
+
+    always @ (posedge axis_rd_has_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        axis_pkt_read    <= 1'b0;
+      else if (axis_rd_eop && (diff_pkt_cnt == 1))
+        axis_pkt_read    <= 1'b0;
+      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
+        axis_pkt_read    <= 1'b1;
+    end
+
+  always @ (posedge axis_wr_rst or posedge S_ACLK)
+    begin
+      if (axis_wr_rst)
+        axis_wpkt_cnt    <= 1'b0;
+      else if (axis_wr_eop)
+        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;
+    end
+
+  always @ (posedge axis_wr_rst or posedge S_ACLK)
+    begin
+      if (axis_wr_rst)
+        axis_wpkt_cnt_gc    <= 1'b0;
+      else 
+        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);
+    end
+
+
+    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;
+    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];
+    assign  axis_af_q[0]                      = axis_almost_full;
+    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
+    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];
+
+
+
+  always @ (posedge axis_rd_has_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        axis_wpkt_cnt_rd    <= 1'b0;
+      else 
+        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
+    end
+
+  always @ (posedge axis_rd_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        axis_rpkt_cnt    <= 1'b0;
+      else if (axis_rd_eop)
+        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;
+    end
+
+
+  // Take the difference of write and read packet count
+  // Logic is similar to rd_pe_as
+   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
+   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;
+   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;
+   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;
+
+
+  always @ ( axis_rd_eop )
+    begin
+      if (!axis_rd_eop) begin
+        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;
+        rpkt_inv_pad_0                <= 1'b1;
+      end else begin 
+        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;
+        rpkt_inv_pad_0                <= 1'b0;
+      end	
+    end
+
+  always @ (posedge axis_rd_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        diff_pkt_cnt_pad    <= 1'b0;
+      else 
+        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
+    end
+
+   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
+
+
+
+
+
+   end endgenerate // gaxis_pkt_fifo_ic
+
+
+
+
+  // Generate the accurate data count for axi stream packet fifo configuration
+  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
+  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_dc_pkt_fifo <= 0;
+      else if (axis_wr_en && (~axis_rd_en))
+        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
+      else if (~axis_wr_en && axis_rd_en)
+        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
+    end
+    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
+  end endgenerate // gdc_pkt
+
+  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
+    assign AXIS_DATA_COUNT = 0;
+  end endgenerate // gndc_pkt
+
+  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
+    assign AXIS_DATA_COUNT = axis_dc;
+  end endgenerate // gdc
+
+  // Register Slice for Write Address Channel
+  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
+    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
+    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)
+            )
+    axis_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (axis_din),
+          .S_VALID                   (axis_wr_en),
+          .S_READY                   (S_AXIS_TREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (axis_dout),
+          .M_VALID                   (M_AXIS_TVALID),
+          .M_READY                   (axis_rd_en)
+          );
+  end endgenerate // gaxis_reg_slice
+
+
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
+    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
+    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
+    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
+    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
+    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
+    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
+    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
+    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
+    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
+    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
+    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
+    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
+    assign axis_din[0] = S_AXIS_TLAST;
+    assign M_AXIS_TLAST   = axis_dout[0];
+  end endgenerate
+
+  //###########################################################################
+  //  AXI FULL Write Channel (axi_write_channel)
+  //###########################################################################
+
+  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
+  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
+
+  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+
+  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+
+  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
+  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
+  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
+  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
+  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
+
+  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
+  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;
+  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
+  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
+  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
+  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
+  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
+  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
+  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
+  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
+  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
+
+  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
+  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;
+  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
+  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
+
+  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
+  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;
+  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
+
+
+  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;
+  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;
+  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;
+  wire                          wach_full         ;
+  wire                          wach_almost_full  ;
+  wire                          wach_prog_full    ;
+  wire                          wach_empty        ;
+  wire                          wach_almost_empty ;
+  wire                          wach_prog_empty   ;
+  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;
+  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;
+  wire                          wdch_full         ;
+  wire                          wdch_almost_full  ;
+  wire                          wdch_prog_full    ;
+  wire                          wdch_empty        ;
+  wire                          wdch_almost_empty ;
+  wire                          wdch_prog_empty   ;
+  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;
+  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;
+  wire                          wrch_full         ;
+  wire                          wrch_almost_full  ;
+  wire                          wrch_prog_full    ;
+  wire                          wrch_empty        ;
+  wire                          wrch_almost_empty ;
+  wire                          wrch_prog_empty   ;
+  wire                          axi_aw_underflow_i;
+  wire                          axi_w_underflow_i ;
+  wire                          axi_b_underflow_i ;
+  wire                          axi_aw_overflow_i ;
+  wire                          axi_w_overflow_i  ;
+  wire                          axi_b_overflow_i  ;
+  wire                          axi_wr_underflow_i;
+  wire                          axi_wr_overflow_i ;
+  wire                          wach_s_axi_awready;
+  wire                          wach_m_axi_awvalid;
+  wire                          wach_wr_en        ;
+  wire                          wach_rd_en        ;
+  wire                          wdch_s_axi_wready ;
+  wire                          wdch_m_axi_wvalid ;
+  wire                          wdch_wr_en        ;
+  wire                          wdch_rd_en        ;
+  wire                          wrch_s_axi_bvalid ;
+  wire                          wrch_m_axi_bready ;
+  wire                          wrch_wr_en        ;
+  wire                          wrch_rd_en        ;
+  wire                          txn_count_up      ;
+  wire                          txn_count_down    ;
+  wire                          awvalid_en        ;
+  wire                          awvalid_pkt       ;
+  wire                          awready_pkt       ;
+  integer                       wr_pkt_count      ;
+  wire                          wach_we           ;
+  wire                          wach_re           ;
+  wire                          wdch_we           ;
+  wire                          wdch_re           ;
+  wire                          wrch_we           ;
+  wire                          wrch_re           ;
+
+  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
+    // Write protection when almost full or prog_full is high
+    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? 
+                        wach_m_axi_awvalid & awready_pkt & awvalid_en : 
+                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? 
+                        M_AXI_AWREADY && wach_m_axi_awvalid :
+                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? 
+                        awready_pkt & awvalid_en : 
+                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? 
+                        M_AXI_AWREADY : 1'b0;
+    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;
+    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_FAMILY			(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE			((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE		((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS			(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY		(0), // always FWFT for AXI
+        .C_DIN_WIDTH			(C_DIN_WIDTH_WACH),
+        .C_INTERFACE_TYPE 		(C_INTERFACE_TYPE),
+        .C_WR_DEPTH			(C_WR_DEPTH_WACH),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH_WACH),
+        .C_DOUT_WIDTH			(C_DIN_WIDTH_WACH),
+        .C_RD_DEPTH			(C_WR_DEPTH_WACH),
+        .C_RD_PNTR_WIDTH		(C_WR_PNTR_WIDTH_WACH),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE_WACH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE_WACH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
+        .C_USE_ECC                      (C_USE_ECC_WACH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),
+        .C_HAS_ALMOST_EMPTY		(0),
+        .C_HAS_ALMOST_FULL		(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST			(0),
+        .C_HAS_RD_RST			(0),
+        .C_HAS_RST			(1),
+        .C_HAS_SRST			(0),
+        .C_DOUT_RST_VAL			(0),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
+        .C_HAS_VALID			(0),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK			(0),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT		((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WACH + 1),
+        .C_HAS_RD_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WACH + 1),
+        .C_USE_FWFT_DATA_COUNT		(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WACH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG		(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_2_5_wach_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (wach_wr_en),
+        .RD_EN                    (wach_rd_en),
+        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
+        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),
+  
+        .DIN                      (wach_din),
+        .DOUT                     (wach_dout_pkt),
+        .FULL                     (wach_full),
+        .EMPTY                    (wach_empty),
+        .ALMOST_FULL              (),
+        .PROG_FULL                (AXI_AW_PROG_FULL),
+        .ALMOST_EMPTY             (),
+        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_aw_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_aw_underflow_i),
+        .DATA_COUNT               (AXI_AW_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),
+        .SBITERR                  (AXI_AW_SBITERR),
+        .DBITERR                  (AXI_AW_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_wach),
+        .rd_rst_busy              (rd_rst_busy_wach),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
+    assign wach_m_axi_awvalid   = ~wach_empty;
+    assign S_AXI_AWREADY        = wach_s_axi_awready;
+
+    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
+    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;
+
+  end endgenerate // axi_write_address_channel
+
+  // Register Slice for Write Address Channel
+  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)
+            )
+    wach_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wach_din),
+          .S_VALID                   (S_AXI_AWVALID),
+          .S_READY                   (S_AXI_AWREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wach_dout),
+          .M_VALID                   (M_AXI_AWVALID),
+          .M_READY                   (M_AXI_AWREADY)
+          );
+  end endgenerate // gwach_reg_slice
+  
+  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),
+            .C_REG_CONFIG            (1)
+            )
+    wach_pkt_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wach_dout_pkt),
+          .S_VALID                   (awvalid_pkt),
+          .S_READY                   (awready_pkt),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wach_dout),
+          .M_VALID                   (M_AXI_AWVALID),
+          .M_READY                   (M_AXI_AWREADY)
+          );
+
+    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
+
+    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; 
+    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
+
+    always@(posedge S_ACLK or posedge inverted_reset) begin
+      if(inverted_reset == 1) begin
+	wr_pkt_count <= 0;
+      end else begin
+	if(txn_count_up == 1 && txn_count_down == 0) begin
+	  wr_pkt_count <= wr_pkt_count + 1;
+	end else if(txn_count_up == 0 && txn_count_down == 1) begin
+	  wr_pkt_count <= wr_pkt_count - 1;
+	end
+      end
+    end //Always end
+    assign awvalid_en = (wr_pkt_count > 0)?1:0;
+  end endgenerate
+  
+  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
+    assign awvalid_en    = 1;    
+    assign wach_dout     = wach_dout_pkt;
+    assign M_AXI_AWVALID = wach_m_axi_awvalid;
+  end
+  endgenerate
+
+
+
+  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
+    // Write protection when almost full or prog_full is high
+    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
+    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;
+    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
+
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_FAMILY			(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE			((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE		((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS			(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY		(0), // always FWFT for AXI
+        .C_DIN_WIDTH			(C_DIN_WIDTH_WDCH),
+        .C_WR_DEPTH			(C_WR_DEPTH_WDCH),
+        .C_INTERFACE_TYPE 		(C_INTERFACE_TYPE),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH_WDCH),
+        .C_DOUT_WIDTH			(C_DIN_WIDTH_WDCH),
+        .C_RD_DEPTH			(C_WR_DEPTH_WDCH),
+        .C_RD_PNTR_WIDTH		(C_WR_PNTR_WIDTH_WDCH),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE_WDCH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE_WDCH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
+        .C_USE_ECC                      (C_USE_ECC_WDCH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),
+        .C_HAS_ALMOST_EMPTY		(0),
+        .C_HAS_ALMOST_FULL		(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST			(0),
+        .C_HAS_RD_RST			(0),
+        .C_HAS_RST			(1),
+        .C_HAS_SRST			(0),
+        .C_DOUT_RST_VAL			(0),
+
+        .C_HAS_VALID			(0),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK			(0),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT		((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WDCH + 1),
+        .C_HAS_RD_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WDCH + 1),
+        .C_USE_FWFT_DATA_COUNT		(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WDCH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG		(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_2_5_wdch_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (wdch_wr_en),
+        .RD_EN                    (wdch_rd_en),
+        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
+        .INJECTDBITERR            (AXI_W_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_W_INJECTSBITERR),
+  
+        .DIN                      (wdch_din),
+        .DOUT                     (wdch_dout),
+        .FULL                     (wdch_full),
+        .EMPTY                    (wdch_empty),
+        .ALMOST_FULL              (),
+        .PROG_FULL                (AXI_W_PROG_FULL),
+        .ALMOST_EMPTY             (),
+        .PROG_EMPTY               (AXI_W_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_w_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_w_underflow_i),
+        .DATA_COUNT               (AXI_W_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),
+        .SBITERR                  (AXI_W_SBITERR),
+        .DBITERR                  (AXI_W_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_wdch),
+        .rd_rst_busy              (rd_rst_busy_wdch),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
+    assign wdch_m_axi_wvalid = ~wdch_empty;
+    assign S_AXI_WREADY      = wdch_s_axi_wready;
+    assign M_AXI_WVALID      = wdch_m_axi_wvalid;
+
+    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;
+    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;
+
+  end endgenerate // axi_write_data_channel
+
+  // Register Slice for Write Data Channel
+  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)
+            )
+    wdch_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wdch_din),
+          .S_VALID                   (S_AXI_WVALID),
+          .S_READY                   (S_AXI_WREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wdch_dout),
+          .M_VALID                   (M_AXI_WVALID),
+          .M_READY                   (M_AXI_WREADY)
+          );
+  end endgenerate // gwdch_reg_slice
+
+  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
+    // Write protection when almost full or prog_full is high
+    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
+    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;
+    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_FAMILY			(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE			((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE		((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS			(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY		(0), // always FWFT for AXI
+        .C_DIN_WIDTH			(C_DIN_WIDTH_WRCH),
+        .C_WR_DEPTH			(C_WR_DEPTH_WRCH),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH_WRCH),
+        .C_DOUT_WIDTH			(C_DIN_WIDTH_WRCH),
+        .C_INTERFACE_TYPE 		(C_INTERFACE_TYPE),
+        .C_RD_DEPTH			(C_WR_DEPTH_WRCH),
+        .C_RD_PNTR_WIDTH		(C_WR_PNTR_WIDTH_WRCH),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE_WRCH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE_WRCH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
+        .C_USE_ECC                      (C_USE_ECC_WRCH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),
+        .C_HAS_ALMOST_EMPTY		(0),
+        .C_HAS_ALMOST_FULL		(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST			(0),
+        .C_HAS_RD_RST			(0),
+        .C_HAS_RST			(1),
+        .C_HAS_SRST			(0),
+        .C_DOUT_RST_VAL			(0),
+
+        .C_HAS_VALID			(0),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK			(0),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT		((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WRCH + 1),
+        .C_HAS_RD_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WRCH + 1),
+        .C_USE_FWFT_DATA_COUNT		(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_WRCH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG		(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_2_5_wrch_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (M_ACLK),
+        .RD_CLK                   (S_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (wrch_wr_en),
+        .RD_EN                    (wrch_rd_en),
+        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
+        .INJECTDBITERR            (AXI_B_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_B_INJECTSBITERR),
+  
+        .DIN                      (wrch_din),
+        .DOUT                     (wrch_dout),
+        .FULL                     (wrch_full),
+        .EMPTY                    (wrch_empty),
+        .ALMOST_FULL              (),
+        .ALMOST_EMPTY             (),
+        .PROG_FULL                (AXI_B_PROG_FULL),
+        .PROG_EMPTY               (AXI_B_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_b_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_b_underflow_i),
+        .DATA_COUNT               (AXI_B_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),
+        .SBITERR                  (AXI_B_SBITERR),
+        .DBITERR                  (AXI_B_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_wrch),
+        .rd_rst_busy              (rd_rst_busy_wrch),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign wrch_s_axi_bvalid = ~wrch_empty;
+    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
+    assign S_AXI_BVALID      = wrch_s_axi_bvalid;
+    assign M_AXI_BREADY      = wrch_m_axi_bready;
+
+    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;
+    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;
+  end endgenerate // axi_write_resp_channel
+
+  // Register Slice for Write Response Channel
+  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)
+            )
+    wrch_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wrch_din),
+          .S_VALID                   (M_AXI_BVALID),
+          .S_READY                   (M_AXI_BREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wrch_dout),
+          .M_VALID                   (S_AXI_BVALID),
+          .M_READY                   (S_AXI_BREADY)
+          );
+  end endgenerate // gwrch_reg_slice
+
+
+    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
+    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;
+
+  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
+    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    
+    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    
+    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    
+    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    
+    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    
+    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    
+    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    
+    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    
+    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;
+    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;
+    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;
+    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
+    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
+    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
+    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
+    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;
+  end endgenerate // axi_wach_output
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
+    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    
+  end endgenerate // axi_awregion
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
+    assign M_AXI_AWREGION  = 0;    
+  end endgenerate // naxi_awregion
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
+    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    
+  end endgenerate // axi_awuser
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
+    assign M_AXI_AWUSER  = 0;    
+  end endgenerate // naxi_awuser
+
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
+    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
+  end endgenerate //axi_awid
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
+    assign M_AXI_AWID      = 0;
+  end endgenerate //naxi_awid
+
+  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
+    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
+    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
+    assign M_AXI_WLAST     = wdch_dout[0];
+    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;
+    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
+    assign wdch_din[0]   = S_AXI_WLAST;
+  end endgenerate // axi_wdch_output
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
+    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
+  end endgenerate
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
+    assign M_AXI_WID       = 0;
+  end endgenerate
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
+    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    
+  end endgenerate
+  generate if (C_HAS_AXI_WUSER == 0) begin
+    assign M_AXI_WUSER       = 0;
+  end endgenerate
+
+  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
+    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; 
+    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;
+  end endgenerate // axi_wrch_output
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
+    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
+  end endgenerate // axi_buser
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
+    assign S_AXI_BUSER = 0;
+  end endgenerate // naxi_buser
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
+    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
+  end endgenerate // axi_bid
+  
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
+    assign S_AXI_BID   =  0 ;
+  end endgenerate // naxi_bid  
+
+
+  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
+    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};
+    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    
+    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    
+  end endgenerate // axi_wach_output1
+
+  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
+    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};
+    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
+    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
+  end endgenerate // axi_wdch_output1
+
+  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
+    assign wrch_din        = M_AXI_BRESP;
+    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; 
+  end endgenerate // axi_wrch_output1
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
+    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;
+  end endgenerate // gwach_din1
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
+    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;
+  end endgenerate // gwach_din2
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
+    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;
+  end endgenerate // gwach_din3
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
+    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
+  end endgenerate // gwdch_din1
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
+    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
+  end endgenerate // gwdch_din2
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
+    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;
+  end endgenerate // gwrch_din1
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
+    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;
+  end endgenerate // gwrch_din2
+
+  //end of  axi_write_channel
+
+  //###########################################################################
+  //  AXI FULL Read Channel (axi_read_channel)
+  //###########################################################################
+  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;
+  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;
+  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;
+  wire                               rach_full           ;
+  wire                               rach_almost_full    ;
+  wire                               rach_prog_full      ;
+  wire                               rach_empty          ;
+  wire                               rach_almost_empty   ;
+  wire                               rach_prog_empty     ;
+  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;
+  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;
+  wire                               rdch_full           ;
+  wire                               rdch_almost_full    ;
+  wire                               rdch_prog_full      ;
+  wire                               rdch_empty          ;
+  wire                               rdch_almost_empty   ;
+  wire                               rdch_prog_empty     ;
+  wire                               axi_ar_underflow_i  ;
+  wire                               axi_r_underflow_i   ;
+  wire                               axi_ar_overflow_i   ;
+  wire                               axi_r_overflow_i    ;
+  wire                               axi_rd_underflow_i  ;
+  wire                               axi_rd_overflow_i   ;
+  wire                               rach_s_axi_arready  ;
+  wire                               rach_m_axi_arvalid  ;
+  wire                               rach_wr_en          ;
+  wire                               rach_rd_en          ;
+  wire                               rdch_m_axi_rready   ;
+  wire                               rdch_s_axi_rvalid   ;
+  wire                               rdch_wr_en          ;
+  wire                               rdch_rd_en          ;
+  wire                               arvalid_pkt         ;
+  wire                               arready_pkt         ;
+  wire                               arvalid_en          ;
+  wire                               rdch_rd_ok          ;
+  wire                               accept_next_pkt     ;
+  integer                            rdch_free_space     ;
+  integer                            rdch_commited_space ;
+  wire                               rach_we             ;
+  wire                               rach_re             ;
+  wire                               rdch_we             ;
+  wire                               rdch_re             ;
+
+  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
+  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;
+  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
+  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
+  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
+  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
+  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
+  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
+  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
+  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
+  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
+
+  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
+  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;
+  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
+  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
+
+
+  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
+
+    // Write protection when almost full or prog_full is high
+    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
+
+    // Read protection when almost empty or prog_empty is high
+//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
+    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? 
+                        rach_m_axi_arvalid & arready_pkt & arvalid_en : 
+                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? 
+                        M_AXI_ARREADY && rach_m_axi_arvalid :
+                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? 
+                        arready_pkt & arvalid_en : 
+                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? 
+                        M_AXI_ARREADY : 1'b0;
+    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;
+    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
+
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_FAMILY			(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE			((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE		((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS			(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY		(0), // always FWFT for AXI
+        .C_DIN_WIDTH			(C_DIN_WIDTH_RACH),
+        .C_WR_DEPTH			(C_WR_DEPTH_RACH),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH_RACH),
+        .C_INTERFACE_TYPE 		(C_INTERFACE_TYPE),
+        .C_DOUT_WIDTH			(C_DIN_WIDTH_RACH),
+        .C_RD_DEPTH			(C_WR_DEPTH_RACH),
+        .C_RD_PNTR_WIDTH		(C_WR_PNTR_WIDTH_RACH),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE_RACH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE_RACH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
+        .C_USE_ECC                      (C_USE_ECC_RACH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),
+        .C_HAS_ALMOST_EMPTY		(0),
+        .C_HAS_ALMOST_FULL		(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST			(0),
+        .C_HAS_RD_RST			(0),
+        .C_HAS_RST			(1),
+        .C_HAS_SRST			(0),
+        .C_DOUT_RST_VAL			(0),
+
+        .C_HAS_VALID			(0),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK			(0),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT		((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_RACH + 1),
+        .C_HAS_RD_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_RACH + 1),
+        .C_USE_FWFT_DATA_COUNT		(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_RACH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG		(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_2_5_rach_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (rach_wr_en),
+        .RD_EN                    (rach_rd_en),
+        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
+        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),
+  
+        .DIN                      (rach_din),
+        .DOUT                     (rach_dout_pkt),
+        .FULL                     (rach_full),
+        .EMPTY                    (rach_empty),
+        .ALMOST_FULL              (),
+        .ALMOST_EMPTY             (),
+        .PROG_FULL                (AXI_AR_PROG_FULL),
+        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_ar_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_ar_underflow_i),
+        .DATA_COUNT               (AXI_AR_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),
+        .SBITERR                  (AXI_AR_SBITERR),
+        .DBITERR                  (AXI_AR_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_rach),
+        .rd_rst_busy              (rd_rst_busy_rach),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
+    assign rach_m_axi_arvalid = ~rach_empty;
+    assign S_AXI_ARREADY      = rach_s_axi_arready;
+
+    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
+    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;
+
+  end endgenerate // axi_read_addr_channel
+
+  // Register Slice for Read Address Channel
+  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)
+            )
+    rach_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (rach_din),
+          .S_VALID                   (S_AXI_ARVALID),
+          .S_READY                   (S_AXI_ARREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (rach_dout),
+          .M_VALID                   (M_AXI_ARVALID),
+          .M_READY                   (M_AXI_ARREADY)
+          );
+  end endgenerate // grach_reg_slice
+
+  // Register Slice for Read Address Channel for MM Packet FIFO
+  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),
+            .C_REG_CONFIG            (1)
+            )
+    reg_slice_mm_pkt_fifo_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (rach_dout_pkt),
+          .S_VALID                   (arvalid_pkt),
+          .S_READY                   (arready_pkt),
+
+          // Master side
+          .M_PAYLOAD_DATA            (rach_dout),
+          .M_VALID                   (M_AXI_ARVALID),
+          .M_READY                   (M_AXI_ARREADY)
+          );
+  end endgenerate // grach_reg_slice_mm_pkt_fifo
+
+  
+  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
+    assign M_AXI_ARVALID      = rach_m_axi_arvalid;
+    assign rach_dout          = rach_dout_pkt;
+  end endgenerate // grach_m_axi_arvalid
+  
+  
+  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
+    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
+    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
+    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;
+
+    always@(posedge S_ACLK or posedge inverted_reset) begin
+      if(inverted_reset) begin
+	rdch_commited_space <= 0;
+      end else begin
+	if(rdch_rd_ok && !accept_next_pkt) begin
+	  rdch_commited_space <= rdch_commited_space-1;
+	end else if(!rdch_rd_ok && accept_next_pkt) begin
+	  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
+	end else if(rdch_rd_ok && accept_next_pkt) begin
+	  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
+	end
+      end
+    end //Always end
+
+    always@(*) begin
+      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
+    end
+
+    assign arvalid_en = (rdch_free_space >= 0)?1:0;
+  end
+  endgenerate
+  
+  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
+    assign arvalid_en = 1;    
+  end
+  endgenerate
+
+  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
+
+    // Write protection when almost full or prog_full is high
+    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;
+    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;
+    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
+
+    fifo_generator_v13_2_5_CONV_VER
+      #(
+        .C_FAMILY			(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE			((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE		((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS			(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY		(0), // always FWFT for AXI
+        .C_DIN_WIDTH			(C_DIN_WIDTH_RDCH),
+        .C_WR_DEPTH			(C_WR_DEPTH_RDCH),
+        .C_WR_PNTR_WIDTH		(C_WR_PNTR_WIDTH_RDCH),
+        .C_DOUT_WIDTH			(C_DIN_WIDTH_RDCH),
+        .C_RD_DEPTH			(C_WR_DEPTH_RDCH),
+        .C_INTERFACE_TYPE 		(C_INTERFACE_TYPE),
+        .C_RD_PNTR_WIDTH		(C_WR_PNTR_WIDTH_RDCH),
+        .C_PROG_FULL_TYPE		(C_PROG_FULL_TYPE_RDCH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL	(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
+        .C_PROG_EMPTY_TYPE		(C_PROG_EMPTY_TYPE_RDCH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL	(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
+        .C_USE_ECC                      (C_USE_ECC_RDCH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),
+        .C_HAS_ALMOST_EMPTY		(0),
+        .C_HAS_ALMOST_FULL		(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST			(0),
+        .C_HAS_RD_RST			(0),
+        .C_HAS_RST			(1),
+        .C_HAS_SRST			(0),
+        .C_DOUT_RST_VAL			(0),
+
+        .C_HAS_VALID			(0),
+        .C_VALID_LOW			(C_VALID_LOW),
+        .C_HAS_UNDERFLOW		(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW		(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK			(0),
+        .C_WR_ACK_LOW			(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW			(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW			(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT		((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_RDCH + 1),
+        .C_HAS_RD_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_RDCH + 1),
+        .C_USE_FWFT_DATA_COUNT		(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT		((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH		(C_WR_PNTR_WIDTH_RDCH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG		(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
+        .C_COUNT_TYPE			(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE		(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS			(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP			(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME		(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE		(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL		(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE		(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE		(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ			(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS		(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ			(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY		(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_2_5_rdch_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (M_ACLK),
+        .RD_CLK                   (S_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (rdch_wr_en),
+        .RD_EN                    (rdch_rd_en),
+        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
+        .INJECTDBITERR            (AXI_R_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_R_INJECTSBITERR),
+  
+        .DIN                      (rdch_din),
+        .DOUT                     (rdch_dout),
+        .FULL                     (rdch_full),
+        .EMPTY                    (rdch_empty),
+        .ALMOST_FULL              (),
+        .ALMOST_EMPTY             (),
+        .PROG_FULL                (AXI_R_PROG_FULL),
+        .PROG_EMPTY               (AXI_R_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_r_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_r_underflow_i),
+        .DATA_COUNT               (AXI_R_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),
+        .SBITERR                  (AXI_R_SBITERR),
+        .DBITERR                  (AXI_R_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_rdch),
+        .rd_rst_busy              (rd_rst_busy_rdch),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign rdch_s_axi_rvalid = ~rdch_empty;
+    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
+    assign S_AXI_RVALID      = rdch_s_axi_rvalid;
+    assign M_AXI_RREADY      = rdch_m_axi_rready;
+
+    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;
+    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;
+
+  end endgenerate //axi_read_data_channel
+
+  // Register Slice for read Data Channel
+  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
+
+    fifo_generator_v13_2_5_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)
+            )
+    rdch_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (rdch_din),
+          .S_VALID                   (M_AXI_RVALID),
+          .S_READY                   (M_AXI_RREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (rdch_dout),
+          .M_VALID                   (S_AXI_RVALID),
+          .M_READY                   (S_AXI_RREADY)
+          );
+  end endgenerate // grdch_reg_slice
+
+
+    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
+    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;
+
+
+  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
+    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    
+    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    
+    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    
+    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    
+    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    
+    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    
+    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    
+    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    
+    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;
+    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;
+    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;
+    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
+    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
+    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
+    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
+    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;
+  end endgenerate // axi_full_rach_output
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
+    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    
+  end endgenerate // axi_arregion
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
+    assign M_AXI_ARREGION  = 0;    
+  end endgenerate // naxi_arregion
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
+    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    
+  end endgenerate // axi_aruser
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
+    assign M_AXI_ARUSER = 0;    
+  end endgenerate // naxi_aruser
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
+    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
+  end endgenerate // axi_arid
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
+    assign M_AXI_ARID      = 0;
+  end endgenerate // naxi_arid
+
+  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
+    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
+    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
+    assign S_AXI_RLAST     = rdch_dout[0];
+    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;
+    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
+    assign rdch_din[0] = M_AXI_RLAST;
+  end endgenerate // axi_full_rdch_output
+  
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
+    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
+  end endgenerate // axi_full_ruser_output
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
+    assign S_AXI_RUSER     =  0;
+  end endgenerate // axi_full_nruser_output
+  
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
+    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
+  end endgenerate // axi_rid
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
+    assign S_AXI_RID       = 0;
+  end endgenerate // naxi_rid
+
+  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
+    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};
+    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
+    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
+  end endgenerate // axi_lite_rach_output
+
+  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
+    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};
+    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
+    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
+  end endgenerate // axi_lite_rdch_output
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
+    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;
+  end endgenerate // grach_din1
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
+    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;
+  end endgenerate // grach_din2
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
+    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
+  end endgenerate
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
+    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;
+  end endgenerate // grdch_din1
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
+    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
+  end endgenerate // grdch_din2
+
+  //end of axi_read_channel
+
+  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
+    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
+                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
+                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
+  end endgenerate // gaxi_comm_uf
+
+  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
+    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
+                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
+                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
+  end endgenerate // gaxi_comm_of
+  
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  // Pass Through Logic or Wiring Logic
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  
+  //-------------------------------------------------------------------------
+  // Pass Through Logic for Read Channel
+  //-------------------------------------------------------------------------
+
+  // Wiring logic for Write Address Channel
+  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
+    assign M_AXI_AWID      = S_AXI_AWID;
+    assign M_AXI_AWADDR    = S_AXI_AWADDR;
+    assign M_AXI_AWLEN     = S_AXI_AWLEN;
+    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;
+    assign M_AXI_AWBURST   = S_AXI_AWBURST;
+    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;
+    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;
+    assign M_AXI_AWPROT    = S_AXI_AWPROT;
+    assign M_AXI_AWQOS     = S_AXI_AWQOS;
+    assign M_AXI_AWREGION  = S_AXI_AWREGION;
+    assign M_AXI_AWUSER    = S_AXI_AWUSER;
+    assign S_AXI_AWREADY   = M_AXI_AWREADY;
+    assign M_AXI_AWVALID   = S_AXI_AWVALID;
+  end endgenerate // gwach_pass_through;
+
+  // Wiring logic for Write Data Channel
+  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
+    assign M_AXI_WID       = S_AXI_WID;
+    assign M_AXI_WDATA     = S_AXI_WDATA;
+    assign M_AXI_WSTRB     = S_AXI_WSTRB;
+    assign M_AXI_WLAST     = S_AXI_WLAST;
+    assign M_AXI_WUSER     = S_AXI_WUSER;
+    assign S_AXI_WREADY    = M_AXI_WREADY;
+    assign M_AXI_WVALID    = S_AXI_WVALID;
+  end endgenerate // gwdch_pass_through;
+
+  // Wiring logic for Write Response Channel
+  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
+    assign S_AXI_BID       = M_AXI_BID;
+    assign S_AXI_BRESP     = M_AXI_BRESP;
+    assign S_AXI_BUSER     = M_AXI_BUSER;
+    assign M_AXI_BREADY    = S_AXI_BREADY;
+    assign S_AXI_BVALID    = M_AXI_BVALID;
+  end endgenerate // gwrch_pass_through;
+
+  //-------------------------------------------------------------------------
+  // Pass Through Logic for Read Channel
+  //-------------------------------------------------------------------------
+
+  // Wiring logic for Read Address Channel
+  generate if (C_RACH_TYPE == 2) begin : grach_pass_through
+    assign M_AXI_ARID      = S_AXI_ARID;
+    assign M_AXI_ARADDR    = S_AXI_ARADDR;
+    assign M_AXI_ARLEN     = S_AXI_ARLEN;
+    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;
+    assign M_AXI_ARBURST   = S_AXI_ARBURST;
+    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;
+    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;
+    assign M_AXI_ARPROT    = S_AXI_ARPROT;
+    assign M_AXI_ARQOS     = S_AXI_ARQOS;
+    assign M_AXI_ARREGION  = S_AXI_ARREGION;
+    assign M_AXI_ARUSER    = S_AXI_ARUSER;
+    assign S_AXI_ARREADY   = M_AXI_ARREADY;
+    assign M_AXI_ARVALID   = S_AXI_ARVALID;
+  end endgenerate // grach_pass_through;
+
+  // Wiring logic for Read Data Channel 
+  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
+    assign S_AXI_RID      = M_AXI_RID;
+    assign S_AXI_RLAST    = M_AXI_RLAST;
+    assign S_AXI_RUSER    = M_AXI_RUSER;
+    assign S_AXI_RDATA    = M_AXI_RDATA;
+    assign S_AXI_RRESP    = M_AXI_RRESP;
+    assign S_AXI_RVALID   = M_AXI_RVALID;
+    assign M_AXI_RREADY   = S_AXI_RREADY;
+  end endgenerate // grdch_pass_through;
+
+  // Wiring logic for AXI Streaming
+  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
+    assign M_AXIS_TDATA   = S_AXIS_TDATA;
+    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;
+    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;
+    assign M_AXIS_TID     = S_AXIS_TID;
+    assign M_AXIS_TDEST   = S_AXIS_TDEST;
+    assign M_AXIS_TUSER   = S_AXIS_TUSER;
+    assign M_AXIS_TLAST   = S_AXIS_TLAST;
+    assign S_AXIS_TREADY  = M_AXIS_TREADY;
+    assign M_AXIS_TVALID  = S_AXIS_TVALID;
+  end endgenerate // gaxis_pass_through;
+
+
+endmodule //fifo_generator_v13_2_5
+
+
+
+/*******************************************************************************
+ * Declaration of top-level module for Conventional FIFO
+ ******************************************************************************/
+module fifo_generator_v13_2_5_CONV_VER
+  #(
+    parameter  C_COMMON_CLOCK                 = 0,
+    parameter  C_INTERFACE_TYPE               = 0,
+    parameter  C_EN_SAFETY_CKT                = 0,
+    parameter  C_COUNT_TYPE                   = 0,
+    parameter  C_DATA_COUNT_WIDTH             = 2,
+    parameter  C_DEFAULT_VALUE                = "",
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = "",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_ENABLE_RLOCS                 = 0,
+    parameter  C_FAMILY                       = "virtex7", //Not allowed in Verilog model
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_ALMOST_EMPTY             = 0,
+    parameter  C_HAS_ALMOST_FULL              = 0,
+    parameter  C_HAS_BACKUP                   = 0,
+    parameter  C_HAS_DATA_COUNT               = 0,
+    parameter  C_HAS_INT_CLK                  = 0,
+    parameter  C_HAS_MEMINIT_FILE             = 0,
+    parameter  C_HAS_OVERFLOW                 = 0,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_RD_RST                   = 0,
+    parameter  C_HAS_RST                      = 0,
+    parameter  C_HAS_SRST                     = 0,
+    parameter  C_HAS_UNDERFLOW                = 0,
+    parameter  C_HAS_VALID                    = 0,
+    parameter  C_HAS_WR_ACK                   = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_HAS_WR_RST                   = 0,
+    parameter  C_IMPLEMENTATION_TYPE          = 0,
+    parameter  C_INIT_WR_PNTR_VAL             = 0,
+    parameter  C_MEMORY_TYPE                  = 1,
+    parameter  C_MIF_FILE_NAME                = "",
+    parameter  C_OPTIMIZATION_MODE            = 0,
+    parameter  C_OVERFLOW_LOW                 = 0,
+    parameter  C_PRELOAD_LATENCY              = 1,
+    parameter  C_PRELOAD_REGS                 = 0,
+    parameter  C_PRIM_FIFO_TYPE               = "",
+    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter  C_PROG_EMPTY_TYPE              = 0,
+    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter  C_PROG_FULL_TYPE               = 0,
+    parameter  C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_FREQ                      = 1,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_UNDERFLOW_LOW                = 0,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_USE_ECC                      = 0,
+    parameter  C_USE_EMBEDDED_REG             = 0,
+    parameter  C_USE_FIFO16_FLAGS             = 0,
+    parameter  C_USE_FWFT_DATA_COUNT          = 0,
+    parameter  C_VALID_LOW                    = 0,
+    parameter  C_WR_ACK_LOW                   = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_FREQ                      = 1,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_WR_RESPONSE_LATENCY          = 1,
+    parameter  C_MSGON_VAL                    = 1,
+    parameter  C_ENABLE_RST_SYNC              = 1,
+    parameter  C_ERROR_INJECTION_TYPE         = 0,
+    parameter  C_FIFO_TYPE                    = 0,
+    parameter  C_SYNCHRONIZER_STAGE           = 2,
+    parameter  C_AXI_TYPE                     = 0
+   )
+
+  (
+   input                               BACKUP,
+   input                               BACKUP_MARKER,
+   input                               CLK,
+   input                               RST,
+   input                               SRST,
+   input                               WR_CLK,
+   input                               WR_RST,
+   input                               RD_CLK,
+   input                               RD_RST,
+   input [C_DIN_WIDTH-1:0]             DIN,
+   input                               WR_EN,
+   input                               RD_EN,
+   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,
+   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,
+   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,
+   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,
+   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,
+   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,
+   input                               INT_CLK,
+   input                               INJECTDBITERR,
+   input                               INJECTSBITERR,
+  
+   output [C_DOUT_WIDTH-1:0]           DOUT,
+   output                              FULL,
+   output                              ALMOST_FULL,
+   output                              WR_ACK,
+   output                              OVERFLOW,
+   output                              EMPTY,
+   output                              ALMOST_EMPTY,
+   output                              VALID,
+   output                              UNDERFLOW,
+   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,
+   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,
+   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,
+   output                              PROG_FULL,
+   output                              PROG_EMPTY,
+   output                              SBITERR,
+   output                              DBITERR,
+   output                              wr_rst_busy_o,
+   output                              wr_rst_busy,
+   output                              rd_rst_busy,
+   output                              wr_rst_i_out,
+   output                              rd_rst_i_out
+  );
+
+/*
+ ******************************************************************************
+ * Definition of Parameters
+ ******************************************************************************
+ *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)
+ *     C_COUNT_TYPE                  :    *not used
+ *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus
+ *     C_DEFAULT_VALUE               :    *not used
+ *     C_DIN_WIDTH                   : Width of DIN bus
+ *     C_DOUT_RST_VAL                : Reset value of DOUT
+ *     C_DOUT_WIDTH                  : Width of DOUT bus
+ *     C_ENABLE_RLOCS                :    *not used
+ *     C_FAMILY                      : not used in bhv model
+ *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)
+ *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag
+ *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag
+ *     C_HAS_BACKUP                  :    *not used
+ *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus
+ *     C_HAS_INT_CLK                 : not used in bhv model
+ *     C_HAS_MEMINIT_FILE            :    *not used
+ *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag
+ *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus
+ *     C_HAS_RD_RST                  :    *not used
+ *     C_HAS_RST                     : 1=Core has Async Rst
+ *     C_HAS_SRST                    : 1=Core has Sync Rst
+ *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag
+ *     C_HAS_VALID                   : 1=Core has VALID flag
+ *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag
+ *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus
+ *     C_HAS_WR_RST                  :    *not used
+ *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram
+ *                                     1=Common-Clock ShiftRam
+ *                                     2=Indep. Clocks Bram/Dram
+ *                                     3=Virtex-4 Built-in
+ *                                     4=Virtex-5 Built-in
+ *     C_INIT_WR_PNTR_VAL            :   *not used
+ *     C_MEMORY_TYPE                 : 1=Block RAM
+ *                                     2=Distributed RAM
+ *                                     3=Shift RAM
+ *                                     4=Built-in FIFO
+ *     C_MIF_FILE_NAME               :   *not used
+ *     C_OPTIMIZATION_MODE           :   *not used
+ *     C_OVERFLOW_LOW                : 1=OVERFLOW active low
+ *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2
+ *     C_PRELOAD_REGS                : 1=Use output registers
+ *     C_PRIM_FIFO_TYPE              : not used in bhv model
+ *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
+ *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
+ *     C_PROG_EMPTY_TYPE             : 0=No programmable empty
+ *                                     1=Single prog empty thresh constant
+ *                                     2=Multiple prog empty thresh constants
+ *                                     3=Single prog empty thresh input
+ *                                     4=Multiple prog empty thresh inputs
+ *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
+ *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
+ *     C_PROG_FULL_TYPE              : 0=No prog full
+ *                                     1=Single prog full thresh constant
+ *                                     2=Multiple prog full thresh constants
+ *                                     3=Single prog full thresh input
+ *                                     4=Multiple prog full thresh inputs
+ *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus
+ *     C_RD_DEPTH                    : Depth of read interface (2^N)
+ *     C_RD_FREQ                     : not used in bhv model
+ *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)
+ *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low
+ *     C_USE_DOUT_RST                : 1=Resets DOUT on RST
+ *     C_USE_ECC                     : Used for error injection purpose
+ *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register
+ *     C_USE_FIFO16_FLAGS            : not used in bhv model
+ *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count
+ *     C_VALID_LOW                   : 1=VALID active low
+ *     C_WR_ACK_LOW                  : 1=WR_ACK active low
+ *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus
+ *     C_WR_DEPTH                    : Depth of write interface (2^N)
+ *     C_WR_FREQ                     : not used in bhv model
+ *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)
+ *     C_WR_RESPONSE_LATENCY         :    *not used
+ *     C_MSGON_VAL                   :    *not used by bhv model
+ *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST
+ *                                     1 = Use RST
+ *     C_ERROR_INJECTION_TYPE        : 0 = No error injection
+ *                                     1 = Single bit error injection only
+ *                                     2 = Double bit error injection only
+ *                                     3 = Single and double bit error injection
+ ******************************************************************************
+ * Definition of Ports
+ ******************************************************************************
+ *   BACKUP       : Not used
+ *   BACKUP_MARKER: Not used
+ *   CLK          : Clock
+ *   DIN          : Input data bus
+ *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag
+ *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
+ *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
+ *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag
+ *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
+ *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
+ *   RD_CLK       : Read Domain Clock
+ *   RD_EN        : Read enable
+ *   RD_RST       : Read Reset
+ *   RST          : Asynchronous Reset
+ *   SRST         : Synchronous Reset
+ *   WR_CLK       : Write Domain Clock
+ *   WR_EN        : Write enable
+ *   WR_RST       : Write Reset
+ *   INT_CLK      : Internal Clock
+ *   INJECTSBITERR: Inject Signle bit error
+ *   INJECTDBITERR: Inject Double bit error
+ *   ALMOST_EMPTY : One word remaining in FIFO
+ *   ALMOST_FULL  : One empty space remaining in FIFO
+ *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)
+ *   DOUT         : Output data bus
+ *   EMPTY        : Empty flag
+ *   FULL         : Full flag
+ *   OVERFLOW     : Last write rejected
+ *   PROG_EMPTY   : Programmable Empty Flag
+ *   PROG_FULL    : Programmable Full Flag
+ *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
+ *   UNDERFLOW    : Last read rejected
+ *   VALID        : Last read acknowledged, DOUT bus VALID
+ *   WR_ACK       : Last write acknowledged
+ *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
+ *   SBITERR      : Single Bit ECC Error Detected
+ *   DBITERR      : Double Bit ECC Error Detected
+ ******************************************************************************
+ */
+
+  //----------------------------------------------------------------------------
+  //- Internal Signals for delayed input signals
+  //- All the input signals except Clock are delayed by 100 ps and then given to
+  //- the models.
+  //----------------------------------------------------------------------------
+ 
+  reg                         rst_delayed                       ;
+  reg                         empty_fb                       ;
+  reg                         srst_delayed                      ;
+  reg                         wr_rst_delayed                    ;
+  reg                         rd_rst_delayed                    ;
+  reg                         wr_en_delayed                     ;
+  reg                         rd_en_delayed                     ;
+  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;
+  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;
+  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;
+  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;
+  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;
+  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;
+  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;
+  reg                         injectdbiterr_delayed             ;
+  reg                         injectsbiterr_delayed             ;
+   wire                        empty_p0_out;
+
+  always @* rst_delayed                       <= #`TCQ RST                      ;
+  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;
+  always @* srst_delayed                      <= #`TCQ SRST                     ; 
+  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; 
+  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; 
+  always @* din_delayed                       <= #`TCQ DIN                      ; 
+  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; 
+  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; 
+  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; 
+  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; 
+  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; 
+  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; 
+  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; 
+  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; 
+  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; 
+  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; 
+
+  /*****************************************************************************
+   * Derived parameters
+   ****************************************************************************/
+  //There are 2 Verilog behavioral models
+  // 0 = Common-Clock FIFO/ShiftRam FIFO
+  // 1 = Independent Clocks FIFO
+  // 2 = Low Latency Synchronous FIFO
+  // 3 = Low Latency Asynchronous FIFO
+  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
+                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
+  localparam IS_8SERIES         = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
+
+  //Internal reset signals
+  reg                                rd_rst_asreg    = 1'b0;
+  reg                                rd_rst_asreg_d1 = 1'b0;
+  reg                                rd_rst_asreg_d2 = 1'b0;
+  reg                                rd_rst_asreg_d3 = 1'b0;
+  reg                                rd_rst_reg      = 1'b0;
+  reg                                rd_rst_comb     = 1'b1;
+  reg                                rd_rst_comb_d1  = 1'b0;
+  reg                                wr_rst_d0       = 1'b0;
+  reg                                wr_rst_d1       = 1'b0;
+  reg                                wr_rst_d2       = 1'b0;
+  reg                                rd_rst_d0       = 1'b0;
+  reg                                rd_rst_d1       = 1'b0;
+  reg                                rd_rst_d2       = 1'b0;
+  reg                                rd_rst_d3       = 1'b0;
+  reg                                wrrst_done      = 1'b0;
+  reg                                rdrst_done      = 1'b0;
+  reg                                wr_rst_asreg    = 1'b0;
+  reg                                wr_rst_asreg_d1 = 1'b0;
+  reg                                wr_rst_asreg_d2 = 1'b0;
+  reg                                wr_rst_asreg_d3 = 1'b0;
+  reg                                rd_rst_wr_d0    = 1'b0;
+  reg                                rd_rst_wr_d1    = 1'b0;
+  reg                                rd_rst_wr_d2    = 1'b0;
+  reg                                wr_rst_reg      = 1'b0;
+  reg                                rst_active_i    = 1'b1;
+  reg                                rst_delayed_d1  = 1'b1;
+  reg                                rst_delayed_d2  = 1'b1;
+  reg                                wr_rst_comb     = 1'b1;
+  reg                                wr_rst_comb_d1  = 1'b0;
+  wire                               wr_rst_i;
+  wire                               rd_rst_i;
+  wire                               rst_i;
+
+  //Internal reset signals
+  reg                                rst_asreg     = 1'b0;
+  reg                                srst_asreg    = 1'b0;
+  reg                                rst_asreg_d1  = 1'b0;
+  reg                                rst_asreg_d2  = 1'b0;
+  reg                                srst_asreg_d1 = 1'b0;
+  reg                                srst_asreg_d2 = 1'b0;
+  reg                                rst_reg       = 1'b0;
+  reg                                srst_reg      = 1'b0;
+  reg                                rst_comb      = 1'b1;
+  reg                                rst_comb_d1   = 1'b0;
+  wire                               srst_comb;
+  reg                                rst_full_gen_i = 0;
+  reg                                rst_full_ff_i = 0;
+  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};
+                                     
+  wire                               RD_CLK_P0_IN;
+  wire                               RST_P0_IN;
+  wire                               RD_EN_FIFO_IN;
+  wire                               RD_EN_P0_IN;
+
+  wire                               ALMOST_EMPTY_FIFO_OUT;
+  wire                               ALMOST_FULL_FIFO_OUT;
+  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;
+  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;
+  wire                               EMPTY_FIFO_OUT;
+  wire                               fifo_empty_fb;
+  wire                               FULL_FIFO_OUT;
+  wire                               OVERFLOW_FIFO_OUT;
+  wire                               PROG_EMPTY_FIFO_OUT;
+  wire                               PROG_FULL_FIFO_OUT;
+  wire                               VALID_FIFO_OUT;
+  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;
+  wire                               UNDERFLOW_FIFO_OUT;
+  wire                               WR_ACK_FIFO_OUT;
+  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;
+
+
+  //***************************************************************************
+  // Internal Signals
+  //   The core uses either the internal_ wires or the preload0_ wires depending
+  //     on whether the core uses Preload0 or not.
+  //   When using preload0, the internal signals connect the internal core to
+  //     the preload logic, and the external core's interfaces are tied to the
+  //     preload0 signals from the preload logic.
+  //***************************************************************************
+  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;
+  wire                               VALID_P0_OUT;
+  wire                               EMPTY_P0_OUT;
+  wire                               ALMOSTEMPTY_P0_OUT;
+  reg                                EMPTY_P0_OUT_Q;
+  reg                                ALMOSTEMPTY_P0_OUT_Q;
+  wire                               UNDERFLOW_P0_OUT;
+  wire                               RDEN_P0_OUT;
+  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;
+  wire                               EMPTY_P0_IN;
+  reg  [31:0]                        DATA_COUNT_FWFT;
+  reg                                SS_FWFT_WR  ;
+  reg                                SS_FWFT_RD ;
+
+  wire                               sbiterr_fifo_out;
+  wire                               dbiterr_fifo_out;
+  wire                               inject_sbit_err;
+  wire                               inject_dbit_err;
+  wire                               sckt_wr_rst_i;
+  wire                               sckt_rd_rst_i;
+  reg                                sckt_wr_rst_i_q = 1'b0;
+ 
+  wire                               w_fab_read_data_valid_i;
+  wire                               w_read_data_valid_i;
+  wire                               w_ram_valid_i;
+  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
+  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
+                           injectsbiterr_delayed : 0;
+  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
+                           injectdbiterr_delayed : 0;
+                           
+  assign wr_rst_i_out = wr_rst_i;
+  assign rd_rst_i_out = rd_rst_i;
+  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
+  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
+    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
+    always @ (posedge clk_i)
+      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; 
+  end endgenerate 
+// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
+// parameter (1=Independent Clocks, 0=Common Clock)
+
+  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
+generate
+case (C_VERILOG_IMPL)
+0 : begin : block1_ss
+  //Common Clock Behavioral Model
+  fifo_generator_v13_2_5_bhv_ver_ss
+  #(
+    .C_FAMILY                            (C_FAMILY),
+    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            
+    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   
+    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                
+    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  
+    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            
+    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            
+    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             
+    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              
+    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                
+    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           
+    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     
+    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    
+    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               
+    .C_HAS_VALID                         (C_HAS_VALID),                   
+    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  
+    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           
+    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         
+    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 
+    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                
+    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             
+    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),
+    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             
+    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), 
+    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), 
+    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              
+    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         
+    .C_RD_DEPTH                          (C_RD_DEPTH),                    
+    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               
+    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               
+    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                
+    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),
+    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            
+    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         
+    .C_VALID_LOW                         (C_VALID_LOW),                   
+    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  
+    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         
+    .C_WR_DEPTH                          (C_WR_DEPTH),                    
+    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               
+    .C_USE_ECC                           (C_USE_ECC),                     
+    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             
+    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),
+    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     
+  )
+  gen_ss
+  (
+    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),
+    .CLK                      (CLK),
+    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),
+    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),
+    .RST_FULL_GEN             (rst_full_gen_i),
+    .RST_FULL_FF              (rst_full_ff_i),
+    .DIN                      (din_delayed),
+    .WR_EN                    (wr_en_delayed),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .RD_EN_USER               (rd_en_delayed),
+    .USER_EMPTY_FB            (empty_fb),
+    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),
+    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
+    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
+    .PROG_FULL_THRESH         (prog_full_thresh_delayed),
+    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),
+    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),
+    .INJECTSBITERR            (inject_sbit_err),
+    .INJECTDBITERR            (inject_dbit_err),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .EMPTY_FB                 (fifo_empty_fb),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),
+    .WR_RST_BUSY              (wr_rst_busy),
+    .RD_RST_BUSY              (rd_rst_busy),
+    .SBITERR                  (sbiterr_fifo_out),
+    .DBITERR                  (dbiterr_fifo_out)
+   );
+end
+1 : begin : block1_as
+  //Independent Clocks Behavioral Model
+  fifo_generator_v13_2_5_bhv_ver_as
+  #(
+    .C_FAMILY                          (C_FAMILY),
+    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),
+    .C_DIN_WIDTH                       (C_DIN_WIDTH),
+    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),
+    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),
+    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),
+    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),
+    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),
+    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),
+    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),
+    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),
+    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),
+    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),
+    .C_HAS_VALID                       (C_HAS_VALID),
+    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),
+    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),
+    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),
+    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),
+    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),
+    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),
+    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),
+    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),
+    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),
+    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),
+    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),
+    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),
+    .C_RD_DEPTH                        (C_RD_DEPTH),
+    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),
+    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),
+    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),
+    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),
+    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), 
+    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),
+    .C_VALID_LOW                       (C_VALID_LOW),
+    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),
+    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),
+    .C_WR_DEPTH                        (C_WR_DEPTH),
+    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),
+    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),
+    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)
+  )
+  gen_as
+  (
+    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),
+    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),
+    .WR_CLK                   (WR_CLK),
+    .RD_CLK                   (RD_CLK),
+    .RST                      (rst_i),
+    .RST_FULL_GEN             (rst_full_gen_i),
+    .RST_FULL_FF              (rst_full_ff_i),
+    .WR_RST                   (wr_rst_i),
+    .RD_RST                   (rd_rst_i),
+    .DIN                      (din_delayed),
+    .WR_EN                    (wr_en_delayed),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .RD_EN_USER               (rd_en_delayed),
+    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),
+    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
+    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
+    .PROG_FULL_THRESH         (prog_full_thresh_delayed),
+    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),
+    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),
+    .INJECTSBITERR            (inject_sbit_err),
+    .INJECTDBITERR            (inject_dbit_err),
+    .USER_EMPTY_FB            (EMPTY_P0_OUT),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .EMPTY_FB                 (fifo_empty_fb),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),
+    .SBITERR                  (sbiterr_fifo_out),
+    .fab_read_data_valid_i    (w_fab_read_data_valid_i),
+    .read_data_valid_i        (w_read_data_valid_i),
+    .ram_valid_i              (w_ram_valid_i),
+    .DBITERR                  (dbiterr_fifo_out)
+   );
+end
+
+2 : begin : ll_afifo_inst
+  fifo_generator_v13_2_5_beh_ver_ll_afifo
+  #(
+    .C_DIN_WIDTH                    (C_DIN_WIDTH),
+    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),
+    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),
+    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),
+    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),
+    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),
+    .C_RD_DEPTH                     (C_RD_DEPTH),
+    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),
+    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),
+    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),
+    .C_WR_DEPTH                     (C_WR_DEPTH),
+    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),
+    .C_FIFO_TYPE                    (C_FIFO_TYPE)
+   )
+  gen_ll_afifo
+  (
+    .DIN                        (din_delayed),
+    .RD_CLK                     (RD_CLK),
+    .RD_EN                      (rd_en_delayed),
+    .WR_RST                     (wr_rst_i),
+    .RD_RST                     (rd_rst_i),
+    .WR_CLK                     (WR_CLK),
+    .WR_EN                      (wr_en_delayed),
+    .DOUT                       (DOUT),
+    .EMPTY                      (EMPTY),
+    .FULL                       (FULL)
+  );
+end
+default : begin : block1_as
+  //Independent Clocks Behavioral Model
+  fifo_generator_v13_2_5_bhv_ver_as
+  #(
+    .C_FAMILY                          (C_FAMILY),
+    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),
+    .C_DIN_WIDTH                       (C_DIN_WIDTH),
+    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),
+    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),
+    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),
+    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),
+    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),
+    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),
+    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),
+    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),
+    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),
+    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),
+    .C_HAS_VALID                       (C_HAS_VALID),
+    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),
+    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),
+    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),
+    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),
+    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),
+    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),
+    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),
+    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),
+    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),
+    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),
+    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),
+    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),
+    .C_RD_DEPTH                        (C_RD_DEPTH),
+    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),
+    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),
+    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),
+    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),
+    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),
+    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),
+    .C_VALID_LOW                       (C_VALID_LOW),
+    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),
+    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),
+    .C_WR_DEPTH                        (C_WR_DEPTH),
+    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),
+    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),
+    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)
+  )
+  gen_as
+  (
+    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),
+    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),
+    .WR_CLK                   (WR_CLK),
+    .RD_CLK                   (RD_CLK),
+    .RST                      (rst_i),
+    .RST_FULL_GEN             (rst_full_gen_i),
+    .RST_FULL_FF              (rst_full_ff_i),
+    .WR_RST                   (wr_rst_i),
+    .RD_RST                   (rd_rst_i),
+    .DIN                      (din_delayed),
+    .WR_EN                    (wr_en_delayed),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .RD_EN_USER               (rd_en_delayed),
+    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),
+    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
+    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
+    .PROG_FULL_THRESH         (prog_full_thresh_delayed),
+    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),
+    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),
+    .INJECTSBITERR            (inject_sbit_err),
+    .INJECTDBITERR            (inject_dbit_err),
+    .USER_EMPTY_FB            (EMPTY_P0_OUT),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .EMPTY_FB                 (fifo_empty_fb),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),
+    .SBITERR                  (sbiterr_fifo_out),
+    .DBITERR                  (dbiterr_fifo_out)
+   );
+end
+
+endcase
+endgenerate
+
+
+   //**************************************************************************
+   // Connect Internal Signals
+   //   (Signals labeled internal_*)
+   //  In the normal case, these signals tie directly to the FIFO's inputs and
+   //    outputs.
+   //  In the case of Preload Latency 0 or 1, there are intermediate
+   //    signals between the internal FIFO and the preload logic.
+   //**************************************************************************
+   
+   
+   //***********************************************
+   // If First-Word Fall-Through, instantiate
+   // the preload0 (FWFT) module
+   //***********************************************
+   wire                        rd_en_to_fwft_fifo;
+   wire                        sbiterr_fwft;
+   wire                        dbiterr_fwft;
+   wire [C_DOUT_WIDTH-1:0]     dout_fwft;
+   wire                        empty_fwft;
+   wire                        rd_en_fifo_in;
+   wire                        stage2_reg_en_i;
+   wire [1:0]                  valid_stages_i;
+   wire                        rst_fwft;
+   //wire                        empty_p0_out;
+   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
+
+   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
+   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;
+   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
+   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
+
+   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft
+
+
+         fifo_generator_v13_2_5_bhv_ver_preload0
+           #(
+             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),
+             .C_DOUT_WIDTH        (C_DOUT_WIDTH),
+             .C_HAS_RST           (C_HAS_RST),
+             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),
+             .C_HAS_SRST          (C_HAS_SRST),
+             .C_USE_DOUT_RST      (C_USE_DOUT_RST),
+             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),
+             .C_USE_ECC           (C_USE_ECC),
+             .C_USERVALID_LOW     (C_VALID_LOW),
+             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
+             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),
+             .C_MEMORY_TYPE       (C_MEMORY_TYPE),
+             .C_FIFO_TYPE         (C_FIFO_TYPE)
+             )
+             fgpl0
+               (
+                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
+                .RD_CLK           (RD_CLK_P0_IN),
+                .RD_RST           (RST_P0_IN),
+                .SRST             (srst_delayed),
+                .WR_RST_BUSY      (wr_rst_busy),
+                .RD_RST_BUSY      (rd_rst_busy),
+                .RD_EN            (RD_EN_P0_IN),
+                .FIFOEMPTY        (EMPTY_P0_IN),
+                .FIFODATA         (DATA_P0_IN),
+                .FIFOSBITERR      (sbiterr_fifo_out),
+                .FIFODBITERR      (dbiterr_fifo_out),
+                // Output
+                .USERDATA         (dout_fwft),
+                .USERVALID        (VALID_P0_OUT),
+                .USEREMPTY        (empty_fwft),
+                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),
+                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),
+                .RAMVALID         (),
+                .FIFORDEN         (rd_en_fifo_in),
+                .USERSBITERR      (sbiterr_fwft),
+                .USERDBITERR      (dbiterr_fwft),
+                .STAGE2_REG_EN    (stage2_reg_en_i),
+                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),
+                .read_data_valid_i_o        (w_read_data_valid_i),
+                .ram_valid_i_o              (w_ram_valid_i),
+                .VALID_STAGES                (valid_stages_i)
+                );
+
+         
+         //***********************************************
+         // Connect inputs to preload (FWFT) module
+         //***********************************************
+         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we 
+         // have a common-clock FIFO, or RD_CLK if we have an 
+         // independent clock FIFO
+         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
+         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
+         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
+         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
+         assign DATA_P0_IN         = DOUT_FIFO_OUT;
+         
+         //***********************************************
+         // Connect outputs from preload (FWFT) module
+         //***********************************************
+         assign VALID              = VALID_P0_OUT ;
+         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;
+         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;
+         
+         assign RD_EN_FIFO_IN      = rd_en_fifo_in;
+         
+         
+         //***********************************************
+         // Create DATA_COUNT from First-Word Fall-Through
+         // data count
+         //***********************************************
+         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
+           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : 
+           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  
+         
+         //***********************************************
+         // Create DATA_COUNT from First-Word Fall-Through
+         // data count
+         //***********************************************
+         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
+            if (RST_P0_IN) begin
+               EMPTY_P0_OUT_Q       <= 1;
+               ALMOSTEMPTY_P0_OUT_Q <= 1;
+            end else begin
+               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;
+//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;
+               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
+            end
+         end //always
+         
+         
+         //***********************************************
+         // logic for common-clock data count when FWFT is selected
+         //***********************************************
+         initial begin
+            SS_FWFT_RD = 1'b0;
+            DATA_COUNT_FWFT = 0 ;
+            SS_FWFT_WR   = 1'b0 ;
+         end //initial
+         
+         
+         //***********************************************
+         // common-clock data count is implemented as an
+         // up-down counter. SS_FWFT_WR and SS_FWFT_RD
+         // are the up/down enables for the counter.
+         //***********************************************
+         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
+            if (C_VALID_LOW == 1) begin
+              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
+            end else begin
+              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
+            end
+            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;
+         end 
+
+         //***********************************************
+         // common-clock data count is implemented as an
+         // up-down counter for FWFT. This always block 
+         // calculates the counter.
+         //***********************************************
+         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
+            if (RST_P0_IN) begin
+               DATA_COUNT_FWFT      <= 0;
+            end else begin
+               //if (srst_delayed && (C_HAS_SRST == 1) ) begin
+               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
+                  DATA_COUNT_FWFT      <= #`TCQ 0;
+               end else begin
+                  case ( {SS_FWFT_WR, SS_FWFT_RD})
+                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
+                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
+                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
+                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
+                  endcase  
+               end //if SRST
+            end //IF RST
+         end //always
+
+      end endgenerate // : block2
+
+    // AXI Streaming Packet FIFO
+    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;
+    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;
+    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;
+    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;
+    reg                         partial_packet     = 0;
+    reg                         stage1_eop_d1      = 0;
+    reg                         rd_en_fifo_in_d1   = 0;
+    reg                         eop_at_stage2      = 0;
+    reg                         ram_pkt_empty      = 0;
+    reg                         ram_pkt_empty_d1   = 0;
+
+    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;
+    wire                        packet_empty_wr;
+    wire                        wr_rst_fwft_pkt_fifo;
+    wire                        dummy_wr_eop;
+    wire                        ram_wr_en_pkt_fifo;
+    wire                        wr_eop;
+    wire                        ram_rd_en_compare;
+    wire                        stage1_eop;
+    wire                        pkt_ready_to_read;
+    wire                        rd_en_2_stage2;
+
+    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
+    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
+    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
+    // write packet count
+    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
+       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin 
+          if (wr_rst_fwft_pkt_fifo)
+             partial_packet   <= 1'b0;
+          else begin
+             if (srst_delayed | wr_rst_busy | rd_rst_busy)
+                partial_packet <= #`TCQ 1'b0;
+             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
+                partial_packet <= #`TCQ 1'b1;
+             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
+                partial_packet <= #`TCQ 1'b0;
+          end
+        end
+    end endgenerate // gdummy_wr_eop
+
+    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft
+      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
+      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
+      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
+  
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+        if (rst_fwft) begin
+          stage1_eop_d1    <= 1'b0;
+          rd_en_fifo_in_d1 <= 1'b0;
+        end else begin
+          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
+            stage1_eop_d1    <= #`TCQ 1'b0;
+            rd_en_fifo_in_d1 <= #`TCQ 1'b0;
+          end else begin
+            stage1_eop_d1    <= #`TCQ stage1_eop;
+            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
+          end
+        end
+      end
+      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
+      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
+      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
+      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
+
+
+         fifo_generator_v13_2_5_bhv_ver_preload0
+           #(
+             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),
+             .C_DOUT_WIDTH        (C_DOUT_WIDTH),
+             .C_HAS_RST           (C_HAS_RST),
+             .C_HAS_SRST          (C_HAS_SRST),
+             .C_USE_DOUT_RST      (C_USE_DOUT_RST),
+             .C_USE_ECC           (C_USE_ECC),
+             .C_USERVALID_LOW     (C_VALID_LOW),
+             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),
+             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
+             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),
+             .C_MEMORY_TYPE       (C_MEMORY_TYPE),
+             .C_FIFO_TYPE         (2) // Enable low latency fwft logic
+             )
+         pkt_fifo_fwft
+               (
+                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
+                .RD_CLK           (RD_CLK_P0_IN),
+                .RD_RST           (rst_fwft),
+                .SRST             (srst_delayed),
+                .WR_RST_BUSY      (wr_rst_busy),
+                .RD_RST_BUSY      (rd_rst_busy),
+                .RD_EN            (rd_en_delayed),
+                .FIFOEMPTY        (pkt_ready_to_read),
+                .FIFODATA         (dout_fwft),
+                .FIFOSBITERR      (sbiterr_fwft),
+                .FIFODBITERR      (dbiterr_fwft),
+                // Output
+                .USERDATA         (dout_p0_out),
+                .USERVALID        (),
+                .USEREMPTY        (empty_p0_out),
+                .USERALMOSTEMPTY  (),
+                .USERUNDERFLOW    (),
+                .RAMVALID         (),
+                .FIFORDEN         (rd_en_2_stage2),
+                .USERSBITERR      (SBITERR),
+                .USERDBITERR      (DBITERR),
+                .STAGE2_REG_EN    (),
+                .VALID_STAGES     ()
+                );
+
+      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
+      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+        if (rst_fwft)
+          eop_at_stage2 <= 1'b0;
+        else if (stage2_reg_en_i)
+          eop_at_stage2 <= #`TCQ stage1_eop;
+      end
+
+      //---------------------------------------------------------------------------
+      // Write and Read Packet Count
+      //---------------------------------------------------------------------------
+      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin 
+         if (wr_rst_fwft_pkt_fifo)
+            wr_pkt_count  <= 0;
+         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)
+            wr_pkt_count  <= #`TCQ 0;
+         else if (wr_eop)
+            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;
+      end
+    
+    end endgenerate //: gpkt_fifo_fwft
+
+    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
+    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
+
+    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft) begin
+            rd_pkt_count       <= 0;
+            rd_pkt_count_plus1 <= 1;
+         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
+            rd_pkt_count       <= #`TCQ 0;
+            rd_pkt_count_plus1 <= #`TCQ 1;
+         end else if (stage2_reg_en_i && stage1_eop) begin
+            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;
+            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
+         end
+      end
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft) begin
+            ram_pkt_empty    <= 1'b1;
+            ram_pkt_empty_d1 <= 1'b1;
+         end else if (SRST | wr_rst_busy | rd_rst_busy) begin
+            ram_pkt_empty    <= #`TCQ 1'b1;
+            ram_pkt_empty_d1 <= #`TCQ 1'b1;
+         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
+            ram_pkt_empty    <= #`TCQ 1'b0;
+            ram_pkt_empty_d1 <= #`TCQ 1'b0;
+         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
+            ram_pkt_empty    <= #`TCQ 1'b1;
+         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
+            ram_pkt_empty_d1 <= #`TCQ 1'b1;
+         end
+      end
+    end endgenerate //grss_pkt_cnt
+    
+    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
+    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
+    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;
+    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;
+    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
+      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
+      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
+         if (wr_rst_fwft_pkt_fifo)
+            wr_pkt_count_b2g  <= 0;
+         else
+            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;
+      end
+
+      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft)
+            wr_pkt_count_q       <= 0;
+         else
+            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
+      end
+
+      always @* begin
+        if (stage1_eop)
+           rd_pkt_count    <= rd_pkt_count_reg + 1;
+        else
+           rd_pkt_count    <= rd_pkt_count_reg;
+      end
+
+      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft)
+            rd_pkt_count_reg       <= 0;
+         else if (rd_en_fifo_in)
+            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;
+      end
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft) begin
+            ram_pkt_empty    <= 1'b1;
+            ram_pkt_empty_d1 <= 1'b1;
+         end else if (rd_pkt_count != wr_pkt_count_rd) begin
+            ram_pkt_empty    <= #`TCQ 1'b0;
+            ram_pkt_empty_d1 <= #`TCQ 1'b0;
+         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
+            ram_pkt_empty    <= #`TCQ 1'b1;
+         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
+            ram_pkt_empty_d1 <= #`TCQ 1'b1;
+         end
+      end
+
+      // Synchronize the empty in write domain
+      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
+         if (wr_rst_fwft_pkt_fifo)
+            pkt_empty_sync  <= 'b1;
+         else
+            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
+      end
+
+    end endgenerate //gras_pkt_cnt
+
+   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
+
+     //***********************************************
+     // If NOT First-Word Fall-Through, wire the outputs
+     // of the internal _ss or _as FIFO directly to the
+     // output, and do not instantiate the preload0
+     // module.
+     //***********************************************
+
+     assign RD_CLK_P0_IN       = 0;
+     assign RST_P0_IN          = 0;
+     assign RD_EN_P0_IN        = 0;
+
+     assign RD_EN_FIFO_IN      = rd_en_delayed;
+
+     assign DOUT               = DOUT_FIFO_OUT;
+     assign DATA_P0_IN         = 0;
+     assign VALID              = VALID_FIFO_OUT;
+     assign EMPTY              = EMPTY_FIFO_OUT;
+     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;
+     assign EMPTY_P0_IN        = 0;
+     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;
+     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;
+     assign SBITERR            = sbiterr_fifo_out;
+     assign DBITERR            = dbiterr_fifo_out;
+
+   end endgenerate // STD_FIFO
+
+   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
+     assign empty_p0_out       = empty_fwft;
+     assign SBITERR            = sbiterr_fwft;
+     assign DBITERR            = dbiterr_fwft;
+     assign DOUT               = dout_fwft;
+     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
+
+   end endgenerate // NO_PKT_FIFO
+
+   //***********************************************
+   // Connect user flags to internal signals
+   //***********************************************
+   
+   //If we are using extra logic for the FWFT data count, then override the
+   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
+   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
+      if (C_COMMON_CLOCK == 0) begin : block_ic
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
+      end //block_ic
+      else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+      end 
+      end //block3
+   endgenerate
+   
+   //If we are using extra logic for the FWFT data count, then override the
+   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
+   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
+       if (C_COMMON_CLOCK == 0) begin : block_ic
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
+       end 
+       else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+        end 
+      end //block30
+   endgenerate
+
+
+    
+   //If we are using extra logic for the FWFT data count, then override the
+   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
+   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
+       if (C_COMMON_CLOCK == 0) begin : block_ic_both
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
+       end 
+       else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+        end 
+      end //block30_both
+   endgenerate
+
+ generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
+      if (C_COMMON_CLOCK == 0) begin : block_ic_both
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
+      end //block_ic_both
+      else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+      end 
+      end //block3_both
+   endgenerate
+
+
+   //If we are not using extra logic for the FWFT data count,
+   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
+   //internal FIFO instance  
+   generate
+      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+      end
+   endgenerate
+
+   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
+   //FIFO instance
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1) begin : block4
+         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
+      end
+      else begin : block4
+         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
+      end
+   endgenerate
+
+
+   //Connect other flags to the internal FIFO instance
+   assign       FULL        = FULL_FIFO_OUT;
+   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
+   assign       WR_ACK      = WR_ACK_FIFO_OUT;
+   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;
+   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;
+   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;
+
+
+  /**************************************************************************
+  * find_log2
+  *   Returns the 'log2' value for the input value for the supported ratios
+  ***************************************************************************/
+  function integer find_log2;
+    input integer int_val;
+    integer i,j;
+    begin
+      i = 1;
+      j = 0;
+      for (i = 1; i < int_val; i = i*2) begin
+        j = j + 1;
+      end
+      find_log2 = j;
+    end
+  endfunction
+
+   // if an asynchronous FIFO has been selected, display a message that the FIFO
+   //   will not be cycle-accurate in simulation
+   initial begin
+      if (C_IMPLEMENTATION_TYPE == 2) begin
+         $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
+      end else if (C_MEMORY_TYPE == 4) begin
+         $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
+         $finish;
+      end
+
+      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
+         $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
+         $finish;
+      end
+
+      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
+         $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
+         $finish;
+      end
+
+      if (C_USE_ECC == 1) begin
+         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
+            $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
+            $finish;
+         end
+         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
+            $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
+            $finish;
+         end
+      end
+
+   end //initial
+
+  /**************************************************************************
+  * Internal reset logic
+  **************************************************************************/
+  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;
+  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;
+  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;
+
+  wire rst_2_sync;
+  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
+
+  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;
+  localparam RST_BUSY_LEN    = 4;
+  reg  wr_rst_busy_i = 0;
+  reg  rd_rst_busy_i = 0;
+  generate
+      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync
+        always @* begin
+          wr_rst_reg <= wr_rst_delayed;
+          rd_rst_reg <= rd_rst_delayed;
+          rst_reg    <= 1'b0;
+          srst_reg    <= 1'b0;
+        end
+        assign rst_2_sync = wr_rst_delayed;
+        assign wr_rst_busy = 1'b0;
+        assign wr_rst_busy_o = 1'b0;
+        assign rd_rst_busy = 1'b0;
+        assign sckt_wr_rst_i = 1'b0;
+        assign sckt_rd_rst_i = 1'b0;
+      end // gnrst_sync
+      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt
+        reg [1:0]                 arst_sync_wr  = 2'b11;
+        reg [1:0]                 arst_sync_rd  = 2'b11;
+        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;
+        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;
+        reg [3:0]                 rd_rst_wr_ext = 0;
+        reg [1:0]                 wr_rst_rd_ext = 0;
+        reg                       sckt_wr_rst_ic = 0;
+        reg                       sckt_rd_rst_ic = 0;
+
+        assign rst_2_sync = arst_sync_wr[1];
+
+        always @(posedge WR_CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1'b1)
+	    arst_sync_wr    <= #`TCQ 2'b11;
+          else
+	    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};
+        end
+
+        always @(posedge RD_CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1'b1)
+	    arst_sync_rd    <= #`TCQ 2'b11;
+          else
+	    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};
+        end
+        always @(posedge WR_CLK) begin
+          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};
+	end
+        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin
+	  if (arst_sync_wr[1]) begin
+	    sckt_wr_rst_ic <= #`TCQ 1'b1;
+	    wr_rst_busy_i  <= #`TCQ 1'b1;
+            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};
+	  end else begin
+            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};
+	    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])
+	      sckt_wr_rst_ic <= #`TCQ 1'b0;
+            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])
+	      wr_rst_busy_i  <= #`TCQ 1'b0;
+	  end
+	end
+        always @(posedge RD_CLK) begin
+          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};
+	end
+        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin
+	  if (arst_sync_rd[1]) begin
+	    sckt_rd_rst_ic <= #`TCQ 1'b1;
+	    rd_rst_busy_i  <= #`TCQ 1'b1;
+            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};
+	  end else begin
+            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};
+	    if (wr_rst_rd_ext[1]) begin
+	      sckt_rd_rst_ic <= #`TCQ 1'b0;
+	      rd_rst_busy_i  <= #`TCQ 1'b0;
+	    end
+	  end
+	end
+
+        assign rd_rst_busy       = rd_rst_busy_i;
+        assign wr_rst_busy       = wr_rst_busy_i;
+        assign wr_rst_busy_o     = wr_rst_busy_i;
+        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];
+        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];
+      end // g7s_ic_rst_nsckt
+      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt
+        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};
+        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};
+        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;
+        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;
+        reg [3:0]                 rd_rst_wr_ext = 0;
+        reg [1:0]                 wr_rst_rd_ext = 0;
+        reg                       sckt_wr_rst_ic = 0;
+        reg                       sckt_rd_rst_ic = 0;
+
+        always @(posedge WR_CLK) begin
+	  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};
+          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};
+          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};
+	  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin
+	    sckt_wr_rst_ic <= #`TCQ 1'b1;
+	    wr_rst_busy_i  <= #`TCQ 1'b1;
+          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])
+	    sckt_wr_rst_ic <= #`TCQ 1'b0;
+          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])
+	    wr_rst_busy_i  <= #`TCQ 1'b0;
+	end
+        always @(posedge RD_CLK) begin
+	  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};
+          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};
+          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};
+	  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin
+	    sckt_rd_rst_ic <= #`TCQ 1'b1;
+	    rd_rst_busy_i  <= #`TCQ 1'b1;
+	  end else if (wr_rst_rd_ext[1]) begin
+	    sckt_rd_rst_ic <= #`TCQ 1'b0;
+	    rd_rst_busy_i  <= #`TCQ 1'b0;
+	  end
+	end
+
+        assign rd_rst_busy       = rd_rst_busy_i;
+        assign wr_rst_busy       = wr_rst_busy_i;
+        assign wr_rst_busy_o     = wr_rst_busy_i;
+        assign sckt_wr_rst_i     = sckt_wr_rst_ic;
+        assign sckt_rd_rst_i     = sckt_rd_rst_ic;
+      end // g7s_ic_rst_sckt
+      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt
+        reg [1:0]              arst_sync_wr  = 0;
+        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;
+        assign rst_2_sync = arst_sync_wr[1];
+
+        always @(posedge CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1'b1)
+	    arst_sync_wr    <= #`TCQ 2'b11;
+          else
+	    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};
+        end
+
+        always @(posedge CLK) begin
+	  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};
+	end
+
+        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; 
+        assign sckt_rd_rst_i  = sckt_wr_rst_i;
+        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];
+        assign rd_rst_busy    = |sckt_wr_rst_cc;
+        assign wr_rst_busy_o  = |sckt_wr_rst_cc;
+      end // g7s_cc_rst_nsckt
+      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt
+        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;
+        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;
+
+        always @(posedge CLK) begin
+	  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};
+	  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};
+	end
+
+        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; 
+        assign sckt_rd_rst_i  = sckt_wr_rst_i;
+        assign wr_rst_busy    = |sckt_wr_rst_cc;
+        assign rd_rst_busy    = |sckt_wr_rst_cc;
+        assign wr_rst_busy_o  = |sckt_wr_rst_cc;
+      end // g7s_cc_rst_sckt
+      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
+        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
+        assign rd_rst_busy = rst_reg;
+        assign rst_2_sync = srst_delayed;
+        assign sckt_wr_rst_i = rst_reg;
+        always @* rst_full_ff_i  <= 1'b0;
+        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
+
+        always @(posedge CLK) begin
+          rst_delayed_d1 <= #`TCQ srst_delayed;
+          rst_delayed_d2 <= #`TCQ rst_delayed_d1;
+          if (rst_reg || rst_delayed_d2) begin
+            rst_active_i <= #`TCQ 1'b1;
+          end else begin
+            rst_active_i <= #`TCQ rst_reg;
+          end    
+        end   
+        always @(posedge CLK) begin
+          if (~rst_reg && srst_delayed) begin
+             rst_reg <= #`TCQ 1'b1;
+           end else if (rst_reg) begin
+             rst_reg <= #`TCQ 1'b0;
+           end else begin
+             rst_reg <= #`TCQ rst_reg;
+           end    
+        end   
+      end // g8s_cc_rst
+      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst
+        assign wr_rst_busy = srst_delayed;
+        assign rd_rst_busy = srst_delayed;
+        assign rst_2_sync = srst_delayed;
+        assign sckt_wr_rst_i = srst_delayed;
+        always @* rst_full_ff_i  <= 1'b0;
+      end // g7s_cc_srst
+  endgenerate 
+
+  reg rst_d1 = 1'b0;
+  reg rst_d2 = 1'b0;
+  reg rst_d3 = 1'b0;
+  reg rst_d4 = 1'b0;
+  generate
+    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
+    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert
+    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
+
+    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
+    // PROG_FULL
+
+      always @ (posedge rst_2_sync or posedge clk_2_sync) begin
+        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin
+          rst_d1         <= 1'b1;
+          rst_d2         <= 1'b1;
+          rst_d3         <= 1'b1;
+          rst_d4         <= 1'b0;
+        end else begin
+          if (srst_delayed) begin
+            rst_d1         <= #`TCQ 1'b1;
+            rst_d2         <= #`TCQ 1'b1;
+            rst_d3         <= #`TCQ 1'b1;
+            rst_d4         <= #`TCQ 1'b0;
+          end else begin
+            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;
+            rst_d2         <= #`TCQ rst_d1;
+            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;
+            rst_d4         <= #`TCQ rst_d3;
+          end
+        end
+      end
+
+      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;
+      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;
+
+    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt
+      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
+      always @* rst_full_gen_i <= 1'b0;
+    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
+      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
+      always @* rst_full_gen_i <= 1'b0;
+    end
+  endgenerate // grstd1
+
+endmodule //fifo_generator_v13_2_5_CONV_VER
+
+
+module fifo_generator_v13_2_5_sync_stage
+  #(
+    parameter  C_WIDTH          = 10
+   )
+   (
+    input                     RST,
+    input                     CLK,
+    input       [C_WIDTH-1:0] DIN,
+    output reg  [C_WIDTH-1:0] DOUT = 0
+   );
+   always @ (posedge RST or posedge CLK) begin
+     if (RST)
+       DOUT <= 0;
+     else
+       DOUT <= #`TCQ DIN;
+   end
+endmodule // fifo_generator_v13_2_5_sync_stage
+
+/*******************************************************************************
+ * Declaration of Independent-Clocks FIFO Module
+ ******************************************************************************/
+module fifo_generator_v13_2_5_bhv_ver_as
+   
+  /***************************************************************************
+   * Declare user parameters and their defaults
+   ***************************************************************************/
+  #(
+    parameter  C_FAMILY                       = "virtex7",
+    parameter  C_DATA_COUNT_WIDTH             = 2,
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = "",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_ALMOST_EMPTY             = 0,
+    parameter  C_HAS_ALMOST_FULL              = 0,
+    parameter  C_HAS_DATA_COUNT               = 0,
+    parameter  C_HAS_OVERFLOW                 = 0,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_RST                      = 0,
+    parameter  C_HAS_UNDERFLOW                = 0,
+    parameter  C_HAS_VALID                    = 0,
+    parameter  C_HAS_WR_ACK                   = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_IMPLEMENTATION_TYPE          = 0,
+    parameter  C_MEMORY_TYPE                  = 1,
+    parameter  C_OVERFLOW_LOW                 = 0,
+    parameter  C_PRELOAD_LATENCY              = 1,
+    parameter  C_PRELOAD_REGS                 = 0,
+    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter  C_PROG_EMPTY_TYPE              = 0,
+    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter  C_PROG_FULL_TYPE               = 0,
+    parameter  C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_UNDERFLOW_LOW                = 0,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_USE_EMBEDDED_REG             = 0,
+    parameter  C_EN_SAFETY_CKT                = 0,
+    parameter  C_USE_FWFT_DATA_COUNT          = 0,
+    parameter  C_VALID_LOW                    = 0,
+    parameter  C_WR_ACK_LOW                   = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_USE_ECC                      = 0, 
+    parameter  C_ENABLE_RST_SYNC              = 1,
+    parameter  C_ERROR_INJECTION_TYPE         = 0,
+    parameter  C_SYNCHRONIZER_STAGE           = 2 
+   )
+
+  /***************************************************************************
+   * Declare Input and Output Ports
+   ***************************************************************************/
+  (
+   input                                         SAFETY_CKT_WR_RST,
+   input                                         SAFETY_CKT_RD_RST,
+   input       [C_DIN_WIDTH-1:0]                 DIN,
+   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,
+   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,
+   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,
+   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,
+   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,
+   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,
+   input                                         RD_CLK,
+   input                                         RD_EN,
+   input                                         RD_EN_USER,
+   input                                         RST,
+   input                                         RST_FULL_GEN,
+   input                                         RST_FULL_FF,
+   input                                         WR_RST,
+   input                                         RD_RST,
+   input                                         WR_CLK,
+   input                                         WR_EN,
+   input                                         INJECTDBITERR,
+   input                                         INJECTSBITERR,
+   input                                         USER_EMPTY_FB,
+   input                                         fab_read_data_valid_i,
+   input                                         read_data_valid_i,
+   input                                         ram_valid_i,
+   output reg                                    ALMOST_EMPTY = 1'b1,
+   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
+   output      [C_DOUT_WIDTH-1:0]                DOUT,
+   output reg                                    EMPTY = 1'b1,
+   output reg                                    EMPTY_FB = 1'b1,
+   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,
+   output                                        OVERFLOW,
+   output                                        PROG_EMPTY,
+   output                                        PROG_FULL,
+   output                                        VALID,
+   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,
+   output                                        UNDERFLOW,
+   output                                        WR_ACK,
+   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,
+   output                                        SBITERR,
+   output                                        DBITERR
+  );
+
+
+   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
+   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
+   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
+   
+  
+   /***************************************************************************
+    * Parameters used as constants
+    **************************************************************************/
+  localparam IS_8SERIES         = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
+   //When RST is present, set FULL reset value to '1'.
+   //If core has no RST, make sure FULL powers-on as '0'.
+   localparam C_DEPTH_RATIO_WR =  
+      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
+   localparam C_DEPTH_RATIO_RD =  
+      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
+   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
+   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
+
+   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC
+   //  -----------------|------------------|-----------------|---------------
+   //  1                | 8                | C_RD_PNTR_WIDTH | 2
+   //  1                | 4                | C_RD_PNTR_WIDTH | 2
+   //  1                | 2                | C_RD_PNTR_WIDTH | 2
+   //  1                | 1                | C_WR_PNTR_WIDTH | 2
+   //  2                | 1                | C_WR_PNTR_WIDTH | 4
+   //  4                | 1                | C_WR_PNTR_WIDTH | 8
+   //  8                | 1                | C_WR_PNTR_WIDTH | 16
+   
+   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
+   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+
+   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
+   
+   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
+   
+   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
+   
+   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
+
+
+
+   /**************************************************************************
+    * FIFO Contents Tracking and Data Count Calculations
+    *************************************************************************/
+   
+   // Memory which will be used to simulate a FIFO
+   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
+   // Local parameters used to determine whether to inject ECC error or not
+   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
+   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
+   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
+   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
+   // Array that holds the error injection type (single/double bit error) on 
+   // a specific write operation, which is returned on read to corrupt the
+   // output data.
+   reg [1:0] ecc_err[C_WR_DEPTH-1:0];
+
+   //The amount of data stored in the FIFO at any time is given
+   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
+   // domain.
+   //num_wr_bits is calculated by considering the total words in the FIFO,
+   // and the state of the read pointer (which may not have yet crossed clock
+   // domains.)
+   //num_rd_bits is calculated by considering the total words in the FIFO,
+   // and the state of the write pointer (which may not have yet crossed clock
+   // domains.)
+   reg [31:0]  num_wr_bits;
+   reg [31:0]  num_rd_bits;
+   reg [31:0]  next_num_wr_bits;
+   reg [31:0]  next_num_rd_bits;
+
+   //The write pointer - tracks write operations
+   // (Works opposite to core: wr_ptr is a DOWN counter)
+   reg  [31:0]                 wr_ptr;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;
+   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;
+   wire                        wr_rst_i = WR_RST;
+   reg                         wr_rst_d1      =0;
+
+   //The read pointer - tracks read operations
+   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
+   reg  [31:0]                 rd_ptr;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;
+   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;
+   wire                        rd_rst_i = RD_RST;
+   wire                        ram_rd_en;
+   wire                        empty_int;
+   wire                        almost_empty_int;
+   wire                        ram_wr_en;
+   wire                        full_int;
+   wire                        almost_full_int;
+   reg                         ram_rd_en_d1 = 1'b0;
+   reg                         fab_rd_en_d1 = 1'b0;
+
+
+
+   // Delayed ram_rd_en is needed only for STD Embedded register option
+   generate
+     if (C_PRELOAD_LATENCY == 2) begin : grd_d
+       always @ (posedge RD_CLK or posedge rd_rst_i) begin
+         if (rd_rst_i)
+           ram_rd_en_d1 <= 1'b0;
+         else
+           ram_rd_en_d1 <= #`TCQ ram_rd_en;
+       end
+     end
+   endgenerate
+   
+    generate
+     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
+       always @ (posedge RD_CLK or posedge rd_rst_i) begin
+         if (rd_rst_i)
+           ram_rd_en_d1 <= 1'b0;
+         else
+           ram_rd_en_d1 <= #`TCQ ram_rd_en;
+           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
+       end
+     end
+   endgenerate
+
+  
+
+   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
+   generate
+     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
+       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
+       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
+     end else begin : rdl // Read depth lesser than or equal to write depth
+       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+     end
+   endgenerate
+
+   // Generate Empty and Almost Empty
+  // ram_rd_en used to determine EMPTY should depend on the EMPTY.
+   assign ram_rd_en        = RD_EN & !EMPTY;
+   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
+   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
+
+   // Register Empty and Almost Empty
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
+         EMPTY             <= 1'b1;
+         ALMOST_EMPTY      <= 1'b1;
+         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
+       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin
+         EMPTY             <= 1'b1;
+         ALMOST_EMPTY      <= 1'b1;
+         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
+       end else begin
+         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
+
+         if (empty_int)
+           EMPTY           <= #`TCQ 1'b1;
+         else
+           EMPTY           <= #`TCQ 1'b0;
+
+         if (!EMPTY) begin
+           if (almost_empty_int)
+             ALMOST_EMPTY  <= #`TCQ 1'b1;
+           else
+             ALMOST_EMPTY  <= #`TCQ 1'b0;
+         end
+       end // rd_rst_i
+     end // always
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
+         EMPTY_FB     <= 1'b1;
+       end else begin
+         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
+           EMPTY_FB   <= #`TCQ 1'b1;
+         else if (empty_int)
+           EMPTY_FB   <= #`TCQ 1'b1;
+         else
+           EMPTY_FB   <= #`TCQ 1'b0;
+       end // rd_rst_i
+     end // always
+
+   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
+   generate
+     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
+       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
+       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
+     end else begin : wdl // Write depth lesser than or equal to read depth
+       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+     end
+   endgenerate
+
+  // Generate FULL and ALMOST_FULL
+  // ram_wr_en used to determine FULL should depend on the FULL.
+  assign ram_wr_en       = WR_EN & !FULL;
+  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
+  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
+
+   // Register FULL and ALMOST_FULL Empty
+   always @ (posedge WR_CLK or posedge RST_FULL_FF)
+     begin
+       if (RST_FULL_FF & C_HAS_RST) begin
+         FULL             <= C_FULL_FLAGS_RST_VAL;
+         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;
+       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin
+         FULL             <= C_FULL_FLAGS_RST_VAL;
+         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;
+       end else begin
+         if (full_int) begin
+           FULL           <= #`TCQ 1'b1;
+         end else begin
+           FULL           <= #`TCQ 1'b0;
+         end
+
+         if (RST_FULL_GEN) begin
+           ALMOST_FULL    <= #`TCQ 1'b0;
+         end else if (!FULL) begin
+           if (almost_full_int)
+             ALMOST_FULL  <= #`TCQ 1'b1;
+           else
+             ALMOST_FULL  <= #`TCQ 1'b0;
+         end
+       end // wr_rst_i
+     end // always
+   always @ (posedge WR_CLK or posedge wr_rst_i)
+     begin
+       if (wr_rst_i) begin
+         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
+       end else begin
+         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
+       end // wr_rst_i
+     end // always
+
+   // Determine which stage in FWFT registers are valid
+   reg stage1_valid = 0;
+   reg stage2_valid = 0;
+   generate
+     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
+       always @ (posedge RD_CLK or posedge rd_rst_i) begin
+         if (rd_rst_i) begin
+           stage1_valid     <= 0;
+           stage2_valid     <= 0;
+         end else begin
+
+           if (!stage1_valid && !stage2_valid) begin
+             if (!EMPTY)
+               stage1_valid    <= #`TCQ 1'b1;
+             else
+               stage1_valid    <= #`TCQ 1'b0;
+           end else if (stage1_valid && !stage2_valid) begin
+             if (EMPTY) begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b1;
+             end
+           end else if (!stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b0;
+             end else if (!EMPTY && RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b0;
+             end else if (!EMPTY && !RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b1;
+             end
+           end else if (stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b1;
+             end
+           end else begin
+             stage1_valid    <= #`TCQ 1'b0;
+             stage2_valid    <= #`TCQ 1'b0;
+           end
+         end // rd_rst_i
+       end // always
+     end
+   endgenerate
+
+   //Pointers passed into opposite clock domain
+   reg [31:0]  wr_ptr_rdclk;
+   reg [31:0]  wr_ptr_rdclk_next;
+   reg [31:0]  rd_ptr_wrclk;
+   reg [31:0]  rd_ptr_wrclk_next;
+
+   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port
+   // (Do not include data in FWFT stages)
+   //Used to calculate PROG_EMPTY.
+   wire [31:0] num_read_words_pe = 
+     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
+
+   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port
+   // (Do not include data in FWFT stages)
+   //Used to calculate PROG_FULL.
+   wire [31:0] num_write_words_pf =
+     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
+
+   /**************************
+    * Read Data Count
+    *************************/
+
+   reg [31:0] num_read_words_dc;
+   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
+   
+   always @(num_rd_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //If using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain, 
+        // and add two read words for FWFT stages
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //If not using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain.
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+   
+   /**************************
+    * Write Data Count
+    *************************/
+
+   reg [31:0] num_write_words_dc;
+   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
+   
+   always @(num_wr_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //Calculate the Data Count value for the number of write words, 
+        // when using First-Word Fall-Through with extra logic for Data 
+        // Counts. This takes into consideration the number of words that 
+        // are expected to be stored in the FWFT register stages (it always 
+        // assumes they are filled).
+        //This value is scaled to the Write Domain.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //EXTRA_WORDS_DC is the number of words added to write_words 
+        // due to FWFT.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
+        
+        //Trim the write words for use with WR_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //Calculate the Data Count value for the number of write words, when NOT
+        // using First-Word Fall-Through with extra logic for Data Counts. This 
+        // calculates only the number of words in the internal FIFO.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //This value is scaled to the Write Domain.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+    
+    
+   /***************************************************************************
+    * Internal registers and wires
+    **************************************************************************/
+
+   //Temporary signals used for calculating the model's outputs. These
+   //are only used in the assign statements immediately following wire,
+   //parameter, and function declarations.
+   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      
+   wire valid_i;
+   wire valid_out1;
+   wire valid_out2;
+   wire valid_out;  
+   wire underflow_i;
+
+   //Ideal FIFO signals. These are the raw output of the behavioral model,
+   //which behaves like an ideal FIFO.
+   reg [1:0]               err_type                 = 0;
+   reg [1:0]               err_type_d1              = 0;
+   reg [1:0]               err_type_both              = 0;
+   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;
+   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;
+   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;
+   reg                     ideal_wr_ack             = 0;
+   reg                     ideal_valid              = 0;
+   reg                     ideal_overflow           = C_OVERFLOW_LOW;
+   reg                     ideal_underflow          = C_UNDERFLOW_LOW;
+   reg                     ideal_prog_full          = 0;
+   reg                     ideal_prog_empty         = 1;
+   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
+   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
+
+   //Assorted reg values for delayed versions of signals   
+   reg         valid_d1     = 0;
+   reg         valid_d2     = 0; 
+   
+   //user specified value for reseting the size of the fifo
+   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;
+   
+   //temporary registers for WR_RESPONSE_LATENCY feature
+   
+   integer                           tmp_wr_listsize;
+   integer                           tmp_rd_listsize;
+   
+   //Signal for registered version of prog full and empty
+   
+   //Threshold values for Programmable Flags
+   integer                           prog_empty_actual_thresh_assert;
+   integer                           prog_empty_actual_thresh_negate;
+   integer                           prog_full_actual_thresh_assert;
+   integer                           prog_full_actual_thresh_negate;
+   
+
+  /****************************************************************************
+   * Function Declarations
+   ***************************************************************************/
+
+  /**************************************************************************
+   * write_fifo
+   *   This task writes a word to the FIFO memory and updates the 
+   * write pointer.
+   *   FIFO size is relative to write domain.
+  ***************************************************************************/
+  task write_fifo;
+    begin
+      memory[wr_ptr]     <= DIN;
+      wr_pntr <= #`TCQ wr_pntr + 1;
+      // Store the type of error injection (double/single) on write
+      case (C_ERROR_INJECTION_TYPE)
+        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};
+        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};
+        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};
+        default: ecc_err[wr_ptr]    <= 0;
+      endcase
+      // (Works opposite to core: wr_ptr is a DOWN counter)
+      if (wr_ptr == 0) begin
+        wr_ptr          <= C_WR_DEPTH - 1;
+      end else begin
+        wr_ptr          <= wr_ptr - 1;
+      end
+    end
+  endtask // write_fifo
+
+  /**************************************************************************
+   * read_fifo
+   *   This task reads a word from the FIFO memory and updates the read 
+   * pointer. It's output is the ideal_dout bus.
+   *   FIFO size is relative to write domain.
+   ***************************************************************************/
+  task read_fifo;
+    integer i;
+    reg [C_DOUT_WIDTH-1:0]      tmp_dout;
+    reg [C_DIN_WIDTH-1:0]       memory_read;
+    reg [31:0]                  tmp_rd_ptr;
+    reg [31:0]                  rd_ptr_high;
+    reg [31:0]                  rd_ptr_low;
+    reg [1:0]                   tmp_ecc_err;
+    begin
+      rd_pntr <= #`TCQ rd_pntr + 1;
+      // output is wider than input
+      if (reads_per_write == 0) begin
+        tmp_dout = 0;
+        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
+        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
+          tmp_dout = tmp_dout << C_DIN_WIDTH;
+          tmp_dout = tmp_dout | memory[tmp_rd_ptr];
+           
+          // (Works opposite to core: rd_ptr is a DOWN counter)
+          if (tmp_rd_ptr == 0) begin
+            tmp_rd_ptr = C_WR_DEPTH - 1;
+          end else begin
+            tmp_rd_ptr = tmp_rd_ptr - 1;
+          end
+        end
+
+      // output is symmetric
+      end else if (reads_per_write == 1) begin
+        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
+        // Retreive the error injection type. Based on the error injection type
+        // corrupt the output data.
+        tmp_ecc_err = ecc_err[rd_ptr];
+        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
+          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
+            if (C_DOUT_WIDTH == 1) begin
+              $display("FAILURE : Data width must be >= 2 for double bit error injection.");
+              $finish;
+            end else if (C_DOUT_WIDTH == 2)
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
+            else
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
+          end else begin
+            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
+          end
+          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
+        end else begin
+          err_type <= 0;
+        end
+
+      // input is wider than output
+      end else begin
+        rd_ptr_high = rd_ptr >> log2_reads_per_write;
+        rd_ptr_low  = rd_ptr & (reads_per_write - 1);
+        memory_read = memory[rd_ptr_high];
+        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
+      end
+      ideal_dout <= tmp_dout;
+       
+      // (Works opposite to core: rd_ptr is a DOWN counter)
+      if (rd_ptr == 0) begin
+        rd_ptr <= C_RD_DEPTH - 1;
+      end else begin
+        rd_ptr <= rd_ptr - 1;
+      end
+    end
+  endtask
+
+  /**************************************************************************
+  * log2_val
+  *   Returns the 'log2' value for the input value for the supported ratios
+  ***************************************************************************/
+  function [31:0] log2_val;
+    input [31:0] binary_val;
+
+    begin
+      if (binary_val == 8) begin
+        log2_val = 3;
+      end else if (binary_val == 4) begin
+        log2_val = 2;
+      end else begin
+        log2_val = 1;
+      end
+    end
+  endfunction
+
+  /***********************************************************************
+  * hexstr_conv
+  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+  ***********************************************************************/
+  function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  /*************************************************************************
+  * Initialize Signals for clean power-on simulation
+  *************************************************************************/
+   initial begin
+      num_wr_bits        = 0;
+      num_rd_bits        = 0;
+      next_num_wr_bits   = 0;
+      next_num_rd_bits   = 0;
+      rd_ptr             = C_RD_DEPTH - 1;
+      wr_ptr             = C_WR_DEPTH - 1;
+      wr_pntr            = 0;
+      rd_pntr            = 0;
+      rd_ptr_wrclk       = rd_ptr;
+      wr_ptr_rdclk       = wr_ptr;
+      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
+      ideal_dout         = dout_reset_val;
+      err_type           = 0;
+      err_type_d1        = 0;
+      err_type_both      = 0;
+      ideal_dout_d1      = dout_reset_val;
+      ideal_wr_ack       = 1'b0;
+      ideal_valid        = 1'b0;
+      valid_d1           = 1'b0;
+      valid_d2           = 1'b0;
+      ideal_overflow     = C_OVERFLOW_LOW;
+      ideal_underflow    = C_UNDERFLOW_LOW;
+      ideal_wr_count     = 0;
+      ideal_rd_count     = 0;
+      ideal_prog_full    = 1'b0;
+      ideal_prog_empty   = 1'b1;
+    end
+
+
+  /*************************************************************************
+   * Connect the module inputs and outputs to the internal signals of the 
+   * behavioral model.
+   *************************************************************************/
+   //Inputs
+   /*
+    wire [C_DIN_WIDTH-1:0] DIN;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   
+   wire RD_CLK;
+   wire RD_EN;
+   wire RST;
+   wire WR_CLK;
+   wire WR_EN;
+    */
+
+   //***************************************************************************
+   // Dout may change behavior based on latency
+   //***************************************************************************
+   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
+                         ideal_dout_d1: ideal_dout;   
+   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; 
+
+   //***************************************************************************
+   // Assign SBITERR and DBITERR based on latency 
+   //***************************************************************************
+   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && 
+                    (C_PRELOAD_LATENCY == 2 &&
+                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
+                    err_type_d1[0]: err_type[0]; 
+   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
+                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
+                    err_type_d1[1]: err_type[1]; 
+  
+   //***************************************************************************
+   // Safety-ckt logic with embedded reg/fabric reg
+   //***************************************************************************
+     generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+
+       //  if (C_HAS_VALID == 1) begin
+       //       assign valid_out = valid_d1;
+       //  end
+             
+        always@(posedge RD_CLK)
+          begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+          end
+        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
+          begin
+          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) 
+              ram_rd_en_d1 <= #`TCQ 1'b0;
+          else 
+               ram_rd_en_d1 <= #`TCQ ram_rd_en;
+          end
+          
+        always@(posedge rst_delayed_sft2 or posedge RD_CLK) 
+           begin
+           if (rst_delayed_sft2 == 1'b1) begin
+              if (C_USE_DOUT_RST == 1'b1) begin
+                  @(posedge RD_CLK)
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+              end
+           end
+           else begin
+                   if (ram_rd_en_d1) begin
+                   ideal_dout_d1   <= #`TCQ ideal_dout;
+                   err_type_d1[0] <= #`TCQ err_type[0];
+                   err_type_d1[1] <= #`TCQ err_type[1];
+                   end
+             end 
+           end  
+      end 
+      endgenerate   
+
+//***************************************************************************
+   // Safety-ckt logic with embedded reg + fabric reg
+   //***************************************************************************
+     generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+
+        always@(posedge RD_CLK) begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+        end
+        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
+          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) 
+              ram_rd_en_d1 <= #`TCQ 1'b0;
+          else begin
+               ram_rd_en_d1 <= #`TCQ ram_rd_en;
+               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
+          end
+        end
+          
+        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
+           if (rst_delayed_sft2 == 1'b1) begin
+              if (C_USE_DOUT_RST == 1'b1) begin
+                   @(posedge RD_CLK)
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+                   ideal_dout_both <= #`TCQ dout_reset_val;
+              end
+           end else begin
+             if (ram_rd_en_d1) begin
+               ideal_dout_both   <= #`TCQ ideal_dout;
+               err_type_both[0] <= #`TCQ err_type[0];
+               err_type_both[1] <= #`TCQ err_type[1];
+             end
+              
+             if (fab_rd_en_d1) begin
+               ideal_dout_d1   <= #`TCQ ideal_dout_both;
+               err_type_d1[0] <= #`TCQ err_type_both[0];
+               err_type_d1[1] <= #`TCQ err_type_both[1];
+             end
+           end 
+         end      
+      end 
+      endgenerate    
+ 
+   //***************************************************************************
+   // Overflow may be active-low
+   //***************************************************************************
+   generate
+      if (C_HAS_OVERFLOW==1) begin : blockOF1
+   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
+      end
+   endgenerate
+
+   assign PROG_EMPTY = ideal_prog_empty;
+   assign PROG_FULL  = ideal_prog_full;
+
+   //***************************************************************************
+   // Valid may change behavior based on latency or active-low
+   //***************************************************************************
+   generate
+      if (C_HAS_VALID==1) begin : blockVL1
+   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
+   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
+                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
+                       valid_d1: valid_i;  
+   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
+                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
+                       valid_d2: valid_i; 
+   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
+   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;
+     end
+   endgenerate
+
+
+   //***************************************************************************
+   // Underflow may change behavior based on latency or active-low   
+   //***************************************************************************
+   generate
+      if (C_HAS_UNDERFLOW==1) begin : blockUF1
+   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
+   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
+    end
+   endgenerate
+
+   //***************************************************************************
+   // Write acknowledge may be active low
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_ACK==1) begin : blockWK1
+   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+     end
+   endgenerate
+
+
+   //***************************************************************************
+   // Generate RD_DATA_COUNT if Use Extra Logic option is selected
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
+
+      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;
+      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;
+      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;
+      wire [C_PNTR_WIDTH:0]    diff_wr_rd;
+      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;
+        always @* begin
+          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
+            adjusted_wr_pntr = wr_pntr;
+            adjusted_rd_pntr = 0;
+            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
+          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
+            adjusted_rd_pntr = rd_pntr_wr;
+            adjusted_wr_pntr = 0;
+            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
+          end else begin
+            adjusted_wr_pntr = wr_pntr;
+            adjusted_rd_pntr = rd_pntr_wr;
+          end
+        end // always @*
+
+        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
+        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};
+
+        always @ (posedge wr_rst_i or posedge WR_CLK)
+        begin
+            if (wr_rst_i)
+              wr_data_count_i <= 0;
+            else
+              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
+        end // always @ (posedge WR_CLK or posedge WR_CLK)
+
+        always @* begin
+          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
+            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
+          else
+            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+        end // always @*
+      end // wdc_fwft_ext
+   endgenerate
+
+   //***************************************************************************
+   // Generate RD_DATA_COUNT if Use Extra Logic option is selected
+   //***************************************************************************
+   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;
+
+   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
+      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
+      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;
+      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;
+      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;
+        always @* begin
+          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
+            adjusted_wr_pntr_rd = 0;
+            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
+          end else begin
+            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+          end
+        end // always @*
+
+        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
+        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};
+
+
+   always @ (posedge rd_rst_i or posedge RD_CLK)
+        begin
+            if (rd_rst_i) begin
+              rdc_fwft_ext_as   <= 0;
+            end else begin
+              if (!stage2_valid)
+                rdc_fwft_ext_as <= #`TCQ 0;
+              else if (!stage1_valid && stage2_valid)
+                rdc_fwft_ext_as <= #`TCQ 1;
+              else
+                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
+            end 
+        end // always @ (posedge WR_CLK or posedge WR_CLK)
+      end // rdc_fwft_ext
+ end
+   endgenerate
+
+
+  generate if (C_USE_EMBEDDED_REG == 3) begin
+     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
+      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;
+      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;
+      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;
+        always @* begin
+          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
+            adjusted_wr_pntr_rd = 0;
+            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
+          end else begin
+            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+          end
+        end // always @*
+
+        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
+        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};
+        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;
+   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;
+
+       always @ (posedge rd_rst_i or posedge RD_CLK)
+        begin
+            if (rd_rst_i) begin
+              rdc_fwft_ext_as   <= #`TCQ 0;
+            end else begin
+          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
+          //    rdc_fwft_ext_as <= 1'b0;
+          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) 
+          //    rdc_fwft_ext_as <= 1'b1;
+          //else
+            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
+        end
+
+
+
+end
+end
+end
+endgenerate
+          
+
+   //***************************************************************************
+   // Assign the read data count value only if it is selected, 
+   // otherwise output zeros.
+   //***************************************************************************
+   generate
+      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
+   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
+          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
+          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
+      end
+   endgenerate
+
+   generate
+      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
+   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
+      end
+   endgenerate
+
+   //***************************************************************************
+   // Assign the write data count value only if it is selected, 
+   // otherwise output zeros
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
+   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
+          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
+          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
+      end
+   endgenerate
+   
+   generate
+      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
+   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
+      end
+   endgenerate
+
+
+  /**************************************************************************
+  * Assorted registers for delayed versions of signals
+  **************************************************************************/
+  //Capture delayed version of valid
+  generate
+      if (C_HAS_VALID==1) begin : blockVL2
+  always @(posedge RD_CLK or posedge rd_rst_i) begin
+    if (rd_rst_i == 1'b1) begin
+      valid_d1 <= 1'b0;
+      valid_d2 <= 1'b0;
+    end else begin
+      valid_d1 <= #`TCQ valid_i;
+      valid_d2 <= #`TCQ valid_d1;
+    end 
+//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
+  //      valid_d2 <= #`TCQ valid_d1;
+      //  end 
+  end 
+      end
+ endgenerate  
+   
+  //Capture delayed version of dout
+  /**************************************************************************
+    *embedded/fabric reg with no safety ckt
+    **************************************************************************/
+  generate 
+       if (C_USE_EMBEDDED_REG < 3) begin
+  always @(posedge RD_CLK or posedge rd_rst_i) begin
+    if (rd_rst_i == 1'b1) begin
+       if (C_USE_DOUT_RST == 1'b1) begin
+         @(posedge RD_CLK)
+           ideal_dout_d1   <= #`TCQ dout_reset_val;
+           ideal_dout   <= #`TCQ dout_reset_val;
+       end
+      // Reset err_type only if ECC is not selected
+      if (C_USE_ECC == 0)
+        err_type_d1     <= #`TCQ 0;
+     end else if (ram_rd_en_d1) begin
+      ideal_dout_d1   <= #`TCQ ideal_dout;
+      err_type_d1     <= #`TCQ err_type;
+           end    
+  end  
+   
+end  
+endgenerate 
+/**************************************************************************
+    *embedded + fabric reg with no safety ckt
+    **************************************************************************/
+
+generate 
+  if (C_USE_EMBEDDED_REG == 3) begin
+    always @(posedge RD_CLK or posedge rd_rst_i) begin
+      if (rd_rst_i == 1'b1) begin
+        if (C_USE_DOUT_RST == 1'b1) begin
+           @(posedge RD_CLK)
+             ideal_dout    <= #`TCQ dout_reset_val;
+             ideal_dout_d1   <= #`TCQ dout_reset_val;
+             ideal_dout_both   <= #`TCQ dout_reset_val;
+        end
+        // Reset err_type only if ECC is not selected
+        if (C_USE_ECC == 0) begin
+          err_type_d1     <= #`TCQ 0;
+          err_type_both   <= #`TCQ 0;
+        end
+      end else begin
+         if (ram_rd_en_d1) begin
+           ideal_dout_both   <= #`TCQ ideal_dout;
+           err_type_both     <= #`TCQ err_type;
+         end    
+         if (fab_rd_en_d1) begin
+           ideal_dout_d1   <= #`TCQ ideal_dout_both;
+           err_type_d1     <= #`TCQ err_type_both;
+         end
+      end
+    end  
+  end  
+endgenerate 
+
+  
+   /**************************************************************************
+    * Overflow and Underflow Flag calculation
+    *  (handled separately because they don't support rst)
+    **************************************************************************/
+   generate
+     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
+       always @(posedge WR_CLK) begin
+         ideal_overflow    <= #`TCQ WR_EN & FULL;
+       end
+     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
+       always @(posedge WR_CLK) begin
+         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);
+         ideal_overflow    <= #`TCQ WR_EN & (FULL );
+       end
+     end
+   endgenerate
+
+   generate
+     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
+       always @(posedge RD_CLK) begin
+         ideal_underflow    <= #`TCQ EMPTY & RD_EN;
+       end
+     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
+       always @(posedge RD_CLK) begin
+         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;
+         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
+       end
+     end
+   endgenerate
+
+   /**************************************************************************
+   * Write/Read Pointer Synchronization
+   **************************************************************************/
+   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
+   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
+   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
+   genvar gss;
+
+   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
+     fifo_generator_v13_2_5_sync_stage
+       #(
+         .C_WIDTH  (C_WR_PNTR_WIDTH)
+        )
+     rd_stg_inst
+        (
+         .RST      (rd_rst_i), 
+         .CLK      (RD_CLK), 
+         .DIN      (wr_pntr_sync_stgs[gss-1]), 
+         .DOUT     (wr_pntr_sync_stgs[gss])
+        );
+ 
+     fifo_generator_v13_2_5_sync_stage
+       #(
+         .C_WIDTH  (C_RD_PNTR_WIDTH)
+        )
+     wr_stg_inst
+        (
+         .RST      (wr_rst_i), 
+         .CLK      (WR_CLK), 
+         .DIN      (rd_pntr_sync_stgs[gss-1]), 
+         .DOUT     (rd_pntr_sync_stgs[gss])
+        );
+   end endgenerate // Sync_stage_inst
+
+   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
+   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
+   always@* begin
+     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
+     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
+   end
+
+   /**************************************************************************
+   * Write Domain Logic
+   **************************************************************************/
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
+   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
+     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
+       wr_pntr           <= 0;
+     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
+       wr_pntr           <= #`TCQ 0;
+   end
+   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
+
+     /****** Reset fifo (case 1)***************************************/
+     if (wr_rst_i == 1'b1) begin
+       num_wr_bits       <= 0;
+       next_num_wr_bits   = 0;
+       wr_ptr            <= C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= C_RD_DEPTH - 1;
+       ideal_wr_ack      <= 0;
+       ideal_wr_count    <= 0;
+       tmp_wr_listsize    = 0;
+       rd_ptr_wrclk_next <= 0;
+       wr_pntr_rd1       <= 0;
+
+     end else begin //wr_rst_i==0
+
+       wr_pntr_rd1   <= #`TCQ wr_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
+                         num_wr_bits/C_DIN_WIDTH;
+       rd_ptr_wrclk_next = rd_ptr;
+       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
+                                          - rd_ptr_wrclk_next);
+       end else begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
+       end
+
+       //If this is a write, handle the write by adding the value
+       // to the linked list, and updating all outputs appropriately
+       if (WR_EN == 1'b1) begin
+         if (FULL == 1'b1) begin
+
+           //If the FIFO is full, do NOT perform the write,
+           // update flags accordingly
+           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD 
+             >= C_FIFO_WR_DEPTH) begin
+             //write unsuccessful - do not change contents
+
+             //Do not acknowledge the write
+             ideal_wr_ack      <= #`TCQ 0;
+             //Reminder that FIFO is still full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is one from full, but reporting full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                C_FIFO_WR_DEPTH-1) begin
+             //No change to FIFO
+
+             //Write not successful
+             ideal_wr_ack      <= #`TCQ 0;
+             //With DEPTH-1 words in the FIFO, it is almost_full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+
+           //If the FIFO is completely empty, but it is
+           // reporting FULL for some reason (like reset)
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
+                C_FIFO_WR_DEPTH-2) begin
+             //No change to FIFO
+
+             //Write not successful
+             ideal_wr_ack      <= #`TCQ 0;
+             //FIFO is really not close to full, so change flag status.
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+           end //(tmp_wr_listsize == 0)
+
+         end else begin
+
+           //If the FIFO is full, do NOT perform the write,
+           // update flags accordingly
+           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
+              C_FIFO_WR_DEPTH) begin
+             //write unsuccessful - do not change contents
+
+             //Do not acknowledge the write
+             ideal_wr_ack       <= #`TCQ 0;
+             //Reminder that FIFO is still full
+
+             ideal_wr_count     <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is one from full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                C_FIFO_WR_DEPTH-1) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
+
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= #`TCQ 1;
+             //This write is CAUSING the FIFO to go full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is 2 from full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 
+                C_FIFO_WR_DEPTH-2) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= #`TCQ 1;
+             //Still 2 from full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is not close to being full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
+                C_FIFO_WR_DEPTH-2) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= #`TCQ 1;
+             //Not even close to full.
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           end
+
+         end
+
+       end else begin //(WR_EN == 1'b1)
+
+         //If user did not attempt a write, then do not
+         // give ack or err
+         ideal_wr_ack   <= #`TCQ 0;
+         ideal_wr_count <= #`TCQ num_write_words_sized_i;
+       end
+       num_wr_bits       <= #`TCQ next_num_wr_bits;
+       rd_ptr_wrclk      <= #`TCQ rd_ptr;
+
+     end //wr_rst_i==0
+   end // gen_fifo_w
+
+
+  /***************************************************************************
+   * Programmable FULL flags
+   ***************************************************************************/
+
+   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
+   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
+
+   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
+     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
+     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
+   end else begin // STD
+     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
+     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
+   end endgenerate
+
+   always @(posedge WR_CLK or posedge wr_rst_i) begin
+
+     if (wr_rst_i == 1'b1) begin
+       diff_pntr         <= 0;
+     end else begin
+       if (ram_wr_en)
+         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
+       else if (!ram_wr_en)
+         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
+    end
+  end
+
+
+   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
+
+     if (RST_FULL_FF & C_HAS_RST) begin
+       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
+     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin
+       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
+     end else begin
+
+       if (RST_FULL_GEN)
+         ideal_prog_full   <= #`TCQ 0;
+       //Single Programmable Full Constant Threshold
+       else if (C_PROG_FULL_TYPE == 1) begin
+         if (FULL == 0) begin
+           if (diff_pntr >= pf_thr_assert_val)
+             ideal_prog_full <= #`TCQ 1;
+           else
+             ideal_prog_full <= #`TCQ 0;
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       //Two Programmable Full Constant Thresholds
+       end else if (C_PROG_FULL_TYPE == 2) begin
+         if (FULL == 0) begin
+           if (diff_pntr >= pf_thr_assert_val)
+             ideal_prog_full <= #`TCQ 1;
+           else if (diff_pntr < pf_thr_negate_val)
+             ideal_prog_full <= #`TCQ 0;
+           else
+             ideal_prog_full <= #`TCQ ideal_prog_full;
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       //Single Programmable Full Threshold Input
+       end else if (C_PROG_FULL_TYPE == 3) begin
+         if (FULL == 0) begin
+           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
+             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
+               ideal_prog_full <= #`TCQ 1;
+             else
+               ideal_prog_full <= #`TCQ 0;
+           end else begin // STD
+             if (diff_pntr >= PROG_FULL_THRESH)
+               ideal_prog_full <= #`TCQ 1;
+             else
+               ideal_prog_full <= #`TCQ 0;
+           end
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       //Two Programmable Full Threshold Inputs
+       end else if (C_PROG_FULL_TYPE == 4) begin
+         if (FULL == 0) begin
+           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
+             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
+               ideal_prog_full <= #`TCQ 1;
+             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
+               ideal_prog_full <= #`TCQ 0;
+             else
+               ideal_prog_full <= #`TCQ ideal_prog_full;
+           end else begin // STD
+             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
+               ideal_prog_full <= #`TCQ 1;
+             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
+               ideal_prog_full <= #`TCQ 0;
+             else
+               ideal_prog_full <= #`TCQ ideal_prog_full;
+           end
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       end // C_PROG_FULL_TYPE
+
+     end //wr_rst_i==0
+   end //
+
+   
+   /**************************************************************************
+   * Read Domain Logic
+   **************************************************************************/
+
+
+   /*********************************************************
+    * Programmable EMPTY flags
+    *********************************************************/
+   //Determine the Assert and Negate thresholds for Programmable Empty
+
+   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
+   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
+   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;
+
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
+
+     if (rd_rst_i & C_HAS_RST) begin
+       diff_pntr_rd       <= 0;
+       ideal_prog_empty   <= 1'b1;
+     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin
+       diff_pntr_rd       <= 0;
+       ideal_prog_empty   <= 1'b1;
+     end else begin
+       if (ram_rd_en)
+         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
+       else if (!ram_rd_en)
+         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);
+       else
+         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;
+  
+       if (C_PROG_EMPTY_TYPE == 1) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else
+             ideal_prog_empty <= #`TCQ 0;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end else if (C_PROG_EMPTY_TYPE == 2) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else if (diff_pntr_rd > pe_thr_negate_val)
+             ideal_prog_empty <= #`TCQ 0;
+           else
+             ideal_prog_empty <= #`TCQ ideal_prog_empty;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end else if (C_PROG_EMPTY_TYPE == 3) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else
+             ideal_prog_empty <= #`TCQ 0;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end else if (C_PROG_EMPTY_TYPE == 4) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else if (diff_pntr_rd > pe_thr_negate_val)
+             ideal_prog_empty <= #`TCQ 0;
+           else
+             ideal_prog_empty <= #`TCQ ideal_prog_empty;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end  //C_PROG_EMPTY_TYPE
+     end
+   end // gen_pe
+
+   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
+     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
+   end endgenerate // single_pe_thr_input
+
+   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
+     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
+     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
+   end endgenerate // multiple_pe_thr_input
+
+   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
+     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
+     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
+   end endgenerate // single_multiple_pe_thr_const
+
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
+     if (rd_rst_i && C_EN_SAFETY_CKT == 0)
+       rd_pntr            <= 0;
+     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
+       rd_pntr            <= #`TCQ 0;
+   end
+
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rd_rst_i & C_HAS_RST) begin
+       num_rd_bits        <= 0;
+       next_num_rd_bits    = 0;
+       rd_ptr             <= C_RD_DEPTH -1;
+       rd_pntr_wr1        <= 0;
+       wr_ptr_rdclk       <= C_WR_DEPTH -1;
+  
+       // DRAM resets asynchronously
+       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
+          ideal_dout    <= dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= 0;
+         err_type_d1      <= 0;
+         err_type_both    <= 0;
+       end
+       ideal_valid        <= 1'b0;
+       ideal_rd_count     <= 0;
+
+     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin
+       num_rd_bits        <= 0;
+       next_num_rd_bits    = 0;
+       rd_ptr             <= C_RD_DEPTH -1;
+       rd_pntr_wr1        <= 0;
+       wr_ptr_rdclk       <= C_WR_DEPTH -1;
+  
+       // DRAM resets asynchronously
+       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
+          ideal_dout    <= dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= 0;
+         err_type_d1      <= 0;
+         err_type_both    <= 0;
+       end
+       ideal_valid        <= 1'b0;
+       ideal_rd_count     <= 0;
+     end else begin //rd_rst_i==0
+
+       rd_pntr_wr1   <= #`TCQ rd_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
+                         num_rd_bits/C_DOUT_WIDTH;
+       wr_ptr_rdclk_next = wr_ptr;
+
+       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
+         next_num_rd_bits = num_rd_bits +
+                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
+                                         - wr_ptr_rdclk_next);
+       end else begin
+         next_num_rd_bits = num_rd_bits +
+                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
+       end
+
+       /*****************************************************************/
+       // Read Operation - Read Latency 1
+       /*****************************************************************/
+       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
+                 ideal_valid        <= #`TCQ 1'b0;
+
+         if (ram_rd_en == 1'b1) begin
+
+           if (EMPTY == 1'b1) begin
+
+             //If the FIFO is completely empty, and is reporting empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= #`TCQ 1'b0;
+                 //Reminder that FIFO is still empty
+
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+               end // if (tmp_rd_listsize <= 0)
+
+             //If the FIFO is one from empty, but it is reporting empty
+             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= #`TCQ 1'b0;
+                 //Note that FIFO is no longer empty, but is almost empty (has one word left)
+
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+               end // if (tmp_rd_listsize == 1)
+
+             //If the FIFO is two from empty, and is reporting empty
+             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= #`TCQ 1'b0;
+                 //Fifo has two words, so is neither empty or almost empty
+
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+               end // if (tmp_rd_listsize == 2)
+
+             //If the FIFO is not close to empty, but is reporting that it is
+             // Treat the FIFO as empty this time, but unset EMPTY flags.
+             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid <= #`TCQ 1'b0;
+                 //Note that the FIFO is No Longer Empty or Almost Empty
+
+                 ideal_rd_count <= #`TCQ num_read_words_sized_i;
+
+               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+             end // else: if(ideal_empty == 1'b1)
+
+           else //if (ideal_empty == 1'b0)
+             begin
+
+               //If the FIFO is completely full, and we are successfully reading from it
+               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1'b1;
+                   //Not close to empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
+
+               //If the FIFO is not close to being empty
+               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1'b1;
+                   //Not close to empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+
+               //If the FIFO is two from empty
+               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1'b1;
+                   //Fifo is not yet empty. It is going almost_empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 2)
+
+               //If the FIFO is one from empty
+               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1'b1;
+                   //Note that FIFO is GOING empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 1)
+
+
+               //If the FIFO is completely empty
+               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+                 begin
+                   //Do not change the contents of the FIFO
+
+                   //Do not acknowledge the read from empty FIFO
+                   ideal_valid        <= #`TCQ 1'b0;
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize <= 0)
+
+             end // if (ideal_empty == 1'b0)
+
+           end //(RD_EN == 1'b1)
+
+         else //if (RD_EN == 1'b0)
+           begin
+             //If user did not attempt a read, do not give an ack or err
+             ideal_valid          <= #`TCQ 1'b0;
+
+             ideal_rd_count       <= #`TCQ num_read_words_sized_i;
+
+           end // else: !if(RD_EN == 1'b1)
+
+       /*****************************************************************/
+       // Read Operation - Read Latency 0
+       /*****************************************************************/
+       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+                 ideal_valid        <= #`TCQ 1'b0;
+         if (ram_rd_en == 1'b1) begin
+
+           if (EMPTY == 1'b1) begin
+
+             //If the FIFO is completely empty, and is reporting empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1'b0;
+               //Reminder that FIFO is still empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is one from empty, but it is reporting empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1'b0;
+               //Note that FIFO is no longer empty, but is almost empty (has one word left)
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is two from empty, and is reporting empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1'b0;
+               //Fifo has two words, so is neither empty or almost empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+               //If the FIFO is not close to empty, but is reporting that it is
+             // Treat the FIFO as empty this time, but unset EMPTY flags.
+             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
+                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1'b0;
+               //Note that the FIFO is No Longer Empty or Almost Empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+
+           end else begin
+
+             //If the FIFO is completely full, and we are successfully reading from it
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1'b1;
+               //Not close to empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is not close to being empty
+             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
+                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1'b1;
+               //Not close to empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is two from empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1'b1;
+               //Fifo is not yet empty. It is going almost_empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is one from empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1'b1;
+               //Note that FIFO is GOING empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is completely empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1'b0;
+               //Reminder that FIFO is still empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             end // if (tmp_rd_listsize <= 0)
+
+           end // if (ideal_empty == 1'b0)
+
+         end else begin//(RD_EN == 1'b0)
+
+         
+           //If user did not attempt a read, do not give an ack or err
+           ideal_valid           <= #`TCQ 1'b0;
+           ideal_rd_count        <= #`TCQ num_read_words_sized_i;
+
+         end // else: !if(RD_EN == 1'b1)
+       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
+
+       num_rd_bits      <= #`TCQ next_num_rd_bits;
+       wr_ptr_rdclk     <= #`TCQ wr_ptr;
+     end //rd_rst_i==0
+   end //always gen_fifo_r_as
+
+endmodule // fifo_generator_v13_2_5_bhv_ver_as
+
+
+/*******************************************************************************
+ * Declaration of Low Latency Asynchronous FIFO
+ ******************************************************************************/
+module fifo_generator_v13_2_5_beh_ver_ll_afifo
+   
+  /***************************************************************************
+   * Declare user parameters and their defaults
+   ***************************************************************************/
+  #(
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = "",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_FIFO_TYPE                    = 0
+   )
+
+  /***************************************************************************
+   * Declare Input and Output Ports
+   ***************************************************************************/
+  (
+   input       [C_DIN_WIDTH-1:0]                 DIN,
+   input                                         RD_CLK,
+   input                                         RD_EN,
+   input                                         WR_RST,
+   input                                         RD_RST,
+   input                                         WR_CLK,
+   input                                         WR_EN,
+   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,
+   output reg                                    EMPTY = 1'b1,
+   output reg                                    FULL = C_FULL_FLAGS_RST_VAL
+  );
+
+  //-----------------------------------------------------------------------------
+  // Low Latency Asynchronous FIFO
+  //-----------------------------------------------------------------------------
+
+  // Memory which will be used to simulate a FIFO
+  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
+  integer i;
+  initial begin
+    for (i = 0; i < C_WR_DEPTH; i = i + 1)
+      memory[i] = 0;
+  end
+
+  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
+  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
+  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
+  reg                        ll_afifo_full    = 1'b0;
+  reg                        ll_afifo_empty   = 1'b1;
+  wire                       write_allow;
+  wire                       read_allow;
+
+  assign write_allow = WR_EN & ~ll_afifo_full;
+  assign read_allow  = RD_EN & ~ll_afifo_empty;
+
+  //-----------------------------------------------------------------------------
+  // Write Pointer Generation
+  //-----------------------------------------------------------------------------
+  always @(posedge WR_CLK or posedge WR_RST) begin
+    if (WR_RST)
+      wr_pntr_ll_afifo   <= 0;
+    else if (write_allow)
+      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
+  end
+
+  //-----------------------------------------------------------------------------
+  // Read Pointer Generation
+  //-----------------------------------------------------------------------------
+  always @(posedge RD_CLK or posedge RD_RST) begin
+    if (RD_RST)
+      rd_pntr_ll_afifo_q   <= 0;
+    else
+      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
+  end
+  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
+  
+  //-----------------------------------------------------------------------------
+  // Fill the Memory
+  //-----------------------------------------------------------------------------
+  always @(posedge WR_CLK) begin
+    if (write_allow)
+      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
+  end
+
+  //-----------------------------------------------------------------------------
+  // Generate DOUT
+  //-----------------------------------------------------------------------------
+  always @(posedge RD_CLK) begin
+      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
+  end
+
+  //-----------------------------------------------------------------------------
+  // Generate EMPTY
+  //-----------------------------------------------------------------------------
+  always @(posedge RD_CLK or posedge RD_RST) begin
+    if (RD_RST)
+      ll_afifo_empty   <= 1'b1;
+    else
+      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | 
+                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
+  end
+
+  //-----------------------------------------------------------------------------
+  // Generate FULL
+  //-----------------------------------------------------------------------------
+  always @(posedge WR_CLK or posedge WR_RST) begin
+    if (WR_RST)
+      ll_afifo_full   <= 1'b1;
+    else
+      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | 
+                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
+  end
+
+  always @* begin
+    FULL  <= ll_afifo_full;
+    EMPTY <= ll_afifo_empty;
+  end
+
+endmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo
+
+/*******************************************************************************
+ * Declaration of top-level module
+ ******************************************************************************/
+module fifo_generator_v13_2_5_bhv_ver_ss
+   
+  /**************************************************************************
+   * Declare user parameters and their defaults
+   *************************************************************************/
+  #(
+    parameter  C_FAMILY                       = "virtex7",
+    parameter  C_DATA_COUNT_WIDTH             = 2,
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = "",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_ALMOST_EMPTY             = 0,
+    parameter  C_HAS_ALMOST_FULL              = 0,
+    parameter  C_HAS_DATA_COUNT               = 0,
+    parameter  C_HAS_OVERFLOW                 = 0,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_RST                      = 0,
+    parameter  C_HAS_SRST                     = 0,
+    parameter  C_HAS_UNDERFLOW                = 0,
+    parameter  C_HAS_VALID                    = 0,
+    parameter  C_HAS_WR_ACK                   = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_IMPLEMENTATION_TYPE          = 0,
+    parameter  C_MEMORY_TYPE                  = 1,
+    parameter  C_OVERFLOW_LOW                 = 0,
+    parameter  C_PRELOAD_LATENCY              = 1,
+    parameter  C_PRELOAD_REGS                 = 0,
+    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter  C_PROG_EMPTY_TYPE              = 0,
+    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter  C_PROG_FULL_TYPE               = 0,
+    parameter  C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_UNDERFLOW_LOW                = 0,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_USE_EMBEDDED_REG             = 0,
+    parameter  C_EN_SAFETY_CKT                = 0,
+    parameter  C_USE_FWFT_DATA_COUNT          = 0,
+    parameter  C_VALID_LOW                    = 0,
+    parameter  C_WR_ACK_LOW                   = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_USE_ECC                      = 0, 
+    parameter  C_ENABLE_RST_SYNC              = 1,
+    parameter  C_ERROR_INJECTION_TYPE         = 0,
+    parameter  C_FIFO_TYPE                    = 0 
+   )
+   
+  /**************************************************************************
+   * Declare Input and Output Ports
+   *************************************************************************/
+   (
+    //Inputs
+    input                                 SAFETY_CKT_WR_RST,
+    input                                 CLK,
+    input       [C_DIN_WIDTH-1:0]         DIN,
+    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,
+    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,
+    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,
+    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,
+    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,
+    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,
+    input                                 RD_EN,
+    input                                 RD_EN_USER,
+    input                                 USER_EMPTY_FB,
+    input                                 RST,
+    input                                 RST_FULL_GEN,
+    input                                 RST_FULL_FF,
+    input                                 SRST,
+    input                                 WR_EN,
+    input                                 INJECTDBITERR,
+    input                                 INJECTSBITERR,
+    input                                 WR_RST_BUSY,
+    input                                 RD_RST_BUSY,
+                                    
+    //Outputs                       
+    output                                ALMOST_EMPTY,
+    output                                ALMOST_FULL,
+    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
+    output       [C_DOUT_WIDTH-1:0]       DOUT,
+    output                                EMPTY,
+    output reg                            EMPTY_FB = 1'b1,
+    output                                FULL,
+    output                                OVERFLOW,
+    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,
+    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,
+    output                                PROG_EMPTY,
+    output                                PROG_FULL,
+    output                                VALID,
+    output                                UNDERFLOW,
+    output                                WR_ACK,
+    output                                SBITERR,
+    output                                DBITERR
+   );
+
+
+   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
+   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
+   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
+   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
+   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
+   /***************************************************************************
+    * Parameters used as constants
+    **************************************************************************/
+  localparam IS_8SERIES         = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
+   localparam C_DEPTH_RATIO_WR =  
+      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
+   localparam C_DEPTH_RATIO_RD =  
+      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
+   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
+   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
+   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; 
+
+
+   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC
+   //  -----------------|------------------|-----------------|---------------
+   //  1                | 8                | C_RD_PNTR_WIDTH | 2
+   //  1                | 4                | C_RD_PNTR_WIDTH | 2
+   //  1                | 2                | C_RD_PNTR_WIDTH | 2
+   //  1                | 1                | C_WR_PNTR_WIDTH | 2
+   //  2                | 1                | C_WR_PNTR_WIDTH | 4
+   //  4                | 1                | C_WR_PNTR_WIDTH | 8
+   //  8                | 1                | C_WR_PNTR_WIDTH | 16
+   
+   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
+   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
+   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
+
+   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
+   
+   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
+   
+   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
+   
+   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
+
+
+   //When RST is present, set FULL reset value to '1'.
+   //If core has no RST, make sure FULL powers-on as '0'.
+   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not 
+   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
+   // Therefore, during SRST, all the FULL flags reset to 0.
+   localparam                      C_HAS_FAST_FIFO = 0;
+   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;
+   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;
+   // Local parameters used to determine whether to inject ECC error or not
+   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
+   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
+   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
+   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
+   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
+   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
+   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
+  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; 
+  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; 
+
+
+   /**************************************************************************
+    * FIFO Contents Tracking and Data Count Calculations
+    *************************************************************************/
+   // Memory which will be used to simulate a FIFO
+   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
+   reg [1:0] ecc_err[C_WR_DEPTH-1:0];
+
+   
+   /**************************************************************************
+    * Internal Registers and wires
+    *************************************************************************/
+
+   //Temporary signals used for calculating the model's outputs. These
+   //are only used in the assign statements immediately following wire,
+   //parameter, and function declarations.
+   wire                           underflow_i;
+   wire                           valid_i;
+   wire                           valid_out;
+   reg [31:0]  num_wr_bits;
+   reg [31:0]  num_rd_bits;
+   reg [31:0]  next_num_wr_bits;
+   reg [31:0]  next_num_rd_bits;
+
+   //The write pointer - tracks write operations
+   // (Works opposite to core: wr_ptr is a DOWN counter)
+   reg  [31:0]                 wr_ptr;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;
+   reg                         wr_rst_d1      =0;
+
+   //The read pointer - tracks read operations
+   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
+   reg  [31:0]                 rd_ptr;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;
+
+   wire                        ram_rd_en;
+   wire                        empty_int;
+   wire                        almost_empty_int;
+   wire                        ram_wr_en;
+   wire                        full_int;
+   wire                        almost_full_int;
+   reg                         ram_rd_en_reg = 1'b0;
+   reg                         ram_rd_en_d1 = 1'b0;
+   reg                         fab_rd_en_d1 = 1'b0;
+   wire                         srst_rrst_busy;
+
+
+
+   //Ideal FIFO signals. These are the raw output of the behavioral model,
+   //which behaves like an ideal FIFO.
+   reg [1:0]                      err_type           = 0;
+   reg [1:0]                      err_type_d1        = 0;
+   reg [1:0]                      err_type_both      = 0;
+   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;
+   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;
+   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;
+   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;
+   wire                           fwft_enabled;
+   reg                            ideal_wr_ack       = 0;
+   reg                            ideal_valid        = 0;
+   reg                            ideal_overflow     = C_OVERFLOW_LOW;
+   reg                            ideal_underflow    = C_UNDERFLOW_LOW;
+
+   reg                            full_i             = C_FULL_FLAGS_RST_VAL;
+   reg                            full_i_temp        = 0;
+   reg                            empty_i            = 1;
+   reg                            almost_full_i      = 0;
+   reg                            almost_empty_i     = 1;
+   reg                            prog_full_i        = 0;
+   reg                            prog_empty_i       = 1;
+   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;
+   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;
+   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;
+   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;
+   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;
+
+   reg                            write_allow_q      = 0;
+   reg                            read_allow_q       = 0;
+   reg                            valid_d1           = 0;
+   reg                            valid_both           = 0;
+   reg                            valid_d2           = 0;
+   wire                           rst_i;
+   wire                           srst_i;
+
+   //user specified value for reseting the size of the fifo
+   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;
+
+   reg [31:0]  wr_ptr_rdclk;
+   reg [31:0]  wr_ptr_rdclk_next;
+   reg [31:0]  rd_ptr_wrclk;
+   reg [31:0]  rd_ptr_wrclk_next;
+
+
+
+
+   /****************************************************************************
+    * Function Declarations
+    ***************************************************************************/
+
+   /****************************************************************************
+    * hexstr_conv
+    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+    ***************************************************************************/
+    function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
+        case (def_data[7:0])
+          8'b00000000 : begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default : begin
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1) begin
+          if ((index*4)+j < C_DOUT_WIDTH) begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+ /**************************************************************************
+  * log2_val
+  *   Returns the 'log2' value for the input value for the supported ratios
+  ***************************************************************************/
+  function [31:0] log2_val;
+    input [31:0] binary_val;
+
+    begin
+      if (binary_val == 8) begin
+        log2_val = 3;
+      end else if (binary_val == 4) begin
+        log2_val = 2;
+      end else begin
+        log2_val = 1;
+      end
+    end
+  endfunction
+
+   reg                     ideal_prog_full          = 0;
+   reg                     ideal_prog_empty         = 1;
+   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
+   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
+
+   //Assorted reg values for delayed versions of signals   
+   //reg         valid_d1     = 0;
+   
+   
+   //user specified value for reseting the size of the fifo
+   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;
+   
+   //temporary registers for WR_RESPONSE_LATENCY feature
+   
+   integer                           tmp_wr_listsize;
+   integer                           tmp_rd_listsize;
+   
+   //Signal for registered version of prog full and empty
+   
+   //Threshold values for Programmable Flags
+   integer                           prog_empty_actual_thresh_assert;
+   integer                           prog_empty_actual_thresh_negate;
+   integer                           prog_full_actual_thresh_assert;
+   integer                           prog_full_actual_thresh_negate;
+
+
+ /**************************************************************************
+   * write_fifo
+   *   This task writes a word to the FIFO memory and updates the 
+   * write pointer.
+   *   FIFO size is relative to write domain.
+  ***************************************************************************/
+  task write_fifo;
+    begin
+      memory[wr_ptr]     <= DIN;
+      wr_pntr <= #`TCQ wr_pntr + 1;
+      // Store the type of error injection (double/single) on write
+      case (C_ERROR_INJECTION_TYPE)
+        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};
+        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};
+        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};
+        default: ecc_err[wr_ptr]    <= 0;
+      endcase
+      // (Works opposite to core: wr_ptr is a DOWN counter)
+      if (wr_ptr == 0) begin
+        wr_ptr          <= C_WR_DEPTH - 1;
+      end else begin
+        wr_ptr          <= wr_ptr - 1;
+      end
+    end
+  endtask // write_fifo
+
+  /**************************************************************************
+   * read_fifo
+   *   This task reads a word from the FIFO memory and updates the read 
+   * pointer. It's output is the ideal_dout bus.
+   *   FIFO size is relative to write domain.
+   ***************************************************************************/
+  task read_fifo;
+    integer i;
+    reg [C_DOUT_WIDTH-1:0]      tmp_dout;
+    reg [C_DIN_WIDTH-1:0]       memory_read;
+    reg [31:0]                  tmp_rd_ptr;
+    reg [31:0]                  rd_ptr_high;
+    reg [31:0]                  rd_ptr_low;
+    reg [1:0]                   tmp_ecc_err;
+    begin
+      rd_pntr <= #`TCQ rd_pntr + 1;
+
+      // output is wider than input
+      if (reads_per_write == 0) begin
+        tmp_dout = 0;
+        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
+        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
+          tmp_dout = tmp_dout << C_DIN_WIDTH;
+          tmp_dout = tmp_dout | memory[tmp_rd_ptr];
+           
+          // (Works opposite to core: rd_ptr is a DOWN counter)
+          if (tmp_rd_ptr == 0) begin
+            tmp_rd_ptr = C_WR_DEPTH - 1;
+          end else begin
+            tmp_rd_ptr = tmp_rd_ptr - 1;
+          end
+        end
+
+      // output is symmetric
+      end else if (reads_per_write == 1) begin
+        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
+        // Retreive the error injection type. Based on the error injection type
+        // corrupt the output data.
+        tmp_ecc_err = ecc_err[rd_ptr];
+        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
+          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
+            if (C_DOUT_WIDTH == 1) begin
+              $display("FAILURE : Data width must be >= 2 for double bit error injection.");
+              $finish;
+            end else if (C_DOUT_WIDTH == 2)
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
+            else
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
+          end else begin
+            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
+          end
+          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
+        end else begin
+          err_type <= 0;
+        end
+
+      // input is wider than output
+      end else begin
+        rd_ptr_high = rd_ptr >> log2_reads_per_write;
+        rd_ptr_low  = rd_ptr & (reads_per_write - 1);
+        memory_read = memory[rd_ptr_high];
+        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
+      end
+      ideal_dout <= tmp_dout;
+       
+      // (Works opposite to core: rd_ptr is a DOWN counter)
+     if (rd_ptr == 0) begin
+        rd_ptr <= C_RD_DEPTH - 1;
+      end else begin
+        rd_ptr <= rd_ptr - 1;
+      end
+
+     end
+  endtask
+
+
+   
+  /*************************************************************************
+  * Initialize Signals for clean power-on simulation
+  *************************************************************************/
+   initial begin
+      num_wr_bits        = 0;
+      num_rd_bits        = 0;
+      next_num_wr_bits   = 0;
+      next_num_rd_bits   = 0;
+      rd_ptr             = C_RD_DEPTH - 1;
+      wr_ptr             = C_WR_DEPTH - 1;
+      wr_pntr            = 0;
+      rd_pntr            = 0;
+      rd_ptr_wrclk       = rd_ptr;
+      wr_ptr_rdclk       = wr_ptr;
+      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
+      ideal_dout         = dout_reset_val;
+      err_type           = 0;
+      err_type_d1        = 0;
+      err_type_both      = 0;
+      ideal_dout_d1      = dout_reset_val;
+      ideal_dout_both    = dout_reset_val;
+      ideal_wr_ack       = 1'b0;
+      ideal_valid        = 1'b0;
+      valid_d1           = 1'b0;
+      valid_both         = 1'b0;
+      ideal_overflow     = C_OVERFLOW_LOW;
+      ideal_underflow    = C_UNDERFLOW_LOW;
+      ideal_wr_count     = 0;
+      ideal_rd_count     = 0;
+      ideal_prog_full    = 1'b0;
+      ideal_prog_empty   = 1'b1;
+
+   end
+
+
+  /*************************************************************************
+   * Connect the module inputs and outputs to the internal signals of the
+   * behavioral model.
+   *************************************************************************/
+   //Inputs
+   /*
+   wire CLK;
+   wire [C_DIN_WIDTH-1:0] DIN;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
+   wire RD_EN;
+   wire RST;
+   wire WR_EN;
+    */
+
+  // Assign ALMOST_EPMTY
+  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
+    assign ALMOST_EMPTY = almost_empty_i;
+  end else begin : gnae
+    assign ALMOST_EMPTY = 0;
+  end endgenerate // gae
+
+  // Assign ALMOST_FULL
+  generate if (C_HAS_ALMOST_FULL==1) begin : gaf
+    assign ALMOST_FULL  = almost_full_i;
+  end else begin : gnaf
+    assign ALMOST_FULL  = 0;
+  end endgenerate // gaf
+
+   // Dout may change behavior based on latency
+  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
+                         1: 0;
+  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
+                         1: 0;
+  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
+                         ideal_dout_d1: ideal_dout; 
+  assign DOUT = ideal_dout_out;
+
+  // Assign SBITERR and DBITERR based on latency 
+  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && 
+                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
+                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
+                   err_type_d1[0]: err_type[0]; 
+  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
+                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
+                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
+                   err_type_d1[1]: err_type[1]; 
+
+  assign EMPTY         = empty_i;
+  assign FULL          = full_i;
+  //saftey_ckt with one register
+
+  generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge CLK)
+          begin
+          rst_delayed_sft1 <= #`TCQ rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+          end
+        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
+          begin
+          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin 
+              ram_rd_en_d1 <= #`TCQ 1'b0;
+              valid_d1 <= #`TCQ 1'b0;
+          end
+          else begin
+               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
+               valid_d1 <= #`TCQ valid_i;
+          end
+          end
+          
+           always@(posedge rst_delayed_sft2 or posedge CLK) 
+           begin
+           if (rst_delayed_sft2 == 1'b1) begin
+              if (C_USE_DOUT_RST == 1'b1) begin
+                   @(posedge CLK)
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+              end
+              end
+           else if (srst_rrst_busy == 1'b1) begin
+                   if (C_USE_DOUT_RST == 1'b1) begin
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+                   end
+           end else if (ram_rd_en_d1) begin
+                   ideal_dout_d1   <= #`TCQ ideal_dout;
+                   err_type_d1[0] <= #`TCQ err_type[0];
+                   err_type_d1[1] <= #`TCQ err_type[1];
+                end
+           end   
+      end //if 
+      endgenerate   
+
+//safety ckt with both registers
+
+generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge CLK) begin
+          rst_delayed_sft1 <= #`TCQ rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+        end
+        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
+          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin 
+            ram_rd_en_d1 <= #`TCQ 1'b0;
+            valid_d1 <= #`TCQ 1'b0;
+          end else begin
+            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
+            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
+            valid_both <= #`TCQ valid_i;
+            valid_d1 <= #`TCQ valid_both;
+          end
+        end
+
+        always@(posedge rst_delayed_sft2 or posedge CLK) begin
+          if (rst_delayed_sft2 == 1'b1) begin
+             if (C_USE_DOUT_RST == 1'b1) begin
+                   @(posedge CLK)
+                  ideal_dout_d1 <= #`TCQ dout_reset_val;
+             end
+          end else if (srst_rrst_busy == 1'b1) begin
+             if (C_USE_DOUT_RST == 1'b1) begin
+               ideal_dout_d1 <= #`TCQ dout_reset_val;
+             end
+          end else begin 
+            if (ram_rd_en_d1) begin
+               ideal_dout_both   <= #`TCQ ideal_dout;
+               err_type_both[0] <= #`TCQ err_type[0];
+               err_type_both[1] <= #`TCQ err_type[1];
+             end
+             if (fab_rd_en_d1) begin
+               ideal_dout_d1   <= #`TCQ ideal_dout_both;
+               err_type_d1[0] <= #`TCQ err_type_both[0];
+               err_type_d1[1] <= #`TCQ err_type_both[1];
+            end
+          end
+        end
+      end //if 
+      endgenerate    
+ 
+ 
+  //Overflow may be active-low
+  generate if (C_HAS_OVERFLOW==1) begin : gof
+    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
+  end else begin : gnof
+    assign OVERFLOW = 0;
+  end endgenerate // gof
+
+  assign PROG_EMPTY    = prog_empty_i;
+  assign PROG_FULL     = prog_full_i;
+
+   //Valid may change behavior based on latency or active-low
+  generate if (C_HAS_VALID==1) begin : gvalid
+    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
+    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
+                            valid_d1 : valid_i; 
+    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;
+  end else begin : gnvalid
+    assign VALID         = 0;
+  end endgenerate // gvalid
+
+  //Trim data count differently depending on set widths
+  generate if (C_HAS_DATA_COUNT == 1) begin : gdc
+    always @* begin
+      diff_count <= wr_pntr - rd_pntr;
+      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
+        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;
+        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; 
+      end else begin
+        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
+      end
+    end
+//  end else begin : gndc
+//    always @* DATA_COUNT <= 0;
+  end endgenerate // gdc
+
+  //Underflow may change behavior based on latency or active-low
+  generate if (C_HAS_UNDERFLOW==1) begin : guf
+    assign underflow_i   = ideal_underflow;
+    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
+  end else begin : gnuf
+    assign UNDERFLOW     = 0;
+  end endgenerate // guf
+ 
+
+  //Write acknowledge may be active low 
+  generate if (C_HAS_WR_ACK==1) begin : gwr_ack
+    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+  end else begin : gnwr_ack
+    assign WR_ACK        = 0;
+  end endgenerate // gwr_ack
+
+
+  /*****************************************************************************
+   * Internal reset logic 
+   ****************************************************************************/
+  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
+  assign rst_i            = C_HAS_RST ? RST : 0;
+  assign srst_wrst_busy   = srst_i;
+  assign srst_rrst_busy   = srst_i;
+
+   /**************************************************************************
+    * Assorted registers for delayed versions of signals
+    **************************************************************************/
+   //Capture delayed version of valid
+   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
+     always @(posedge CLK or posedge rst_i) begin
+        if (rst_i == 1'b1) begin
+           valid_d1 <= 1'b0;
+        end else begin
+           if (srst_rrst_busy) begin
+              valid_d1 <= #`TCQ 1'b0;
+           end else begin
+              valid_d1 <= #`TCQ valid_i;
+           end
+        end    
+     end // always @ (posedge CLK or posedge rst_i)
+     end 
+   endgenerate // blockVL20
+
+  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin 
+     always @(posedge CLK or posedge rst_i) begin
+        if (rst_i == 1'b1) begin
+           valid_d1   <= 1'b0;
+           valid_both <= 1'b0;
+        end else begin
+           if (srst_rrst_busy) begin
+              valid_d1 <= #`TCQ 1'b0;
+              valid_both <= #`TCQ 1'b0;
+              
+           end else begin
+              valid_both <= #`TCQ valid_i;
+               valid_d1 <= #`TCQ valid_both;
+           end
+        end    
+     end // always @ (posedge CLK or posedge rst_i)
+  end
+ endgenerate // blockVL20
+
+
+   // Determine which stage in FWFT registers are valid
+   reg stage1_valid = 0;
+   reg stage2_valid = 0;
+   generate
+     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
+       always @ (posedge CLK or posedge rst_i) begin
+         if (rst_i) begin
+           stage1_valid     <= #`TCQ 0;
+           stage2_valid     <= #`TCQ 0;
+         end else begin
+
+           if (!stage1_valid && !stage2_valid) begin
+             if (!EMPTY)
+               stage1_valid    <= #`TCQ 1'b1;
+             else
+               stage1_valid    <= #`TCQ 1'b0;
+           end else if (stage1_valid && !stage2_valid) begin
+             if (EMPTY) begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b1;
+             end
+           end else if (!stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN) begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b0;
+             end else if (!EMPTY && RD_EN) begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b0;
+             end else if (!EMPTY && !RD_EN) begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b1;
+             end
+           end else if (stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN) begin
+               stage1_valid    <= #`TCQ 1'b0;
+               stage2_valid    <= #`TCQ 1'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1'b1;
+               stage2_valid    <= #`TCQ 1'b1;
+             end
+           end else begin
+             stage1_valid    <= #`TCQ 1'b0;
+             stage2_valid    <= #`TCQ 1'b0;
+           end
+         end // rd_rst_i
+       end // always
+     end
+   endgenerate
+
+
+
+   //***************************************************************************
+   // Assign the read data count value only if it is selected, 
+   // otherwise output zeros.
+   //***************************************************************************
+   generate
+      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
+       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
+      end
+   endgenerate
+
+   generate
+      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
+   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
+      end
+   endgenerate
+
+   //***************************************************************************
+   // Assign the write data count value only if it is selected, 
+   // otherwise output zeros
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
+       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
+      end
+   endgenerate
+   
+   generate
+      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
+   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
+      end
+   endgenerate
+   
+   //reg ram_rd_en_d1 = 1'b0;
+   //Capture delayed version of dout
+   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
+   always @(posedge CLK or posedge rst_i) begin
+      if (rst_i == 1'b1) begin
+         // Reset err_type only if ECC is not selected
+         if (C_USE_ECC == 0) begin
+            err_type_d1      <= #`TCQ 0;
+            err_type_both    <= #`TCQ 0;
+         end
+         // DRAM and SRAM reset asynchronously
+         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+         end
+         ram_rd_en_d1 <= #`TCQ 1'b0;
+        if (C_USE_DOUT_RST == 1) begin
+            @(posedge CLK)
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+        end
+      end else begin
+         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
+         if (srst_rrst_busy) begin
+            ram_rd_en_d1 <= #`TCQ 1'b0;
+            // Reset err_type only if ECC is not selected
+            if (C_USE_ECC == 0) begin
+               err_type_d1   <= #`TCQ 0;
+               err_type_both <= #`TCQ 0;
+            end
+            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
+            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+               ideal_dout_d1 <= #`TCQ dout_reset_val;
+            end 
+         if (C_USE_DOUT_RST == 1) begin
+           // @(posedge CLK)
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+         end
+         end else begin
+            if (ram_rd_en_d1 ) begin
+            ideal_dout_d1 <= #`TCQ ideal_dout;
+            err_type_d1   <= #`TCQ err_type;
+            end
+         end
+      end    
+   end   // always
+end
+endgenerate 
+
+//no safety ckt with both registers
+ generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
+   always @(posedge CLK or posedge rst_i) begin
+      if (rst_i == 1'b1) begin
+          ram_rd_en_d1 <= #`TCQ 1'b0;
+          fab_rd_en_d1 <= #`TCQ 1'b0;
+         // Reset err_type only if ECC is not selected
+         if (C_USE_ECC == 0) begin
+            err_type_d1      <= #`TCQ 0;
+            err_type_both    <= #`TCQ 0;
+         end
+         // DRAM and SRAM reset asynchronously
+         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+            ideal_dout_both <= #`TCQ dout_reset_val; 
+            
+      end
+        if (C_USE_DOUT_RST == 1) begin
+            @(posedge CLK)
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+            ideal_dout_both <= #`TCQ dout_reset_val;
+       end
+      end else begin
+         if (srst_rrst_busy) begin 
+           ram_rd_en_d1 <= #`TCQ 1'b0;
+           fab_rd_en_d1 <= #`TCQ 1'b0;
+           // Reset err_type only if ECC is not selected
+           if (C_USE_ECC == 0) begin
+              err_type_d1   <= #`TCQ 0;
+              err_type_both <= #`TCQ 0;
+           end
+           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
+           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+              ideal_dout_d1 <= #`TCQ dout_reset_val;
+           end 
+           if (C_USE_DOUT_RST == 1) begin
+             ideal_dout_d1 <= #`TCQ dout_reset_val;
+           end
+         end else begin
+           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
+           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
+           if (ram_rd_en_d1 ) begin
+             ideal_dout_both <= #`TCQ ideal_dout;
+             err_type_both   <= #`TCQ err_type;
+           end
+           if (fab_rd_en_d1 ) begin
+             ideal_dout_d1 <= #`TCQ ideal_dout_both;
+             err_type_d1   <= #`TCQ err_type_both;
+           end
+         end
+      end    
+   end   // always
+end
+endgenerate 
+   /**************************************************************************
+    * Overflow and Underflow Flag calculation
+    *  (handled separately because they don't support rst)
+    **************************************************************************/
+   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
+     always @(posedge CLK) begin
+       ideal_overflow    <= #`TCQ WR_EN & full_i;
+     end
+   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
+     always @(posedge CLK) begin
+       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);
+       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
+     end
+   end endgenerate // blockOF20
+ 
+   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
+     always @(posedge CLK) begin
+       ideal_underflow   <= #`TCQ empty_i & RD_EN;
+     end
+   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
+     always @(posedge CLK) begin
+       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;
+       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
+     end
+   end endgenerate // blockUF20
+
+
+   /**************************
+    * Read Data Count
+    *************************/
+
+   reg [31:0] num_read_words_dc;
+   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
+   
+   always @(num_rd_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //If using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain, 
+        // and add two read words for FWFT stages
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //If not using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain.
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+   
+   /**************************
+    * Write Data Count
+    *************************/
+
+   reg [31:0] num_write_words_dc;
+   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
+   
+   always @(num_wr_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //Calculate the Data Count value for the number of write words, 
+        // when using First-Word Fall-Through with extra logic for Data 
+        // Counts. This takes into consideration the number of words that 
+        // are expected to be stored in the FWFT register stages (it always 
+        // assumes they are filled).
+        //This value is scaled to the Write Domain.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //EXTRA_WORDS_DC is the number of words added to write_words 
+        // due to FWFT.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
+        
+        //Trim the write words for use with WR_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //Calculate the Data Count value for the number of write words, when NOT
+        // using First-Word Fall-Through with extra logic for Data Counts. This 
+        // calculates only the number of words in the internal FIFO.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //This value is scaled to the Write Domain.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+
+  /*************************************************************************
+   * Write and Read Logic  
+   ************************************************************************/
+   wire              write_allow;
+   wire              read_allow;
+   wire              read_allow_dc;
+   wire              write_only;
+   wire              read_only;
+   //wire              write_only_q;
+   reg              write_only_q;
+   //wire              read_only_q;
+   reg              read_only_q;
+   reg              full_reg;
+   reg              rst_full_ff_reg1;
+   reg              rst_full_ff_reg2;
+   wire              ram_full_comb;
+   wire              carry;
+   
+   assign write_allow  = WR_EN & ~full_i;
+   assign read_allow   = RD_EN & ~empty_i;
+   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
+   //assign write_only   = write_allow & ~read_allow;
+   //assign write_only_q = write_allow_q;
+   //assign read_only    = read_allow    & ~write_allow;
+   //assign read_only_q  = read_allow_q ;
+   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
+   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
+   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
+   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
+   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
+   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
+   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
+   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
+
+   assign diff_pntr_pe_max = DIFF_MAX_RD;
+   assign diff_pntr_max = DIFF_MAX_WR;
+
+
+
+   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
+    assign write_only   = write_allow & ~read_allow;
+    assign read_only    = read_allow    & ~write_allow;
+    end endgenerate
+    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
+     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
+     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
+    end endgenerate
+    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
+     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
+     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
+    end endgenerate
+
+
+   //-----------------------------------------------------------------------------
+   // Write and Read pointer generation
+   //-----------------------------------------------------------------------------
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i && C_EN_SAFETY_CKT == 0) begin
+       wr_pntr         <= 0;
+       rd_pntr         <= 0;
+     end else begin
+       if (srst_i) begin
+         wr_pntr       <= #`TCQ 0;
+         rd_pntr       <= #`TCQ 0;
+       end else begin
+         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
+         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;
+       end
+     end
+   end
+
+   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
+   always @(posedge CLK) begin
+     if (write_allow) begin
+       if (ENABLE_ERR_INJECTION == 1)
+         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
+       else
+         memory[wr_pntr] <= #`TCQ DIN;
+     end
+   end
+
+   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;
+   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
+   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
+   always @(posedge CLK) begin
+     dout_tmp_q <= #`TCQ ideal_dout;
+   end
+
+
+
+     always @* begin
+       if (read_allow)
+         ideal_dout <= memory[rd_pntr];
+       else
+         ideal_dout <= dout_tmp_q;
+     end
+   end endgenerate // gll_dm_dout
+
+
+   /**************************************************************************
+   * Write Domain Logic
+   **************************************************************************/
+   assign ram_rd_en        = RD_EN & !EMPTY;
+
+   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
+   generate if (C_FIFO_TYPE != 2) begin : gnll_din
+   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rst_i == 1'b1) begin
+       num_wr_bits       <= #`TCQ 0;
+       next_num_wr_bits   = #`TCQ 0;
+       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;
+       ideal_wr_ack      <= #`TCQ 0;
+       ideal_wr_count    <= #`TCQ 0;
+       tmp_wr_listsize    = #`TCQ 0;
+       rd_ptr_wrclk_next <= #`TCQ 0;
+       wr_pntr           <= #`TCQ 0;
+       wr_pntr_rd1       <= #`TCQ 0;
+
+     end else begin //rst_i==0
+     if (srst_wrst_busy) begin
+       num_wr_bits       <= #`TCQ 0;
+       next_num_wr_bits   = #`TCQ 0;
+       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;
+       ideal_wr_ack      <= #`TCQ 0;
+       ideal_wr_count    <= #`TCQ 0;
+       tmp_wr_listsize    = #`TCQ 0;
+       rd_ptr_wrclk_next <= #`TCQ 0;
+       wr_pntr           <= #`TCQ 0;
+       wr_pntr_rd1       <= #`TCQ 0;
+     end else begin//srst_i=0
+
+       wr_pntr_rd1   <= #`TCQ wr_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
+                         num_wr_bits/C_DIN_WIDTH;
+       rd_ptr_wrclk_next = rd_ptr;
+       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
+                                          - rd_ptr_wrclk_next);
+       end else begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
+       end
+
+       if (WR_EN == 1'b1) begin
+         if (FULL == 1'b1) begin
+
+             ideal_wr_ack      <= #`TCQ 0;
+             //Reminder that FIFO is still full
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+         end else begin
+             write_fifo;
+             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error  
+             ideal_wr_ack      <= #`TCQ 1;
+             //Not even close to full.
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           //end
+
+         end
+
+       end else begin //(WR_EN == 1'b1)
+
+         //If user did not attempt a write, then do not
+         // give ack or err
+         ideal_wr_ack   <= #`TCQ 0;
+         ideal_wr_count <= #`TCQ num_write_words_sized_i;
+       end
+       num_wr_bits       <= #`TCQ next_num_wr_bits;
+       rd_ptr_wrclk      <= #`TCQ rd_ptr;
+
+     end //srst_i==0
+     end //wr_rst_i==0
+   end // gen_fifo_w
+    end endgenerate
+
+   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
+     always @(posedge CLK) begin
+       if (rst_i || srst_rrst_busy) begin
+         if (C_USE_DOUT_RST == 1) begin
+           ideal_dout <= #`TCQ dout_reset_val;
+           ideal_dout_both <= #`TCQ dout_reset_val;
+         end
+       end
+     end
+    end endgenerate
+
+
+
+
+   generate if (C_FIFO_TYPE != 2) begin : gnll_dout
+   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rst_i) begin
+       num_rd_bits        <= #`TCQ 0;
+       next_num_rd_bits    = #`TCQ 0;
+       rd_ptr             <= #`TCQ C_RD_DEPTH -1;
+       rd_pntr            <= #`TCQ 0;
+       //rd_pntr_wr1       <= #`TCQ 0;
+       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;
+  
+       // DRAM resets asynchronously
+       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
+          ideal_dout    <= #`TCQ dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= #`TCQ 0;
+         err_type_d1      <= 0;
+         err_type_both    <= 0;
+       end
+       ideal_valid        <= #`TCQ 1'b0;
+       ideal_rd_count     <= #`TCQ 0;
+
+     end else begin //rd_rst_i==0
+     if (srst_rrst_busy) begin
+       num_rd_bits        <= #`TCQ 0;
+       next_num_rd_bits    = #`TCQ 0;
+       rd_ptr             <= #`TCQ C_RD_DEPTH -1;
+       rd_pntr            <= #`TCQ 0;
+       //rd_pntr_wr1       <= #`TCQ 0;
+       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;
+  
+       // DRAM resets synchronously
+       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
+          ideal_dout    <= #`TCQ dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= #`TCQ 0;
+         err_type_d1      <= #`TCQ 0;
+         err_type_both    <= #`TCQ 0;
+       end
+       ideal_valid        <= #`TCQ 1'b0;
+       ideal_rd_count     <= #`TCQ 0;
+      end //srst_i
+      else begin
+
+       //rd_pntr_wr1   <= #`TCQ rd_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
+                         num_rd_bits/C_DOUT_WIDTH;
+       wr_ptr_rdclk_next = wr_ptr;
+
+       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
+         next_num_rd_bits = num_rd_bits +
+                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
+                                         - wr_ptr_rdclk_next);
+       end else begin
+         next_num_rd_bits = num_rd_bits +
+                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
+       end
+
+         if (RD_EN == 1'b1) begin
+
+           if (EMPTY == 1'b1) begin
+                 ideal_valid        <= #`TCQ 1'b0;
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+               end 
+           else 
+             begin
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1'b1;
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 2)
+         end
+
+       num_rd_bits      <= #`TCQ next_num_rd_bits;
+       wr_ptr_rdclk     <= #`TCQ wr_ptr;
+     end //s_rst_i==0
+     end //rd_rst_i==0
+   end //always
+  end endgenerate
+
+   //-----------------------------------------------------------------------------
+   // Generate diff_pntr for PROG_FULL generation
+   // Generate diff_pntr_pe for PROG_EMPTY generation
+   //-----------------------------------------------------------------------------
+   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
+     always @(posedge CLK ) begin
+       if (rst_i) begin
+         write_only_q   <= 1'b0;
+         read_only_q    <= 1'b0;
+         diff_pntr_reg1       <= 0;
+         diff_pntr_pe_reg1    <= 0;
+         diff_pntr_reg2       <= 0;
+         diff_pntr_pe_reg2    <= 0;
+       end else begin
+         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
+          if (srst_rrst_busy) begin
+           read_only_q  <= #`TCQ 1'b0;
+           diff_pntr_pe_reg1  <= #`TCQ 0;
+           diff_pntr_pe_reg2  <= #`TCQ 0;
+          end
+          if (srst_wrst_busy) begin
+           write_only_q <= #`TCQ 1'b0;
+           diff_pntr_reg1     <= #`TCQ 0;
+           diff_pntr_reg2     <= #`TCQ 0;
+          end
+         end else begin
+           write_only_q <= #`TCQ write_only;
+           read_only_q  <= #`TCQ read_only;
+           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;
+           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;
+
+           // Add 1 to the difference pointer value when only write happens.
+           if (write_only)  
+             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
+           else
+             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
+
+           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.
+           if (read_only)  
+             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
+           else
+             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
+         end
+       end
+     end
+   assign diff_pntr_pe = diff_pntr_pe_reg1;
+   assign diff_pntr = diff_pntr_reg1;
+   end endgenerate // reg_write_allow
+
+   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
+    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
+    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
+     always @(posedge CLK ) begin
+       if (rst_i) begin
+         diff_pntr_pe_asym    <= 0;
+         diff_pntr_reg1       <= 0;
+         full_reg             <= 0;
+         rst_full_ff_reg1     <= 1;
+         rst_full_ff_reg2     <= 1;
+         diff_pntr_pe_reg1    <= 0;
+       end else begin
+         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
+          if (srst_wrst_busy)
+           diff_pntr_reg1     <= #`TCQ 0;
+          if (srst_rrst_busy)
+           full_reg             <=  #`TCQ 0;
+           rst_full_ff_reg1     <=  #`TCQ 1;
+           rst_full_ff_reg2     <=  #`TCQ 1;
+           diff_pntr_pe_asym    <=  #`TCQ 0;
+           diff_pntr_pe_reg1  <= #`TCQ 0;
+         end else begin
+             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
+             full_reg          <= #`TCQ full_i;
+             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;
+             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;
+           if (~full_i) begin  
+             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;
+          end
+         end
+       end
+     end
+   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
+   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
+   assign diff_pntr = diff_pntr_reg1;
+   end endgenerate // reg_write_allow_asym
+
+
+   //-----------------------------------------------------------------------------
+   // Generate FULL flag
+   //-----------------------------------------------------------------------------
+   wire                 comp0;
+   wire                 comp1;
+   wire                 going_full;
+   wire                 leaving_full;
+ 
+ generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad 	
+    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
+    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
+  end endgenerate
+
+  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim 
+    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+  end endgenerate
+
+   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
+   assign comp0         = (adj_rd_pntr_wr == wr_pntr);
+
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
+     assign going_full    = (comp1 & write_allow & ~read_allow);
+     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;
+    end endgenerate
+
+    // Write data width is bigger than read data width
+    // Write depth is smaller than read depth
+    // One write could be equal to 2 or 4 or 8 reads
+    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
+      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
+      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp 
+      assign going_full = (comp1 & write_allow & ~read_allow);
+      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
+    end endgenerate
+
+
+   assign ram_full_comb = going_full | (~leaving_full & full_i);
+
+   generate if (C_HAS_RST == 1) begin : grst_full
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       if (RST_FULL_FF & C_HAS_RST)
+         full_i   <= C_FULL_FLAGS_RST_VAL;
+       else
+         full_i   <= #`TCQ ram_full_comb;
+      end
+   end endgenerate
+
+   generate if (C_HAS_SRST == 1) begin : gsrst_full
+     always @(posedge CLK) begin
+       if (srst_wrst_busy)
+         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else
+         full_i   <= #`TCQ ram_full_comb;
+      end
+   end endgenerate
+
+   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full
+     always @(posedge CLK) begin
+         full_i   <= #`TCQ ram_full_comb;
+     end
+   end endgenerate
+
+   //-----------------------------------------------------------------------------
+   // Generate EMPTY flag
+   //-----------------------------------------------------------------------------
+   wire                 ecomp0;
+   wire                 ecomp1;
+   wire                 going_empty;
+   wire                 leaving_empty;
+   wire                 ram_empty_comb;
+
+  
+ generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad 	
+    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
+    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
+  end endgenerate
+
+  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim 
+    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+  end endgenerate
+
+   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
+   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);
+
+
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
+     assign going_empty    = (ecomp1 & ~write_allow & read_allow);
+     assign leaving_empty  = (ecomp0 & write_allow);
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
+      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
+      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
+    end endgenerate
+  
+   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp 
+      assign going_empty = (ecomp1 & ~write_allow & read_allow);
+      assign leaving_empty =(ecomp0 & write_allow);
+    end endgenerate
+
+
+
+    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
+
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i)
+       empty_i  <= 1'b1;
+     else if (srst_rrst_busy)
+       empty_i  <= #`TCQ 1'b1;
+     else
+       empty_i  <= #`TCQ ram_empty_comb;
+    end
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i && C_EN_SAFETY_CKT == 0) begin
+       EMPTY_FB     <= 1'b1;
+     end else begin
+       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
+         EMPTY_FB   <= #`TCQ 1'b1;
+       else
+         EMPTY_FB   <= #`TCQ ram_empty_comb;
+     end
+   end // always
+
+   //-----------------------------------------------------------------------------
+   // Generate Read and write data counts for asymmetic common clock
+   //-----------------------------------------------------------------------------
+
+    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; 
+    wire [C_GRTR_PNTR_WIDTH :0] ratio; 
+    wire decr_by_one;
+    wire incr_by_ratio;
+    wire incr_by_one;
+    wire decr_by_ratio;
+
+   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
+
+   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr 
+      assign ratio         = C_DEPTH_RATIO_RD;
+      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;
+      assign incr_by_ratio = write_allow;
+
+      always @(posedge CLK or posedge rst_i) begin
+       if (rst_i)
+         count_dc  <= #`TCQ 0;
+       else if (srst_wrst_busy)
+         count_dc  <= #`TCQ 0;
+       else begin
+	 if (decr_by_one) begin
+	   if (!incr_by_ratio) 
+            count_dc <= #`TCQ count_dc - 1;
+           else
+	    count_dc <= #`TCQ count_dc - 1  + ratio ;
+	 end
+	 else begin
+	   if (!incr_by_ratio) 
+            count_dc <= #`TCQ count_dc ;
+           else
+	    count_dc <= #`TCQ count_dc + ratio ;
+	end
+       end
+       end
+
+       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
+       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+
+    end endgenerate
+
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd 
+      assign ratio         = C_DEPTH_RATIO_WR;
+      assign incr_by_one   = write_allow;
+      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
+
+      always @(posedge CLK or posedge rst_i) begin
+       if (rst_i)
+         count_dc  <= #`TCQ 0;
+       else if (srst_wrst_busy)
+         count_dc  <= #`TCQ 0;
+       else begin
+	 if (incr_by_one) begin
+	   if (!decr_by_ratio) 
+            count_dc <= #`TCQ count_dc + 1;
+           else
+	    count_dc <= #`TCQ count_dc + 1  - ratio ;
+	 end
+	 else begin
+	   if (!decr_by_ratio) 
+            count_dc <= #`TCQ count_dc ;
+           else
+	    count_dc <= #`TCQ count_dc - ratio ;
+	end
+       end
+       end
+
+       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
+       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+
+    end endgenerate
+
+
+
+
+
+
+   //-----------------------------------------------------------------------------
+   // Generate WR_ACK flag
+   //-----------------------------------------------------------------------------
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i)
+       ideal_wr_ack  <= 1'b0;
+     else if (srst_wrst_busy)
+       ideal_wr_ack  <= #`TCQ 1'b0;
+     else if (WR_EN & ~full_i)
+       ideal_wr_ack  <= #`TCQ 1'b1;
+     else
+       ideal_wr_ack  <= #`TCQ 1'b0;
+    end
+
+   //-----------------------------------------------------------------------------
+   // Generate VALID flag
+   //-----------------------------------------------------------------------------
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i)
+       ideal_valid  <= 1'b0;
+     else if (srst_rrst_busy)
+       ideal_valid  <= #`TCQ 1'b0;
+     else if (RD_EN & ~empty_i)
+       ideal_valid  <= #`TCQ 1'b1;
+     else
+       ideal_valid  <= #`TCQ 1'b0;
+    end
+
+
+   //-----------------------------------------------------------------------------
+   // Generate ALMOST_FULL flag
+   //-----------------------------------------------------------------------------
+   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
+
+     wire                 fcomp2;
+     wire                 going_afull;
+     wire                 leaving_afull;
+     wire                 ram_afull_comb;
+
+
+   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
+
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
+     assign going_afull    = (fcomp2 & write_allow & ~read_allow);
+     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
+    end endgenerate
+
+    // Write data width is bigger than read data width
+    // Write depth is smaller than read depth
+    // One write could be equal to 2 or 4 or 8 reads
+    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
+      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
+      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp 
+      assign going_afull = (fcomp2 & write_allow & ~read_allow);
+      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
+    end endgenerate
+
+     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);
+
+
+    generate if (C_HAS_RST == 1) begin : grst_afull
+      always @(posedge CLK or posedge RST_FULL_FF) begin
+        if (RST_FULL_FF & C_HAS_RST)
+          almost_full_i   <= C_FULL_FLAGS_RST_VAL;
+        else
+          almost_full_i   <= #`TCQ ram_afull_comb;
+       end
+    end endgenerate
+
+    generate if (C_HAS_SRST == 1) begin : gsrst_afull
+      always @(posedge CLK) begin
+        if (srst_wrst_busy)
+          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;
+        else
+          almost_full_i   <= #`TCQ ram_afull_comb;
+       end
+    end endgenerate
+
+    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull
+      always @(posedge CLK) begin
+          almost_full_i   <= #`TCQ ram_afull_comb;
+      end
+    end endgenerate
+
+   //-----------------------------------------------------------------------------
+   // Generate ALMOST_EMPTY flag
+   //-----------------------------------------------------------------------------
+   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
+
+     wire                 ecomp2;
+     wire                 going_aempty;
+     wire                 leaving_aempty;
+     wire                 ram_aempty_comb;
+      
+     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
+   
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
+     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);
+     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
+      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
+      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
+    end endgenerate
+  
+   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp 
+      assign going_aempty = (ecomp2 & ~write_allow & read_allow);
+      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
+    end endgenerate
+
+
+     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
+
+     always @(posedge CLK or posedge rst_i) begin
+       if (rst_i)
+         almost_empty_i  <= 1'b1;
+       else if (srst_rrst_busy)
+         almost_empty_i  <= #`TCQ 1'b1;
+       else
+         almost_empty_i  <= #`TCQ ram_aempty_comb;
+      end
+  // end endgenerate // gae_ss
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL
+   //-----------------------------------------------------------------------------
+
+   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? 
+                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT 
+                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD
+   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? 
+                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
+                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for single programmable threshold constant
+   //-----------------------------------------------------------------------------
+   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   
+   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin 
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (RST_FULL_GEN)
+          prog_full_i <= #`TCQ 1'b0;
+         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
+           prog_full_i <= #`TCQ 1'b1;
+         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
+           prog_full_i <= #`TCQ 1'b0;
+         else
+           prog_full_i <= #`TCQ prog_full_i;
+       end
+       else begin
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1'b0;
+       else if (~RST_FULL_GEN ) begin 
+        if (diff_pntr>= C_PF_ASSERT_VAL )
+          prog_full_i <= #`TCQ 1'b1;
+        else if  ((diff_pntr) < C_PF_ASSERT_VAL )
+        prog_full_i <= #`TCQ 1'b0;
+       else
+         prog_full_i <= #`TCQ 1'b0;
+        end 
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+       end
+      end
+     end
+   end endgenerate // single_pf_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for multiple programmable threshold constants
+   //-----------------------------------------------------------------------------
+   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       //if (RST_FULL_FF)
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (RST_FULL_GEN)
+           prog_full_i <= #`TCQ 1'b0;
+         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
+           prog_full_i <= #`TCQ 1'b1;
+         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
+           prog_full_i <= #`TCQ 1'b0;
+         else
+           prog_full_i <= #`TCQ prog_full_i;
+       end
+       else begin
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1'b0;
+       else if (~RST_FULL_GEN ) begin 
+        if (diff_pntr >= C_PF_ASSERT_VAL )
+          prog_full_i <= #`TCQ 1'b1;
+       else if  (diff_pntr < C_PF_NEGATE_VAL)
+         prog_full_i <= #`TCQ 1'b0;
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+        end 
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+       end
+      end
+     end
+   end endgenerate //multiple_pf_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for single programmable threshold input port
+   //-----------------------------------------------------------------------------
+   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? 
+                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
+                                               PROG_FULL_THRESH; // STD
+   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
+
+     always @(posedge CLK or posedge RST_FULL_FF) begin//0
+       //if (RST_FULL_FF)
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin //1
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin//2 
+         if (RST_FULL_GEN)
+           prog_full_i <= #`TCQ 1'b0;
+         else if (~almost_full_i) begin//3
+           if (diff_pntr > pf3_assert_val)
+             prog_full_i <= #`TCQ 1'b1;
+           else if (diff_pntr == pf3_assert_val) begin//4
+             if (read_only_q)
+               prog_full_i <= #`TCQ 1'b0;
+             else
+               prog_full_i <= #`TCQ 1'b1;
+           end else//4
+             prog_full_i <= #`TCQ 1'b0;
+         end else//3
+           prog_full_i <= #`TCQ prog_full_i;
+       end //2
+       else begin//5
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1'b0;
+       else if (~full_i ) begin//6 
+        if (diff_pntr >= pf3_assert_val )
+          prog_full_i <= #`TCQ 1'b1;
+        else if  (diff_pntr < pf3_assert_val) begin//7
+         prog_full_i <= #`TCQ 1'b0;
+       end//7
+       end//6
+      else
+           prog_full_i <= #`TCQ prog_full_i;
+       end//5
+     end//1
+     end//0
+   end endgenerate //single_pf_input
+  
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for multiple programmable threshold input ports
+   //-----------------------------------------------------------------------------
+   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? 
+                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
+                                               PROG_FULL_THRESH_ASSERT; // STD
+   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? 
+                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
+                                               PROG_FULL_THRESH_NEGATE; // STD
+
+   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (RST_FULL_GEN)
+           prog_full_i <= #`TCQ 1'b0;
+         else if (~almost_full_i) begin
+           if (diff_pntr >= pf_assert_val)
+             prog_full_i <= #`TCQ 1'b1;
+           else if ((diff_pntr == pf_negate_val && read_only_q) ||
+                  diff_pntr < pf_negate_val)
+             prog_full_i <= #`TCQ 1'b0;
+           else
+             prog_full_i <= #`TCQ prog_full_i;
+         end else
+           prog_full_i <= #`TCQ prog_full_i;
+       end
+       else begin
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1'b0;
+       else if (~full_i ) begin 
+        if (diff_pntr >= pf_assert_val )
+          prog_full_i <= #`TCQ 1'b1;
+       else if (diff_pntr < pf_negate_val) 
+         prog_full_i <= #`TCQ 1'b0;
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+        end 
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+       end
+
+     end
+   end
+   end endgenerate //multiple_pf_inputs
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY
+   //-----------------------------------------------------------------------------
+   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
+                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
+                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
+   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
+                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
+                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for single programmable threshold constant
+   //-----------------------------------------------------------------------------
+   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i) 
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1'b1;
+       else begin
+         if (srst_rrst_busy) 
+           prog_empty_i <= #`TCQ 1'b1;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
+           prog_empty_i <= #`TCQ 1'b1;
+         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
+           prog_empty_i <= #`TCQ 1'b0;
+         else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+       if (~rst_i ) begin 
+        if (diff_pntr_pe <= C_PE_ASSERT_VAL)
+          prog_empty_i <= #`TCQ 1'b1;
+        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)
+         prog_empty_i <= #`TCQ 1'b0;
+        end 
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+       end
+     end
+     end
+   end endgenerate // single_pe_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for multiple programmable threshold constants
+   //-----------------------------------------------------------------------------
+   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i)
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1'b1;
+       else begin
+         if (srst_rrst_busy)
+           prog_empty_i <= #`TCQ 1'b1;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
+           prog_empty_i <= #`TCQ 1'b1;
+         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
+           prog_empty_i <= #`TCQ 1'b0;
+         else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+       if (~rst_i ) begin 
+        if (diff_pntr_pe <= C_PE_ASSERT_VAL )
+          prog_empty_i <= #`TCQ 1'b1;
+        else if (diff_pntr_pe > C_PE_NEGATE_VAL) 
+         prog_empty_i <= #`TCQ 1'b0;
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+        end 
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+       end
+
+     end
+
+     end
+   end endgenerate //multiple_pe_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for single programmable threshold input port
+   //-----------------------------------------------------------------------------
+   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
+                                               (PROG_EMPTY_THRESH -2) : // FWFT
+                                                PROG_EMPTY_THRESH; // STD
+   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i)
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1'b1;
+       else begin
+         if (srst_rrst_busy)
+           prog_empty_i <= #`TCQ 1'b1;
+       else if (IS_ASYMMETRY == 0) begin 
+          if (~almost_full_i) begin
+           if (diff_pntr_pe < pe3_assert_val)
+             prog_empty_i <= #`TCQ 1'b1;
+           else if (diff_pntr_pe == pe3_assert_val) begin
+             if (write_only_q)
+               prog_empty_i <= #`TCQ 1'b0;
+             else
+               prog_empty_i <= #`TCQ 1'b1;
+           end else
+             prog_empty_i <= #`TCQ 1'b0;
+         end else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+        if (diff_pntr_pe <= pe3_assert_val )
+          prog_empty_i <= #`TCQ 1'b1;
+        else if  (diff_pntr_pe > pe3_assert_val)
+         prog_empty_i <= #`TCQ 1'b0;
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+        end 
+     end
+
+     end
+   end endgenerate // single_pe_input
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for multiple programmable threshold input ports
+   //-----------------------------------------------------------------------------
+   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
+                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
+                                                PROG_EMPTY_THRESH_ASSERT; // STD
+   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
+                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
+                                                PROG_EMPTY_THRESH_NEGATE; // STD
+   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i)
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1'b1;
+       else begin
+         if (srst_rrst_busy)
+           prog_empty_i <= #`TCQ 1'b1;
+      else if (IS_ASYMMETRY == 0) begin 
+          if (~almost_full_i) begin
+           if (diff_pntr_pe <= pe4_assert_val)
+             prog_empty_i <= #`TCQ 1'b1;
+           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || 
+                     (diff_pntr_pe > pe4_negate_val)) begin
+             prog_empty_i <= #`TCQ 1'b0;
+           end else
+             prog_empty_i <= #`TCQ prog_empty_i;
+         end else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+        if (diff_pntr_pe <= pe4_assert_val )
+          prog_empty_i <= #`TCQ 1'b1;
+        else if (diff_pntr_pe > pe4_negate_val) 
+         prog_empty_i <= #`TCQ 1'b0;
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+        end 
+     end
+     end
+   end endgenerate // multiple_pe_inputs
+
+endmodule // fifo_generator_v13_2_5_bhv_ver_ss
+
+
+
+/**************************************************************************
+ * First-Word Fall-Through module (preload 0)
+ **************************************************************************/
+module fifo_generator_v13_2_5_bhv_ver_preload0
+  #(
+    parameter  C_DOUT_RST_VAL            = "",
+    parameter  C_DOUT_WIDTH              = 8,
+    parameter  C_HAS_RST                 = 0,
+    parameter  C_ENABLE_RST_SYNC         = 0,
+    parameter  C_HAS_SRST                = 0,
+    parameter  C_USE_EMBEDDED_REG        = 0,
+    parameter  C_EN_SAFETY_CKT           = 0, 
+    parameter  C_USE_DOUT_RST            = 0,
+    parameter  C_USE_ECC                 = 0,
+    parameter  C_USERVALID_LOW           = 0,
+    parameter  C_USERUNDERFLOW_LOW       = 0,
+    parameter  C_MEMORY_TYPE             = 0,
+    parameter  C_FIFO_TYPE               = 0
+  )
+  (
+    //Inputs
+    input                          SAFETY_CKT_RD_RST,
+    input                          RD_CLK,
+    input                          RD_RST,
+    input                          SRST,
+    input                          WR_RST_BUSY,
+    input                          RD_RST_BUSY,
+    input                          RD_EN,
+    input                          FIFOEMPTY,
+    input       [C_DOUT_WIDTH-1:0] FIFODATA,
+    input                          FIFOSBITERR,
+    input                          FIFODBITERR,
+   
+    //Outputs
+    output reg  [C_DOUT_WIDTH-1:0] USERDATA,
+    output                         USERVALID,
+    output                         USERUNDERFLOW,
+    output                         USEREMPTY,
+    output                         USERALMOSTEMPTY,
+    output                         RAMVALID,
+    output                         FIFORDEN,
+    output reg                     USERSBITERR,
+    output reg                     USERDBITERR,
+    output reg                     STAGE2_REG_EN,
+    output                         fab_read_data_valid_i_o,
+    output                         read_data_valid_i_o,
+    output                         ram_valid_i_o,
+    output      [1:0]              VALID_STAGES 
+  );
+ //Internal signals
+ wire                      preloadstage1;
+ wire                      preloadstage2;
+ reg                       ram_valid_i;
+ reg                       fab_valid;
+ reg                       read_data_valid_i;
+ reg                       fab_read_data_valid_i;
+ reg                       fab_read_data_valid_i_1;
+ reg                       ram_valid_i_d;
+ reg                       read_data_valid_i_d;
+ reg                       fab_read_data_valid_i_d;
+ wire                      ram_regout_en;
+ reg                       ram_regout_en_d1;
+ reg                       ram_regout_en_d2;
+ wire                      fab_regout_en;
+ wire                      ram_rd_en;
+ reg                       empty_i        = 1'b1;
+ reg                       empty_sckt     = 1'b1;
+ reg                       sckt_rrst_q    = 1'b0;
+ reg                       sckt_rrst_done = 1'b0;
+ reg                       empty_q        = 1'b1;
+ reg                       rd_en_q        = 1'b0;
+ reg                       almost_empty_i = 1'b1;
+ reg                       almost_empty_q = 1'b1;
+ wire                      rd_rst_i;
+ wire                      srst_i;
+ reg  [C_DOUT_WIDTH-1:0]   userdata_both;
+ wire                      uservalid_both;
+ wire                      uservalid_one;
+ reg                       user_sbiterr_both = 1'b0;
+ reg                       user_dbiterr_both = 1'b0;
+  
+assign ram_valid_i_o = ram_valid_i;
+assign read_data_valid_i_o = read_data_valid_i;
+assign fab_read_data_valid_i_o = fab_read_data_valid_i; 
+
+
+
+/*************************************************************************
+* FUNCTIONS
+*************************************************************************/
+
+   /*************************************************************************
+    * hexstr_conv
+    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+    ***********************************************************************/
+    function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+   
+   //*************************************************************************
+   //  Set power-on states for regs
+   //*************************************************************************
+   initial begin
+      ram_valid_i       = 1'b0;
+      fab_valid         = 1'b0;
+      read_data_valid_i = 1'b0;
+      fab_read_data_valid_i = 1'b0;
+      fab_read_data_valid_i_1 = 1'b0;
+      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);
+      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);
+      USERSBITERR       = 1'b0;
+      USERDBITERR       = 1'b0;
+      user_sbiterr_both = 1'b0;
+      user_dbiterr_both = 1'b0;
+   end //initial
+
+   //***************************************************************************
+   //  connect up optional reset
+   //***************************************************************************
+   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
+   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
+
+   reg  sckt_rd_rst_fwft = 1'b0;
+   reg  fwft_rst_done_i  = 1'b0;
+   wire fwft_rst_done;
+   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
+   always @ (posedge RD_CLK) begin
+     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
+   end
+
+   always @ (posedge rd_rst_i or posedge RD_CLK) begin
+     if (rd_rst_i)
+       fwft_rst_done_i  <= 1'b0;
+     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
+       fwft_rst_done_i  <= #`TCQ 1'b1;
+   end
+
+   localparam INVALID             = 0;
+   localparam STAGE1_VALID        = 2;
+   localparam STAGE2_VALID        = 1;
+   localparam BOTH_STAGES_VALID   = 3;
+
+   reg  [1:0] curr_fwft_state = INVALID;
+   reg  [1:0] next_fwft_state = INVALID;
+
+
+generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
+         always @* begin
+         case (curr_fwft_state)
+            INVALID: begin
+               if (~FIFOEMPTY)
+                  next_fwft_state     <= STAGE1_VALID;
+               else
+                  next_fwft_state     <= INVALID;
+               end
+            STAGE1_VALID: begin
+               if (FIFOEMPTY)
+                  next_fwft_state     <= STAGE2_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            STAGE2_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= INVALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE1_VALID;
+               else if (~FIFOEMPTY && ~RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= STAGE2_VALID;
+               end
+            BOTH_STAGES_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE2_VALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            default: next_fwft_state     <= INVALID;
+         endcase
+      end
+
+      always @ (posedge rd_rst_i or posedge RD_CLK) begin
+         if (rd_rst_i && C_EN_SAFETY_CKT == 0)
+            curr_fwft_state  <= INVALID;
+         else if (srst_i)
+            curr_fwft_state  <= #`TCQ INVALID;
+         else
+            curr_fwft_state  <= #`TCQ next_fwft_state;
+      end
+
+      always @* begin
+         case (curr_fwft_state)
+            INVALID:           STAGE2_REG_EN <= 1'b0;
+            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;
+            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;
+            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
+            default:           STAGE2_REG_EN <= 1'b0;
+         endcase
+      end
+
+ 
+    assign VALID_STAGES = curr_fwft_state;
+
+     //***************************************************************************
+     //  preloadstage2 indicates that stage2 needs to be updated. This is true
+     //  whenever read_data_valid is false, and RAM_valid is true.
+     //***************************************************************************
+     
+     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
+    
+
+     //***************************************************************************
+     //  preloadstage1 indicates that stage1 needs to be updated. This is true
+     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
+     //  false (indicating that Stage1 needs updating), or preloadstage2 is active
+     //  (indicating that Stage2 is going to update, so Stage1, therefore, must
+     //  also be updated to keep it valid.
+     //***************************************************************************
+     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
+  
+     //***************************************************************************
+     // Calculate RAM_REGOUT_EN
+     //  The output registers are controlled by the ram_regout_en signal.
+     //  These registers should be updated either when the output in Stage2 is
+     //  invalid (preloadstage2), OR when the user is reading, in which case the
+     //  Stage2 value will go invalid unless it is replenished.
+     //***************************************************************************
+     assign ram_regout_en = preloadstage2;
+
+     //***************************************************************************
+     // Calculate RAM_RD_EN
+     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
+     //  update the value in Stage1.
+     //   One case when this happens is when preloadstage1=true, which indicates
+     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically
+     //  be updated.
+     //   The other case is when the user is reading from the FIFO, which 
+     // guarantees that Stage1 or Stage2 will be invalid on the next clock 
+     // cycle, unless it is replinished by data from the memory. So, as long 
+     // as the RAM has data in it, a read of the RAM should occur.
+     //***************************************************************************
+     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
+   end
+endgenerate // gnll_fifo
+
+   reg curr_state         = 0;
+   reg next_state         = 0;
+   reg leaving_empty_fwft = 0;
+   reg going_empty_fwft   = 0;
+   reg empty_i_q          = 0;
+   reg ram_rd_en_fwft     = 0;
+   generate if (C_FIFO_TYPE == 2) begin : gll_fifo
+     always @* begin // FSM fo FWFT
+       case (curr_state)
+         1'b0: begin
+           if (~FIFOEMPTY)
+             next_state <= 1'b1;
+           else
+             next_state <= 1'b0;
+           end
+         1'b1: begin
+           if (FIFOEMPTY && RD_EN)
+             next_state <= 1'b0;
+           else
+             next_state <= 1'b1;
+           end
+         default: next_state <= 1'b0;
+       endcase
+     end
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           empty_i       <= 1'b1;
+           empty_i_q     <= 1'b1;
+           ram_valid_i   <= 1'b0;
+        end else if (srst_i) begin
+           empty_i       <= #`TCQ 1'b1;
+           empty_i_q     <= #`TCQ 1'b1;
+           ram_valid_i   <= #`TCQ 1'b0;
+        end else begin
+           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
+           empty_i_q     <= #`TCQ FIFOEMPTY;
+           ram_valid_i   <= #`TCQ next_state;
+        end
+     end //always
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
+           curr_state    <= 1'b0;
+        end else if (srst_i) begin
+           curr_state    <= #`TCQ 1'b0;
+        end else begin
+           curr_state    <= #`TCQ next_state;
+        end
+     end //always
+
+     wire                  fe_of_empty; 
+     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;
+
+     always @* begin // Finding leaving empty
+       case (curr_state)
+         1'b0:    leaving_empty_fwft <= fe_of_empty;
+         1'b1:    leaving_empty_fwft <= 1'b1;
+         default: leaving_empty_fwft <= 1'b0;
+       endcase
+     end
+
+     always @* begin // Finding going empty
+       case (curr_state)
+         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;
+         default: going_empty_fwft <= 1'b0;
+       endcase
+     end
+
+     always @* begin // Generating FWFT rd_en
+       case (curr_state)
+         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;
+         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
+         default: ram_rd_en_fwft <= 1'b0;
+       endcase
+     end
+
+     assign ram_regout_en = ram_rd_en_fwft;
+     //assign ram_regout_en_d1 = ram_rd_en_fwft;
+     //assign ram_regout_en_d2 = ram_rd_en_fwft;
+     assign ram_rd_en     = ram_rd_en_fwft;
+   end endgenerate // gll_fifo
+
+
+   //***************************************************************************
+   // Calculate RAMVALID_P0_OUT
+   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
+   //
+   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then
+   //   RAMVALID_P0_OUT is certainly going to be true.
+   //   If the RAM is not being read from, but the output registers are being
+   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
+   //   therefore causing RAMVALID_P0_OUT to be false.
+   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.
+   //***************************************************************************
+   // PROCESS regout_valid
+   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin  
+        if (rd_rst_i) begin 
+           // asynchronous reset (active high)
+           ram_valid_i     <= #`TCQ 1'b0;
+        end else begin
+           if (srst_i) begin 
+              // synchronous reset (active high)
+              ram_valid_i     <= #`TCQ 1'b0;
+           end else begin
+              if (ram_rd_en == 1'b1) begin
+                 ram_valid_i   <= #`TCQ 1'b1;
+              end else begin
+                 if (ram_regout_en == 1'b1)
+                   ram_valid_i <= #`TCQ 1'b0;
+                 else
+                   ram_valid_i <= #`TCQ ram_valid_i;
+              end
+           end //srst_i
+        end //rd_rst_i
+     end //always
+   end endgenerate // gnll_fifo_ram_valid
+   
+   //***************************************************************************
+   // Calculate READ_DATA_VALID
+   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
+   //  Stage2 has valid data whenever Stage1 had valid data and 
+   //  ram_regout_en_i=1, such that the data in Stage1 is propogated 
+   //  into Stage2.
+   //***************************************************************************
+  
+ generate if(C_USE_EMBEDDED_REG < 3) begin
+ always @ (posedge RD_CLK or posedge rd_rst_i) begin
+      if (rd_rst_i)
+        read_data_valid_i <= #`TCQ 1'b0;
+      else if (srst_i)
+        read_data_valid_i <= #`TCQ 1'b0;
+      else
+        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
+   end //always
+end 
+endgenerate
+
+   
+   
+   //**************************************************************************
+   // Calculate EMPTY
+   //  Defined as the inverse of READ_DATA_VALID
+   //
+   // Description:
+   //
+   //  If read_data_valid_i indicates that the output is not valid,
+   // and there is no valid data on the output of the ram to preload it
+   // with, then we will report empty.
+   //
+   //  If there is no valid data on the output of the ram and we are
+   // reading, then the FIFO will go empty.
+   //
+   //**************************************************************************
+   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           // asynchronous reset (active high)
+           empty_i <= #`TCQ 1'b1;
+        end else begin
+           if (srst_i) begin
+              // synchronous reset (active high)
+              empty_i <= #`TCQ 1'b1;
+           end else begin
+              // rising clock edge
+              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
+           end
+        end
+     end //always
+   end endgenerate // gnll_fifo_empty
+   
+   // Register RD_EN from user to calculate USERUNDERFLOW.
+   // Register empty_i to calculate USERUNDERFLOW.
+   always @ (posedge RD_CLK) begin
+     rd_en_q <= #`TCQ RD_EN;
+     empty_q <= #`TCQ empty_i;
+   end //always
+   
+   
+   //***************************************************************************
+   // Calculate user_almost_empty
+   //  user_almost_empty is defined such that, unless more words are written
+   //  to the FIFO, the next read will cause the FIFO to go EMPTY.
+   //
+   //  In most cases, whenever the output registers are updated (due to a user
+   // read or a preload condition), then user_almost_empty will update to
+   // whatever RAM_EMPTY is.
+   //
+   //  The exception is when the output is valid, the user is not reading, and
+   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the
+   // memory, so we need to make sure user_almost_empty deasserts properly under
+   // this condition.
+   //***************************************************************************
+ generate if ( C_USE_EMBEDDED_REG < 3) begin
+  always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin         // asynchronous reset (active high)
+             almost_empty_i <= #`TCQ 1'b1;
+             almost_empty_q <= #`TCQ 1'b1;
+        end else begin // rising clock edge
+           if (srst_i) begin          // synchronous reset (active high)
+              almost_empty_i <= #`TCQ 1'b1;
+              almost_empty_q <= #`TCQ 1'b1;
+           end else begin
+              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
+                 almost_empty_i <= #`TCQ FIFOEMPTY;
+              end
+              almost_empty_q   <= #`TCQ empty_i;
+           end
+        end
+     end //always
+end
+endgenerate
+   
+   
+     
+  // BRAM resets synchronously
+ generate 
+        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
+   always @ ( posedge rd_rst_i)
+     begin
+        if (rd_rst_i || srst_i) begin
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
+           @(posedge RD_CLK)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+        end
+     end //always
+
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin //asynchronous reset (active high)
+          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+            USERSBITERR    <= #`TCQ 0;
+            USERDBITERR    <= #`TCQ 0;
+          end
+          // DRAM resets asynchronously
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)
+             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+        end
+        end  else begin // rising clock edge
+          if (srst_i) begin
+            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+              USERSBITERR  <= #`TCQ 0;
+              USERDBITERR  <= #`TCQ 0;
+            end
+            if (C_USE_DOUT_RST == 1) begin
+              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+          end
+          end  else if (fwft_rst_done) begin
+            if (ram_regout_en) begin
+               USERDATA     <= #`TCQ FIFODATA;
+               USERSBITERR  <= #`TCQ FIFOSBITERR;
+               USERDBITERR  <= #`TCQ FIFODBITERR;
+            end
+          end
+        end
+     end //always
+   end   //if
+  endgenerate
+//safety ckt with one register
+generate
+       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge RD_CLK)
+          begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+          end
+        always @ (posedge RD_CLK)
+     begin
+        if (rd_rst_i || srst_i) begin
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
+            @(posedge RD_CLK)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+          end
+        end
+     end //always
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin //asynchronous reset (active high)
+          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+            USERSBITERR    <= #`TCQ 0;
+            USERDBITERR    <= #`TCQ 0;
+          end
+          // DRAM resets asynchronously
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)
+          //@(posedge RD_CLK)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         end 
+       end
+        else begin // rising clock edge
+          if (srst_i) begin
+            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+              USERSBITERR  <= #`TCQ 0;
+              USERDBITERR  <= #`TCQ 0;
+            end
+            if (C_USE_DOUT_RST == 1) begin
+            //  @(posedge RD_CLK)
+              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+          end
+          end else if (fwft_rst_done) begin
+            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
+               USERDATA     <= #`TCQ FIFODATA;
+               USERSBITERR  <= #`TCQ FIFOSBITERR;
+               USERDBITERR  <= #`TCQ FIFODBITERR;
+            end          
+          end
+        end
+       end //always
+  end //if
+endgenerate
+
+
+generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
+         
+
+      always @* begin
+         case (curr_fwft_state)
+            INVALID: begin
+               if (~FIFOEMPTY)
+                  next_fwft_state     <= STAGE1_VALID;
+               else
+                  next_fwft_state     <= INVALID;
+               end
+            STAGE1_VALID: begin
+               if (FIFOEMPTY)
+                  next_fwft_state     <= STAGE2_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            STAGE2_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= INVALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE1_VALID;
+               else if (~FIFOEMPTY && ~RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= STAGE2_VALID;
+               end
+            BOTH_STAGES_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE2_VALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            default: next_fwft_state     <= INVALID;
+         endcase
+      end
+
+      always @ (posedge rd_rst_i or posedge RD_CLK) begin
+         if (rd_rst_i && C_EN_SAFETY_CKT == 0)
+            curr_fwft_state  <= INVALID;
+         else if (srst_i)
+            curr_fwft_state  <= #`TCQ INVALID;
+         else
+            curr_fwft_state  <= #`TCQ next_fwft_state;
+      end
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
+            if (rd_rst_i == 1) begin
+                ram_regout_en_d1 <= #`TCQ 1'b0;
+            end
+            else begin
+                 if (srst_i == 1'b1) 
+                 ram_regout_en_d1 <= #`TCQ 1'b0;
+                 else
+                 ram_regout_en_d1 <= #`TCQ ram_regout_en;
+                 end
+            end //always
+   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
+       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
+            if (rd_rst_i == 1) begin
+                ram_regout_en_d2 <= #`TCQ 1'b0;
+            end
+            else begin
+                 if (srst_i == 1'b1) 
+                 ram_regout_en_d2 <= #`TCQ 1'b0;
+                 else
+                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
+                 end
+            end //always
+
+    
+
+      always @* begin
+         case (curr_fwft_state)
+            INVALID:           STAGE2_REG_EN <= 1'b0;
+            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;
+            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;
+            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
+            default:           STAGE2_REG_EN <= 1'b0;
+         endcase
+      end
+
+     always @ (posedge RD_CLK) begin
+        ram_valid_i_d <= #`TCQ ram_valid_i;
+        read_data_valid_i_d <= #`TCQ read_data_valid_i;
+        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
+
+     end
+    assign VALID_STAGES = curr_fwft_state;
+
+     //***************************************************************************
+     //  preloadstage2 indicates that stage2 needs to be updated. This is true
+     //  whenever read_data_valid is false, and RAM_valid is true.
+     //***************************************************************************
+    
+     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
+
+     //***************************************************************************
+     //  preloadstage1 indicates that stage1 needs to be updated. This is true
+     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
+     //  false (indicating that Stage1 needs updating), or preloadstage2 is active
+     //  (indicating that Stage2 is going to update, so Stage1, therefore, must
+     //  also be updated to keep it valid.
+     //***************************************************************************
+     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
+  
+     //***************************************************************************
+     // Calculate RAM_REGOUT_EN
+     //  The output registers are controlled by the ram_regout_en signal.
+     //  These registers should be updated either when the output in Stage2 is
+     //  invalid (preloadstage2), OR when the user is reading, in which case the
+     //  Stage2 value will go invalid unless it is replenished.
+     //***************************************************************************
+     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
+
+     //***************************************************************************
+     // Calculate RAM_RD_EN
+     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
+     //  update the value in Stage1.
+     //   One case when this happens is when preloadstage1=true, which indicates
+     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically
+     //  be updated.
+     //   The other case is when the user is reading from the FIFO, which 
+     // guarantees that Stage1 or Stage2 will be invalid on the next clock 
+     // cycle, unless it is replinished by data from the memory. So, as long 
+     // as the RAM has data in it, a read of the RAM should occur.
+     //***************************************************************************
+     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
+   end
+   endgenerate // gnll_fifo
+
+   
+
+   //***************************************************************************
+   // Calculate RAMVALID_P0_OUT
+   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
+   //
+   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then
+   //   RAMVALID_P0_OUT is certainly going to be true.
+   //   If the RAM is not being read from, but the output registers are being
+   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
+   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.
+   //***************************************************************************
+   // PROCESS regout_valid
+     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
+
+     
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin  
+        if (rd_rst_i) begin 
+           // asynchronous reset (active high)
+           fab_valid     <= #`TCQ 1'b0;
+        end else begin
+           if (srst_i) begin 
+              // synchronous reset (active high)
+              fab_valid    <= #`TCQ 1'b0;
+           end else begin
+              if (ram_regout_en == 1'b1) begin
+                 fab_valid  <= #`TCQ 1'b1;
+              end else begin
+                 if (fab_regout_en == 1'b1)
+                   fab_valid <= #`TCQ 1'b0;
+                 else
+                   fab_valid <= #`TCQ fab_valid;
+              end
+           end //srst_i
+        end //rd_rst_i
+     end //always
+   end endgenerate // gnll_fifo_fab_valid
+
+   
+   //***************************************************************************
+   // Calculate READ_DATA_VALID
+   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
+   //  Stage2 has valid data whenever Stage1 had valid data and 
+   //  ram_regout_en_i=1, such that the data in Stage1 is propogated 
+   //  into Stage2.
+   //***************************************************************************
+    generate if(C_USE_EMBEDDED_REG == 3) begin
+   always @ (posedge RD_CLK or posedge rd_rst_i) begin
+      if (rd_rst_i)
+        read_data_valid_i <= #`TCQ 1'b0;
+      else if (srst_i)
+        read_data_valid_i <= #`TCQ 1'b0;
+      else begin
+        if (ram_regout_en == 1'b1) begin
+          read_data_valid_i <= #`TCQ 1'b1;
+        end else begin
+         if (fab_regout_en == 1'b1)
+          read_data_valid_i <= #`TCQ 1'b0;
+        else
+          read_data_valid_i <= #`TCQ read_data_valid_i;
+        end 
+      end 
+   end //always
+end
+endgenerate
+
+//generate if(C_USE_EMBEDDED_REG == 3) begin
+//   always @ (posedge RD_CLK or posedge rd_rst_i) begin
+//      if (rd_rst_i)
+//        read_data_valid_i <= #`TCQ 1'b0;
+//      else if (srst_i)
+//        read_data_valid_i <= #`TCQ 1'b0;
+//
+//      if (ram_regout_en == 1'b1) begin
+//        fab_read_data_valid_i <= #`TCQ 1'b0;
+//      end else begin
+//       if (fab_regout_en == 1'b1)
+//        fab_read_data_valid_i <= #`TCQ 1'b1;
+//      else
+//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
+//      end 
+//   end //always
+//end
+//endgenerate
+
+     generate if(C_USE_EMBEDDED_REG == 3 ) begin 
+    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
+      if (rd_rst_i)
+        fab_read_data_valid_i <= #`TCQ 1'b0;
+      else if (srst_i)
+        fab_read_data_valid_i <= #`TCQ 1'b0;
+      else 
+        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
+   end //always
+end
+endgenerate
+ 
+always @ (posedge RD_CLK ) begin : proc_del1
+             begin
+                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
+              end
+            end //always
+ 
+ 
+   //**************************************************************************
+   // Calculate EMPTY
+   //  Defined as the inverse of READ_DATA_VALID
+   //
+   // Description:
+   //
+   //  If read_data_valid_i indicates that the output is not valid,
+   // and there is no valid data on the output of the ram to preload it
+   // with, then we will report empty.
+   //
+   //  If there is no valid data on the output of the ram and we are
+   // reading, then the FIFO will go empty.
+   //
+   //**************************************************************************
+   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           // asynchronous reset (active high)
+           empty_i <= #`TCQ 1'b1;
+        end else begin
+           if (srst_i) begin
+              // synchronous reset (active high)
+              empty_i <= #`TCQ 1'b1;
+           end else begin
+              // rising clock edge
+              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
+           end
+        end
+     end //always
+   end endgenerate // gnll_fifo_empty_both
+   
+   // Register RD_EN from user to calculate USERUNDERFLOW.
+   // Register empty_i to calculate USERUNDERFLOW.
+   always @ (posedge RD_CLK) begin
+     rd_en_q <= #`TCQ RD_EN;
+     empty_q <= #`TCQ empty_i;
+   end //always
+   
+   
+   //***************************************************************************
+   // Calculate user_almost_empty
+   //  user_almost_empty is defined such that, unless more words are written
+   //  to the FIFO, the next read will cause the FIFO to go EMPTY.
+   //
+   //  In most cases, whenever the output registers are updated (due to a user
+   // read or a preload condition), then user_almost_empty will update to
+   // whatever RAM_EMPTY is.
+   //
+   //  The exception is when the output is valid, the user is not reading, and
+   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the
+   // memory, so we need to make sure user_almost_empty deasserts properly under
+   // this condition.
+   //***************************************************************************
+   reg FIFOEMPTY_1;
+   generate if (C_USE_EMBEDDED_REG == 3 ) begin
+    always @(posedge RD_CLK) begin
+            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
+           end
+    end
+endgenerate
+    generate if (C_USE_EMBEDDED_REG == 3 ) begin
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+   begin
+      if (rd_rst_i) begin         // asynchronous reset (active high)
+           almost_empty_i <= #`TCQ 1'b1;
+             almost_empty_q <= #`TCQ 1'b1;
+        end else begin // rising clock edge
+           if (srst_i) begin          // synchronous reset (active high)
+              almost_empty_i <= #`TCQ 1'b1;
+              almost_empty_q <= #`TCQ 1'b1;
+           end else begin
+              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
+                 almost_empty_i <= #`TCQ (~ram_valid_i);
+              end
+              almost_empty_q   <= #`TCQ empty_i;
+           end
+        end
+     end //always
+end
+endgenerate
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           empty_sckt <= #`TCQ 1'b1;
+           sckt_rrst_q <= #`TCQ 1'b0;
+           sckt_rrst_done <= #`TCQ 1'b0;
+        end else begin
+           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
+           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
+              sckt_rrst_done <= #`TCQ 1'b1;
+           end else if (sckt_rrst_done) begin
+              // rising clock edge
+              empty_sckt <= #`TCQ 1'b0;
+           end
+        end
+     end //always
+   
+   
+//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
+   assign USEREMPTY       = empty_i;
+   assign USERALMOSTEMPTY = almost_empty_i;
+   assign FIFORDEN        = ram_rd_en;
+   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
+   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
+   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
+   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
+   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
+//no safety ckt with both reg
+generate 
+        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
+   always @ (posedge RD_CLK)
+     begin
+        if (rd_rst_i || srst_i) begin
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
+            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            user_sbiterr_both <= #`TCQ 0;
+            user_dbiterr_both <= #`TCQ 0;
+        end
+     end //always
+
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin //asynchronous reset (active high)
+          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+            USERSBITERR    <= #`TCQ 0;
+            USERDBITERR    <= #`TCQ 0;
+            user_sbiterr_both <= #`TCQ 0;
+            user_dbiterr_both <= #`TCQ 0;
+          end
+          // DRAM resets asynchronously
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            user_sbiterr_both <= #`TCQ 0;
+            user_dbiterr_both <= #`TCQ 0;
+        end
+        end  else begin // rising clock edge
+          if (srst_i) begin
+            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+              USERSBITERR  <= #`TCQ 0;
+              USERDBITERR  <= #`TCQ 0;
+              user_sbiterr_both <= #`TCQ 0;
+              user_dbiterr_both <= #`TCQ 0;
+            end
+            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
+              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+              user_sbiterr_both <= #`TCQ 0;
+              user_dbiterr_both <= #`TCQ 0;
+            end
+          end else begin
+            if (fwft_rst_done) begin
+              if (ram_regout_en) begin
+                 userdata_both     <= #`TCQ FIFODATA; 
+                 user_dbiterr_both <= #`TCQ FIFODBITERR;
+                 user_sbiterr_both <= #`TCQ FIFOSBITERR; 
+              end
+              if (fab_regout_en) begin
+                 USERDATA     <= #`TCQ userdata_both;
+                 USERDBITERR  <= #`TCQ user_dbiterr_both;
+                 USERSBITERR  <= #`TCQ user_sbiterr_both; 
+              end             
+            end             
+          end
+        end
+     end //always
+   end   //if
+  endgenerate
+
+//safety_ckt with both registers
+ generate
+       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge RD_CLK) begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+        end
+        always @ (posedge RD_CLK) begin
+          if (rd_rst_i || srst_i) begin
+            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
+              @(posedge RD_CLK)
+              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+              user_sbiterr_both <= #`TCQ 0;
+              user_dbiterr_both <= #`TCQ 0;
+            end
+          end
+        end //always
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i) begin
+     if (rd_rst_i) begin //asynchronous reset (active high)
+       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+         USERSBITERR       <= #`TCQ 0;
+         USERDBITERR       <= #`TCQ 0;
+         user_sbiterr_both <= #`TCQ 0;
+         user_dbiterr_both <= #`TCQ 0;
+       end
+       // DRAM resets asynchronously
+       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)
+         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         user_sbiterr_both <= #`TCQ 0;
+         user_dbiterr_both <= #`TCQ 0;
+       end 
+     end else begin // rising clock edge
+       if (srst_i) begin
+         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+           USERSBITERR       <= #`TCQ 0;
+           USERDBITERR       <= #`TCQ 0;
+           user_sbiterr_both <= #`TCQ 0;
+           user_dbiterr_both <= #`TCQ 0;
+         end
+         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
+           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         end
+       end else if (fwft_rst_done) begin
+         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
+            userdata_both     <= #`TCQ FIFODATA;
+            user_dbiterr_both <= #`TCQ FIFODBITERR;
+            user_sbiterr_both <= #`TCQ FIFOSBITERR; 
+         end
+         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
+            USERDATA          <= #`TCQ userdata_both;
+            USERDBITERR       <= #`TCQ user_dbiterr_both;
+            USERSBITERR       <= #`TCQ user_sbiterr_both;
+         end
+       end
+     end
+   end //always
+  end //if
+endgenerate
+
+endmodule //fifo_generator_v13_2_5_bhv_ver_preload0
+
+
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+//   Register one AXI channel on forward and/or reverse signal path
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   reg_slice
+//
+//--------------------------------------------------------------------------
+
+module fifo_generator_v13_2_5_axic_reg_slice #
+  (
+   parameter C_FAMILY     = "virtex7",
+   parameter C_DATA_WIDTH = 32,
+   parameter C_REG_CONFIG = 32'h00000000
+   )
+  (
+   // System Signals
+   input  wire                      ACLK,
+   input  wire                      ARESET,
+
+   // Slave side
+   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,
+   input  wire                      S_VALID,
+   output wire                      S_READY,
+
+   // Master side
+   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,
+   output wire                      M_VALID,
+   input  wire                      M_READY
+   );
+
+  localparam RST_SYNC_STAGES = 5;
+  localparam RST_BUSY_LEN    = 6;
+  reg [1:0] arst_sync_wr  = 2'b11;
+  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;
+  wire sync_reset;
+  wire extnd_reset;
+
+
+  always @(posedge ARESET or posedge ACLK) begin
+    if (ARESET)
+      arst_sync_wr <= 2'b11;
+    else
+      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};
+  end
+
+  always @(posedge ACLK) begin
+    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};
+  end
+
+  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; 
+  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];
+  generate
+  ////////////////////////////////////////////////////////////////////
+  //
+  // Both FWD and REV mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    if (C_REG_CONFIG == 32'h00000000)
+    begin
+      reg [1:0] state;
+      localparam [1:0] 
+        ZERO = 2'b10,
+        ONE  = 2'b11,
+        TWO  = 2'b01;
+      
+      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
+      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
+      reg                    load_s1;
+      wire                   load_s2;
+      wire                   load_s1_from_s2;
+      reg                    s_ready_i; //local signal of output
+      wire                   m_valid_i; //local signal of output
+
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+
+      reg  areset_d1; // Reset delay register
+      always @(posedge ACLK) begin
+        areset_d1 <= extnd_reset;
+      end
+      
+      // Load storage1 with either slave side data or from storage2
+      always @(posedge ACLK) 
+      begin
+        if (load_s1)
+          if (load_s1_from_s2)
+            storage_data1 <= storage_data2;
+          else
+            storage_data1 <= S_PAYLOAD_DATA;        
+      end
+
+      // Load storage2 with slave side data
+      always @(posedge ACLK) 
+      begin
+        if (load_s2)
+          storage_data2 <= S_PAYLOAD_DATA;
+      end
+
+      assign M_PAYLOAD_DATA = storage_data1;
+
+      // Always load s2 on a valid transaction even if it's unnecessary
+      assign load_s2 = S_VALID & s_ready_i;
+
+      // Loading s1
+      always @ *
+      begin
+        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
+             // Load when ONE if we both have read and write at the same time
+             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
+             // Load when TWO and we have a transaction on Master side
+             ((state == TWO) && (M_READY == 1)))
+          load_s1 = 1'b1;
+        else
+          load_s1 = 1'b0;
+      end // always @ *
+
+      assign load_s1_from_s2 = (state == TWO);
+                       
+      // State Machine for handling output signals
+      always @(posedge ACLK) begin
+        if (sync_reset || extnd_reset) begin
+          s_ready_i <= 1'b0;
+          state <= ZERO;
+        end else if (areset_d1 && ~extnd_reset) begin
+          s_ready_i <= 1'b1;
+        end else begin
+          case (state)
+            // No transaction stored locally
+            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
+
+            // One transaction stored locally
+            ONE: begin
+              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
+              if (~M_READY & S_VALID) begin
+                state <= TWO;  // Got another one so move to TWO
+                s_ready_i <= 1'b0;
+              end
+            end
+
+            // TWO transaction stored locally
+            TWO: if (M_READY) begin
+              state <= ONE; // Read out one so move to ONE
+              s_ready_i <= 1'b1;
+            end
+          endcase // case (state)
+        end
+      end // always @ (posedge ACLK)
+      
+      assign m_valid_i = state[0];
+
+    end // if (C_REG_CONFIG == 1)
+  ////////////////////////////////////////////////////////////////////
+  //
+  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+  // Operates same as 1-deep FIFO
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if (C_REG_CONFIG == 32'h00000001)
+    begin
+      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
+      reg                    s_ready_i; //local signal of output
+      reg                    m_valid_i; //local signal of output
+
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+
+      reg  areset_d1; // Reset delay register
+      always @(posedge ACLK) begin
+        areset_d1 <= extnd_reset;
+      end
+      
+      // Load storage1 with slave side data
+      always @(posedge ACLK) 
+      begin
+        if (sync_reset || extnd_reset) begin
+          s_ready_i <= 1'b0;
+          m_valid_i <= 1'b0;
+        end else if (areset_d1 && ~extnd_reset) begin
+          s_ready_i <= 1'b1;
+        end else if (m_valid_i & M_READY) begin
+          s_ready_i <= 1'b1;
+          m_valid_i <= 1'b0;
+        end else if (S_VALID & s_ready_i) begin
+          s_ready_i <= 1'b0;
+          m_valid_i <= 1'b1;
+        end
+        if (~m_valid_i) begin
+          storage_data1 <= S_PAYLOAD_DATA;        
+        end
+      end
+      assign M_PAYLOAD_DATA = storage_data1;
+    end // if (C_REG_CONFIG == 7)
+    
+    else begin : default_case
+      // Passthrough
+      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+      assign M_VALID        = S_VALID;
+      assign S_READY        = M_READY;      
+    end
+
+  endgenerate
+endmodule // reg_slice
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/mem_init_files/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/mem_init_files/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_read.coe b/projects/U200/U200.ip_user_files/mem_init_files/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_read_mem.mif b/projects/U200/U200.ip_user_files/mem_init_files/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_ref.coe b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/pr_zq.coe b/projects/U200/U200.ip_user_files/mem_init_files/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/mem_init_files/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/simmem.coe b/projects/U200/U200.ip_user_files/mem_init_files/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0000000000000110000000000000000000000000100010000000000000000000,
+0000000000000110000000000000000000000000101100000000000100000000,
+0000000000000110000000000000000000000000000000000000000010000000,
+0000000000000110000000000000000000000000000100000000000000010000,
+0000000000000110000000000000000000000000001000000000000000010000,
+0001000000000000000000000000000000000000101000000000000000110000,
+0100000000000011000000000000000000000000000000000000000000000011,
+0001000000000001000000000000000000000000000100000000000000110000,
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+0000000000000111000000000000000000000000000000000000000000001100,
+0000000000000111000000000000000000000000000100000000000000001100,
+0000000000000111000000000000000000000000001000000000000000001100,
+0000000000000111000000000000000000000000001100000000000000001100,
+0000000000000111000000000000000000000000010000000000000000001100,
+0000000000000111000000000000000000000000010100000000000000001100,
+0000000000000111000000000000000000000000011000000000000000001100,
+0000000000000111000000000000000000000000011100000000000000001100,
+0000000000000111000000000000000000000000100000000000000000001100,
+0000000000000111000000000000000000000000100100000000000000001100,
+0000000000000111000000000000000000000000101000000000000000001100,
+0000000000000111000000000000000000000000101100000000000000001100,
+0000000000000111000000000000000000000000110000000000000000001100,
+0000000000000111000000000000000000000000110100000000000000001100,
+0000000000000111000000000000000000000000111000000000000000001100,
+0000000000000111000000000000000000000000111100000000000000001100,
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+0000000000000110000000000000000000000000011000000000000000000000,
+0000000000000110000000000000000000000000010000000000000000000000,
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+0000000000000110000000000000000000000000111000000000100000000000,
+0000000000000110000000000000000000000000110100000000000000000000,
+1111000000000000111100000000000011110000000000001000100001000111,
+0000000000000101000000000000000000000000110000000000000000001100,
+0000000000000111000000000000000000000000000000000000000000001100,
+0000000000000111000000000000000000000000000100000000000000001100,
+0000000000000111000000000000000000000000001000000000000000001100,
+0000000000000111000000000000000000000000001100000000000000001100,
+0000000000000111000000000000000000000000010000000000000000001100,
+0000000000000111000000000000000000000000010100000000000000001100,
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+0000000000000111000000000000000000000000111100000000000000001100,
+0000000000000001000000000000000000000000110100000000000000011101,
+0100000000000000000000000000000000000000000000000010010111101101,
+0000000000000100000000000000000000000000111100000000000000001100,
+0000000000000000000000000000000000000000110000000000000011111100,
+0000000000000000000000000000000000000000110000000000000011111100,
+0000000000000111000000000000000000000000000000000000000000001100,
+0000000000000111000000000000000000000000000100000000000000001100,
+0000000000000111000000000000000000000000001000000000000000001100,
+0000000000000111000000000000000000000000001100000000000000001100,
+0000000000000111000000000000000000000000010000000000000000001100,
+0000000000000111000000000000000000000000010100000000000000001100,
+0000000000000111000000000000000000000000011000000000000000001100,
+0000000000000111000000000000000000000000011100000000000000001100,
+0000000000000111000000000000000000000000100000000000000000001100,
+0000000000000111000000000000000000000000100100000000000000001100,
+0000000000000111000000000000000000000000101000000000000000001100,
+0000000000000111000000000000000000000000101100000000000000001100,
+0000000000000111000000000000000000000000110000000000000000001100,
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+0000000000000111000000000000000000000000111000000000000000001110,
+0000000000000111000000000000000000000000111100000000000000001111,
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+1111000000000000111100000000000011110000000000001111000000000000,
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+1111000000000000111100000000000011110000000000001111000000000000,
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/summary.log b/projects/U200/U200.ip_user_files/mem_init_files/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/mem_init_files/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/mem_init_files/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/mem_init_files/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/README.txt
new file mode 100644
index 0000000..e96a5fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.sh
new file mode 100755
index 0000000..1693801
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/compile.do
new file mode 100644
index 0000000..0b13d95
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/compile.do
@@ -0,0 +1,46 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/axis_infrastructure_v1_1_0
+vlib activehdl/axis_clock_converter_v1_1_23
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap axis_infrastructure_v1_1_0 activehdl/axis_infrastructure_v1_1_0
+vmap axis_clock_converter_v1_1_23 activehdl/axis_clock_converter_v1_1_23
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work axis_infrastructure_v1_1_0  -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+
+vlog -work axis_clock_converter_v1_1_23  -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/file_info.txt
new file mode 100644
index 0000000..4607b03
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/simulate.do
new file mode 100644
index 0000000..8144d45
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+axis_clock_converter -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axis_clock_converter xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {axis_clock_converter.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/README.txt
new file mode 100644
index 0000000..348b315
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/axis_clock_converter.sh
new file mode 100755
index 0000000..634ad59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/axis_clock_converter.sh
@@ -0,0 +1,178 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_23 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.axis_clock_converter \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../ipstatic/hdl" \
+       +incdir+"../../../ipstatic/hdl" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/file_info.txt
new file mode 100644
index 0000000..9f6127d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/run.f
new file mode 100644
index 0000000..234ef29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/run.f
@@ -0,0 +1,32 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/axis_infrastructure_v1_1_0 \
+  "../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+-endlib
+-makelib ies_lib/axis_clock_converter_v1_1_23 \
+  "../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/README.txt
new file mode 100644
index 0000000..e96a5fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.sh
new file mode 100755
index 0000000..5e3eaa9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/compile.do
new file mode 100644
index 0000000..b58f682
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/compile.do
@@ -0,0 +1,46 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/axis_infrastructure_v1_1_0
+vlib modelsim_lib/msim/axis_clock_converter_v1_1_23
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap axis_infrastructure_v1_1_0 modelsim_lib/msim/axis_infrastructure_v1_1_0
+vmap axis_clock_converter_v1_1_23 modelsim_lib/msim/axis_clock_converter_v1_1_23
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work axis_infrastructure_v1_1_0 -64 -incr "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+
+vlog -work axis_clock_converter_v1_1_23 -64 -incr "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/file_info.txt
new file mode 100644
index 0000000..4607b03
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/simulate.do
new file mode 100644
index 0000000..7b1f2ad
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {axis_clock_converter.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/README.txt
new file mode 100644
index 0000000..e96a5fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.sh
new file mode 100755
index 0000000..5e727c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/compile.do
new file mode 100644
index 0000000..99047ec
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/compile.do
@@ -0,0 +1,46 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/axis_infrastructure_v1_1_0
+vlib questa_lib/msim/axis_clock_converter_v1_1_23
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap axis_infrastructure_v1_1_0 questa_lib/msim/axis_infrastructure_v1_1_0
+vmap axis_clock_converter_v1_1_23 questa_lib/msim/axis_clock_converter_v1_1_23
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work axis_infrastructure_v1_1_0 -64 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+
+vlog -work axis_clock_converter_v1_1_23 -64 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/elaborate.do
new file mode 100644
index 0000000..4f6cea8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -o axis_clock_converter_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/file_info.txt
new file mode 100644
index 0000000..4607b03
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/simulate.do
new file mode 100644
index 0000000..744838d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib axis_clock_converter_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {axis_clock_converter.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/README.txt
new file mode 100644
index 0000000..e96a5fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.sh
new file mode 100755
index 0000000..9e8c90c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/compile.do
new file mode 100644
index 0000000..96d4454
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/compile.do
@@ -0,0 +1,46 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/axis_infrastructure_v1_1_0
+vlib riviera/axis_clock_converter_v1_1_23
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap axis_infrastructure_v1_1_0 riviera/axis_infrastructure_v1_1_0
+vmap axis_clock_converter_v1_1_23 riviera/axis_clock_converter_v1_1_23
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work axis_infrastructure_v1_1_0  -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+
+vlog -work axis_clock_converter_v1_1_23  -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/file_info.txt
new file mode 100644
index 0000000..4607b03
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/simulate.do
new file mode 100644
index 0000000..8144d45
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+axis_clock_converter -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axis_clock_converter xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {axis_clock_converter.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/README.txt
new file mode 100644
index 0000000..e96a5fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/axis_clock_converter.sh
new file mode 100755
index 0000000..d4759a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/axis_clock_converter.sh
@@ -0,0 +1,251 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_23 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work axis_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work axis_clock_converter_v1_1_23 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -o axis_clock_converter_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./axis_clock_converter_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key axis_clock_converter_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc axis_clock_converter_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/file_info.txt
new file mode 100644
index 0000000..9f6127d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/README.txt
new file mode 100644
index 0000000..348b315
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/axis_clock_converter.sh
new file mode 100755
index 0000000..f0d0536
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/axis_clock_converter.sh
@@ -0,0 +1,178 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'axis_clock_converter.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_23 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.axis_clock_converter \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../ipstatic/hdl" \
+       +incdir+"../../../ipstatic/hdl" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/file_info.txt
new file mode 100644
index 0000000..9f6127d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/file_info.txt
@@ -0,0 +1,17 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/run.f
new file mode 100644
index 0000000..d38b4ff
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/run.f
@@ -0,0 +1,32 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/axis_infrastructure_v1_1_0 \
+  "../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
+-endlib
+-makelib xcelium_lib/axis_clock_converter_v1_1_23 \
+  "../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/README.txt
new file mode 100644
index 0000000..e96a5fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./axis_clock_converter.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './axis_clock_converter.sh' script.
+
+./axis_clock_converter.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./axis_clock_converter.sh -noclean_files
+
+For more information on the script, please type './axis_clock_converter.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/axis_clock_converter.sh
new file mode 100755
index 0000000..181c27e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/axis_clock_converter.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : axis_clock_converter.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: axis_clock_converter.sh [-help]
+# usage: axis_clock_converter.sh [-lib_map_path]
+# usage: axis_clock_converter.sh [-noclean_files]
+# usage: axis_clock_converter.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot axis_clock_converter xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim axis_clock_converter -key {Behavioral:sim_1:Functional:axis_clock_converter} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=(xil_defaultlib)
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb axis_clock_converter.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: axis_clock_converter.sh [-help]\n\
+Usage: axis_clock_converter.sh [-lib_map_path]\n\
+Usage: axis_clock_converter.sh [-reset_run]\n\
+Usage: axis_clock_converter.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/file_info.txt
new file mode 100644
index 0000000..7914184
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/file_info.txt
@@ -0,0 +1,2 @@
+axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/vlog.prj
new file mode 100644
index 0000000..c8e0879
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib --include "../../../ipstatic/hdl" \
+"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt
new file mode 100644
index 0000000..cbe0c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do
new file mode 100644
index 0000000..b14c2e3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh
new file mode 100755
index 0000000..d39e0a1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do
new file mode 100644
index 0000000..1602422
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+instr_blk_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {instr_blk_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt
new file mode 100644
index 0000000..26d8f67
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh
new file mode 100755
index 0000000..d7f5271
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.instr_blk_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f
new file mode 100644
index 0000000..377bea5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f
@@ -0,0 +1,29 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt
new file mode 100644
index 0000000..cbe0c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do
new file mode 100644
index 0000000..41f1286
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do
@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh
new file mode 100755
index 0000000..88dd8f6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do
new file mode 100644
index 0000000..9a42a0c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.instr_blk_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {instr_blk_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt
new file mode 100644
index 0000000..cbe0c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do
new file mode 100644
index 0000000..94def16
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do
@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do
new file mode 100644
index 0000000..417eabc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -o instr_blk_mem_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh
new file mode 100755
index 0000000..817277e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do
new file mode 100644
index 0000000..5832b28
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib instr_blk_mem_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {instr_blk_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt
new file mode 100644
index 0000000..cbe0c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do
new file mode 100644
index 0000000..35e9fea
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh
new file mode 100755
index 0000000..63c4a88
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do
new file mode 100644
index 0000000..1602422
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+instr_blk_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {instr_blk_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt
new file mode 100644
index 0000000..cbe0c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh
new file mode 100755
index 0000000..f0524d8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh
@@ -0,0 +1,247 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -o instr_blk_mem_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./instr_blk_mem_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key instr_blk_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc instr_blk_mem_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt
new file mode 100644
index 0000000..26d8f67
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt
new file mode 100644
index 0000000..9ed9f5f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh
new file mode 100755
index 0000000..6863d0d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.instr_blk_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f
new file mode 100644
index 0000000..071771d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f
@@ -0,0 +1,29 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt
new file mode 100644
index 0000000..cbe0c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem.sh' script.
+
+./instr_blk_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt
new file mode 100644
index 0000000..0fd4037
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt
@@ -0,0 +1,2 @@
+instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh
new file mode 100755
index 0000000..aab8ed7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem.sh [-help]
+# usage: instr_blk_mem.sh [-lib_map_path]
+# usage: instr_blk_mem.sh [-noclean_files]
+# usage: instr_blk_mem.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot instr_blk_mem xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim instr_blk_mem -key {Behavioral:sim_1:Functional:instr_blk_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb instr_blk_mem.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem.sh [-help]\n\
+Usage: instr_blk_mem.sh [-lib_map_path]\n\
+Usage: instr_blk_mem.sh [-reset_run]\n\
+Usage: instr_blk_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log
new file mode 100755
index 0000000..5094079
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [2048]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [4]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     7.524303 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj
new file mode 100644
index 0000000..6207c87
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt
new file mode 100644
index 0000000..dc30976
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do
new file mode 100644
index 0000000..6dccd0b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..65660b2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0000000000000110000000000000000000000000100010000000000000000000,
+0000000000000110000000000000000000000000101100000000000100000000,
+0000000000000110000000000000000000000000000000000000000010000000,
+0000000000000110000000000000000000000000000100000000000000010000,
+0000000000000110000000000000000000000000001000000000000000010000,
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+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do
new file mode 100644
index 0000000..3af7c4b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+instr_blk_mem_sim -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {instr_blk_mem_sim.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt
new file mode 100644
index 0000000..e9e84f9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..791fc5d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.instr_blk_mem_sim \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f
new file mode 100644
index 0000000..a0a3c78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f
@@ -0,0 +1,29 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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+0000000000000111000000000000000000000000000100000000000000000001,
+0000000000000111000000000000000000000000001000000000000000000010,
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+0000000000000111000000000000000000000000010000000000000000000100,
+0000000000000111000000000000000000000000010100000000000000000101,
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000011111101,
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+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt
new file mode 100644
index 0000000..dc30976
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do
new file mode 100644
index 0000000..ae902a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do
@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..43115ec
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do
new file mode 100644
index 0000000..aff26ea
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {instr_blk_mem_sim.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt
new file mode 100644
index 0000000..dc30976
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do
new file mode 100644
index 0000000..57c64ef
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do
@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do
new file mode 100644
index 0000000..8c66a9a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -o instr_blk_mem_sim_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..5d38c86
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
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+1111000000000000111100000000000011110000000000001001100001000111,
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+1111000000000000111100000000000011110000000000001001100001000111,
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001010000000000111,
+0000000000000001000000000000000000000000011000000000000000010110,
+0100000000000000000000000000000000000000000000000001110010000110,
+0000000000000001000000000000000000000000011100000000000000010111,
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+1111000000000000111100000000000011110000000000001111000000000000,
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+0000000000000110000000000000000000000000110100000000000011110000,
+0000000000000110000000000000000000000000111000000000000000000000,
+0000000000000110000000000000000000000000111100000000000000000000,
+0000000000000000000000000000000000000000000000000000000000000001,
+1111000000000000111100000000000011110000000000001010100000001101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000011101101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001000000011111101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000011111101,
+0000000000000111000000000000000000000000000000000000000000000000,
+0000000000000111000000000000000000000000000100000000000000000001,
+0000000000000111000000000000000000000000001000000000000000000010,
+0000000000000111000000000000000000000000001100000000000000000011,
+0000000000000111000000000000000000000000010000000000000000000100,
+0000000000000111000000000000000000000000010100000000000000000101,
+0000000000000111000000000000000000000000011000000000000000000110,
+0000000000000111000000000000000000000000011100000000000000000111,
+0000000000000111000000000000000000000000100000000000000000001000,
+0000000000000111000000000000000000000000100100000000000000001001,
+0000000000000111000000000000000000000000101000000000000000001010,
+0000000000000111000000000000000000000000101100000000000000001011,
+0000000000000111000000000000000000000000110000000000000000001100,
+0000000000000111000000000000000000000000110100000000000000001101,
+0000000000000111000000000000000000000000111000000000000000001110,
+0000000000000111000000000000000000000000111100000000000000001111,
+0000000000000000000000000000000000000000000000000000000000000001,
+1111000000000000111100000000000011110000000000001000000011111101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000011111101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do
new file mode 100644
index 0000000..1966060
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib instr_blk_mem_sim_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {instr_blk_mem_sim.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt
new file mode 100644
index 0000000..dc30976
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do
new file mode 100644
index 0000000..983f077
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..8d95e5d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do
new file mode 100644
index 0000000..3af7c4b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+instr_blk_mem_sim -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {instr_blk_mem_sim.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt
new file mode 100644
index 0000000..dc30976
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..22303ba
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.sh
@@ -0,0 +1,247 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -o instr_blk_mem_sim_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./instr_blk_mem_sim_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key instr_blk_mem_sim_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc instr_blk_mem_sim_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe
@@ -0,0 +1,398 @@
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+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt
new file mode 100644
index 0000000..e9e84f9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt
new file mode 100644
index 0000000..cd1d040
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..5964eda
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.instr_blk_mem_sim \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f
new file mode 100644
index 0000000..42c442c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f
@@ -0,0 +1,29 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt
new file mode 100644
index 0000000..dc30976
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./instr_blk_mem_sim.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './instr_blk_mem_sim.sh' script.
+
+./instr_blk_mem_sim.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./instr_blk_mem_sim.sh -noclean_files
+
+For more information on the script, please type './instr_blk_mem_sim.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt
new file mode 100644
index 0000000..2ecac04
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt
@@ -0,0 +1,2 @@
+instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif
new file mode 100755
index 0000000..e9bd6fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif
@@ -0,0 +1,396 @@
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diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.sh
new file mode 100755
index 0000000..cc849f9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : instr_blk_mem_sim.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: instr_blk_mem_sim.sh [-help]
+# usage: instr_blk_mem_sim.sh [-lib_map_path]
+# usage: instr_blk_mem_sim.sh [-noclean_files]
+# usage: instr_blk_mem_sim.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot instr_blk_mem_sim xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim instr_blk_mem_sim -key {Behavioral:sim_1:Functional:instr_blk_mem_sim} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb instr_blk_mem_sim.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: instr_blk_mem_sim.sh [-help]\n\
+Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\
+Usage: instr_blk_mem_sim.sh [-reset_run]\n\
+Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe
new file mode 100755
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0000000000000110000000000000000000000000100010000000000000000000,
+0000000000000110000000000000000000000000101100000000000100000000,
+0000000000000110000000000000000000000000000000000000000010000000,
+0000000000000110000000000000000000000000000100000000000000010000,
+0000000000000110000000000000000000000000001000000000000000010000,
+0001000000000000000000000000000000000000101000000000000000110000,
+0100000000000011000000000000000000000000000000000000000000000011,
+0001000000000001000000000000000000000000000100000000000000110000,
+0100000000000011000000000000000000000000000000000000000000000011,
+0000000000000110000000000100111011101110110000010100001010100000,
+0000000000000111000000000000000000000000000000000000000000001100,
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+0000000000000111000000000000000000000000010100000000000000001100,
+0000000000000111000000000000000000000000011000000000000000001100,
+0000000000000111000000000000000000000000011100000000000000001100,
+0000000000000111000000000000000000000000100000000000000000001100,
+0000000000000111000000000000000000000000100100000000000000001100,
+0000000000000111000000000000000000000000101000000000000000001100,
+0000000000000111000000000000000000000000101100000000000000001100,
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+0000000000000110000000000000000000000000110100000000000000000000,
+1111000000000000111100000000000011110000000000001000100001000111,
+0000000000000101000000000000000000000000110000000000000000001100,
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+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log
new file mode 100755
index 0000000..db51362
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [2]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     4.238151 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj
new file mode 100644
index 0000000..e315bbf
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do
new file mode 100644
index 0000000..066ff39
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/microblaze_v11_0_4
+vlib activehdl/xil_defaultlib
+vlib activehdl/lib_cdc_v1_0_2
+vlib activehdl/proc_sys_reset_v5_0_13
+vlib activehdl/lmb_v10_v3_0_11
+vlib activehdl/lmb_bram_if_cntlr_v4_0_19
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/iomodule_v3_1_6
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap microblaze_v11_0_4 activehdl/microblaze_v11_0_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 activehdl/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 activehdl/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 activehdl/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt
new file mode 100644
index 0000000..a852294
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh
new file mode 100755
index 0000000..bec5b04
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do
new file mode 100644
index 0000000..98bfe9c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_ddr4 -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_ddr4.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt
new file mode 100644
index 0000000..8eae52e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt
new file mode 100644
index 0000000..c7c8650
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh
new file mode 100755
index 0000000..ba1c4b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh
@@ -0,0 +1,182 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_ddr4 \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/run.f
new file mode 100644
index 0000000..6ddac70
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/run.f
@@ -0,0 +1,113 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/microblaze_v11_0_4 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+-endlib
+-makelib ies_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib ies_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_v10_v3_0_11 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_bram_if_cntlr_v4_0_19 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/iomodule_v3_1_6 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do
new file mode 100644
index 0000000..e566929
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do
@@ -0,0 +1,137 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/microblaze_v11_0_4
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/lib_cdc_v1_0_2
+vlib modelsim_lib/msim/proc_sys_reset_v5_0_13
+vlib modelsim_lib/msim/lmb_v10_v3_0_11
+vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/iomodule_v3_1_6
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap microblaze_v11_0_4 modelsim_lib/msim/microblaze_v11_0_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 modelsim_lib/msim/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 modelsim_lib/msim/iomodule_v3_1_6
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -64 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -64 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -64 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -64 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -64 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt
new file mode 100644
index 0000000..a852294
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh
new file mode 100755
index 0000000..7bc25d8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do
new file mode 100644
index 0000000..7a40dbd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_ddr4 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {phy_ddr4.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do
new file mode 100644
index 0000000..2ef7694
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do
@@ -0,0 +1,137 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/microblaze_v11_0_4
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/lib_cdc_v1_0_2
+vlib questa_lib/msim/proc_sys_reset_v5_0_13
+vlib questa_lib/msim/lmb_v10_v3_0_11
+vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/iomodule_v3_1_6
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap microblaze_v11_0_4 questa_lib/msim/microblaze_v11_0_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 questa_lib/msim/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 questa_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 questa_lib/msim/iomodule_v3_1_6
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -64 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -64 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -64 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -64 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -64 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do
new file mode 100644
index 0000000..ecdddc7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -o phy_ddr4_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt
new file mode 100644
index 0000000..a852294
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh
new file mode 100755
index 0000000..9f0acc7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do
new file mode 100644
index 0000000..a04d2c1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib phy_ddr4_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {phy_ddr4.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do
new file mode 100644
index 0000000..3598ac3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/microblaze_v11_0_4
+vlib riviera/xil_defaultlib
+vlib riviera/lib_cdc_v1_0_2
+vlib riviera/proc_sys_reset_v5_0_13
+vlib riviera/lmb_v10_v3_0_11
+vlib riviera/lmb_bram_if_cntlr_v4_0_19
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/iomodule_v3_1_6
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt
new file mode 100644
index 0000000..a852294
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh
new file mode 100755
index 0000000..a649ee0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do
new file mode 100644
index 0000000..98bfe9c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_ddr4 -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_ddr4.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt
new file mode 100644
index 0000000..c7c8650
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh
new file mode 100755
index 0000000..dd806cb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh
@@ -0,0 +1,346 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work microblaze_v11_0_4 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lmb_v10_v3_0_11 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lmb_bram_if_cntlr_v4_0_19 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work iomodule_v3_1_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -o phy_ddr4_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./phy_ddr4_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key phy_ddr4_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_ddr4_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt
new file mode 100644
index 0000000..8eae52e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt
new file mode 100644
index 0000000..c7c8650
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh
new file mode 100755
index 0000000..d794dd7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh
@@ -0,0 +1,182 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_ddr4 \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f
new file mode 100644
index 0000000..f7914cf
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f
@@ -0,0 +1,113 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/microblaze_v11_0_4 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+-endlib
+-makelib xcelium_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+-endlib
+-makelib xcelium_lib/lmb_v10_v3_0_11 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+-endlib
+-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_19 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+-endlib
+-makelib xcelium_lib/iomodule_v3_1_6 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt
new file mode 100644
index 0000000..67e5cc5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100755
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt
new file mode 100644
index 0000000..b5599f5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt
@@ -0,0 +1,50 @@
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.h
new file mode 100755
index 0000000..d82087e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.h
@@ -0,0 +1,472 @@
+#ifndef IP_PHY_DDR4_H_
+#define IP_PHY_DDR4_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4 : public phy_ddr4_sc
+{
+public:
+
+  phy_ddr4(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_out< bool > addn_ui_clkout1;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh
new file mode 100755
index 0000000..7fce527
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh
@@ -0,0 +1,214 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_ddr4 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim phy_ddr4 -key {Behavioral:sim_1:Functional:phy_ddr4} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_ddr4.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4_sc.h
new file mode 100755
index 0000000..036743e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_SC_H_
+#define IP_PHY_DDR4_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_sc(const phy_ddr4_sc&);
+  const phy_ddr4_sc& operator=(const phy_ddr4_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj
new file mode 100644
index 0000000..fe85343
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj
@@ -0,0 +1,12 @@
+vhdl xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj
new file mode 100644
index 0000000..29c5593
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj
@@ -0,0 +1,47 @@
+verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+
+sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/README.txt
new file mode 100644
index 0000000..06ceb3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/compile.do
new file mode 100644
index 0000000..60fc190
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/microblaze_v11_0_4
+vlib activehdl/xil_defaultlib
+vlib activehdl/lib_cdc_v1_0_2
+vlib activehdl/proc_sys_reset_v5_0_13
+vlib activehdl/lmb_v10_v3_0_11
+vlib activehdl/lmb_bram_if_cntlr_v4_0_19
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/iomodule_v3_1_6
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap microblaze_v11_0_4 activehdl/microblaze_v11_0_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 activehdl/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 activehdl/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 activehdl/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/file_info.txt
new file mode 100644
index 0000000..c6f10bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..5f61c2c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/simulate.do
new file mode 100644
index 0000000..2451173
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_ddr4_udimm -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_ddr4_udimm.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/README.txt
new file mode 100644
index 0000000..7905ff1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/file_info.txt
new file mode 100644
index 0000000..af33135
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+phy_ddr4_udimm_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..cb90c3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.sh
@@ -0,0 +1,182 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_ddr4_udimm \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/run.f
new file mode 100644
index 0000000..bee9b75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/run.f
@@ -0,0 +1,113 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/microblaze_v11_0_4 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+-endlib
+-makelib ies_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib ies_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_v10_v3_0_11 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_bram_if_cntlr_v4_0_19 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/iomodule_v3_1_6 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/README.txt
new file mode 100644
index 0000000..06ceb3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/compile.do
new file mode 100644
index 0000000..b8f3428
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/compile.do
@@ -0,0 +1,137 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/microblaze_v11_0_4
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/lib_cdc_v1_0_2
+vlib modelsim_lib/msim/proc_sys_reset_v5_0_13
+vlib modelsim_lib/msim/lmb_v10_v3_0_11
+vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/iomodule_v3_1_6
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap microblaze_v11_0_4 modelsim_lib/msim/microblaze_v11_0_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 modelsim_lib/msim/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 modelsim_lib/msim/iomodule_v3_1_6
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -64 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -64 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -64 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -64 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -64 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/file_info.txt
new file mode 100644
index 0000000..c6f10bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..b88c0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/simulate.do
new file mode 100644
index 0000000..316c990
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {phy_ddr4_udimm.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/README.txt
new file mode 100644
index 0000000..06ceb3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/compile.do
new file mode 100644
index 0000000..e5a9152
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/compile.do
@@ -0,0 +1,137 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/microblaze_v11_0_4
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/lib_cdc_v1_0_2
+vlib questa_lib/msim/proc_sys_reset_v5_0_13
+vlib questa_lib/msim/lmb_v10_v3_0_11
+vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/iomodule_v3_1_6
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap microblaze_v11_0_4 questa_lib/msim/microblaze_v11_0_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 questa_lib/msim/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 questa_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 questa_lib/msim/iomodule_v3_1_6
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -64 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -64 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -64 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -64 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -64 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/elaborate.do
new file mode 100644
index 0000000..96e5ee3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl -o phy_ddr4_udimm_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/file_info.txt
new file mode 100644
index 0000000..c6f10bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..407b1e6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/simulate.do
new file mode 100644
index 0000000..3ef7865
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib phy_ddr4_udimm_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {phy_ddr4_udimm.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/README.txt
new file mode 100644
index 0000000..06ceb3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/compile.do
new file mode 100644
index 0000000..c67c0c9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/microblaze_v11_0_4
+vlib riviera/xil_defaultlib
+vlib riviera/lib_cdc_v1_0_2
+vlib riviera/proc_sys_reset_v5_0_13
+vlib riviera/lmb_v10_v3_0_11
+vlib riviera/lmb_bram_if_cntlr_v4_0_19
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/iomodule_v3_1_6
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/file_info.txt
new file mode 100644
index 0000000..c6f10bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+bd_ba6a_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..b1f6870
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/simulate.do
new file mode 100644
index 0000000..2451173
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_ddr4_udimm -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_ddr4_udimm.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/README.txt
new file mode 100644
index 0000000..06ceb3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/file_info.txt
new file mode 100644
index 0000000..af33135
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..79d917c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.sh
@@ -0,0 +1,346 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work microblaze_v11_0_4 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lmb_v10_v3_0_11 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lmb_bram_if_cntlr_v4_0_19 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work iomodule_v3_1_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl -o phy_ddr4_udimm_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./phy_ddr4_udimm_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key phy_ddr4_udimm_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_ddr4_udimm_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/README.txt
new file mode 100644
index 0000000..7905ff1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/file_info.txt
new file mode 100644
index 0000000..af33135
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
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+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..0c3429e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.sh
@@ -0,0 +1,182 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_ddr4_udimm \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/run.f
new file mode 100644
index 0000000..e89fc29
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/run.f
@@ -0,0 +1,113 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/microblaze_v11_0_4 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+-endlib
+-makelib xcelium_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+-endlib
+-makelib xcelium_lib/lmb_v10_v3_0_11 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+-endlib
+-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_19 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+-endlib
+-makelib xcelium_lib/iomodule_v3_1_6 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/README.txt
new file mode 100644
index 0000000..06ceb3a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4_udimm.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4_udimm.sh' script.
+
+./phy_ddr4_udimm.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4_udimm.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4_udimm.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/file_info.txt
new file mode 100644
index 0000000..1a16c3d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/file_info.txt
@@ -0,0 +1,50 @@
+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+bd_ba6a.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.h
new file mode 100755
index 0000000..ec2d0cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.h
@@ -0,0 +1,467 @@
+#ifndef IP_PHY_DDR4_UDIMM_H_
+#define IP_PHY_DDR4_UDIMM_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_ddr4_udimm_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc
+{
+public:
+
+  phy_ddr4_udimm(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<512> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<512> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_DDR4_UDIMM_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.sh
new file mode 100755
index 0000000..5d62690
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.sh
@@ -0,0 +1,214 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_ddr4_udimm.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4_udimm.sh [-help]
+# usage: phy_ddr4_udimm.sh [-lib_map_path]
+# usage: phy_ddr4_udimm.sh [-noclean_files]
+# usage: phy_ddr4_udimm.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_ddr4_udimm xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim phy_ddr4_udimm -key {Behavioral:sim_1:Functional:phy_ddr4_udimm} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_ddr4_udimm.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4_udimm.sh [-help]\n\
+Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\
+Usage: phy_ddr4_udimm.sh [-reset_run]\n\
+Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm_sc.h
new file mode 100755
index 0000000..e31f3a2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_DDR4_UDIMM_SC_H_
+#define IP_PHY_DDR4_UDIMM_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module
+{
+public:
+
+  phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_ddr4_udimm_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&);
+  const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&);
+
+};
+
+#endif // IP_PHY_DDR4_UDIMM_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vhdl.prj
new file mode 100644
index 0000000..a2f5f6c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vhdl.prj
@@ -0,0 +1,12 @@
+vhdl xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vlog.prj
new file mode 100644
index 0000000..6357e2a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vlog.prj
@@ -0,0 +1,47 @@
+verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \
+
+sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/README.txt
new file mode 100644
index 0000000..5254a3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/compile.do
new file mode 100644
index 0000000..fd40a0e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/microblaze_v11_0_4
+vlib activehdl/xil_defaultlib
+vlib activehdl/lib_cdc_v1_0_2
+vlib activehdl/proc_sys_reset_v5_0_13
+vlib activehdl/lmb_v10_v3_0_11
+vlib activehdl/lmb_bram_if_cntlr_v4_0_19
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/iomodule_v3_1_6
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap microblaze_v11_0_4 activehdl/microblaze_v11_0_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 activehdl/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 activehdl/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 activehdl/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/file_info.txt
new file mode 100644
index 0000000..48f86b9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
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+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..20f6be7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/simulate.do
new file mode 100644
index 0000000..c364255
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_rdimm_x8_dual -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_rdimm_x8_dual.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/README.txt
new file mode 100644
index 0000000..cad0d93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/file_info.txt
new file mode 100644
index 0000000..1d20825
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..3ff2d6e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.sh
@@ -0,0 +1,182 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_rdimm_x8_dual \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/run.f
new file mode 100644
index 0000000..5804bac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/run.f
@@ -0,0 +1,113 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/microblaze_v11_0_4 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+-endlib
+-makelib ies_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib ies_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_v10_v3_0_11 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_bram_if_cntlr_v4_0_19 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/iomodule_v3_1_6 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/README.txt
new file mode 100644
index 0000000..5254a3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/compile.do
new file mode 100644
index 0000000..4189b83
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/compile.do
@@ -0,0 +1,137 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/microblaze_v11_0_4
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/lib_cdc_v1_0_2
+vlib modelsim_lib/msim/proc_sys_reset_v5_0_13
+vlib modelsim_lib/msim/lmb_v10_v3_0_11
+vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/iomodule_v3_1_6
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap microblaze_v11_0_4 modelsim_lib/msim/microblaze_v11_0_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 modelsim_lib/msim/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 modelsim_lib/msim/iomodule_v3_1_6
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -64 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -64 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -64 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -64 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -64 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/file_info.txt
new file mode 100644
index 0000000..48f86b9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
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+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..f6f7bba
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/simulate.do
new file mode 100644
index 0000000..efa07d3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {phy_rdimm_x8_dual.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/README.txt
new file mode 100644
index 0000000..5254a3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/compile.do
new file mode 100644
index 0000000..7436bae
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/compile.do
@@ -0,0 +1,137 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/microblaze_v11_0_4
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/lib_cdc_v1_0_2
+vlib questa_lib/msim/proc_sys_reset_v5_0_13
+vlib questa_lib/msim/lmb_v10_v3_0_11
+vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/iomodule_v3_1_6
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap microblaze_v11_0_4 questa_lib/msim/microblaze_v11_0_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 questa_lib/msim/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 questa_lib/msim/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 questa_lib/msim/iomodule_v3_1_6
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -64 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -64 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -64 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -64 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -64 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/elaborate.do
new file mode 100644
index 0000000..cc36de1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl -o phy_rdimm_x8_dual_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/file_info.txt
new file mode 100644
index 0000000..48f86b9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
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+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..e3d05fc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/simulate.do
new file mode 100644
index 0000000..74f65a1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib phy_rdimm_x8_dual_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {phy_rdimm_x8_dual.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/README.txt
new file mode 100644
index 0000000..5254a3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/compile.do
new file mode 100644
index 0000000..4dbd432
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/compile.do
@@ -0,0 +1,137 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/microblaze_v11_0_4
+vlib riviera/xil_defaultlib
+vlib riviera/lib_cdc_v1_0_2
+vlib riviera/proc_sys_reset_v5_0_13
+vlib riviera/lmb_v10_v3_0_11
+vlib riviera/lmb_bram_if_cntlr_v4_0_19
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/iomodule_v3_1_6
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2
+vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13
+vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11
+vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work microblaze_v11_0_4 -93 \
+"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+
+vcom -work lib_cdc_v1_0_2 -93 \
+"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+
+vcom -work proc_sys_reset_v5_0_13 -93 \
+"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+
+vcom -work lmb_v10_v3_0_11 -93 \
+"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+
+vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \
+"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+
+vcom -work iomodule_v3_1_6 -93 \
+"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/file_info.txt
new file mode 100644
index 0000000..48f86b9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
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+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..d7a697b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/simulate.do
new file mode 100644
index 0000000..c364255
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+phy_rdimm_x8_dual -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {phy_rdimm_x8_dual.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/README.txt
new file mode 100644
index 0000000..5254a3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/file_info.txt
new file mode 100644
index 0000000..1d20825
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..58ae743
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.sh
@@ -0,0 +1,346 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work microblaze_v11_0_4 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lmb_v10_v3_0_11 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work lmb_bram_if_cntlr_v4_0_19 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work iomodule_v3_1_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl -o phy_rdimm_x8_dual_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./phy_rdimm_x8_dual_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key phy_rdimm_x8_dual_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_rdimm_x8_dual_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/README.txt
new file mode 100644
index 0000000..cad0d93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/file_info.txt
new file mode 100644
index 0000000..1d20825
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/file_info.txt
@@ -0,0 +1,70 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_6,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..be05b23
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.sh
@@ -0,0 +1,182 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_rdimm_x8_dual \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/run.f
new file mode 100644
index 0000000..510c873
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/run.f
@@ -0,0 +1,113 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/microblaze_v11_0_4 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+-endlib
+-makelib xcelium_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+-endlib
+-makelib xcelium_lib/lmb_v10_v3_0_11 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+-endlib
+-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_19 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+-endlib
+-makelib xcelium_lib/iomodule_v3_1_6 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+  "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/README.txt
new file mode 100644
index 0000000..5254a3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_rdimm_x8_dual.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script.
+
+./phy_rdimm_x8_dual.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_rdimm_x8_dual.sh -noclean_files
+
+For more information on the script, please type './phy_rdimm_x8_dual.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/file_info.txt
new file mode 100644
index 0000000..2119c88
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/file_info.txt
@@ -0,0 +1,50 @@
+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+bd_afa8.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.h
new file mode 100755
index 0000000..ba46738
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.h
@@ -0,0 +1,477 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_H_
+#define IP_PHY_RDIMM_X8_DUAL_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "phy_rdimm_x8_dual_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc
+{
+public:
+
+  phy_rdimm_x8_dual(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_out< bool > c0_init_calib_complete;
+  sc_core::sc_out< bool > dbg_clk;
+  sc_core::sc_in< bool > c0_sys_clk_p;
+  sc_core::sc_in< bool > c0_sys_clk_n;
+  sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus;
+  sc_core::sc_out< bool > c0_ddr4_parity;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk;
+  sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+  sc_core::sc_in< bool > sys_rst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd;
+  sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done;
+  sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n;
+  sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn;
+  sc_core::sc_in< sc_dt::sc_bv<1> > winRmw;
+  sc_core::sc_in< bool > gt_data_ready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > winRank;
+  sc_core::sc_out< sc_dt::sc_bv<6> > tCWL;
+  sc_core::sc_in< sc_dt::sc_bv<576> > wrData;
+  sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask;
+  sc_core::sc_out< sc_dt::sc_bv<576> > rdData;
+  sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n;
+  sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT;
+  sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr;
+  sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr;
+  sc_core::sc_in< sc_dt::sc_bv<5> > winBuf;
+  sc_core::sc_out< bool > ddr4_act_n;
+  sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba;
+  sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg;
+  sc_core::sc_out< bool > ddr4_par;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt;
+  sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n;
+  sc_core::sc_out< bool > ddr4_ck_t;
+  sc_core::sc_out< bool > ddr4_ck_c;
+  sc_core::sc_out< bool > ddr4_reset_n;
+  sc_core::sc_out< bool > ddr4_parity;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n;
+  sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c;
+  sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t;
+  sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+
+  // Transactor stubs
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PHY_RDIMM_X8_DUAL_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.sh
new file mode 100755
index 0000000..47249e6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.sh
@@ -0,0 +1,214 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : phy_rdimm_x8_dual.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_rdimm_x8_dual.sh [-help]
+# usage: phy_rdimm_x8_dual.sh [-lib_map_path]
+# usage: phy_rdimm_x8_dual.sh [-noclean_files]
+# usage: phy_rdimm_x8_dual.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_rdimm_x8_dual xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim phy_rdimm_x8_dual -key {Behavioral:sim_1:Functional:phy_rdimm_x8_dual} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_rdimm_x8_dual.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\
+Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\
+Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\
+Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual_sc.h
new file mode 100755
index 0000000..cdbac59
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual_sc.h
@@ -0,0 +1,94 @@
+#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_
+#define IP_PHY_RDIMM_X8_DUAL_SC_H_
+
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class sim_ddr_v2_0;
+
+class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module
+{
+public:
+
+  phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm);
+  virtual ~phy_rdimm_x8_dual_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  sim_ddr_v2_0* mp_impl;
+
+private:
+
+  phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&);
+  const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&);
+
+};
+
+#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/sim_ddr_v2_0.h
new file mode 100755
index 0000000..8dc8c75
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/sim_ddr_v2_0.h
@@ -0,0 +1,221 @@
+// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "utils/xtlm_cmnhdr.h"
+#include "xtlm.h"
+#include "report_handler.h"
+#include <sstream>
+#ifdef SDACCEL_WITH_DATA_CONVERTER 
+#include "sdaccel_data_converter.h"
+#endif
+#include "sim_ddrx.h"
+#ifdef TLM2_PROTOCOL_CHEKER
+#include "tlm2_base_protocol_checker.h"
+#endif
+#ifndef sim_ddr_v2_0_H
+#define sim_ddr_v2_0_H
+#include "utils/xsc_stub_port.h"
+#include <utils/xtlm_aximm_passthru_module.h>
+class sim_ddr_v2_0 :public sc_module{
+  public:
+    explicit sim_ddr_v2_0(sc_core::sc_module_name name,
+        xsc::common_cpp::properties model_param_props);
+    ~sim_ddr_v2_0();
+
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket;
+    xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket;
+    
+    xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    SC_HAS_PROCESS(sim_ddr_v2_0);
+
+#ifdef SDACCEL_WITH_DATA_CONVERTER
+    sdaccel_data_converter* sdaccel_data_converter_model;
+#endif
+
+#ifdef TLM2_PROTOCOL_CHEKER        
+    tlm2_base_protocol_checker* checker;
+#endif
+    sc_core::sc_out<bool> c0_ddr4_ui_clk;	
+    sc_core::sc_in<bool> c0_ddr4_aresetn;
+    sc_core::sc_in<bool> sys_rst;
+    sc_core::sc_out< bool > c0_init_calib_complete;
+    sc_core::sc_out< bool > dbg_clk;
+    sc_core::sc_in< bool > c0_sys_clk_p;
+    sc_core::sc_in< bool > c0_sys_clk_n;
+    xsc::utils::xsc_stub_port dbg_bus;
+    xsc::utils::xsc_stub_port c0_ddr4_adr;
+    xsc::utils::xsc_stub_port c0_ddr4_ba;
+    xsc::utils::xsc_stub_port c0_ddr4_cke;
+    xsc::utils::xsc_stub_port c0_ddr4_cs_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port c0_ddr4_dq;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_c;
+    xsc::utils::xsc_stub_port c0_ddr4_dqs_t;
+    xsc::utils::xsc_stub_port c0_ddr4_odt;
+    xsc::utils::xsc_stub_port c0_ddr4_bg;
+    xsc::utils::xsc_stub_port c0_ddr4_parity;
+    xsc::utils::xsc_stub_port c0_ddr4_reset_n;
+    xsc::utils::xsc_stub_port c0_ddr4_act_n;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_c;
+    xsc::utils::xsc_stub_port c0_ddr4_ck_t;
+    xsc::utils::xsc_stub_port c0_ddr4_interrupt;
+    xsc::utils::xsc_stub_port addn_ui_clkout1;
+    xsc::utils::xsc_stub_port dbg_rd_data_cmp;
+    xsc::utils::xsc_stub_port dbg_expected_data;
+    xsc::utils::xsc_stub_port dbg_cal_seq;
+    xsc::utils::xsc_stub_port dbg_cal_seq_cnt;
+    xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt;
+    xsc::utils::xsc_stub_port dbg_rd_valid;
+    xsc::utils::xsc_stub_port dbg_cmp_byte;
+    xsc::utils::xsc_stub_port dbg_rd_data;
+    xsc::utils::xsc_stub_port dbg_cplx_config;
+    xsc::utils::xsc_stub_port dbg_cplx_status;
+    xsc::utils::xsc_stub_port dbg_io_address;
+    xsc::utils::xsc_stub_port dbg_pllGate;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low;
+    xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp;
+    xsc::utils::xsc_stub_port cal_r0_status;
+    xsc::utils::xsc_stub_port cal_post_status;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce;
+    xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete;
+    xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_req;
+    xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack;
+    xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error;
+    xsc::utils::xsc_stub_port c0_ddr4_app_addr;
+    xsc::utils::xsc_stub_port c0_ddr4_app_cmd;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data;
+    xsc::utils::xsc_stub_port c0_ddr4_app_en;
+    xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid;
+    xsc::utils::xsc_stub_port c0_ddr4_app_rdy;
+    xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy;
+    xsc::utils::xsc_stub_port rdDataEn;
+    xsc::utils::xsc_stub_port rdDataEnd;
+    xsc::utils::xsc_stub_port per_rd_done;
+    xsc::utils::xsc_stub_port rmw_rd_done;
+    xsc::utils::xsc_stub_port wrDataEn;
+    xsc::utils::xsc_stub_port mc_ACT_n;
+    xsc::utils::xsc_stub_port mcCasSlot;
+    xsc::utils::xsc_stub_port mcCasSlot2;
+    xsc::utils::xsc_stub_port mcRdCAS;
+    xsc::utils::xsc_stub_port mcWrCAS;
+    xsc::utils::xsc_stub_port winInjTxn;
+    xsc::utils::xsc_stub_port winRmw;
+    xsc::utils::xsc_stub_port gt_data_ready;
+    xsc::utils::xsc_stub_port winRank;
+    xsc::utils::xsc_stub_port tCWL;
+    xsc::utils::xsc_stub_port wrData;
+    xsc::utils::xsc_stub_port wrDataMask;
+    xsc::utils::xsc_stub_port rdData;
+    xsc::utils::xsc_stub_port mc_ADR;
+    xsc::utils::xsc_stub_port mc_BA;
+    xsc::utils::xsc_stub_port mc_CKE;
+    xsc::utils::xsc_stub_port mc_CS_n;
+    xsc::utils::xsc_stub_port mc_ODT;
+    xsc::utils::xsc_stub_port dBufAdr;
+    xsc::utils::xsc_stub_port rdDataAddr;
+    xsc::utils::xsc_stub_port wrDataAddr;
+    xsc::utils::xsc_stub_port winBuf;
+    xsc::utils::xsc_stub_port ddr4_act_n;
+    xsc::utils::xsc_stub_port ddr4_adr;
+    xsc::utils::xsc_stub_port ddr4_ba;
+    xsc::utils::xsc_stub_port ddr4_bg;
+    xsc::utils::xsc_stub_port ddr4_par;
+    xsc::utils::xsc_stub_port ddr4_cke;
+    xsc::utils::xsc_stub_port ddr4_odt;
+    xsc::utils::xsc_stub_port ddr4_cs_n;
+    xsc::utils::xsc_stub_port ddr4_ck_t;
+    xsc::utils::xsc_stub_port ddr4_ck_c;
+    xsc::utils::xsc_stub_port ddr4_reset_n;
+    xsc::utils::xsc_stub_port ddr4_dm_dbi_n;
+    xsc::utils::xsc_stub_port ddr4_dq;
+    xsc::utils::xsc_stub_port ddr4_dqs_c;
+    xsc::utils::xsc_stub_port ddr4_dqs_t;
+    xsc::utils::xsc_stub_port mc_BG;
+    
+    sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst;
+    sc_core::sc_in< bool > c0_sys_clk_i;
+    sc_core::sc_signal<bool>out1;
+    sc_core::sc_signal<bool>out2;
+    xsc::common_cpp::report_handler* m_report_handler;
+    std::stringstream m_ss;
+    float clk;
+    void generateReset();
+  protected:
+
+  private:
+    xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model;
+
+    std::map<std::string, int> user_param_int;
+    std::map<std::string, std::string> user_param_string;
+
+};
+#endif
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vhdl.prj
new file mode 100644
index 0000000..0382c33
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vhdl.prj
@@ -0,0 +1,12 @@
+vhdl xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vlog.prj
new file mode 100644
index 0000000..fdcf685
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vlog.prj
@@ -0,0 +1,47 @@
+verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \
+
+sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \
+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt
new file mode 100644
index 0000000..f904239
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do
new file mode 100644
index 0000000..b1b6b86
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh
new file mode 100755
index 0000000..1435f6c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do
new file mode 100644
index 0000000..357f2a3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+pr_read_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_read_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {pr_read_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt
new file mode 100644
index 0000000..d5ba57d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh
new file mode 100755
index 0000000..be93888
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.pr_read_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/run.f
new file mode 100644
index 0000000..ea2704b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/run.f
@@ -0,0 +1,29 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt
new file mode 100644
index 0000000..f904239
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do
new file mode 100644
index 0000000..83f62b1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do
@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh
new file mode 100755
index 0000000..6b34932
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do
new file mode 100644
index 0000000..9dd5de1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pr_read_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {pr_read_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt
new file mode 100644
index 0000000..f904239
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do
new file mode 100644
index 0000000..ddbc2f1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do
@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do
new file mode 100644
index 0000000..443408f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.pr_read_mem xil_defaultlib.glbl -o pr_read_mem_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh
new file mode 100755
index 0000000..6a63354
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do
new file mode 100644
index 0000000..4989f3c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib pr_read_mem_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {pr_read_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt
new file mode 100644
index 0000000..f904239
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do
new file mode 100644
index 0000000..6800dfd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh
new file mode 100755
index 0000000..afc4fb3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do
new file mode 100644
index 0000000..357f2a3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+pr_read_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_read_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {pr_read_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt
new file mode 100644
index 0000000..f904239
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh
new file mode 100755
index 0000000..32e2dec
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh
@@ -0,0 +1,247 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.pr_read_mem xil_defaultlib.glbl -o pr_read_mem_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./pr_read_mem_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key pr_read_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc pr_read_mem_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt
new file mode 100644
index 0000000..d5ba57d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt
new file mode 100644
index 0000000..00864a6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh
new file mode 100755
index 0000000..efe3f37
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_read_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.pr_read_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f
new file mode 100644
index 0000000..c99cd33
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f
@@ -0,0 +1,29 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt
new file mode 100644
index 0000000..f904239
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_read_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_read_mem.sh' script.
+
+./pr_read_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_read_mem.sh -noclean_files
+
+For more information on the script, please type './pr_read_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt
new file mode 100644
index 0000000..8baa891
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt
@@ -0,0 +1,2 @@
+pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe
new file mode 100755
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010000000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000001100101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif
new file mode 100755
index 0000000..ef3787e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif
@@ -0,0 +1,13 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010000000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001011000001100101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001001000001000101
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh
new file mode 100755
index 0000000..532cd8d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_read_mem.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_read_mem.sh [-help]
+# usage: pr_read_mem.sh [-lib_map_path]
+# usage: pr_read_mem.sh [-noclean_files]
+# usage: pr_read_mem.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pr_read_mem xil_defaultlib.pr_read_mem xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim pr_read_mem -key {Behavioral:sim_1:Functional:pr_read_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb pr_read_mem.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_read_mem.sh [-help]\n\
+Usage: pr_read_mem.sh [-lib_map_path]\n\
+Usage: pr_read_mem.sh [-reset_run]\n\
+Usage: pr_read_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log
new file mode 100755
index 0000000..abd7c4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [16]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj
new file mode 100644
index 0000000..47ef914
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt
new file mode 100644
index 0000000..2983911
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do
new file mode 100644
index 0000000..24a4914
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh
new file mode 100755
index 0000000..2c4cb46
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do
new file mode 100644
index 0000000..991d7aa
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+pr_ref_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_ref_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {pr_ref_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt
new file mode 100644
index 0000000..aeafe09
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh
new file mode 100755
index 0000000..e5319c6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.pr_ref_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f
new file mode 100644
index 0000000..1b0ab35
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f
@@ -0,0 +1,29 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt
new file mode 100644
index 0000000..2983911
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do
new file mode 100644
index 0000000..86720f7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do
@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh
new file mode 100755
index 0000000..de1374e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do
new file mode 100644
index 0000000..f3e4fcd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pr_ref_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {pr_ref_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt
new file mode 100644
index 0000000..2983911
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do
new file mode 100644
index 0000000..e4871d4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do
@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do
new file mode 100644
index 0000000..c4c1bb4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -o pr_ref_mem_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh
new file mode 100755
index 0000000..ffb79d8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do
new file mode 100644
index 0000000..44c93df
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib pr_ref_mem_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {pr_ref_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt
new file mode 100644
index 0000000..2983911
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do
new file mode 100644
index 0000000..115a790
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh
new file mode 100755
index 0000000..5803e51
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do
new file mode 100644
index 0000000..991d7aa
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+pr_ref_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_ref_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {pr_ref_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt
new file mode 100644
index 0000000..2983911
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh
new file mode 100755
index 0000000..faec53d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh
@@ -0,0 +1,247 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -o pr_ref_mem_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./pr_ref_mem_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key pr_ref_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc pr_ref_mem_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt
new file mode 100644
index 0000000..aeafe09
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt
new file mode 100644
index 0000000..b74ac4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh
new file mode 100755
index 0000000..d8ba376
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'pr_ref_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.pr_ref_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f
new file mode 100644
index 0000000..9e68376
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f
@@ -0,0 +1,29 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt
new file mode 100644
index 0000000..2983911
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./pr_ref_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './pr_ref_mem.sh' script.
+
+./pr_ref_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./pr_ref_mem.sh -noclean_files
+
+For more information on the script, please type './pr_ref_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt
new file mode 100644
index 0000000..ff9f878
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt
@@ -0,0 +1,2 @@
+pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe
new file mode 100755
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001101000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif
new file mode 100755
index 0000000..b3e8583
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif
@@ -0,0 +1,49 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001101000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh
new file mode 100755
index 0000000..04a3dfb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : pr_ref_mem.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: pr_ref_mem.sh [-help]
+# usage: pr_ref_mem.sh [-lib_map_path]
+# usage: pr_ref_mem.sh [-noclean_files]
+# usage: pr_ref_mem.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pr_ref_mem xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim pr_ref_mem -key {Behavioral:sim_1:Functional:pr_ref_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb pr_ref_mem.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: pr_ref_mem.sh [-help]\n\
+Usage: pr_ref_mem.sh [-lib_map_path]\n\
+Usage: pr_ref_mem.sh [-reset_run]\n\
+Usage: pr_ref_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj
new file mode 100644
index 0000000..c886734
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt
new file mode 100644
index 0000000..6aedcac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do
new file mode 100644
index 0000000..16739bc
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do
@@ -0,0 +1,47 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/fifo_generator_v13_2_5
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap fifo_generator_v13_2_5 activehdl/fifo_generator_v13_2_5
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_5  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_5 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_5  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh
new file mode 100755
index 0000000..e6fa5c8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do
new file mode 100644
index 0000000..85b1785
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+rdback_fifo -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rdback_fifo xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {rdback_fifo.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt
new file mode 100644
index 0000000..66cb393
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh
new file mode 100755
index 0000000..4e1e027
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm fifo_generator_v13_2_5 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.rdback_fifo \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/run.f
new file mode 100644
index 0000000..67477c0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/run.f
@@ -0,0 +1,35 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_5 \
+  "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_5 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_5 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt
new file mode 100644
index 0000000..6aedcac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do
new file mode 100644
index 0000000..2a07e86
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do
@@ -0,0 +1,47 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/fifo_generator_v13_2_5
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap fifo_generator_v13_2_5 modelsim_lib/msim/fifo_generator_v13_2_5
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_5 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_5 -64 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_5 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh
new file mode 100755
index 0000000..8596a31
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do
new file mode 100644
index 0000000..13d9d23
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {rdback_fifo.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt
new file mode 100644
index 0000000..6aedcac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do
new file mode 100644
index 0000000..593e8f3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do
@@ -0,0 +1,47 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/fifo_generator_v13_2_5
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap fifo_generator_v13_2_5 questa_lib/msim/fifo_generator_v13_2_5
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_5 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_5 -64 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_5 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do
new file mode 100644
index 0000000..e16495d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh
new file mode 100755
index 0000000..e466991
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do
new file mode 100644
index 0000000..36dd6b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib rdback_fifo_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {rdback_fifo.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt
new file mode 100644
index 0000000..6aedcac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do
new file mode 100644
index 0000000..75b575c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do
@@ -0,0 +1,47 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/fifo_generator_v13_2_5
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap fifo_generator_v13_2_5 riviera/fifo_generator_v13_2_5
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_5  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_5 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_5  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh
new file mode 100755
index 0000000..1a4dd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do
new file mode 100644
index 0000000..85b1785
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+rdback_fifo -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rdback_fifo xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {rdback_fifo.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt
new file mode 100644
index 0000000..6aedcac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh
new file mode 100755
index 0000000..4f840a9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh
@@ -0,0 +1,255 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm fifo_generator_v13_2_5 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work fifo_generator_v13_2_5 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./rdback_fifo_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key rdback_fifo_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rdback_fifo_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt
new file mode 100644
index 0000000..66cb393
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt
new file mode 100644
index 0000000..b3bd811
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt
@@ -0,0 +1,18 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh
new file mode 100755
index 0000000..b1f1037
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm fifo_generator_v13_2_5 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.rdback_fifo \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f
new file mode 100644
index 0000000..415504c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f
@@ -0,0 +1,35 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/fifo_generator_v13_2_5 \
+  "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+-endlib
+-makelib xcelium_lib/fifo_generator_v13_2_5 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/fifo_generator_v13_2_5 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt
new file mode 100644
index 0000000..6aedcac
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt
new file mode 100644
index 0000000..4ebc368
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt
@@ -0,0 +1,2 @@
+rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh
new file mode 100755
index 0000000..199b134
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh
@@ -0,0 +1,214 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rdback_fifo xil_defaultlib.rdback_fifo xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim rdback_fifo -key {Behavioral:sim_1:Functional:rdback_fifo} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rdback_fifo.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj
new file mode 100644
index 0000000..359cbd5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj
@@ -0,0 +1,2 @@
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj
new file mode 100644
index 0000000..094bca5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt
new file mode 100644
index 0000000..2eae1bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do
new file mode 100644
index 0000000..ef7be87
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh
new file mode 100755
index 0000000..62643c3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do
new file mode 100644
index 0000000..6c79e4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+scratchpad -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.scratchpad xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {scratchpad.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/README.txt
new file mode 100644
index 0000000..7abac0d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/run.f
new file mode 100644
index 0000000..af75aa4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/run.f
@@ -0,0 +1,29 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh
new file mode 100755
index 0000000..8784621
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.scratchpad \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt
new file mode 100644
index 0000000..2eae1bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do
new file mode 100644
index 0000000..e8c4be4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do
@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh
new file mode 100755
index 0000000..e0a9ed5
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do
new file mode 100644
index 0000000..6e1a057
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.scratchpad xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {scratchpad.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/README.txt
new file mode 100644
index 0000000..2eae1bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/compile.do
new file mode 100644
index 0000000..78fc227
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/compile.do
@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do
new file mode 100644
index 0000000..f4279c7
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.scratchpad xil_defaultlib.glbl -o scratchpad_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh
new file mode 100755
index 0000000..26758fa
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/simulate.do
new file mode 100644
index 0000000..aa4b5cd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib scratchpad_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {scratchpad.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/README.txt
new file mode 100644
index 0000000..2eae1bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do
new file mode 100644
index 0000000..ffa5c78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh
new file mode 100755
index 0000000..2baf52b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do
new file mode 100644
index 0000000..6c79e4a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+scratchpad -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.scratchpad xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {scratchpad.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/README.txt
new file mode 100644
index 0000000..2eae1bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh
new file mode 100755
index 0000000..886794d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh
@@ -0,0 +1,247 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.scratchpad xil_defaultlib.glbl -o scratchpad_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./scratchpad_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key scratchpad_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc scratchpad_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt
new file mode 100644
index 0000000..7abac0d
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt
new file mode 100644
index 0000000..df82e18
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/run.f
new file mode 100644
index 0000000..fe626da
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/run.f
@@ -0,0 +1,29 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh
new file mode 100755
index 0000000..5f71422
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'scratchpad.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.scratchpad \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/README.txt
new file mode 100644
index 0000000..2eae1bd
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./scratchpad.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './scratchpad.sh' script.
+
+./scratchpad.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./scratchpad.sh -noclean_files
+
+For more information on the script, please type './scratchpad.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt
new file mode 100644
index 0000000..a593cef
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt
@@ -0,0 +1,2 @@
+scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh
new file mode 100755
index 0000000..3ee51c2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : scratchpad.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: scratchpad.sh [-help]
+# usage: scratchpad.sh [-lib_map_path]
+# usage: scratchpad.sh [-noclean_files]
+# usage: scratchpad.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot scratchpad xil_defaultlib.scratchpad xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim scratchpad -key {Behavioral:sim_1:Functional:scratchpad} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb scratchpad.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: scratchpad.sh [-help]\n\
+Usage: scratchpad.sh [-lib_map_path]\n\
+Usage: scratchpad.sh [-reset_run]\n\
+Usage: scratchpad.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/summary.log
new file mode 100755
index 0000000..28dc68a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [32]
+Port A Write Width         :     [32]
+Memory Depth               :     [1024]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     2.119075 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj
new file mode 100644
index 0000000..cd813ef
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/README.txt
new file mode 100644
index 0000000..80d792b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/compile.do
new file mode 100644
index 0000000..030f535
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/compile.do
@@ -0,0 +1,122 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/gtwizard_ultrascale_v1_7_9
+vlib activehdl/xil_defaultlib
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xdma_v4_1_8
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap gtwizard_ultrascale_v1_7_9 activehdl/gtwizard_ultrascale_v1_7_9
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xdma_v4_1_8 activehdl/xdma_v4_1_8
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work gtwizard_ultrascale_v1_7_9  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+
+vlog -work xdma_v4_1_8  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt
new file mode 100644
index 0000000..4b7b0db
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
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+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/simulate.do
new file mode 100644
index 0000000..34e7202
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+xdma -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.xdma xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {xdma.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh
new file mode 100755
index 0000000..9f94baf
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/README.txt
new file mode 100644
index 0000000..4fcaf1f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/file_info.txt
new file mode 100644
index 0000000..06871a0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/run.f
new file mode 100644
index 0000000..b87a2cf
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/run.f
@@ -0,0 +1,106 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/gtwizard_ultrascale_v1_7_9 \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+-endlib
+-makelib ies_lib/xdma_v4_1_8 -sv \
+  "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+-endlib
+-makelib ies_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/xdma.sh
new file mode 100755
index 0000000..7e1b3b4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/xdma.sh
@@ -0,0 +1,180 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm gtwizard_ultrascale_v1_7_9 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_8)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.xdma \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \
+       +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \
+       +incdir+"../../../ipstatic/hdl/verilog" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/README.txt
new file mode 100644
index 0000000..80d792b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/compile.do
new file mode 100644
index 0000000..c8f906f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/compile.do
@@ -0,0 +1,122 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/gtwizard_ultrascale_v1_7_9
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xdma_v4_1_8
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap gtwizard_ultrascale_v1_7_9 modelsim_lib/msim/gtwizard_ultrascale_v1_7_9
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xdma_v4_1_8 modelsim_lib/msim/xdma_v4_1_8
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work gtwizard_ultrascale_v1_7_9 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+
+vlog -work xdma_v4_1_8 -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+
+vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt
new file mode 100644
index 0000000..4b7b0db
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/simulate.do
new file mode 100644
index 0000000..dc180fb
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.xdma xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {xdma.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh
new file mode 100755
index 0000000..95e2767
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/README.txt
new file mode 100644
index 0000000..80d792b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/compile.do
new file mode 100644
index 0000000..3de0736
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/compile.do
@@ -0,0 +1,122 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/gtwizard_ultrascale_v1_7_9
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xdma_v4_1_8
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap gtwizard_ultrascale_v1_7_9 questa_lib/msim/gtwizard_ultrascale_v1_7_9
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xdma_v4_1_8 questa_lib/msim/xdma_v4_1_8
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work gtwizard_ultrascale_v1_7_9 -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+
+vlog -work xdma_v4_1_8 -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+
+vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/elaborate.do
new file mode 100644
index 0000000..33613c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.xdma xil_defaultlib.glbl -o xdma_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/file_info.txt
new file mode 100644
index 0000000..4b7b0db
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/simulate.do
new file mode 100644
index 0000000..76f4faa
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib xdma_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {xdma.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.sh
new file mode 100755
index 0000000..fbc7127
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/README.txt
new file mode 100644
index 0000000..80d792b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/compile.do
new file mode 100644
index 0000000..e219d31
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/compile.do
@@ -0,0 +1,122 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/gtwizard_ultrascale_v1_7_9
+vlib riviera/xil_defaultlib
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xdma_v4_1_8
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap gtwizard_ultrascale_v1_7_9 riviera/gtwizard_ultrascale_v1_7_9
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xdma_v4_1_8 riviera/xdma_v4_1_8
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work gtwizard_ultrascale_v1_7_9  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+
+vlog -work xdma_v4_1_8  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/file_info.txt
new file mode 100644
index 0000000..4b7b0db
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
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+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/simulate.do
new file mode 100644
index 0000000..34e7202
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+xdma -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.xdma xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {xdma.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.sh
new file mode 100755
index 0000000..92736d2
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/README.txt
new file mode 100644
index 0000000..80d792b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/file_info.txt
new file mode 100644
index 0000000..06871a0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/xdma.sh
new file mode 100755
index 0000000..865fe76
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/xdma.sh
@@ -0,0 +1,328 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm gtwizard_ultrascale_v1_7_9 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_8)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work gtwizard_ultrascale_v1_7_9 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+    "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xdma_v4_1_8 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.xdma xil_defaultlib.glbl -o xdma_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./xdma_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key xdma_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc xdma_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/README.txt
new file mode 100644
index 0000000..4fcaf1f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt
new file mode 100644
index 0000000..06871a0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt
@@ -0,0 +1,85 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/run.f
new file mode 100644
index 0000000..5b72987
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/run.f
@@ -0,0 +1,106 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/gtwizard_ultrascale_v1_7_9 \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \
+  "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+  "../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+-endlib
+-makelib xcelium_lib/xdma_v4_1_8 -sv \
+  "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+  "../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh
new file mode 100755
index 0000000..e70b217
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh
@@ -0,0 +1,180 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'xdma.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm gtwizard_ultrascale_v1_7_9 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_8)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.xdma \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \
+       +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \
+       +incdir+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \
+       +incdir+"../../../ipstatic/hdl/verilog" \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/README.txt
new file mode 100644
index 0000000..80d792b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./xdma.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './xdma.sh' script.
+
+./xdma.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./xdma.sh -noclean_files
+
+For more information on the script, please type './xdma.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/file_info.txt
new file mode 100644
index 0000000..31e1717
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/file_info.txt
@@ -0,0 +1,47 @@
+gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/vlog.prj
new file mode 100644
index 0000000..27b76e4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/vlog.prj
@@ -0,0 +1,53 @@
+verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \
+"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \
+
+sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \
+"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/xdma.sh
new file mode 100755
index 0000000..016da74
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/xdma.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : xdma.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: xdma.sh [-help]
+# usage: xdma.sh [-lib_map_path]
+# usage: xdma.sh [-noclean_files]
+# usage: xdma.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot xdma xil_defaultlib.xdma xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim xdma -key {Behavioral:sim_1:Functional:xdma} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=(xil_defaultlib)
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb xdma.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: xdma.sh [-help]\n\
+Usage: xdma.sh [-lib_map_path]\n\
+Usage: xdma.sh [-reset_run]\n\
+Usage: xdma.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/README.txt
new file mode 100644
index 0000000..5acdd2f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt
new file mode 100644
index 0000000..9c5c2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do
new file mode 100644
index 0000000..ebe0a4e
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xilinx_vip
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_4
+vlib activehdl/xil_defaultlib
+
+vmap xilinx_vip activehdl/xilinx_vip
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do
new file mode 100644
index 0000000..98824fe
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+zq_calib_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.zq_calib_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {zq_calib_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh
new file mode 100755
index 0000000..c698103
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt
new file mode 100644
index 0000000..c57722c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f
new file mode 100644
index 0000000..123f2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f
@@ -0,0 +1,29 @@
+-makelib ies_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh
new file mode 100755
index 0000000..c2171a1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.zq_calib_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt
new file mode 100644
index 0000000..9c5c2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do
new file mode 100644
index 0000000..ca24810
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do
@@ -0,0 +1,41 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xilinx_vip
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_4
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xilinx_vip modelsim_lib/msim/xilinx_vip
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do
new file mode 100644
index 0000000..05efcd8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.zq_calib_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {zq_calib_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh
new file mode 100755
index 0000000..e158b8a
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt
new file mode 100644
index 0000000..9c5c2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do
new file mode 100644
index 0000000..01d7b08
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do
@@ -0,0 +1,41 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xilinx_vip
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_4
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xilinx_vip questa_lib/msim/xilinx_vip
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do
new file mode 100644
index 0000000..c1d3233
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -o zq_calib_mem_opt
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do
new file mode 100644
index 0000000..c04f9f4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib zq_calib_mem_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {zq_calib_mem.udo}
+
+run -all
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh
new file mode 100755
index 0000000..6e09ac3
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt
new file mode 100644
index 0000000..9c5c2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do
new file mode 100644
index 0000000..f940f79
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do
@@ -0,0 +1,41 @@
+vlib work
+vlib riviera
+
+vlib riviera/xilinx_vip
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_4
+vlib riviera/xil_defaultlib
+
+vmap xilinx_vip riviera/xilinx_vip
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xilinx_vip  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+
+vlog -work xpm  -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_4  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do
new file mode 100644
index 0000000..98824fe
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+zq_calib_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.zq_calib_mem xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {zq_calib_mem.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh
new file mode 100755
index 0000000..0138397
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo
new file mode 100644
index 0000000..e69de29
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt
new file mode 100644
index 0000000..9c5c2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do
new file mode 100644
index 0000000..58afc78
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh
new file mode 100755
index 0000000..095e6f1
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh
@@ -0,0 +1,247 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \
+    "$ref_dir/../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -o zq_calib_mem_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./zq_calib_mem_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key zq_calib_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc zq_calib_mem_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt
new file mode 100644
index 0000000..c57722c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt
new file mode 100644
index 0000000..6503f24
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt
@@ -0,0 +1,16 @@
+axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
+axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
+xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
+axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
+axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,
+axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
+axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,
+clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,
+rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f
new file mode 100644
index 0000000..53b8cb9
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f
@@ -0,0 +1,29 @@
+-makelib xcelium_lib/xilinx_vip -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
+-endlib
+-makelib xcelium_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh
new file mode 100755
index 0000000..72db278
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'zq_calib_mem.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.zq_calib_mem \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt
new file mode 100644
index 0000000..9c5c2d0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./zq_calib_mem.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './zq_calib_mem.sh' script.
+
+./zq_calib_mem.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./zq_calib_mem.sh -noclean_files
+
+For more information on the script, please type './zq_calib_mem.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/U200.smi
new file mode 100644
index 0000000..f20b0a8
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/U200.smi
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Nov 18 2020                                             -->
+<!--                                                         -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
+    <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
+      <BusBlock>
+        <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="16383"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl
new file mode 100644
index 0000000..eef7a0f
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt
new file mode 100644
index 0000000..cacfd7c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt
@@ -0,0 +1,2 @@
+zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe
new file mode 100755
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
+0001100000000000000000000000000000000000010100000000000000000000,
+0001100000000000000000000000000000000000011000000000000000000000,
+1111000000000000111100000000000011110000000000001010100000000101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001100000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst
new file mode 100644
index 0000000..cf73fce
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_9f2c": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_afa8.protoinst
new file mode 100644
index 0000000..a0656b6
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_afa8.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_afa8": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_ba6a.protoinst
new file mode 100644
index 0000000..c42e1c4
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_ba6a.protoinst
@@ -0,0 +1,9 @@
+{
+	"version": "1.0",
+	"modules": {
+		"bd_ba6a": {
+			"proto_instances": {
+			}
+		}
+	}
+}
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log
new file mode 100755
index 0000000..7930542
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log
@@ -0,0 +1,20 @@
+
+User Configuration
+--------------------------------------------------------------------------------
+Algorithm                  :     Minimum_Area
+Memory Type                :     Single_Port_RAM
+Port A Read Width          :     [64]
+Port A Write Width         :     [64]
+Memory Depth               :     [64]
+
+----------------------------------------------------------------------------------
+
+Block RAM resource(s) (18K BRAMs)    : [0]
+Block RAM resource(s) (36K BRAMs)    : [1]
+----------------------------------------------------------------------------------
+Clock A Frequency          :         [100]
+Port A Enable Rate         :         [100]
+Port A Write Rate          :         [50]
+----------------------------------------------------------------------------------
+Estimated Power for IP     :     5.931282 mW
+----------------------------------------------------------------------------------
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj
new file mode 100644
index 0000000..c533a42
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj
@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif
new file mode 100755
index 0000000..fdf3bb0
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif
@@ -0,0 +1,40 @@
+0001100000000000000000000000000000000000010000000000000000000000
+0001100000000000000000000000000000000000010100000000000000000000
+0001100000000000000000000000000000000000011000000000000000000000
+1111000000000000111100000000000011110000000000001010100000000101
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001100000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
+1111000000000000111100000000000011110000000000001111000000000000
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh
new file mode 100755
index 0000000..0dd964b
--- /dev/null
+++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : zq_calib_mem.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: zq_calib_mem.sh [-help]
+# usage: zq_calib_mem.sh [-lib_map_path]
+# usage: zq_calib_mem.sh [-noclean_files]
+# usage: zq_calib_mem.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax -L xdma_v4_1_8"
+
+
+# Script info
+echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot zq_calib_mem xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim zq_calib_mem -key {Behavioral:sim_1:Functional:zq_calib_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb zq_calib_mem.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: zq_calib_mem.sh [-help]\n\
+Usage: zq_calib_mem.sh [-lib_map_path]\n\
+Usage: zq_calib_mem.sh [-reset_run]\n\
+Usage: zq_calib_mem.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci
new file mode 100644
index 0000000..dd35b7f
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci
@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>axis_clock_converter</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_clock_converter" spirit:version="1.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_RSTIF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_RSTIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_RSTIF.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_RSTIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_SIGNAL_SET">0b00000000000000000000000000011011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_ACLK_ASYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_ACLK_RATIO">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_ACLK_RATIO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLK_RATIO">1:2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axis_clock_converter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_ACLK_ASYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">21</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml
new file mode 100644
index 0000000..f22c124
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xml
@@ -0,0 +1,1514 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>axis_clock_converter</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS</spirit:name>
+      <spirit:displayName>S_AXIS</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS</spirit:name>
+      <spirit:displayName>M_AXIS</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_RSTIF</spirit:name>
+      <spirit:displayName>S_RSTIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_RSTIF.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_RSTIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_RSTIF</spirit:name>
+      <spirit:displayName>M_RSTIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_RSTIF.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_RSTIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_CLKIF</spirit:name>
+      <spirit:displayName>S_CLKIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_CLKIF</spirit:name>
+      <spirit:displayName>M_CLKIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_CLKENIF</spirit:name>
+      <spirit:displayName>S_CLKENIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clockenable" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clockenable_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aclken</spirit:name>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci
new file mode 100644
index 0000000..76ea065
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xci
@@ -0,0 +1,133 @@
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;s_axis_aresetn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_aresetn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_aclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_tvalid&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_tready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_tdata&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_tkeep&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_tlast&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_aclk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_tvalid&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_tready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_tdata&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_tkeep&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;phys
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+physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;s_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;s_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;M_AXIS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;H
+AS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;m_axis_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logic
+al_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;m_axis_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;m_axis_tdata&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;m_axis_tkeep&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;m_axis_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;S_RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;s_axis_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;
+M_RSTIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;m_axis_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;S_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:
+&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;s_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;M_CLKIF&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;gen
+erated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;m_axis_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml
new file mode 100644
index 0000000..e58898e
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/axis_clock_converter_1/axis_clock_converter.xml
@@ -0,0 +1,1478 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>axis_clock_converter</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS</spirit:name>
+      <spirit:displayName>S_AXIS</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS</spirit:name>
+      <spirit:displayName>M_AXIS</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_RSTIF</spirit:name>
+      <spirit:displayName>S_RSTIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_RSTIF.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_RSTIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_RSTIF</spirit:name>
+      <spirit:displayName>M_RSTIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_RSTIF.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_RSTIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_CLKIF</spirit:name>
+      <spirit:displayName>S_CLKIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_CLKIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_CLKIF</spirit:name>
+      <spirit:displayName>M_CLKIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_CLKIF.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_CLKENIF</spirit:name>
+      <spirit:displayName>S_CLKENIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clockenable" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clockenable_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_aclken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_CLKENIF.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_CLKENIF" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.ACLKEN_CONV_MODE&apos;)) = 1) or (spirit:decode(id(&apos;PARAM_VALUE.ACLKEN_CONV_MODE&apos;)) = 3)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_CLKENIF</spirit:name>
+      <spirit:displayName>M_CLKENIF</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clockenable" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clockenable_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_aclken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_CLKENIF.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_CLKENIF" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.ACLKEN_CONV_MODE&apos;)) > 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>s_axis_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_axis_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axis_aclken</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:bitStringLength="1">0x1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_aclken" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.ACLKEN_CONV_MODE&apos;)) = 1) or (spirit:decode(id(&apos;PARAM_VALUE.ACLKEN_CONV_MODE&apos;)) = 3)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>m_axis_aclken</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXIS_ACLK_RATIO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXIS_ACLK_RATIO">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXIS_ACLK_RATIO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXIS_ACLK_RATIO">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ACLKEN_CONV_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ACLKEN_CONV_MODE">0</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
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+    <spirit:choice>
+      <spirit:name>choice_list_27ecedf0</spirit:name>
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+      <spirit:enumeration>13:1</spirit:enumeration>
+      <spirit:enumeration>12:1</spirit:enumeration>
+      <spirit:enumeration>11:1</spirit:enumeration>
+      <spirit:enumeration>10:1</spirit:enumeration>
+      <spirit:enumeration>9:1</spirit:enumeration>
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+      <spirit:enumeration>1:7</spirit:enumeration>
+      <spirit:enumeration>1:8</spirit:enumeration>
+      <spirit:enumeration>1:9</spirit:enumeration>
+      <spirit:enumeration>1:10</spirit:enumeration>
+      <spirit:enumeration>1:11</spirit:enumeration>
+      <spirit:enumeration>1:12</spirit:enumeration>
+      <spirit:enumeration>1:13</spirit:enumeration>
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+      <spirit:enumeration spirit:text="Yes">1</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_pairs_7e3eb5e2</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="S AXIS Only">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="M AXIS Only">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="S AXIS M AXIS">3</spirit:enumeration>
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+  </spirit:choices>
+  <spirit:description>The AXI4-Stream Clock Converter IP provides the infrastructure to change the clocking rate between a AXI4-Stream master and slave.</spirit:description>
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+      <spirit:displayName>TDATA Width (bytes)</spirit:displayName>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TID_WIDTH</spirit:name>
+      <spirit:displayName>TID Width (bits)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TID_WIDTH" spirit:order="3" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
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+        <xilinx:parameterInfo>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TDEST_WIDTH</spirit:name>
+      <spirit:displayName>TDEST Width (bits)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TDEST_WIDTH" spirit:order="4" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TUSER_WIDTH</spirit:name>
+      <spirit:displayName>TUSER Width (bits)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TUSER_WIDTH" spirit:order="5" spirit:minimum="0" spirit:maximum="4096" spirit:rangeType="long">0</spirit:value>
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+        <xilinx:parameterInfo>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_ACLK_ASYNC</spirit:name>
+      <spirit:displayName>Asynchronous Clocks</spirit:displayName>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>HAS_TSTRB</spirit:name>
+      <spirit:displayName>Enable TSTRB</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_TSTRB" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="7">0</spirit:value>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>HAS_TKEEP</spirit:name>
+      <spirit:displayName>Enable TKEEP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_TKEEP" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="8">1</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>HAS_TLAST</spirit:name>
+      <spirit:displayName>Enable TLAST</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_TLAST" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="9">1</spirit:value>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages across Cross Clock Domain Logic</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNCHRONIZATION_STAGES" spirit:order="10" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">2</spirit:value>
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+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLKEN_CONV_MODE</spirit:name>
+      <spirit:displayName>ACLKEN Conversion Mode</spirit:displayName>
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+    <spirit:parameter>
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+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI4-Stream Clock Converter</xilinx:displayName>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
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+    <xilinx:packagingInfo>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci
new file mode 100644
index 0000000..83d955e
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci
@@ -0,0 +1,327 @@
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     7.524303 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">instr_blk_mem.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">instr_blk_mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;10&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;va
+lue_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissi
+on&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;10&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;10&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_
+left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml
new file mode 100644
index 0000000..471bbb6
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xml
@@ -0,0 +1,4182 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>instr_blk_mem</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">10</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">instr_blk_mem.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2048</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">2048</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">2048</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">2048</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     7.524303 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0e6ad450</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+      <spirit:enumeration>2048</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">instr_blk_mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Single_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">2048</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_0e6ad450" spirit:order="22">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="25">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="26">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Always_Enabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci
new file mode 100644
index 0000000..9432348
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci
@@ -0,0 +1,330 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">instr_blk_mem_sim.mif</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">instr_blk_mem_sim</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+          <xilinx:configElementInfos>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;9&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;val
+ue_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissio
+n&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;9&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;9&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_lef
+t&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
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+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xml b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xml
new file mode 100644
index 0000000..9c61605
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xml
@@ -0,0 +1,4185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>instr_blk_mem_sim</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">9</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_READ_WIDTH_A&apos;))-1">63</spirit:left>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_rid</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_rready</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_injectsbiterr</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>s_axi_injectdbiterr</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_sbiterr</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
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+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">instr_blk_mem_sim.mif</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">instr_blk_mem_sim.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     4.238151 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0e6ad450</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+      <spirit:enumeration>2048</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">instr_blk_mem_sim</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Single_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">1024</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_0e6ad450" spirit:order="22">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="25">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="26">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Always_Enabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">../../../../coe/simmem.coe</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_27c66b0d" spirit:order="3">Stand_Alone</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">no_mem_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9c3516e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd
new file mode 100644
index 0000000..f3a1633
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bd
@@ -0,0 +1,513 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0xBCE55F3980178BC9",
+      "design_src": "SBD",
+      "device": "xcu200-fsgd2104-2-e",
+      "name": "bd_9f2c",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "scoped": "true",
+      "synth_flow_mode": "None",
+      "tool_version": "2020.2",
+      "validated": "true"
+    },
+    "design_tree": {
+      "microblaze_I": "",
+      "rst_0": "",
+      "ilmb": "",
+      "dlmb": "",
+      "dlmb_cntlr": "",
+      "ilmb_cntlr": "",
+      "lmb_bram_I": "",
+      "second_dlmb_cntlr": "",
+      "second_ilmb_cntlr": "",
+      "second_lmb_bram_I": "",
+      "iomodule_0": ""
+    },
+    "interface_ports": {
+      "IO": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:mcsio_bus_rtl:1.0"
+      },
+      "TRACE": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:mbtrace_rtl:2.0"
+      }
+    },
+    "ports": {
+      "Clk": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "ASSOCIATED_ASYNC_RESET": {
+            "value": "Reset"
+          },
+          "CLK_DOMAIN": {
+            "value": "bd_9f2c_Clk",
+            "value_src": "constant"
+          },
+          "FREQ_HZ": {
+            "value": "100000000"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.000",
+            "value_src": "default"
+          }
+        }
+      },
+      "Reset": {
+        "type": "rst",
+        "direction": "I",
+        "parameters": {
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "POLARITY": {
+            "value": "ACTIVE_HIGH"
+          }
+        }
+      }
+    },
+    "components": {
+      "microblaze_I": {
+        "vlnv": "xilinx.com:ip:microblaze:11.0",
+        "xci_name": "bd_9f2c_microblaze_I_0",
+        "parameters": {
+          "C_ASYNC_WAKEUP": {
+            "value": "3"
+          },
+          "C_DEBUG_ENABLED": {
+            "value": "0"
+          },
+          "C_FAULT_TOLERANT": {
+            "value": "0"
+          },
+          "C_INSTANCE": {
+            "value": "mb_microblaze_0"
+          },
+          "C_PC_WIDTH": {
+            "value": "17"
+          },
+          "C_TRACE": {
+            "value": "1"
+          },
+          "C_USE_BARREL": {
+            "value": "1"
+          },
+          "C_USE_DIV": {
+            "value": "1"
+          },
+          "C_USE_EXT_BRK": {
+            "value": "0"
+          },
+          "C_USE_EXT_NM_BRK": {
+            "value": "0"
+          },
+          "C_USE_HW_MUL": {
+            "value": "1"
+          },
+          "C_USE_PCMP_INSTR": {
+            "value": "1"
+          },
+          "C_USE_REORDER_INSTR": {
+            "value": "0"
+          }
+        },
+        "addressing": {
+          "address_spaces": {
+            "Data": {
+              "range": "4G",
+              "width": "32"
+            },
+            "Instruction": {
+              "range": "4G",
+              "width": "32"
+            }
+          }
+        },
+        "interface_ports": {
+          "DLMB": {
+            "mode": "Master",
+            "address_space_ref": "Data",
+            "base_address": {
+              "minimum": "0x00000000",
+              "maximum": "0xFFFFFFFF",
+              "width": "32"
+            }
+          },
+          "ILMB": {
+            "mode": "Master",
+            "address_space_ref": "Instruction",
+            "base_address": {
+              "minimum": "0x00000000",
+              "maximum": "0xFFFFFFFF",
+              "width": "32"
+            }
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_PROCESSOR": {
+            "value": "microblaze-le > bd_9f2c dlmb_cntlr",
+            "value_src": "default"
+          },
+          "KEEP_HIERARCHY": {
+            "value": "yes",
+            "value_src": "default"
+          }
+        }
+      },
+      "rst_0": {
+        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
+        "xci_name": "bd_9f2c_rst_0_0"
+      },
+      "ilmb": {
+        "vlnv": "xilinx.com:ip:lmb_v10:3.0",
+        "xci_name": "bd_9f2c_ilmb_0",
+        "parameters": {
+          "C_LMB_NUM_SLAVES": {
+            "value": "2"
+          }
+        },
+        "interface_ports": {
+          "LMB_M": {
+            "mode": "MirroredMaster",
+            "bridges": [
+              "LMB_Sl_0",
+              "LMB_Sl_1"
+            ]
+          }
+        }
+      },
+      "dlmb": {
+        "vlnv": "xilinx.com:ip:lmb_v10:3.0",
+        "xci_name": "bd_9f2c_dlmb_0",
+        "parameters": {
+          "C_LMB_NUM_SLAVES": {
+            "value": "3"
+          }
+        },
+        "interface_ports": {
+          "LMB_M": {
+            "mode": "MirroredMaster",
+            "bridges": [
+              "LMB_Sl_0",
+              "LMB_Sl_1",
+              "LMB_Sl_2"
+            ]
+          }
+        }
+      },
+      "dlmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_9f2c_dlmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000000000FFFF"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0010000"
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_ADDRESS_SPACE": {
+            "value": "byte  0x00000000 32 >  bd_9f2c lmb_bram_I bd_9f2c second_lmb_bram_I",
+            "value_src": "default"
+          },
+          "KEEP_HIERARCHY": {
+            "value": "yes",
+            "value_src": "default"
+          }
+        }
+      },
+      "ilmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_9f2c_ilmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000000000FFFF"
+          },
+          "C_MASK": {
+            "value": "0x0000000080010000"
+          }
+        }
+      },
+      "lmb_bram_I": {
+        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
+        "xci_name": "bd_9f2c_lmb_bram_I_0",
+        "parameters": {
+          "Memory_Type": {
+            "value": "True_Dual_Port_RAM"
+          }
+        }
+      },
+      "second_dlmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_9f2c_second_dlmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000010000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x0000000000017FFF"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0010000"
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_ADDRESS_RANGE": {
+            "value": " ",
+            "value_src": "default"
+          }
+        }
+      },
+      "second_ilmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_9f2c_second_ilmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000010000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x0000000000017FFF"
+          },
+          "C_MASK": {
+            "value": "0x0000000080010000"
+          }
+        }
+      },
+      "second_lmb_bram_I": {
+        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
+        "xci_name": "bd_9f2c_second_lmb_bram_I_0",
+        "parameters": {
+          "Memory_Type": {
+            "value": "True_Dual_Port_RAM"
+          }
+        }
+      },
+      "iomodule_0": {
+        "vlnv": "xilinx.com:ip:iomodule:3.1",
+        "xci_name": "bd_9f2c_iomodule_0_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000080000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000008000FFFF"
+          },
+          "C_INSTANCE": {
+            "value": "iomodule"
+          },
+          "C_INTC_ADDR_WIDTH": {
+            "value": "17"
+          },
+          "C_INTC_HAS_FAST": {
+            "value": "1"
+          },
+          "C_INTC_USE_IRQ_OUT": {
+            "value": "1"
+          },
+          "C_IO_BASEADDR": {
+            "value": "0x00000000C0000000"
+          },
+          "C_IO_HIGHADDR": {
+            "value": "0x00000000FFFFFFFF"
+          },
+          "C_IO_MASK": {
+            "value": "0x00000000C0000000"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0000000"
+          },
+          "C_USE_IO_BUS": {
+            "value": "1"
+          }
+        }
+      }
+    },
+    "interface_nets": {
+      "iomodule_0_IO": {
+        "interface_ports": [
+          "IO",
+          "iomodule_0/IO_BUS"
+        ]
+      },
+      "ilmb": {
+        "interface_ports": [
+          "microblaze_I/ILMB",
+          "ilmb/LMB_M"
+        ]
+      },
+      "dlmb": {
+        "interface_ports": [
+          "microblaze_I/DLMB",
+          "dlmb/LMB_M"
+        ]
+      },
+      "ilmb_sl_0": {
+        "interface_ports": [
+          "ilmb/LMB_Sl_0",
+          "ilmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb_sl_0": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_0",
+          "dlmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb_sl_1": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_1",
+          "iomodule_0/SLMB"
+        ]
+      },
+      "ilmb_port": {
+        "interface_ports": [
+          "ilmb_cntlr/BRAM_PORT",
+          "lmb_bram_I/BRAM_PORTB"
+        ]
+      },
+      "dlmb_port": {
+        "interface_ports": [
+          "dlmb_cntlr/BRAM_PORT",
+          "lmb_bram_I/BRAM_PORTA"
+        ]
+      },
+      "ilmb_sl_1": {
+        "interface_ports": [
+          "ilmb/LMB_Sl_1",
+          "second_ilmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb_sl_2": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_2",
+          "second_dlmb_cntlr/SLMB"
+        ]
+      },
+      "ilmb_port_2": {
+        "interface_ports": [
+          "second_ilmb_cntlr/BRAM_PORT",
+          "second_lmb_bram_I/BRAM_PORTB"
+        ]
+      },
+      "dlmb_port_2": {
+        "interface_ports": [
+          "second_dlmb_cntlr/BRAM_PORT",
+          "second_lmb_bram_I/BRAM_PORTA"
+        ]
+      },
+      "microblaze_I_Trace": {
+        "interface_ports": [
+          "TRACE",
+          "microblaze_I/TRACE"
+        ]
+      }
+    },
+    "nets": {
+      "Clk2": {
+        "ports": [
+          "Clk",
+          "microblaze_I/Clk",
+          "ilmb/LMB_Clk",
+          "dlmb/LMB_Clk",
+          "dlmb_cntlr/LMB_Clk",
+          "ilmb_cntlr/LMB_Clk",
+          "second_dlmb_cntlr/LMB_Clk",
+          "second_ilmb_cntlr/LMB_Clk",
+          "iomodule_0/Clk",
+          "rst_0/slowest_sync_clk"
+        ]
+      },
+      "Reset": {
+        "ports": [
+          "Reset",
+          "rst_0/ext_reset_in"
+        ]
+      },
+      "MB_Reset": {
+        "ports": [
+          "rst_0/mb_reset",
+          "microblaze_I/Reset"
+        ]
+      },
+      "LMB_Rst2": {
+        "ports": [
+          "rst_0/bus_struct_reset",
+          "ilmb/SYS_Rst",
+          "dlmb/SYS_Rst",
+          "ilmb_cntlr/LMB_Rst",
+          "dlmb_cntlr/LMB_Rst",
+          "second_ilmb_cntlr/LMB_Rst",
+          "second_dlmb_cntlr/LMB_Rst"
+        ]
+      },
+      "IO_Rst": {
+        "ports": [
+          "rst_0/peripheral_reset",
+          "iomodule_0/Rst"
+        ]
+      }
+    },
+    "addressing": {
+      "/microblaze_I": {
+        "address_spaces": {
+          "Data": {
+            "segments": {
+              "SEG_dlmb_cntlr_Mem": {
+                "address_block": "/dlmb_cntlr/SLMB/Mem",
+                "offset": "0x00000000",
+                "range": "64K"
+              },
+              "SEG_iomodule_0_IO": {
+                "address_block": "/iomodule_0/SLMB/IO",
+                "offset": "0xC0000000",
+                "range": "1G"
+              },
+              "SEG_iomodule_0_Reg": {
+                "address_block": "/iomodule_0/SLMB/Reg",
+                "offset": "0x80000000",
+                "range": "64K"
+              },
+              "SEG_second_dlmb_cntlr_Mem": {
+                "address_block": "/second_dlmb_cntlr/SLMB/Mem",
+                "offset": "0x00010000",
+                "range": "32K"
+              }
+            }
+          },
+          "Instruction": {
+            "segments": {
+              "SEG_ilmb_cntlr_Mem": {
+                "address_block": "/ilmb_cntlr/SLMB/Mem",
+                "offset": "0x00000000",
+                "range": "64K"
+              },
+              "SEG_second_ilmb_cntlr_Mem": {
+                "address_block": "/second_ilmb_cntlr/SLMB/Mem",
+                "offset": "0x00010000",
+                "range": "32K"
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml
new file mode 100644
index 0000000..0462690
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/bd_9f2c.bxml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="39">
+  <CompositeFile CompositeFileTopName="bd_9f2c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="RESET" Timestamp="1646750765"/>
+    <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1646750765"/>
+    <Generation Name="SIMULATION" State="RESET" Timestamp="1646750765"/>
+    <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1646750765"/>
+    <FileCollection Name="SOURCES" Type="SOURCES">
+      <File Name="ip/ip_0/bd_9f2c_microblaze_I_0.xci" Type="IP">
+        <Instance HierarchyPath="microblaze_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_1/bd_9f2c_rst_0_0.xci" Type="IP">
+        <Instance HierarchyPath="rst_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_2/bd_9f2c_ilmb_0.xci" Type="IP">
+        <Instance HierarchyPath="ilmb"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_3/bd_9f2c_dlmb_0.xci" Type="IP">
+        <Instance HierarchyPath="dlmb"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="dlmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="ilmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_6/bd_9f2c_lmb_bram_I_0.xci" Type="IP">
+        <Instance HierarchyPath="lmb_bram_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="second_dlmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="second_ilmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci" Type="IP">
+        <Instance HierarchyPath="second_lmb_bram_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_10/bd_9f2c_iomodule_0_0.xci" Type="IP">
+        <Instance HierarchyPath="iomodule_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+    </FileCollection>
+  </CompositeFile>
+</Root>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v
new file mode 100644
index 0000000..eb836a2
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/hdl/bd_9f2c_wrapper.v
@@ -0,0 +1,173 @@
+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Command: generate_target bd_9f2c_wrapper.bd
+//Design : bd_9f2c_wrapper
+//Purpose: IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module bd_9f2c_wrapper
+   (Clk,
+    IO_addr_strobe,
+    IO_address,
+    IO_byte_enable,
+    IO_read_data,
+    IO_read_strobe,
+    IO_ready,
+    IO_write_data,
+    IO_write_strobe,
+    Reset,
+    TRACE_data_access,
+    TRACE_data_address,
+    TRACE_data_byte_enable,
+    TRACE_data_read,
+    TRACE_data_write,
+    TRACE_data_write_value,
+    TRACE_dcache_hit,
+    TRACE_dcache_rdy,
+    TRACE_dcache_read,
+    TRACE_dcache_req,
+    TRACE_delay_slot,
+    TRACE_ex_piperun,
+    TRACE_exception_kind,
+    TRACE_exception_taken,
+    TRACE_icache_hit,
+    TRACE_icache_rdy,
+    TRACE_icache_req,
+    TRACE_instruction,
+    TRACE_jump_hit,
+    TRACE_jump_taken,
+    TRACE_mb_halted,
+    TRACE_mem_piperun,
+    TRACE_msr_reg,
+    TRACE_new_reg_value,
+    TRACE_of_piperun,
+    TRACE_pc,
+    TRACE_pid_reg,
+    TRACE_reg_addr,
+    TRACE_reg_write,
+    TRACE_valid_instr);
+  input Clk;
+  output IO_addr_strobe;
+  output [31:0]IO_address;
+  output [3:0]IO_byte_enable;
+  input [31:0]IO_read_data;
+  output IO_read_strobe;
+  input IO_ready;
+  output [31:0]IO_write_data;
+  output IO_write_strobe;
+  input Reset;
+  output TRACE_data_access;
+  output [0:31]TRACE_data_address;
+  output [0:3]TRACE_data_byte_enable;
+  output TRACE_data_read;
+  output TRACE_data_write;
+  output [0:31]TRACE_data_write_value;
+  output TRACE_dcache_hit;
+  output TRACE_dcache_rdy;
+  output TRACE_dcache_read;
+  output TRACE_dcache_req;
+  output TRACE_delay_slot;
+  output TRACE_ex_piperun;
+  output [0:4]TRACE_exception_kind;
+  output TRACE_exception_taken;
+  output TRACE_icache_hit;
+  output TRACE_icache_rdy;
+  output TRACE_icache_req;
+  output [0:31]TRACE_instruction;
+  output TRACE_jump_hit;
+  output TRACE_jump_taken;
+  output TRACE_mb_halted;
+  output TRACE_mem_piperun;
+  output [0:14]TRACE_msr_reg;
+  output [0:31]TRACE_new_reg_value;
+  output TRACE_of_piperun;
+  output [0:31]TRACE_pc;
+  output [0:7]TRACE_pid_reg;
+  output [0:4]TRACE_reg_addr;
+  output TRACE_reg_write;
+  output TRACE_valid_instr;
+
+  wire Clk;
+  wire IO_addr_strobe;
+  wire [31:0]IO_address;
+  wire [3:0]IO_byte_enable;
+  wire [31:0]IO_read_data;
+  wire IO_read_strobe;
+  wire IO_ready;
+  wire [31:0]IO_write_data;
+  wire IO_write_strobe;
+  wire Reset;
+  wire TRACE_data_access;
+  wire [0:31]TRACE_data_address;
+  wire [0:3]TRACE_data_byte_enable;
+  wire TRACE_data_read;
+  wire TRACE_data_write;
+  wire [0:31]TRACE_data_write_value;
+  wire TRACE_dcache_hit;
+  wire TRACE_dcache_rdy;
+  wire TRACE_dcache_read;
+  wire TRACE_dcache_req;
+  wire TRACE_delay_slot;
+  wire TRACE_ex_piperun;
+  wire [0:4]TRACE_exception_kind;
+  wire TRACE_exception_taken;
+  wire TRACE_icache_hit;
+  wire TRACE_icache_rdy;
+  wire TRACE_icache_req;
+  wire [0:31]TRACE_instruction;
+  wire TRACE_jump_hit;
+  wire TRACE_jump_taken;
+  wire TRACE_mb_halted;
+  wire TRACE_mem_piperun;
+  wire [0:14]TRACE_msr_reg;
+  wire [0:31]TRACE_new_reg_value;
+  wire TRACE_of_piperun;
+  wire [0:31]TRACE_pc;
+  wire [0:7]TRACE_pid_reg;
+  wire [0:4]TRACE_reg_addr;
+  wire TRACE_reg_write;
+  wire TRACE_valid_instr;
+
+  bd_9f2c bd_9f2c_i
+       (.Clk(Clk),
+        .IO_addr_strobe(IO_addr_strobe),
+        .IO_address(IO_address),
+        .IO_byte_enable(IO_byte_enable),
+        .IO_read_data(IO_read_data),
+        .IO_read_strobe(IO_read_strobe),
+        .IO_ready(IO_ready),
+        .IO_write_data(IO_write_data),
+        .IO_write_strobe(IO_write_strobe),
+        .Reset(Reset),
+        .TRACE_data_access(TRACE_data_access),
+        .TRACE_data_address(TRACE_data_address),
+        .TRACE_data_byte_enable(TRACE_data_byte_enable),
+        .TRACE_data_read(TRACE_data_read),
+        .TRACE_data_write(TRACE_data_write),
+        .TRACE_data_write_value(TRACE_data_write_value),
+        .TRACE_dcache_hit(TRACE_dcache_hit),
+        .TRACE_dcache_rdy(TRACE_dcache_rdy),
+        .TRACE_dcache_read(TRACE_dcache_read),
+        .TRACE_dcache_req(TRACE_dcache_req),
+        .TRACE_delay_slot(TRACE_delay_slot),
+        .TRACE_ex_piperun(TRACE_ex_piperun),
+        .TRACE_exception_kind(TRACE_exception_kind),
+        .TRACE_exception_taken(TRACE_exception_taken),
+        .TRACE_icache_hit(TRACE_icache_hit),
+        .TRACE_icache_rdy(TRACE_icache_rdy),
+        .TRACE_icache_req(TRACE_icache_req),
+        .TRACE_instruction(TRACE_instruction),
+        .TRACE_jump_hit(TRACE_jump_hit),
+        .TRACE_jump_taken(TRACE_jump_taken),
+        .TRACE_mb_halted(TRACE_mb_halted),
+        .TRACE_mem_piperun(TRACE_mem_piperun),
+        .TRACE_msr_reg(TRACE_msr_reg),
+        .TRACE_new_reg_value(TRACE_new_reg_value),
+        .TRACE_of_piperun(TRACE_of_piperun),
+        .TRACE_pc(TRACE_pc),
+        .TRACE_pid_reg(TRACE_pid_reg),
+        .TRACE_reg_addr(TRACE_reg_addr),
+        .TRACE_reg_write(TRACE_reg_write),
+        .TRACE_valid_instr(TRACE_valid_instr));
+endmodule
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci
new file mode 100644
index 0000000..97cfe2b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xci
@@ -0,0 +1,1032 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>bd_9f2c_microblaze_I_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze" spirit:version="11.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_HZ">30000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_INTR.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M0_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M0_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_M_AXI_IP_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUMBER_OF_PC_BRK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPCODE_0x0_ILLEGAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPTIMIZATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PC_WIDTH">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PVR">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PVR_USER2">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_BIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_DCE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_EE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_EIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_ICE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_IE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S0_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S0_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S10_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S10_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S11_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S11_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S12_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S12_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S13_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S13_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S14_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S14_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S15_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S15_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S1_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S1_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S2_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S2_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S3_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S3_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S4_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S4_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S5_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S5_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S6_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S6_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S7_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S7_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S8_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S8_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S9_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S9_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCO">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRACE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UNALIGNED_EXCEPTIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BARREL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BRANCH_TARGET_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_DCACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_DIV">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXTENDED_FSL_INSTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXT_BRK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FPU">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_HW_MUL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_ICACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_MMU">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_MSR_INSTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_NON_SECURE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PCMP_INSTR">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STACK_PROTECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_9f2c_microblaze_I_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.G_TEMPLATE_LIST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.G_USE_EXCEPTIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ASYNC_WAKEUP" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DEBUG_ENABLED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_D_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EDGE_IS_POSITIVE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FAULT_TOLERANT" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_IS_EDGE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_I_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUMBER_OF_PC_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PC_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TRACE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_BARREL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_DIV" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_HW_MUL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_INTERRUPT" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_NON_SECURE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_PCMP_INSTR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
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+l_right&quot;:&quot;31&quot;},&quot;Data_Read&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Data_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;D_AS&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Read_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Write_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DReady&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DWait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DCE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DUE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Trace_Instruction&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Valid_Instr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_PC&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Reg_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,
+&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Reg_Addr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;},&quot;Trace_MSR_Reg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;},&quot;Trace_PID_Reg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;},&quot;Trace_New_Reg_Value&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Exception_Taken&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Exception_Kind&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;},&quot;Trace_Jump_Taken&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Delay_Slot&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Address&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Data_Write_Value&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Data_Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Trace_Data_Access&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:
+&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Read&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Rdy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Read&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Rdy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_OF_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_EX_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_MEM_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_MB_Ha
+lted&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Jump_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;Reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;
+value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:
+[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;INTERRUPT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbinterrupt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbinterrupt_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;SENSITIVITY&quot;:[{&quot;value&quot;:&quot;LEVEL_HIGH&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LOW_LATENCY&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ACK&quot;:{&quot;physical_name&quot;:&quot;Interrupt_Ack&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;1&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;Interrupt_Address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;INTERRUPT&quot;:{&quot;physical_name&quot;:&quot;Interrupt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;DLMB&quot;:{&quot;vl
+nv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;Data_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;D_AS&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;Byte_Enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;DCE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical
+_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Data_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;Read_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;DReady&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;DUE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;DWait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;Data_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;Write_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ILMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;
+master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_ONLY&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;Instr_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;I_AS&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;ICE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;IFetch&quot;,&quot;phy
+sical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IReady&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;IUE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;IWAIT&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;TRACE&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbtrace:2.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbtrace_rtl:2.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;DATA_ACCESS&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_ADDRESS&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DATA_BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Byte_Enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;DATA_READ&quot;:{&quot;physi
+cal_name&quot;:&quot;Trace_Data_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE_VALUE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Write_Value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DCACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_READ&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DELAY_SLOT&quot;:{&quot;physical_name&quot;:&quot;Trace_Delay_Slot&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;log
+ical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EX_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_EX_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EXCEPTION_KIND&quot;:{&quot;physical_name&quot;:&quot;Trace_Exception_Kind&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;EXCEPTION_TAKEN&quot;:{&quot;physical_name&quot;:&quot;Trace_Exception_Taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;INSTRUCTION&quot;:{&quot;physical_name&quot;:&quot;Trace_Instruction&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;JUMP_HIT&quot;:{&quot;physical_name&quot;:&quot;Tr
+ace_Jump_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;JUMP_TAKEN&quot;:{&quot;physical_name&quot;:&quot;Trace_Jump_Taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MB_HALTED&quot;:{&quot;physical_name&quot;:&quot;Trace_MB_Halted&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MEM_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_MEM_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MSR_REG&quot;:{&quot;physical_name&quot;:&quot;Trace_MSR_Reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;14&quot;},&quot;NEW_REG_VALUE&quot;:{&quot;physical_name&quot;:&quot;Trace_New_Reg_Value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;OF_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_OF_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PC&quot;:{&quot;physical_name&quot;:&quot;Trace_PC&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;PID
+_REG&quot;:{&quot;physical_name&quot;:&quot;Trace_PID_Reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;7&quot;},&quot;REG_ADDR&quot;:{&quot;physical_name&quot;:&quot;Trace_Reg_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;REG_WRITE&quot;:{&quot;physical_name&quot;:&quot;Trace_Reg_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;VALID_INSTR&quot;:{&quot;physical_name&quot;:&quot;Trace_Valid_Instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml
new file mode 100644
index 0000000..611646c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/bd_9f2c_microblaze_I_0.xml
@@ -0,0 +1,27445 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_microblaze_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.CLK</spirit:name>
+      <spirit:displayName>Clk</spirit:displayName>
+      <spirit:description>Clock input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF">M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET">Reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Clk frequency</spirit:displayName>
+          <spirit:description>Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.RESET</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.RESET.TYPE">PROCESSOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT</spirit:name>
+      <spirit:displayName>INTERRUPT</spirit:displayName>
+      <spirit:description>Interrupt Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 0))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_INTERRUPT</spirit:name>
+      <spirit:displayName>INTERRUPT</spirit:displayName>
+      <spirit:description>Interrupt Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_INTERRUPT.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DLMB</spirit:name>
+      <spirit:displayName>DLMB</spirit:displayName>
+      <spirit:description>Data Local Memory Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>D_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DCE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Read_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DWait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Write_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.DLMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.DLMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DLMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB_MON&apos;)) = 0)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_DLMB</spirit:name>
+      <spirit:displayName>DLMB</spirit:displayName>
+      <spirit:description>Data Local Memory Bus Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>D_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DCE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Read_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DWait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Write_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_DLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_DLMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ILMB</spirit:name>
+      <spirit:displayName>ILMB</spirit:displayName>
+      <spirit:description>Instruction Local Memory Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>I_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ICE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IFetch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IWAIT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ILMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.ILMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ILMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ILMB.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ILMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB_MON&apos;)) = 0)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ILMB</spirit:name>
+      <spirit:displayName>ILMB</spirit:displayName>
+      <spirit:description>Instruction Local Memory Bus Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>I_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ICE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IFetch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IWAIT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ILMB.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ILMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_DP</spirit:name>
+      <spirit:displayName>M_AXI_DP</spirit:displayName>
+      <spirit:description>Master AXI4 Data Peripheral Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.PROTOCOL" spirit:dependency="substring(&quot;AXI4LITE&quot;, 1, 4 + 4 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) &lt; 2) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 0)))">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_DP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_DP</spirit:name>
+      <spirit:displayName>M_AXI_DP</spirit:displayName>
+      <spirit:description>Master AXI4 Data Peripheral Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.PROTOCOL" spirit:dependency="substring(&quot;AXI4LITE&quot;, 1, 4 + 4 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) &lt; 2) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 0)))">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_DP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_IP</spirit:name>
+      <spirit:displayName>M_AXI_IP</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Peripheral Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_IP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_IP</spirit:name>
+      <spirit:displayName>M_AXI_IP</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Peripheral Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_IP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IP_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M0_AXIS</spirit:name>
+      <spirit:displayName>M0_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M0_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S0_AXIS</spirit:name>
+      <spirit:displayName>S0_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S0_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M1_AXIS</spirit:name>
+      <spirit:displayName>M1_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M1_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S1_AXIS</spirit:name>
+      <spirit:displayName>S1_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S1_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M2_AXIS</spirit:name>
+      <spirit:displayName>M2_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M2_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S2_AXIS</spirit:name>
+      <spirit:displayName>S2_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S2_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M3_AXIS</spirit:name>
+      <spirit:displayName>M3_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M3_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S3_AXIS</spirit:name>
+      <spirit:displayName>S3_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S3_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M4_AXIS</spirit:name>
+      <spirit:displayName>M4_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M4_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S4_AXIS</spirit:name>
+      <spirit:displayName>S4_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S4_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M5_AXIS</spirit:name>
+      <spirit:displayName>M5_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M5_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S5_AXIS</spirit:name>
+      <spirit:displayName>S5_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S5_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M6_AXIS</spirit:name>
+      <spirit:displayName>M6_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M6_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S6_AXIS</spirit:name>
+      <spirit:displayName>S6_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S6_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M7_AXIS</spirit:name>
+      <spirit:displayName>M7_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M7_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S7_AXIS</spirit:name>
+      <spirit:displayName>S7_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S7_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M8_AXIS</spirit:name>
+      <spirit:displayName>M8_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M8_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S8_AXIS</spirit:name>
+      <spirit:displayName>S8_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S8_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M9_AXIS</spirit:name>
+      <spirit:displayName>M9_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M9_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S9_AXIS</spirit:name>
+      <spirit:displayName>S9_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S9_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M10_AXIS</spirit:name>
+      <spirit:displayName>M10_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M10_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S10_AXIS</spirit:name>
+      <spirit:displayName>S10_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S10_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M11_AXIS</spirit:name>
+      <spirit:displayName>M11_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M11_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S11_AXIS</spirit:name>
+      <spirit:displayName>S11_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S11_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M12_AXIS</spirit:name>
+      <spirit:displayName>M12_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M12_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S12_AXIS</spirit:name>
+      <spirit:displayName>S12_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S12_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M13_AXIS</spirit:name>
+      <spirit:displayName>M13_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M13_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S13_AXIS</spirit:name>
+      <spirit:displayName>S13_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S13_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M14_AXIS</spirit:name>
+      <spirit:displayName>M14_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M14_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S14_AXIS</spirit:name>
+      <spirit:displayName>S14_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S14_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M15_AXIS</spirit:name>
+      <spirit:displayName>M15_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M15_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S15_AXIS</spirit:name>
+      <spirit:displayName>S15_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S15_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_DC</spirit:name>
+      <spirit:displayName>M_AXI_DC</spirit:displayName>
+      <spirit:description>Master AXI4 Data Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_DC</spirit:name>
+      <spirit:displayName>M_AXI_DC</spirit:displayName>
+      <spirit:description>Master AXI4 Data Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_ACE_DC</spirit:name>
+      <spirit:displayName>M_ACE_DC</spirit:displayName>
+      <spirit:description>Master ACE Data Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_ACE_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ACE_DC</spirit:name>
+      <spirit:displayName>M_ACE_DC</spirit:displayName>
+      <spirit:description>Master ACE Data Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ACE_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_IC</spirit:name>
+      <spirit:displayName>M_AXI_IC</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_IC</spirit:name>
+      <spirit:displayName>M_AXI_IC</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_ACE_IC</spirit:name>
+      <spirit:displayName>M_ACE_IC</spirit:displayName>
+      <spirit:description>Master ACE Instruction Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_ACE_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ACE_IC</spirit:name>
+      <spirit:displayName>M_ACE_IC</spirit:displayName>
+      <spirit:description>Master ACE Instruction Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ACE_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DEBUG</spirit:name>
+      <spirit:displayName>DEBUG</spirit:displayName>
+      <spirit:description>MicroBlaze Debug Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbdebug" spirit:version="3.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbdebug_rtl" spirit:version="3.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CAPTURE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Capture</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DISABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Disable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Reg_En</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Debug_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SHIFT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Shift</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDI</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_TDI</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDO</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_TDO</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRCLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_ACK_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Ack_In</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_ACK_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Ack_Out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_In</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UPDATE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Update</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DEBUG" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) &lt; 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_DEBUG</spirit:name>
+      <spirit:displayName>DEBUG</spirit:displayName>
+      <spirit:description>AXI4-Lite Debug</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_DEBUG"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_DEBUG" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.DEBUG_ACLK</spirit:name>
+      <spirit:displayName>DEBUG_ACLK</spirit:displayName>
+      <spirit:description>Parallel Debug Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DEBUG_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.ASSOCIATED_BUSIF">DEBUG:S_AXI_DEBUG</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.ASSOCIATED_RESET">DEBUG_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>DEBUG_ACLK frequency</spirit:displayName>
+          <spirit:description>DEBUG_ACLK frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_HZ">30000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.DEBUG_ACLK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) > 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.DEBUG_ARESETN</spirit:name>
+      <spirit:displayName>DEBUG_ARESETN</spirit:displayName>
+      <spirit:description>Parallel Debug Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DEBUG_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.DEBUG_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.DEBUG_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.DEBUG_ARESETN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) > 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DBG_INTR</spirit:name>
+      <spirit:displayName>Dbg_Intr</spirit:displayName>
+      <spirit:description>Debug Interrupt Output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Intr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_INTR.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DBG_INTR.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DBG_INTR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_ENABLE_DISCRETE_PORTS&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:displayName>TRACE</spirit:displayName>
+      <spirit:description>MicroBlaze Trace Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace" spirit:version="2.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace_rtl" spirit:version="2.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Access</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Write_Value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DELAY_SLOT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Delay_Slot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EX_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_EX_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_KIND</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Exception_Kind</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Exception_Taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INSTRUCTION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Instruction</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Jump_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Jump_Taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MB_HALTED</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MB_Halted</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MEM_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MEM_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MSR_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MSR_Reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NEW_REG_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_New_Reg_Value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>OF_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_OF_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PC</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_PC</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PID_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_PID_Reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Reg_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Reg_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_INSTR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Valid_Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.TRACE" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_TRACE&apos;)) = 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:width>
+      <spirit:localMemoryMap>
+        <spirit:name>local_memory_map</spirit:name>
+        <spirit:addressBlock>
+          <spirit:name>microblaze_0</spirit:name>
+          <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+          <spirit:range spirit:format="long">98304</spirit:range>
+          <spirit:width spirit:format="long">32</spirit:width>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>lsb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.lsb">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>msb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.msb">31</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>workflow</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.workflow">simulation</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>controlpaths</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.controlpaths">dlmb_cntlr=lmb_bram_I,second_dlmb_cntlr=second_lmb_bram_I</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>memorytypename</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.memorytypename"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>simmemfile</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.simmemfile"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>combined</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.combined">{&quot;AddressBlocks&quot;:[{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:0,&quot;AddrEnd&quot;:65535,&quot;Workflow&quot;:&quot;simulation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot; bd_9f2c lmb_bram_I_MEM_DEVICE&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:65536,&quot;MemFile&quot;:&quot;bd_9f2c_lmb_bram_I_0.mem&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;dlmb_cntlr&quot;,&quot;Val&quot;:&quot;lmb_bram_I&quot;}]},{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:65536,&quot;AddrEnd&quot;:98303,&quot;Workflow&quot;:&quot;simulation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot; bd_9f2c lmb_bram_I bd_9f2c
+ second_lmb_bram_I_MEM_DEVICE&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:32768,&quot;MemFile&quot;:&quot;bd_9f2c_second_lmb_bram_I_0.mem&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;second_dlmb_cntlr&quot;,&quot;Val&quot;:&quot;second_lmb_bram_I&quot;}]}]}</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </spirit:addressBlock>
+        <spirit:addressBlock>
+          <spirit:name>microblaze_1</spirit:name>
+          <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+          <spirit:range spirit:format="long">98304</spirit:range>
+          <spirit:width spirit:format="long">32</spirit:width>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>lsb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.lsb">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>msb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.msb">31</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>workflow</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.workflow">implementation</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>controlpaths</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.controlpaths">dlmb_cntlr=lmb_bram_I,second_dlmb_cntlr=second_lmb_bram_I</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>memorytypename</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.memorytypename"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>simmemfile</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.simmemfile"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>combined</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.combined">{&quot;AddressBlocks&quot;:[{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:0,&quot;AddrEnd&quot;:65535,&quot;Workflow&quot;:&quot;implementation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot;&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:65536,&quot;MemFile&quot;:&quot;&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;dlmb_cntlr&quot;,&quot;Val&quot;:&quot;lmb_bram_I&quot;}]},{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:65536,&quot;AddrEnd&quot;:98303,&quot;Workflow&quot;:&quot;implementation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot;&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:32768,&quot;MemFile&quot;:&quot;&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;second_d
+lmb_cntlr&quot;,&quot;Val&quot;:&quot;second_lmb_bram_I&quot;}]}]}</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </spirit:addressBlock>
+      </spirit:localMemoryMap>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Instruction</spirit:name>
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+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:width>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_DEBUG</spirit:name>
+      <spirit:description>AXI debug memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Debug Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="32768" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Mb_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Mb_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Config_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Scan_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_Reset_Sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_En</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>RAM_To</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">255</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>RAM_From</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">255</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
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+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+      <spirit:port>
+        <spirit:name>Interrupt_Address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_IADDR_SIZE&apos;)) - 1)">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+      <spirit:port>
+        <spirit:name>Interrupt_Ack</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">1</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt_Ack" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 0))">true</xilinx:isEnabled>
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+        <spirit:name>Ext_BRK</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:name>Ext_NM_BRK</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>Byte_Enable</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        <spirit:name>M_AXI_DP_AWADDR</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_AWADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_WVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_CRRESP</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_CRREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_CDVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>M_AXI_IC_CDDATA</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_CDDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_CDLAST</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>M_AXI_IC_CDREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DC_AWID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_AWADDR</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+        <spirit:name>M_AXI_DC_BUSER</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_WACK</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_WACK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARLEN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARSIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARBURST</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARBURST" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARLOCK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARCACHE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARPROT</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARPROT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_ARQOS</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARQOS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_ARVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_ARREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DC_ARUSER</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_CDREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_SCO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SCO">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREQ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CONFIG_RESET" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK_IRQ</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region for interrupt input</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK_DEBUG</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region in debug module</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_DBG_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Dbg_Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_DBG_TRACE_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Dbg_Trace_Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_TOLERANT</spirit:name>
+        <spirit:displayName>Enable Fault Tolerance Support</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_TOLERANT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_USE_CE_EXCEPTION</spirit:name>
+        <spirit:displayName>Correctable Error Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_USE_CE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCKSTEP_SLAVE</spirit:name>
+        <spirit:displayName>Lockstep Slave</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKSTEP_SLAVE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCKSTEP_MASTER</spirit:name>
+        <spirit:displayName>Lockstep Master</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKSTEP_MASTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ENDIANNESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENDIANNESS" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DATA_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_SIZE" spirit:choiceRef="choice_list_99ba8646">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DATA_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_LMB_DATA_SIZE">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INSTR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_INSTR_SIZE">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_INSTANCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INSTANCE">bd_9f2c_microblaze_I_0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AVOID_PRIMITIVES" spirit:choiceRef="choice_pairs_22d9f392">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AREA_OPTIMIZED</spirit:name>
+        <spirit:displayName>Select implementation optimization</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AREA_OPTIMIZED" spirit:choiceRef="choice_pairs_3eb333f8">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPTIMIZATION</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Bus Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_ff364cce">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASE_VECTORS</spirit:name>
+        <spirit:displayName>Vector Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASE_VECTORS" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_DATA_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_EXCLUSIVE_ACCESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_EXCLUSIVE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_D_BUS_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Data-side AXI Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_D_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_D_BUS_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_DATA_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_I_BUS_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Instruction-side AXI Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_I_BUS_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_LMB</spirit:name>
+        <spirit:displayName>Enable Local Memory Bus Data Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_LMB" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>Local Memory Bus Data Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_AXI</spirit:name>
+        <spirit:displayName>Enable Peripheral AXI Data Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_AXI" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_LMB</spirit:name>
+        <spirit:displayName>Enable Local Memory Bus Instruction Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_LMB" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>Local Memory Bus Instruction Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_AXI</spirit:name>
+        <spirit:displayName>Enable Peripheral AXI Instruction Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_AXI" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>G_TEMPLATE_LIST</spirit:name>
+        <spirit:displayName>Select Configuration</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.G_TEMPLATE_LIST" spirit:choiceRef="choice_pairs_7dd2834f">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_MSR_INSTR</spirit:name>
+        <spirit:displayName>Enable Additional Machine Status Register Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MSR_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PCMP_INSTR</spirit:name>
+        <spirit:displayName>Enable Pattern Comparator</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PCMP_INSTR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_BARREL</spirit:name>
+        <spirit:displayName>Enable Barrel Shifter</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BARREL" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DIV</spirit:name>
+        <spirit:displayName>Enable Integer Divider</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DIV" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_HW_MUL</spirit:name>
+        <spirit:displayName>Enable Integer Multiplier</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_HW_MUL" spirit:choiceRef="choice_pairs_1075faf2">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FPU</spirit:name>
+        <spirit:displayName>Enable Floating Point Unit</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FPU" spirit:choiceRef="choice_pairs_7bfd418d">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_REORDER_INSTR</spirit:name>
+        <spirit:displayName>Enable Reversed Load/Store and Swap Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_REORDER_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UNALIGNED_EXCEPTIONS</spirit:name>
+        <spirit:displayName>Enable Unaligned Data Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UNALIGNED_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ILL_OPCODE_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Illegal Instruction Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ILL_OPCODE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIV_ZERO_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Integer Divide Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIV_ZERO_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DIV_ZERO_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DIV&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FPU_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Floating Point Unit Exceptions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FPU_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FPU_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FPU&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FSL_LINKS</spirit:name>
+        <spirit:displayName>Number of Stream Links</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FSL_LINKS" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXTENDED_FSL_INSTR</spirit:name>
+        <spirit:displayName>Enable Additional Stream Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXTENDED_FSL_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FSL_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Stream Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FSL_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FSL_EXCEPTION" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_EXTENDED_FSL_INSTR&apos;)) > 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_STACK_PROTECTION</spirit:name>
+        <spirit:displayName>Enable stack protection</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STACK_PROTECTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_STACK_PROTECTION" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) = 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) = 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPRECISE_EXCEPTIONS</spirit:name>
+        <spirit:displayName>Allow Imprecise Exceptions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPRECISE_EXCEPTIONS" spirit:choiceRef="choice_pairs_2058dc69">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INTERRUPT" spirit:choiceRef="choice_pairs_db57ca32">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXT_BRK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXT_BRK" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXT_NM_BRK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXT_NM_BRK" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_NON_SECURE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_NON_SECURE" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_MMU</spirit:name>
+        <spirit:displayName>Memory Management</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MMU" spirit:choiceRef="choice_pairs_0000a26c">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_MMU" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_DTLB_SIZE</spirit:name>
+        <spirit:displayName>Data Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_DTLB_SIZE" spirit:choiceRef="choice_list_dd2843c6">4</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_DTLB_SIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_ITLB_SIZE</spirit:name>
+        <spirit:displayName>Instruction Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_ITLB_SIZE" spirit:choiceRef="choice_list_dd2843c6">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_ITLB_SIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_TLB_ACCESS</spirit:name>
+        <spirit:displayName>Enable Access to Memory Management Special Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_TLB_ACCESS" spirit:choiceRef="choice_pairs_7ad6afc0">3</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_TLB_ACCESS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_ZONES</spirit:name>
+        <spirit:displayName>Number of Memory Protection Zones</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_ZONES" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">16</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_ZONES" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_PRIVILEGED_INSTR</spirit:name>
+        <spirit:displayName>Privileged Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_PRIVILEGED_INSTR" spirit:choiceRef="choice_pairs_443ae6cc">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_PRIVILEGED_INSTR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_BRANCH_TARGET_CACHE</spirit:name>
+        <spirit:displayName>Enable Branch Target Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRANCH_TARGET_CACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_BRANCH_TARGET_CACHE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRANCH_TARGET_CACHE_SIZE</spirit:name>
+        <spirit:displayName>Branch Target Cache Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRANCH_TARGET_CACHE_SIZE" spirit:choiceRef="choice_pairs_e7a1eb81">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_BRANCH_TARGET_CACHE_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PC_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PC_WIDTH" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PVR</spirit:name>
+        <spirit:displayName>Specifies Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR" spirit:choiceRef="choice_pairs_5ab38e91">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 7)">
+        <spirit:name>C_PVR_USER1</spirit:name>
+        <spirit:displayName>Specify USER1 Bits in Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR_USER1" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 31)">
+        <spirit:name>C_PVR_USER2</spirit:name>
+        <spirit:displayName>Specify USER2 Bits in Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR_USER2" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DYNAMIC_BUS_SIZING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DYNAMIC_BUS_SIZING">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 31)">
+        <spirit:name>C_RESET_MSR</spirit:name>
+        <spirit:displayName>Specify Reset Value for Select MSR Bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_MSR" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPCODE_0x0_ILLEGAL</spirit:name>
+        <spirit:displayName>Generate Illegal Instruction Exception for NULL Instruction</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPCODE_0x0_ILLEGAL" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_ENABLED</spirit:name>
+        <spirit:displayName>MicroBlaze Debug Module Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_ENABLED" spirit:choiceRef="choice_pairs_7bfd418d">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_INTERFACE</spirit:name>
+        <spirit:displayName>MicroBlaze Debug Connection</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_INTERFACE" spirit:choiceRef="choice_pairs_56d5ba32">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_PC_BRK</spirit:name>
+        <spirit:displayName>Number of PC Breakpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_PC_BRK" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_RD_ADDR_BRK</spirit:name>
+        <spirit:displayName>Number of Read Address Watchpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_WR_ADDR_BRK</spirit:name>
+        <spirit:displayName>Number of Write Address Watchpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_EVENT_COUNTERS</spirit:name>
+        <spirit:displayName>Number of Performance Monitor Event Counters</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_EVENT_COUNTERS" spirit:minimum="0" spirit:maximum="48" spirit:rangeType="long">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_LATENCY_COUNTERS</spirit:name>
+        <spirit:displayName>Number of Performance Monitor Latency Counters</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_LATENCY_COUNTERS" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Performance Monitor Counter Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_COUNTER_WIDTH" spirit:choiceRef="choice_list_b1aff63c">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_TRACE_SIZE</spirit:name>
+        <spirit:displayName>Trace Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_TRACE_SIZE" spirit:choiceRef="choice_pairs_13d40c7c">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_EXTERNAL_TRACE</spirit:name>
+        <spirit:displayName>External Trace</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_TRACE_ASYNC_RESET</spirit:name>
+        <spirit:displayName>Use Asynchrnous Reset for External Trace</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_TRACE_ASYNC_RESET" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_PROFILE_SIZE</spirit:name>
+        <spirit:displayName>Profile Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_PROFILE_SIZE" spirit:choiceRef="choice_pairs_5b1842a1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERRUPT_IS_EDGE</spirit:name>
+        <spirit:displayName>Sense Interrupt on Edge vs. Level</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERRUPT_IS_EDGE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EDGE_IS_POSITIVE</spirit:name>
+        <spirit:displayName>Sense Interrupt on Rising vs. Falling Edge</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EDGE_IS_POSITIVE" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ASYNC_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ASYNC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ASYNC_WAKEUP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ASYNC_WAKEUP" spirit:choiceRef="choice_list_6e3ded9c">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M0_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M0_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S0_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S0_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M1_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M1_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S1_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S1_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M2_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M2_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S2_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S2_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M3_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M3_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S3_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S3_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M4_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M4_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S4_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S4_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M5_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M5_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S5_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S5_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M6_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M6_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S6_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S6_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M7_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M7_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S7_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S7_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M8_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M8_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S8_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S8_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M9_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M9_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S9_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S9_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M10_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M10_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S10_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S10_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M11_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M11_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S11_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S11_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M12_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M12_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S12_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S12_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M13_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M13_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S13_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S13_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M14_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M14_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S14_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S14_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M15_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M15_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S15_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S15_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ICACHE_BASEADDR</spirit:name>
+        <spirit:displayName>Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ICACHE_HIGHADDR</spirit:name>
+        <spirit:displayName>High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_HIGHADDR" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ICACHE</spirit:name>
+        <spirit:displayName>Enable Instruction Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ICACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ALLOW_ICACHE_WR</spirit:name>
+        <spirit:displayName>Enable Writes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALLOW_ICACHE_WR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ADDR_TAG_BITS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDR_TAG_BITS" spirit:minimum="0" spirit:maximum="26" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CACHE_BYTE_SIZE</spirit:name>
+        <spirit:displayName>Size in Bytes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_LINE_LEN</spirit:name>
+        <spirit:displayName>Line Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_ALWAYS_USED</spirit:name>
+        <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_STREAMS</spirit:name>
+        <spirit:displayName>Number of Streams</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_STREAMS" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_STREAMS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_VICTIMS</spirit:name>
+        <spirit:displayName>Number of Victims</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_VICTIMS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_FORCE_TAG_LUTRAM</spirit:name>
+        <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_FORCE_TAG_LUTRAM" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CACHE_BYTE_SIZE&apos;)) &lt;= (2048 * spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;))))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_DATA_WIDTH" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_TOLERANT&apos;)) = 0)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CACHE_BYTE_SIZE&apos;)) > ((2048 * spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;))) - 1)))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_USER_VALUE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_USER_VALUE" spirit:minimum="0" spirit:maximum="31" spirit:rangeType="long">31</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_USER_VALUE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_AWUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_AWUSER_WIDTH">5</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_AWUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_ARUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_ARUSER_WIDTH">5</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_ARUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_WUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_WUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_RUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_RUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_RUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_BUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_BUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_BUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_DCACHE_BASEADDR</spirit:name>
+        <spirit:displayName>Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_DCACHE_HIGHADDR</spirit:name>
+        <spirit:displayName>High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_HIGHADDR" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DCACHE</spirit:name>
+        <spirit:displayName>Enable Data Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DCACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ALLOW_DCACHE_WR</spirit:name>
+        <spirit:displayName>Enable Writes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALLOW_DCACHE_WR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_ADDR_TAG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_ADDR_TAG" spirit:minimum="0" spirit:maximum="58" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_BYTE_SIZE</spirit:name>
+        <spirit:displayName>Size in Bytes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_LINE_LEN</spirit:name>
+        <spirit:displayName>Line Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_ALWAYS_USED</spirit:name>
+        <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_USE_WRITEBACK</spirit:name>
+        <spirit:displayName>Enable Write-back Storage Policy</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DCACHE_USE_WRITEBACK" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_TOLERANT&apos;)) = 0">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_VICTIMS</spirit:name>
+        <spirit:displayName>Number of Victims</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DCACHE_VICTIMS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>C_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FREQ" spirit:order="1130" spirit:configGroups="1 NoDisplay">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FREQ">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DATA_SIZE</spirit:name>
+      <spirit:displayName>Select Processor Implementation</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_SIZE" spirit:choiceRef="choice_list_99ba8646" spirit:order="1160" spirit:configGroups="1 Instructions">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DATA_SIZE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ADDR_SIZE</spirit:name>
+      <spirit:displayName>Select Extended Addressing</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_SIZE" spirit:choiceRef="choice_pairs_c471ed24" spirit:order="1165" spirit:configGroups="1 Instructions">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ADDR_SIZE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DYNAMIC_BUS_SIZING</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DYNAMIC_BUS_SIZING" spirit:order="1220" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DYNAMIC_BUS_SIZING">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PC_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PC_WIDTH" spirit:order="1200" spirit:configGroups="1 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PC_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INSTANCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="1140" spirit:configGroups="1 NoDisplay">mb_microblaze_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INSTANCE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AVOID_PRIMITIVES" spirit:order="1170" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_AVOID_PRIMITIVES">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_TOLERANT</spirit:name>
+      <spirit:displayName>Enable Fault Tolerance Support</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_TOLERANT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1110" spirit:configGroups="1 Fault Tolerance">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_TOLERANT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_USE_CE_EXCEPTION</spirit:name>
+      <spirit:displayName>Correctable Error Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_USE_CE_EXCEPTION" spirit:order="1150" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_USE_CE_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LOCKSTEP_SLAVE</spirit:name>
+      <spirit:displayName>Lockstep Slave</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LOCKSTEP_SLAVE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1230" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LOCKSTEP_SLAVE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ENDIANNESS</spirit:name>
+      <spirit:displayName>Endianness</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ENDIANNESS" spirit:order="1235" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ENDIANNESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AREA_OPTIMIZED</spirit:name>
+      <spirit:displayName>Select implementation optimization</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AREA_OPTIMIZED" spirit:choiceRef="choice_pairs_3eb333f8" spirit:order="1080" spirit:configGroups="1 Optimization">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_AREA_OPTIMIZED">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPTIMIZATION</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPTIMIZATION" spirit:order="1180" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_OPTIMIZATION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Bus Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_ff364cce" spirit:order="2036" spirit:configGroups="8 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_BASE_VECTORS</spirit:name>
+      <spirit:displayName>Vector Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASE_VECTORS" spirit:order="1190" spirit:configGroups="1 NoDisplay" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASE_VECTORS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CONFIG_RESET" spirit:order="1210" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CONFIG_RESET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK" spirit:order="1220" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK_IRQ</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region for interrupt input</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ" spirit:order="1230" spirit:configGroups="1 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK_IRQ">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK_DEBUG</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region in debug module</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG" spirit:order="1240" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK_DEBUG">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_DBG_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Dbg_Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK" spirit:order="1250" spirit:configGroups="1 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_DBG_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_DBG_TRACE_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Dbg_Trace_Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK" spirit:order="1260" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_DBG_TRACE_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_THREAD_ID_WIDTH" spirit:order="8120" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_DATA_WIDTH" spirit:order="8130" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH" spirit:order="8140" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_EXCLUSIVE_ACCESS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS" spirit:order="8150" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_EXCLUSIVE_ACCESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_AXI</spirit:name>
+      <spirit:displayName>Enable Peripheral AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_AXI" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8030" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DP_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Peripheral AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DP_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8032" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DP_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DC_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Cache AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DC_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8034" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DC_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB</spirit:name>
+      <spirit:displayName>Enable Local Memory Bus Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8050" spirit:configGroups="8 Buses">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>Local Memory Bus Data Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="8052" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Local Memory Bus Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8055" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH" spirit:order="8200" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_DATA_WIDTH" spirit:order="8210" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH" spirit:order="8220" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_AXI</spirit:name>
+      <spirit:displayName>Enable Peripheral AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_AXI" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8060" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IP_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Peripheral AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IP_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8062" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IP_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IC_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Cache AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IC_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8064" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IC_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB</spirit:name>
+      <spirit:displayName>Enable Local Memory Bus Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8080" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>Local Memory Bus Instruction Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="8082" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Local Memory Bus Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8085" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_TRACE</spirit:name>
+      <spirit:displayName>Enable Trace Bus Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8090" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_TRACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LOCKSTEP_SELECT</spirit:name>
+      <spirit:displayName>Lockstep Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LOCKSTEP_SELECT" spirit:choiceRef="choice_pairs_75c71b2b" spirit:order="8100" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LOCKSTEP_SELECT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ENABLE_DISCRETE_PORTS</spirit:name>
+      <spirit:displayName>Enable Discrete Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ENABLE_DISCRETE_PORTS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8470" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ENABLE_DISCRETE_PORTS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_USER_SIGNALS</spirit:name>
+      <spirit:displayName>Enable M_AXI_DC User Signals</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8370" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_USER_SIGNALS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_USER_SIGNALS</spirit:name>
+      <spirit:displayName>Enable M_AXI_IC User Signals</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8460" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_USER_SIGNALS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>G_TEMPLATE_LIST</spirit:name>
+      <spirit:displayName>Select Configuration</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_TEMPLATE_LIST" spirit:choiceRef="choice_pairs_7dd2834f" spirit:order="10" spirit:configGroups="9 GUI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.G_TEMPLATE_LIST">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>G_USE_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Enable Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_USE_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="50" spirit:configGroups="9 GUI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.G_USE_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_MSR_INSTR</spirit:name>
+      <spirit:displayName>Enable Additional Machine Status Register Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_MSR_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1040" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_MSR_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PCMP_INSTR</spirit:name>
+      <spirit:displayName>Enable Pattern Comparator</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PCMP_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1050" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_PCMP_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_REORDER_INSTR</spirit:name>
+      <spirit:displayName>Enable Reversed Load/Store and Swap Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_REORDER_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1060" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_REORDER_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_BARREL</spirit:name>
+      <spirit:displayName>Enable Barrel Shifter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_BARREL" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1000" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_BARREL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_DIV</spirit:name>
+      <spirit:displayName>Enable Integer Divider</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_DIV" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1030" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_DIV">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_HW_MUL</spirit:name>
+      <spirit:displayName>Enable Integer Multiplier</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_HW_MUL" spirit:choiceRef="choice_pairs_1075faf2" spirit:order="1020" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_HW_MUL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FPU</spirit:name>
+      <spirit:displayName>Enable Floating Point Unit</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FPU" spirit:choiceRef="choice_pairs_7bfd418d" spirit:order="1010" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_FPU">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UNALIGNED_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Enable Unaligned Data Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UNALIGNED_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2090" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UNALIGNED_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ILL_OPCODE_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Illegal Instruction Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ILL_OPCODE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2060" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ILL_OPCODE_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_I_BUS_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Instruction-side AXI Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2040" spirit:configGroups="2 Bus Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_I_BUS_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_D_BUS_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Data-side AXI Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_D_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2050" spirit:configGroups="2 Bus Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_D_BUS_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DIV_ZERO_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Integer Divide Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DIV_ZERO_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 Math Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DIV_ZERO_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FPU_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Floating Point Unit Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FPU_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2010" spirit:configGroups="2 Math Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FPU_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FSL_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Stream Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FSL_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8008" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FSL_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_STACK_PROTECTION</spirit:name>
+      <spirit:displayName>Enable stack protection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_STACK_PROTECTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4004" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_STACK_PROTECTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IMPRECISE_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Allow Imprecise Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IMPRECISE_EXCEPTIONS" spirit:choiceRef="choice_pairs_2058dc69" spirit:order="2090" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IMPRECISE_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR</spirit:name>
+      <spirit:displayName>Specifies Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR" spirit:choiceRef="choice_pairs_5ab38e91" spirit:order="7000" spirit:configGroups="7 Processor Version Registers">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR_USER1</spirit:name>
+      <spirit:displayName>Specify USER1 Bits in Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR_USER1" spirit:order="7100" spirit:configGroups="7 Processor Version Registers" spirit:bitStringLength="8">0x00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR_USER1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR_USER2</spirit:name>
+      <spirit:displayName>Specify USER2 Bits in Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR_USER2" spirit:order="7200" spirit:configGroups="7 Processor Version Registers" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR_USER2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_ENABLED</spirit:name>
+      <spirit:displayName>MicroBlaze Debug Module Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_ENABLED" spirit:choiceRef="choice_pairs_7bfd418d" spirit:order="5000" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_ENABLED">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_INTERFACE</spirit:name>
+      <spirit:displayName>MicroBlaze Debug Connection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_INTERFACE" spirit:choiceRef="choice_pairs_56d5ba32" spirit:order="5010" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_INTERFACE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_PC_BRK</spirit:name>
+      <spirit:displayName>Number of PC Breakpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_PC_BRK" spirit:order="5100" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_PC_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_RD_ADDR_BRK</spirit:name>
+      <spirit:displayName>Number of Read Address Watchpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK" spirit:order="5300" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_RD_ADDR_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_WR_ADDR_BRK</spirit:name>
+      <spirit:displayName>Number of Write Address Watchpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK" spirit:order="5200" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_WR_ADDR_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_EVENT_COUNTERS</spirit:name>
+      <spirit:displayName>Number of Performance Monitor Event Counters</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_EVENT_COUNTERS" spirit:order="5400" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="48" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_EVENT_COUNTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_LATENCY_COUNTERS</spirit:name>
+      <spirit:displayName>Number of Performance Monitor Latency Counters</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_LATENCY_COUNTERS" spirit:order="5500" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_LATENCY_COUNTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Performance Monitor Counter Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_COUNTER_WIDTH" spirit:choiceRef="choice_list_b1aff63c" spirit:order="5600" spirit:configGroups="5 Hardware Breakpoints">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_TRACE_SIZE</spirit:name>
+      <spirit:displayName>Trace Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_TRACE_SIZE" spirit:choiceRef="choice_pairs_126baff7" spirit:order="5700" spirit:configGroups="5 Hardware Breakpoints">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_TRACE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_EXTERNAL_TRACE</spirit:name>
+      <spirit:displayName>External Trace</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5650" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_EXTERNAL_TRACE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_TRACE_ASYNC_RESET</spirit:name>
+      <spirit:displayName>Use Asynchrnous Reset for External Trace</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_TRACE_ASYNC_RESET" spirit:order="5655" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_TRACE_ASYNC_RESET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_PROFILE_SIZE</spirit:name>
+      <spirit:displayName>Profile Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_PROFILE_SIZE" spirit:choiceRef="choice_pairs_5b1842a1" spirit:order="5800" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_PROFILE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERRUPT_IS_EDGE</spirit:name>
+      <spirit:displayName>Sense Interrupt on Edge vs. Level</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERRUPT_IS_EDGE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6000" spirit:configGroups="6 Interrupt">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERRUPT_IS_EDGE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EDGE_IS_POSITIVE</spirit:name>
+      <spirit:displayName>Sense Interrupt on Rising vs. Falling Edge</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EDGE_IS_POSITIVE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 Interrupt">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_EDGE_IS_POSITIVE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ASYNC_INTERRUPT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ASYNC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703" spirit:order="6600" spirit:configGroups="6 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ASYNC_INTERRUPT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ASYNC_WAKEUP</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ASYNC_WAKEUP" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="6650" spirit:configGroups="6 NoDisplay">3</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ASYNC_WAKEUP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_IE</spirit:name>
+      <spirit:displayName>IE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_IE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6201" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_IE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_BIP</spirit:name>
+      <spirit:displayName>BIP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_BIP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6202" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_BIP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_ICE</spirit:name>
+      <spirit:displayName>ICE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_ICE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6203" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_ICE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_DCE</spirit:name>
+      <spirit:displayName>DCE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_DCE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6204" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_DCE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_EE</spirit:name>
+      <spirit:displayName>EE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_EE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6205" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_EE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_EIP</spirit:name>
+      <spirit:displayName>EIP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_EIP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6206" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_EIP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPCODE_0x0_ILLEGAL</spirit:name>
+      <spirit:displayName>Generate Illegal Instruction Exception for NULL Instruction</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPCODE_0x0_ILLEGAL" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2070" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_OPCODE_0x0_ILLEGAL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FSL_LINKS</spirit:name>
+      <spirit:displayName>Number of Stream Links</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FSL_LINKS" spirit:order="8000" spirit:configGroups="8 NoDisplay" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FSL_LINKS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_EXTENDED_FSL_INSTR</spirit:name>
+      <spirit:displayName>Enable Additional Stream Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_EXTENDED_FSL_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8004" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_EXTENDED_FSL_INSTR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M0_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M0_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8520" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M0_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S0_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S0_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8530" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S0_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M1_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M1_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8560" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M1_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S1_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S1_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8570" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S1_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M2_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M2_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8600" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M2_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S2_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S2_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8610" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S2_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M3_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M3_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8640" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M3_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S3_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S3_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8650" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S3_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M4_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M4_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8680" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M4_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S4_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S4_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8690" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S4_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M5_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M5_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8720" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M5_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S5_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S5_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8730" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S5_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M6_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M6_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8760" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M6_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S6_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S6_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8770" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S6_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M7_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M7_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8800" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M7_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S7_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S7_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8810" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S7_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M8_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M8_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8840" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M8_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S8_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S8_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8850" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S8_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M9_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M9_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8880" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M9_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S9_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S9_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8890" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S9_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M10_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M10_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8920" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M10_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S10_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S10_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8930" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S10_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M11_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M11_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8960" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M11_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S11_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S11_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8970" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S11_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M12_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M12_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9000" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M12_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S12_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S12_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9010" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S12_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M13_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M13_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9040" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M13_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S13_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S13_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9050" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S13_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M14_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M14_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9080" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M14_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S14_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S14_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9090" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S14_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M15_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M15_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9120" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M15_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S15_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S15_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9130" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S15_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M0_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M0_AXIS_DATA_WIDTH" spirit:order="8500" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M0_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S0_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S0_AXIS_DATA_WIDTH" spirit:order="8510" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S0_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M1_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M1_AXIS_DATA_WIDTH" spirit:order="8540" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M1_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S1_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S1_AXIS_DATA_WIDTH" spirit:order="8550" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S1_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M2_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M2_AXIS_DATA_WIDTH" spirit:order="8580" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M2_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S2_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S2_AXIS_DATA_WIDTH" spirit:order="8590" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S2_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M3_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M3_AXIS_DATA_WIDTH" spirit:order="8620" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M3_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S3_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S3_AXIS_DATA_WIDTH" spirit:order="8630" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S3_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M4_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M4_AXIS_DATA_WIDTH" spirit:order="8660" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M4_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S4_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S4_AXIS_DATA_WIDTH" spirit:order="8670" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S4_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M5_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M5_AXIS_DATA_WIDTH" spirit:order="8700" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M5_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S5_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S5_AXIS_DATA_WIDTH" spirit:order="8710" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S5_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M6_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M6_AXIS_DATA_WIDTH" spirit:order="8740" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M6_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S6_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S6_AXIS_DATA_WIDTH" spirit:order="8750" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S6_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M7_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M7_AXIS_DATA_WIDTH" spirit:order="8780" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M7_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S7_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S7_AXIS_DATA_WIDTH" spirit:order="8790" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S7_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M8_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M8_AXIS_DATA_WIDTH" spirit:order="8820" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M8_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S8_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S8_AXIS_DATA_WIDTH" spirit:order="8830" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S8_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M9_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M9_AXIS_DATA_WIDTH" spirit:order="8860" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M9_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S9_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S9_AXIS_DATA_WIDTH" spirit:order="8870" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S9_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M10_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M10_AXIS_DATA_WIDTH" spirit:order="8900" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M10_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S10_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S10_AXIS_DATA_WIDTH" spirit:order="8910" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S10_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M11_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M11_AXIS_DATA_WIDTH" spirit:order="8940" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M11_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S11_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S11_AXIS_DATA_WIDTH" spirit:order="8950" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S11_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M12_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M12_AXIS_DATA_WIDTH" spirit:order="8980" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M12_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S12_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S12_AXIS_DATA_WIDTH" spirit:order="8990" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S12_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M13_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M13_AXIS_DATA_WIDTH" spirit:order="9020" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M13_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S13_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S13_AXIS_DATA_WIDTH" spirit:order="9030" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S13_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M14_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M14_AXIS_DATA_WIDTH" spirit:order="9060" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M14_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S14_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S14_AXIS_DATA_WIDTH" spirit:order="9070" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S14_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M15_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M15_AXIS_DATA_WIDTH" spirit:order="9100" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M15_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S15_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S15_AXIS_DATA_WIDTH" spirit:order="9110" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S15_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_BASEADDR</spirit:name>
+      <spirit:displayName>Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_BASEADDR" spirit:order="3040" spirit:configGroups="3 Instruction Cache Feature" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_HIGHADDR</spirit:name>
+      <spirit:displayName>High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_HIGHADDR" spirit:order="3030" spirit:configGroups="3 Instruction Cache Feature" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_ICACHE</spirit:name>
+      <spirit:displayName>Enable Instruction Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_ICACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3000" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_ICACHE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ALLOW_ICACHE_WR</spirit:name>
+      <spirit:displayName>Enable Writes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALLOW_ICACHE_WR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3050" spirit:configGroups="3 Instruction Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ALLOW_ICACHE_WR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ADDR_TAG_BITS</spirit:name>
+      <spirit:displayName>Set number of I-cache address tag bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_TAG_BITS" spirit:order="3200" spirit:configGroups="3 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ADDR_TAG_BITS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CACHE_BYTE_SIZE</spirit:name>
+      <spirit:displayName>Size in Bytes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448" spirit:order="3010" spirit:configGroups="3 Instruction Cache Feature">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CACHE_BYTE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_LINE_LEN</spirit:name>
+      <spirit:displayName>Line Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf" spirit:order="3020" spirit:configGroups="3 Instruction Cache Feature">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_LINE_LEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_ALWAYS_USED</spirit:name>
+      <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3060" spirit:configGroups="3 Instruction Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_ALWAYS_USED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_VICTIMS</spirit:name>
+      <spirit:displayName>Number of Victims</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab" spirit:order="3090" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_VICTIMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_STREAMS</spirit:name>
+      <spirit:displayName>Number of Streams</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_STREAMS" spirit:choiceRef="choice_list_8af5a703" spirit:order="3080" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_STREAMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_FORCE_TAG_LUTRAM</spirit:name>
+      <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3070" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_FORCE_TAG_LUTRAM">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9" spirit:order="3220" spirit:configGroups="3 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_THREAD_ID_WIDTH" spirit:order="8380" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH" spirit:order="8390" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_AWUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_AWUSER_WIDTH" spirit:order="8400" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_AWUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_ARUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_ARUSER_WIDTH" spirit:order="8410" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_ARUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_WUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH" spirit:order="8420" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_WUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_RUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_RUSER_WIDTH" spirit:order="8430" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_RUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_BUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_BUSER_WIDTH" spirit:order="8440" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_BUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_USER_VALUE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_USER_VALUE" spirit:order="8450" spirit:configGroups="8 NoDisplay">31</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_USER_VALUE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_BASEADDR</spirit:name>
+      <spirit:displayName>Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_BASEADDR" spirit:order="3140" spirit:configGroups="3 Data Cache Feature" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_HIGHADDR</spirit:name>
+      <spirit:displayName>High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_HIGHADDR" spirit:order="3130" spirit:configGroups="3 Data Cache Feature" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_DCACHE</spirit:name>
+      <spirit:displayName>Enable Data Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_DCACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3100" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_DCACHE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ALLOW_DCACHE_WR</spirit:name>
+      <spirit:displayName>Enable Writes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALLOW_DCACHE_WR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3150" spirit:configGroups="3 Data Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ALLOW_DCACHE_WR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_ADDR_TAG</spirit:name>
+      <spirit:displayName>Set number of D-cache address tag bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_ADDR_TAG" spirit:order="3230" spirit:configGroups="3 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_ADDR_TAG">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_BYTE_SIZE</spirit:name>
+      <spirit:displayName>Size in Bytes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448" spirit:order="3110" spirit:configGroups="3 Data Cache Feature">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_BYTE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_LINE_LEN</spirit:name>
+      <spirit:displayName>Line Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf" spirit:order="3120" spirit:configGroups="3 Data Cache Feature">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_LINE_LEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_ALWAYS_USED</spirit:name>
+      <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3160" spirit:configGroups="3 Data Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_ALWAYS_USED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_USE_WRITEBACK</spirit:name>
+      <spirit:displayName>Enable Write-back Storage Policy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_USE_WRITEBACK" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3180" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_USE_WRITEBACK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_VICTIMS</spirit:name>
+      <spirit:displayName>Number of Victims</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab" spirit:order="3190" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_VICTIMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_FORCE_TAG_LUTRAM</spirit:name>
+      <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3170" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_FORCE_TAG_LUTRAM">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9" spirit:order="3250" spirit:configGroups="3 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_THREAD_ID_WIDTH" spirit:order="8280" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH" spirit:order="8290" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_AWUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_AWUSER_WIDTH" spirit:order="8300" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_AWUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_ARUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_ARUSER_WIDTH" spirit:order="8310" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_ARUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_WUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_WUSER_WIDTH" spirit:order="8320" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_WUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_RUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_RUSER_WIDTH" spirit:order="8330" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_RUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_BUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_BUSER_WIDTH" spirit:order="8340" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_BUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_EXCLUSIVE_ACCESS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS" spirit:order="8350" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_EXCLUSIVE_ACCESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_USER_VALUE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_USER_VALUE" spirit:order="8360" spirit:configGroups="8 NoDisplay">31</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_USER_VALUE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_MMU</spirit:name>
+      <spirit:displayName>Memory Management</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_MMU" spirit:choiceRef="choice_pairs_0000a26c" spirit:order="4000" spirit:configGroups="4 Memory Management Unit">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_MMU">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MMU_DTLB_SIZE</spirit:name>
+      <spirit:displayName>Data Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_DTLB_SIZE" spirit:choiceRef="choice_list_dd2843c6" spirit:order="4100" spirit:configGroups="4 Memory Management Unit">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MMU_DTLB_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MMU_ITLB_SIZE</spirit:name>
+      <spirit:displayName>Instruction Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_ITLB_SIZE" spirit:choiceRef="choice_list_dd2843c6" spirit:order="4200" spirit:configGroups="4 Memory Management Unit">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MMU_ITLB_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
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+      <spirit:displayName>Privileged Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_PRIVILEGED_INSTR" spirit:choiceRef="choice_pairs_443ae6cc" spirit:order="4500" spirit:configGroups="4 Memory Management Unit">0</spirit:value>
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+      <spirit:displayName>Use Interrupt</spirit:displayName>
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+      <spirit:displayName>Use Monitor Interface for Interrupt</spirit:displayName>
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+      <spirit:displayName>Use Non-Secure AXI access permission</spirit:displayName>
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+      <spirit:displayName>Enable Branch Target Cache</spirit:displayName>
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+      <spirit:displayName>Branch Target Cache Size</spirit:displayName>
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+          <xilinx:enablement>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_microblaze_I_0</spirit:value>
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+    <xilinx:coreExtensions>
+      <xilinx:displayName>MicroBlaze</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.DATA_WIDTH" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_D_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EDGE_IS_POSITIVE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_I_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUMBER_OF_PC_BRK" xilinx:valueSource="user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_BRK" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_HW_MUL" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_INTERRUPT" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_NON_SECURE" xilinx:valueSource="propagated"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR" xilinx:valueSource="user"/>
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+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cf8c578c"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="33347ad3"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci
new file mode 100644
index 0000000..f42d0e4
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xci
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:library>xci</spirit:library>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;slowest_sync_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ext_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;aux_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mb_debug_sys_rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dcm_locked&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mb_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;bus_struct_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;peripheral_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;interconnect_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;peripheral_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;clock&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;mb_reset:bus_struct_re
+set:interconnect_aresetn:peripheral_aresetn:peripheral_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;slowest_sync_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ext_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:res
+et:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;ext_reset_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;aux_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;aux_reset_in&quot;,&quot;ph
+ysical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;dbg_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;mb_debug_sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;mb_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissi
+on&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;mb_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;bus_struct_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;bus_struct_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;interconnect_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_perm
+ission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;interconnect_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;peripheral_high_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;peripheral_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,
+&quot;logical_right&quot;:&quot;0&quot;}}},&quot;peripheral_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;peripheral_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml
new file mode 100644
index 0000000..5e5d064
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/bd_9f2c_rst_0_0.xml
@@ -0,0 +1,691 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_rst_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>clock</spirit:name>
+      <spirit:displayName>Clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>slowest_sync_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
+          <spirit:description>Slowest Synchronous clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ext_reset</spirit:name>
+      <spirit:displayName>Ext_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>aux_reset</spirit:name>
+      <spirit:displayName>aux_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aux_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>dbg_reset</spirit:name>
+      <spirit:displayName>DBG_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>mb_debug_sys_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>mb_rst</spirit:name>
+      <spirit:displayName>MB_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mb_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>bus_struct_reset</spirit:name>
+      <spirit:displayName>bus_struct_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>bus_struct_reset</spirit:name>
+          </spirit:physicalPort>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interconnect_low_rst</spirit:name>
+      <spirit:displayName>interconnect_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interconnect_aresetn</spirit:name>
+          </spirit:physicalPort>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>peripheral_high_rst</spirit:name>
+      <spirit:displayName>peripheral_high_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>peripheral_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>peripheral_low_rst</spirit:name>
+      <spirit:displayName>peripheral_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>peripheral_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>slowest_sync_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_reset_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>aux_reset_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mb_debug_sys_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dcm_locked</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mb_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>bus_struct_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_BUS_RST&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>peripheral_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_RST&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>interconnect_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>peripheral_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_ARESETN&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+        <spirit:displayName>Ext Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+        <spirit:displayName>Aux Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+        <spirit:displayName>Aux Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_BUS_RST</spirit:name>
+        <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_RST</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+        <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_caf95c77</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>resetn</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Processor Reset System</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+      <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_RST</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_BUS_RST</spirit:name>
+      <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+      <spirit:displayName>Aux Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+      <spirit:displayName>Ext Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+      <spirit:displayName>Aux Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+      <spirit:displayName>Ext Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_rst_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_caf95c77" spirit:order="3">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Processor System Reset</xilinx:displayName>
+      <xilinx:coreRevision>13</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci
new file mode 100644
index 0000000..6c5836a
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xci
@@ -0,0 +1,309 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>bd_9f2c_iomodule_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="iomodule" spirit:version="3.1"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTC_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTC_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT2_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_INTR_SIZE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_NUM_SYNC_FF">2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IO_BASEADDR">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IO_HIGHADDR">0x00000000FFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IO_MASK">0x00000000C0000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO2_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO3_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO4_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x000000008000FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">iomodule</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS">0x0000000000000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_NUM_SYNC_FF">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_POSITIVE">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_USE_EXT_INTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IO_BASEADDR">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IO_HIGHADDR">0x00000000FFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IO_MASK">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TMR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_BAUDRATE">9600</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_DATA_BITS">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_ERROR_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_ODD_PARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_PROG_BAUDRATE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_RX_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_TX_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_USE_PARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_IO_BUS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TMR_DISABLE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_UART_RX">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_UART_TX">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_9f2c_iomodule_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO3_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_HAS_FAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_INTR_SIZE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_LEVEL_EDGE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_POSITIVE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_IO_BUS" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Addr_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Read_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Write_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Address&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Write_Data&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Read_Data&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LM
+B_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_s
+rc&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,
+&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;Rst:TMR_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{
+&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.TMR_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;IO_BUS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mcsio_bus:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mcsio_bus_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Addr_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;IO_Address&quot;,&quot;phy
+sical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;IO_Byte_Enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_Read_Data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Read_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IO_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_Write_Data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Write_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml
new file mode 100644
index 0000000..8d364bd
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/bd_9f2c_iomodule_0_0.xml
@@ -0,0 +1,8812 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_iomodule_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.CLK</spirit:name>
+      <spirit:displayName>Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF">SLMB</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET">Rst:TMR_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Clk frequency</spirit:displayName>
+          <spirit:description>Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.Rst</spirit:name>
+      <spirit:displayName>Rst</spirit:displayName>
+      <spirit:description>Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
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+          <spirit:vendorExtensions>
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+      <spirit:displayName>FIT1_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+      <spirit:displayName>FIT2_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+          <spirit:vendorExtensions>
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+      <spirit:displayName>FIT3_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>FIT3_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+      <spirit:name>INTERRUPT.FIT4_Interrupt</spirit:name>
+      <spirit:displayName>FIT4_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>FIT4_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:displayName>PIT1_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>PIT1_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT1_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:displayName>PIT2_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+            <spirit:name>PIT2_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT2_INTERRUPT.PortWidth">1</spirit:value>
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+      <spirit:name>INTERRUPT.PIT3_Interrupt</spirit:name>
+      <spirit:displayName>PIT3_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+            <spirit:name>PIT3_Interrupt</spirit:name>
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+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT3_INTERRUPT.PortWidth">1</spirit:value>
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+      <spirit:name>INTERRUPT.PIT4_Interrupt</spirit:name>
+      <spirit:displayName>PIT4_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>PIT4_Interrupt</spirit:name>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.PIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI1_Interrupt</spirit:name>
+      <spirit:displayName>GPI1_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI1_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI2_Interrupt</spirit:name>
+      <spirit:displayName>GPI2_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI2_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI3_Interrupt</spirit:name>
+      <spirit:displayName>GPI3_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI3_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI4_Interrupt</spirit:name>
+      <spirit:displayName>GPI4_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI4_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Interrupt</spirit:name>
+      <spirit:displayName>INTC_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Interrupt" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Irq_Single</spirit:name>
+      <spirit:displayName>INTC_IRQ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Irq_Single" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Irq</spirit:name>
+      <spirit:displayName>INTC_IRQ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Processor_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTC_IRQ.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_IRQ.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Irq" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTC_Irq_Out</spirit:name>
+      <spirit:displayName>INTC_IRQ_OUT</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ_OUT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTC_Irq_Out" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_USE_IRQ_OUT&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART</spirit:name>
+      <spirit:displayName>UART</spirit:displayName>
+      <spirit:description>UART TX/RX</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RxD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TxD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART.BOARD.ASSOCIATED_PARAM">UART_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART_CLK.CLK</spirit:name>
+      <spirit:displayName>UART_Clk</spirit:displayName>
+      <spirit:description>Asynchronous UART Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.ASSOCIATED_BUSIF">SLMB</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.ASSOCIATED_RESET">UART_Rst:TMR_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>UART Clk frequency</spirit:displayName>
+          <spirit:description>UART Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART_CLK.CLK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART_RST.Rst</spirit:name>
+      <spirit:displayName>UART_Rst</spirit:displayName>
+      <spirit:description>Asynchronous UART Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART_RST.Rst" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO1</spirit:name>
+      <spirit:displayName>GPIO1</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO1</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_USE_GPO1" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_USE_GPO1" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO1_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPO1_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPO1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO1_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPO1_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPO1_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI1</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_USE_GPI1" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_USE_GPI1" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI1_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPI1_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPI1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPI1_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPI1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO1.BOARD.ASSOCIATED_PARAM">GPIO1_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO2</spirit:name>
+      <spirit:displayName>GPIO2</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO2</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_USE_GPO2" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_USE_GPO2" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO2_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPO2_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPO2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO2_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPO2_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPO2_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI2</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_USE_GPI2" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_USE_GPI2" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI2_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPI2_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPI2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPI2_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPI2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO2.BOARD.ASSOCIATED_PARAM">GPIO2_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO3</spirit:name>
+      <spirit:displayName>GPIO3</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO3</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_USE_GPO3" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_USE_GPO3" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO3_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPO3_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPO3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO3_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPO3_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPO3_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI3</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_USE_GPI3" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_USE_GPI3" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI3_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPI3_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPI3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPI3_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPI3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO3.BOARD.ASSOCIATED_PARAM">GPIO3_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO4</spirit:name>
+      <spirit:displayName>GPIO4</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO4</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_USE_GPO4" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_USE_GPO4" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO4_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPO4_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPO4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO4_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPO4_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPO4_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI4</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_USE_GPI4" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_USE_GPI4" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI4_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPI4_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPI4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPI4_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPI4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO4.BOARD.ASSOCIATED_PARAM">GPIO4_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>LMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="2048" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.REG.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.REG.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>UART_RX</spirit:name>
+          <spirit:displayName>UART Receive Data Register</spirit:displayName>
+          <spirit:description>UART Receive Data Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>Receive Data</spirit:displayName>
+            <spirit:description>Data received by the UART.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_RX" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_TX</spirit:name>
+          <spirit:displayName>UART Transmit Data Register</spirit:displayName>
+          <spirit:description>UART Transmit Data Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>Transmit Data</spirit:displayName>
+            <spirit:description>Data to be transmitted by the UART.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_TX" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_Status</spirit:name>
+          <spirit:displayName>UART Status Register</spirit:displayName>
+          <spirit:description>UART Status Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Rx_Valid_Data</spirit:name>
+            <spirit:displayName>Rx Valid Data</spirit:displayName>
+            <spirit:description>Indicates if the receive register has valid data:
+  0 - Receive register is empty.
+  1 - Receive register has valid data.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Tx_Used</spirit:name>
+            <spirit:displayName>Tx Used</spirit:displayName>
+            <spirit:description>Indicates if the transmit register is in use:
+  0 - Transmit register is not in use.
+  1 - Transmit register is in use.
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Overrun_Error</spirit:name>
+            <spirit:displayName>Overrun Error</spirit:displayName>
+            <spirit:description>Indicates that an overrun error has occurred:
+  0 - No overrun has occurred.
+  1 - An overrun has occurred.
+</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Frame_Error</spirit:name>
+            <spirit:displayName>Frame Error</spirit:displayName>
+            <spirit:description>Indicates that an frame error has occurred:
+  0 - No frame error has occurred.
+  1 - A frame error has occurred.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Parity_Error</spirit:name>
+            <spirit:displayName>Parity Error</spirit:displayName>
+            <spirit:description>Indicates that a parity error has occurred:
+  0 - No parity error has occurred.
+  1 - A parity error occurred.
+</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_MODE</spirit:name>
+          <spirit:displayName>Interrupt Mode Register</spirit:displayName>
+          <spirit:description>Interrupt Mode Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Mode</spirit:name>
+            <spirit:displayName>IRQ Mode</spirit:displayName>
+            <spirit:description>Interrupt Mode.
+For each bit:
+  W - When written with 1 the corresponding interrupt will use fast mode.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_MODE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_1</spirit:name>
+          <spirit:displayName>General Purpose Output 1 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 1 Register</spirit:description>
+          <spirit:addressOffset>0x10</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_2</spirit:name>
+          <spirit:displayName>General Purpose Output 2 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 2 Register</spirit:description>
+          <spirit:addressOffset>0x14</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_3</spirit:name>
+          <spirit:displayName>General Purpose Output 3 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 3 Register</spirit:description>
+          <spirit:addressOffset>0x18</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_4</spirit:name>
+          <spirit:displayName>General Purpose Output 4 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 4 Register</spirit:description>
+          <spirit:addressOffset>0x1C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_1</spirit:name>
+          <spirit:displayName>General Purpose Input 1 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 1 Register</spirit:description>
+          <spirit:addressOffset>0x20</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_2</spirit:name>
+          <spirit:displayName>General Purpose Input 2 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 2 Register</spirit:description>
+          <spirit:addressOffset>0x24</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_3</spirit:name>
+          <spirit:displayName>General Purpose Input 3 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 3 Register</spirit:description>
+          <spirit:addressOffset>0x28</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_4</spirit:name>
+          <spirit:displayName>General Purpose Input 4 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 4 Register</spirit:description>
+          <spirit:addressOffset>0x2C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_STATUS</spirit:name>
+          <spirit:displayName>Interrupt Status Register</spirit:displayName>
+          <spirit:description>Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>0x30</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 lapsed.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 lapsed.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 lapsed.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 lapsed.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 strobe.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 strobe.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 strobe.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 strobe.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 changed.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 changed.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 changed.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 changed.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>External interrupt input signal</spirit:displayName>
+            <spirit:description>Interrupt Status Register.
+For each bit:
+  R - Reads active interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_STATUS" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_PENDING</spirit:name>
+          <spirit:displayName>Interrupt Pending Register</spirit:displayName>
+          <spirit:description>Interrupt Pending Register</spirit:description>
+          <spirit:addressOffset>0x34</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 lapsed.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 lapsed.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 lapsed.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 lapsed.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 strobe.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 strobe.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 strobe.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 strobe.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 changed.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 changed.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 changed.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 changed.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>Enabled interrupt events that have occurred</spirit:displayName>
+            <spirit:description>Interrupt Pending.
+For each bit:
+  R - Reads enabled interrupt event that has occurred.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_PENDING" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_ENABLE</spirit:name>
+          <spirit:displayName>Interrupt Enable Register</spirit:displayName>
+          <spirit:description>Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x38</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt enabled.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>Enable external interrupt input signals</spirit:displayName>
+            <spirit:description>Interrupt Enable.
+For each bit:
+  W - Enable external interrupt input signal.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_ENABLE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_ACK</spirit:name>
+          <spirit:displayName>Interrupt Acknowledge Register</spirit:displayName>
+          <spirit:description>Interrupt Acknowledge Register</spirit:description>
+          <spirit:addressOffset>0x3C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Acknowledge</spirit:name>
+            <spirit:displayName>IRQ Acknowledge</spirit:displayName>
+            <spirit:description>Interrupt Acknowledge.
+For each bit:
+  W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_ACK" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 1 Preload Register</spirit:displayName>
+          <spirit:description>PIT 1 Preload Register</spirit:description>
+          <spirit:addressOffset>0x40</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT1_Preload</spirit:name>
+            <spirit:displayName>PIT1 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_COUNTER</spirit:name>
+          <spirit:displayName>PIT 1 Counter Register</spirit:displayName>
+          <spirit:description>PIT 1 Counter Register</spirit:description>
+          <spirit:addressOffset>0x44</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT1_Counter</spirit:name>
+            <spirit:displayName>PIT1 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_CONTROL</spirit:name>
+          <spirit:displayName>PIT 1 Control Register</spirit:displayName>
+          <spirit:description>PIT 1 Control Register</spirit:description>
+          <spirit:addressOffset>0x48</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT1_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_BAUD</spirit:name>
+          <spirit:displayName>UART Programmable Baud Rate</spirit:displayName>
+          <spirit:description>UART Programmable Baud Rate</spirit:description>
+          <spirit:addressOffset>0x4C</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_BAUD</spirit:name>
+            <spirit:displayName>Baud Rate</spirit:displayName>
+            <spirit:description>Programmable UART Baud Rate.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">20</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_BAUD" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_PROG_BAUDRATE&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 2 Preload Register</spirit:displayName>
+          <spirit:description>PIT 2 Preload Register</spirit:description>
+          <spirit:addressOffset>0x50</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT2_Preload</spirit:name>
+            <spirit:displayName>PIT2 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_COUNTER</spirit:name>
+          <spirit:displayName>PIT 2 Counter Register</spirit:displayName>
+          <spirit:description>PIT 2 Counter Register</spirit:description>
+          <spirit:addressOffset>0x54</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT2_Counter</spirit:name>
+            <spirit:displayName>PIT2 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_CONTROL</spirit:name>
+          <spirit:displayName>PIT 2 Control Register</spirit:displayName>
+          <spirit:description>PIT 2 Control Register</spirit:description>
+          <spirit:addressOffset>0x58</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT2_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 3 Preload Register</spirit:displayName>
+          <spirit:description>PIT 3 Preload Register</spirit:description>
+          <spirit:addressOffset>0x60</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT3_Preload</spirit:name>
+            <spirit:displayName>PIT3 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_COUNTER</spirit:name>
+          <spirit:displayName>PIT 3 Counter Register</spirit:displayName>
+          <spirit:description>PIT 3 Counter Register</spirit:description>
+          <spirit:addressOffset>0x64</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT3_Counter</spirit:name>
+            <spirit:displayName>PIT3 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_CONTROL</spirit:name>
+          <spirit:displayName>PIT 3 Control Register</spirit:displayName>
+          <spirit:description>PIT 3 Control Register</spirit:description>
+          <spirit:addressOffset>0x68</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT3_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 4 Preload Register</spirit:displayName>
+          <spirit:description>PIT 4 Preload Register</spirit:description>
+          <spirit:addressOffset>0x70</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT4_Preload</spirit:name>
+            <spirit:displayName>PIT4 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_COUNTER</spirit:name>
+          <spirit:displayName>PIT 4 Counter Register</spirit:displayName>
+          <spirit:description>PIT 4 Counter Register</spirit:description>
+          <spirit:addressOffset>0x74</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT4_Counter</spirit:name>
+            <spirit:displayName>PIT4 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_CONTROL</spirit:name>
+          <spirit:displayName>PIT 4 Control Register</spirit:displayName>
+          <spirit:description>PIT 4 Control Register</spirit:description>
+          <spirit:addressOffset>0x78</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT4_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_0</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 0</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 0</spirit:description>
+          <spirit:addressOffset>0x80</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 0 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_1</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 1</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 1</spirit:description>
+          <spirit:addressOffset>0x84</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 1 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_2</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 2</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 2</spirit:description>
+          <spirit:addressOffset>0x88</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 2 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_3</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 3</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 3</spirit:description>
+          <spirit:addressOffset>0x8C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 3 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_4</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 4</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 4</spirit:description>
+          <spirit:addressOffset>0x90</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 4 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_5</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 5</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 5</spirit:description>
+          <spirit:addressOffset>0x94</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 5 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_6</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 6</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 6</spirit:description>
+          <spirit:addressOffset>0x98</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 6 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_7</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 7</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 7</spirit:description>
+          <spirit:addressOffset>0x9C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 7 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_8</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 8</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 8</spirit:description>
+          <spirit:addressOffset>0xA0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 8 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_9</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 9</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 9</spirit:description>
+          <spirit:addressOffset>0xA4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 9 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_10</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 10</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 10</spirit:description>
+          <spirit:addressOffset>0xA8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 10 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_11</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 11</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 11</spirit:description>
+          <spirit:addressOffset>0xAC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 11 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_12</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 12</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 12</spirit:description>
+          <spirit:addressOffset>0xB0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 12 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_13</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 13</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 13</spirit:description>
+          <spirit:addressOffset>0xB4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 13 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_14</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 14</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 14</spirit:description>
+          <spirit:addressOffset>0xB8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 14 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_14" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_16</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 16</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 16</spirit:description>
+          <spirit:addressOffset>0xC0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 16 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_16" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_17</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 17</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 17</spirit:description>
+          <spirit:addressOffset>0xC4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 17 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_17" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 2)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_18</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 18</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 18</spirit:description>
+          <spirit:addressOffset>0xC8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 18 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_18" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 3)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_19</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 19</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 19</spirit:description>
+          <spirit:addressOffset>0xCC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 19 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_19" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 4)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_20</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 20</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 20</spirit:description>
+          <spirit:addressOffset>0xD0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 20 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_20" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 5)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_21</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 21</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 21</spirit:description>
+          <spirit:addressOffset>0xD4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 21 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_21" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 6)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_22</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 22</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 22</spirit:description>
+          <spirit:addressOffset>0xD8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 22 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_22" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 7)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_23</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 23</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 23</spirit:description>
+          <spirit:addressOffset>0xDC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 23 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_23" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 8)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_24</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 24</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 24</spirit:description>
+          <spirit:addressOffset>0xE0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 24 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_24" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 9)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_25</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 25</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 25</spirit:description>
+          <spirit:addressOffset>0xE4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 25 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_25" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 10)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_26</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 26</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 26</spirit:description>
+          <spirit:addressOffset>0xE8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 26 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_26" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 11)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_27</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 27</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 27</spirit:description>
+          <spirit:addressOffset>0xEC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 27 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_27" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 12)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_28</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 28</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 28</spirit:description>
+          <spirit:addressOffset>0xF0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 28 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_28" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 13)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_29</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 29</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 29</spirit:description>
+          <spirit:addressOffset>0xF4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 29 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_29" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 14)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_30</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 30</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 30</spirit:description>
+          <spirit:addressOffset>0xF8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 30 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_30" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 15)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_31</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 31</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 31</spirit:description>
+          <spirit:addressOffset>0xFC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 31 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_31" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 16)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_0</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 0</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 0</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 0 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_1</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 1</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 1</spirit:description>
+          <spirit:addressOffset>0x108</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 1 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_2</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 2</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 2</spirit:description>
+          <spirit:addressOffset>0x110</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 2 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_3</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 3</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 3</spirit:description>
+          <spirit:addressOffset>0x118</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 3 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_4</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 4</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 4</spirit:description>
+          <spirit:addressOffset>0x120</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 4 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_5</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 5</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 5</spirit:description>
+          <spirit:addressOffset>0x128</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 5 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_6</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 6</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 6</spirit:description>
+          <spirit:addressOffset>0x130</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 6 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_7</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 7</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 7</spirit:description>
+          <spirit:addressOffset>0x138</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 7 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_8</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 8</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 8</spirit:description>
+          <spirit:addressOffset>0x140</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 8 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_9</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 9</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 9</spirit:description>
+          <spirit:addressOffset>0x148</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 9 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_10</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 10</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 10</spirit:description>
+          <spirit:addressOffset>0x150</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 10 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_11</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 11</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 11</spirit:description>
+          <spirit:addressOffset>0x158</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 11 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_12</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 12</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 12</spirit:description>
+          <spirit:addressOffset>0x160</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 12 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_13</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 13</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 13</spirit:description>
+          <spirit:addressOffset>0x168</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 13 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_14</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 14</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 14</spirit:description>
+          <spirit:addressOffset>0x170</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 14 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_14" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_16</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 16</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 16</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 16 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_16" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_17</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 17</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 17</spirit:description>
+          <spirit:addressOffset>0x188</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 17 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_17" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 2)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_18</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 18</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 18</spirit:description>
+          <spirit:addressOffset>0x190</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 18 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_18" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 3)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_19</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 19</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 19</spirit:description>
+          <spirit:addressOffset>0x198</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 19 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_19" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 4)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_20</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 20</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 20</spirit:description>
+          <spirit:addressOffset>0x1A0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 20 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_20" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 5)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_21</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 21</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 21</spirit:description>
+          <spirit:addressOffset>0x1A8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 21 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_21" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 6)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_22</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 22</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 22</spirit:description>
+          <spirit:addressOffset>0x1B0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 22 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_22" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 7)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_23</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 23</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 23</spirit:description>
+          <spirit:addressOffset>0x1B8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 23 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_23" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 8)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_24</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 24</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 24</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 24 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_24" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 9)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_25</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 25</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 25</spirit:description>
+          <spirit:addressOffset>0x1C8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 25 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_25" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 10)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_26</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 26</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 26</spirit:description>
+          <spirit:addressOffset>0x1D0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 26 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_26" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 11)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_27</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 27</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 27</spirit:description>
+          <spirit:addressOffset>0x1D8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 27 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_27" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 12)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_28</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 28</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 28</spirit:description>
+          <spirit:addressOffset>0x1E0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 28 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_28" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 13)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_29</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 29</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 29</spirit:description>
+          <spirit:addressOffset>0x1E8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 29 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_29" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 14)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_30</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 30</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 30</spirit:description>
+          <spirit:addressOffset>0x1F0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 30 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_30" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 15)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_31</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 31</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 31</spirit:description>
+          <spirit:addressOffset>0x1F8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 31 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>IO_Read_Strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>IO_Write_Strobe</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Write_Strobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Byte_Enable" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:displayName>Serial Data In</spirit:displayName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UART_Rx" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT1_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT1_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT2_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT2_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>FIT3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT3_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT3_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT4_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT4_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT4_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT3_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT3_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT4_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        <spirit:name>PIT4_Interrupt</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
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+        <spirit:name>PIT4_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>GPO1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPO1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPO2</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI4</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI4_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Interrupt</spirit:name>
+        <spirit:displayName>Interrupt Inputs</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Interrupt" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_IRQ</spirit:name>
+        <spirit:displayName>Interrupt Request Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Processor_Ack</spirit:name>
+        <spirit:displayName>Interrupt Acknowledgement Input</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Processor_Ack" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Interrupt_Address</spirit:name>
+        <spirit:displayName>Interrupt Vector Address Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(( ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) + 31) / 64) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) - 32) + 32) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Interrupt_Address" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_IRQ_OUT</spirit:name>
+        <spirit:displayName>Interrupt Request Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_IRQ_OUT" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_USE_IRQ_OUT&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREQ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_INSTANCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INSTANCE">iomodule</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AVOID_PRIMITIVES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TMR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TMR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_TMR_DISABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_TMR_DISABLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000008000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_HIGHADDR" spirit:bitStringLength="64">0x00000000FFFFFFFF</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_HIGHADDR" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_BASEADDR" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_BASEADDR" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_MASK</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_MASK" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_MASK" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_IO_BUS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_IO_BUS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_UART_RX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_UART_RX">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_UART_TX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_UART_TX">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_BAUDRATE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_BAUDRATE">9600</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_BAUDRATE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_DATA_BITS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_DATA_BITS" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_DATA_BITS" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_USE_PARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_USE_PARITY">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_USE_PARITY" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ODD_PARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ODD_PARITY">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_ODD_PARITY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_USE_PARITY&apos;)) >= 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_RX_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_RX_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_RX_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_TX_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_TX_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_TX_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ERROR_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_ERROR_INTERRUPT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_PROG_BAUDRATE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_PROG_BAUDRATE">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_PROG_BAUDRATE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_FREQ" spirit:minimum="0" spirit:rangeType="long">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ASYNC</spirit:name>
+        <spirit:displayName>Asynchronous Clock</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ASYNC" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_NUM_SYNC_FF</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_NUM_SYNC_FF" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT1_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT1_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT1_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT1_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT2_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT2_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT2_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT2_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT3_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT3_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT3_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT3_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT4_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT4_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT4_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT4_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO1_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO1_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO1_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO2_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO2_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO2_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO3_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO3_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO3_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO4_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO4_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO4_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI1_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI2_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI3_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI4_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_USE_EXT_INTR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_USE_EXT_INTR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_INTR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_INTR_SIZE" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_INTR_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_LEVEL_EDGE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_LEVEL_EDGE" spirit:bitStringLength="16">0x0000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_LEVEL_EDGE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_POSITIVE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_POSITIVE" spirit:bitStringLength="16">0xFFFF</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_POSITIVE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_HAS_FAST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_HAS_FAST" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_ADDR_WIDTH" spirit:minimum="5" spirit:maximum="64" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_INTC_BASE_VECTORS</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_BASE_VECTORS" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_ASYNC_INTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_ASYNC_INTR" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_NUM_SYNC_FF</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_NUM_SYNC_FF" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0739ee39</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>rs232_uart</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_38e5a9f1</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>dip_switches_4bits</spirit:enumeration>
+      <spirit:enumeration>led_3bits</spirit:enumeration>
+      <spirit:enumeration>qsfp0_lowspeed</spirit:enumeration>
+      <spirit:enumeration>qsfp1_lowspeed</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8af5a703</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f585525a</spirit:name>
+      <spirit:enumeration>110</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>1200</spirit:enumeration>
+      <spirit:enumeration>2400</spirit:enumeration>
+      <spirit:enumeration>4800</spirit:enumeration>
+      <spirit:enumeration>9600</spirit:enumeration>
+      <spirit:enumeration>19200</spirit:enumeration>
+      <spirit:enumeration>38400</spirit:enumeration>
+      <spirit:enumeration>57600</spirit:enumeration>
+      <spirit:enumeration>115200</spirit:enumeration>
+      <spirit:enumeration>128000</spirit:enumeration>
+      <spirit:enumeration>230400</spirit:enumeration>
+      <spirit:enumeration>460800</spirit:enumeration>
+      <spirit:enumeration>921600</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_007f01e9</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4847022f</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_5f1e379e</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_7ba91213</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Both Edges">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Rising Edge">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="Falling Edge">3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_d4609148</spirit:name>
+      <spirit:enumeration spirit:text="Bus">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f0f6eb36</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ffa336e4</spirit:name>
+      <spirit:enumeration spirit:text="Even">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Odd">1</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>LMB module which includes plenty of I/O peripherals</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CONFIG_RESET" spirit:order="1110" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AVOID_PRIMITIVES" spirit:order="1120" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_TMR</spirit:name>
+      <spirit:displayName>Use Triple Modular Redundancy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TMR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1125" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_TMR_DISABLE</spirit:name>
+      <spirit:displayName>Activate TMR Disable Input</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_TMR_DISABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1128" spirit:configGroups="1 System">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_TMR_DISABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FREQ" spirit:order="1090" spirit:configGroups="1 System">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INSTANCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="1100" spirit:configGroups="1 System">iomodule</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_BASE_VECTORS</spirit:name>
+      <spirit:displayName>MicroBlaze Relocatable Base Vector Value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_BASE_VECTORS" spirit:order="1130" spirit:configGroups="1 NoDisplay" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>I/O Module Register Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1000" spirit:configGroups="1 System" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>I/O Module Register High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1010" spirit:configGroups="1 System" spirit:bitStringLength="64">0x000000008000FFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>I/O Module Register Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1020" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_IO_BUS</spirit:name>
+      <spirit:displayName>Enable IO Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_IO_BUS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1030" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_BASEADDR</spirit:name>
+      <spirit:displayName>I/O Module IO Bus Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_BASEADDR" spirit:order="1040" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_BASEADDR" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_HIGHADDR</spirit:name>
+      <spirit:displayName>I/O Module IO Bus High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_HIGHADDR" spirit:order="1050" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000FFFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_HIGHADDR" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_MASK</spirit:name>
+      <spirit:displayName>I/O Module IO Bus Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_MASK" spirit:order="1060" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_MASK" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1070" spirit:configGroups="1 System" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1080" spirit:configGroups="1 System">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1085" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_UART_RX</spirit:name>
+      <spirit:displayName>Enable Receiver</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_UART_RX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 UART">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_UART_TX</spirit:name>
+      <spirit:displayName>Enable Transmitter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_UART_TX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100" spirit:configGroups="2 UART">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_BAUDRATE</spirit:name>
+      <spirit:displayName>Define Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_BAUDRATE" spirit:choiceRef="choice_list_f585525a" spirit:order="2200" spirit:configGroups="2 UART">9600</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_BAUDRATE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_PROG_BAUDRATE</spirit:name>
+      <spirit:displayName>Programmable Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_PROG_BAUDRATE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_PROG_BAUDRATE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_DATA_BITS</spirit:name>
+      <spirit:displayName>Number of Data Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_DATA_BITS" spirit:order="2400" spirit:configGroups="2 UART" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_DATA_BITS" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_USE_PARITY</spirit:name>
+      <spirit:displayName>Use Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_USE_PARITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_USE_PARITY" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_ODD_PARITY</spirit:name>
+      <spirit:displayName>Even or Odd Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_ODD_PARITY" spirit:choiceRef="choice_pairs_ffa336e4" spirit:order="2600" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_ODD_PARITY" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_RX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Receive Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_RX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2700" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_RX_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_TX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Transmit Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_TX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2800" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_TX_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_ERROR_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Error Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_ERROR_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2900" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_ERROR_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT1</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3010" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT1_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT1_No_CLOCKS" spirit:order="3020" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT1_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3030" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT2</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3040" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT2_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT2_No_CLOCKS" spirit:order="3050" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT2_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3060" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT3</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3070" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT3_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT3_No_CLOCKS" spirit:order="3080" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT3_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3090" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT4</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3100" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT4_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT4_No_CLOCKS" spirit:order="3110" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT4_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3120" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT1</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4010" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_SIZE" spirit:order="4020" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4030" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_PRESCALER" spirit:choiceRef="choice_pairs_f0f6eb36" spirit:order="4040" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4050" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT2</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4060" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_SIZE" spirit:order="4070" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4080" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_PRESCALER" spirit:choiceRef="choice_pairs_007f01e9" spirit:order="4090" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4100" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT3</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4110" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_SIZE" spirit:order="4120" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4130" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_PRESCALER" spirit:choiceRef="choice_pairs_4847022f" spirit:order="4140" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4150" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT4</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4160" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_SIZE" spirit:order="4170" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4180" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_PRESCALER" spirit:choiceRef="choice_pairs_5f1e379e" spirit:order="4190" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4200" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO1</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5010" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO1_SIZE" spirit:order="5020" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO1_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO1_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO1_INIT" spirit:order="5030" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO1_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO2</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5040" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO2_SIZE" spirit:order="5050" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO2_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO2_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO2_INIT" spirit:order="5060" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO2_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO3</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5070" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO3_SIZE" spirit:order="5080" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO3_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO3_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO3_INIT" spirit:order="5090" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO3_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO4</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5100" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO4_SIZE" spirit:order="5110" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO4_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO4_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO4_INIT" spirit:order="5120" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO4_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI1</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6010" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI1_SIZE" spirit:order="6020" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI1_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI1_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6030" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI1_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI2</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6040" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI2_SIZE" spirit:order="6050" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI2_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI2_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6060" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI2_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI3</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6070" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI3_SIZE" spirit:order="6080" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI3_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI3_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6090" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI3_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI4</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI4_SIZE" spirit:order="6110" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI4_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI4_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6120" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI4_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_HAS_FAST</spirit:name>
+      <spirit:displayName>Use Low-latency Interrupt Handling</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_HAS_FAST" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7100" spirit:configGroups="7 Interrupt">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_USE_EXT_INTR</spirit:name>
+      <spirit:displayName>Use External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_USE_EXT_INTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7200" spirit:configGroups="7 Interrupt">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_USE_IRQ_OUT</spirit:name>
+      <spirit:displayName>Use Separate Interrupt Output</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_USE_IRQ_OUT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7250" spirit:configGroups="7 Interrupt">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_IRQ_CONNECTION</spirit:name>
+      <spirit:displayName>Interrupt Output Connection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_IRQ_CONNECTION" spirit:choiceRef="choice_pairs_d4609148" spirit:order="7280">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_IRQ_CONNECTION" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_INTR_SIZE</spirit:name>
+      <spirit:displayName>Number of External Inputs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_INTR_SIZE" spirit:order="7300" spirit:configGroups="7 Interrupt" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_INTR_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_LEVEL_EDGE</spirit:name>
+      <spirit:displayName>Level or Edge of External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_LEVEL_EDGE" spirit:order="7400" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0x0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_LEVEL_EDGE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_POSITIVE</spirit:name>
+      <spirit:displayName>Positive or Negative External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_POSITIVE" spirit:order="7500" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_POSITIVE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Interrupt Address Width</spirit:displayName>
+      <spirit:description>Interrupt address width with Fast Mode Interrupt.</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_ADDR_WIDTH" spirit:order="7600" spirit:configGroups="7 Interrupt" spirit:minimum="5" spirit:maximum="64" spirit:rangeType="long">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_ADDR_WIDTH" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_ASYNC_INTR</spirit:name>
+      <spirit:displayName>Interrupts asynchronous</spirit:displayName>
+      <spirit:description>The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous.</spirit:description>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_ASYNC_INTR" spirit:order="7700" spirit:bitStringLength="16">0xFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_NUM_SYNC_FF</spirit:name>
+      <spirit:displayName>Number of synchronization flip-flops</spirit:displayName>
+      <spirit:description>Number of synchronization flip-flops used to synchronize asynchronous interupt inputs</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_NUM_SYNC_FF" spirit:order="7800" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_iomodule_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="100" spirit:configGroups="0 Board">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO1_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="110" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO2_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="120" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO3_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO3_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="130" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO4_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="140" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:choiceRef="choice_list_0739ee39" spirit:order="150" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>IOModule</xilinx:displayName>
+      <xilinx:coreRevision>6</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_HAS_FAST" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_INTR_SIZE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_LEVEL_EDGE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_POSITIVE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_IO_BUS" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3e38f1f1"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="00000000"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="08f03615"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="8aacb230"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="53aec875"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="4fae1825"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci
new file mode 100644
index 0000000..a41a888
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xci
@@ -0,0 +1,159 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>bd_9f2c_ilmb_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_v10" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_9f2c_ilmb_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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+      <spirit:vendorExtensions>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;SYS_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;63&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;1&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;}},&quot;interfaces&quot;:{&quot;LMB_Sl_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_W
+IDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_
+rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBU
+S&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;63&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_M&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb
+:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredMaster&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_ONLY&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;M_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;M_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;LMB_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;
+,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;LMB_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;LMB_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;LMB_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;M_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;M_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;SYS_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[
+{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.SYS_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;SYS_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml
new file mode 100644
index 0000000..0f1e8eb
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/bd_9f2c_ilmb_0.xml
@@ -0,0 +1,3532 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_ilmb_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_0</spirit:name>
+      <spirit:displayName>LMB_Sl_00</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">31</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_0" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_1</spirit:name>
+      <spirit:displayName>LMB_Sl_01</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">32</spirit:left>
+              <spirit:right spirit:format="long">63</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_2</spirit:name>
+      <spirit:displayName>LMB_Sl_02</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">64</spirit:left>
+              <spirit:right spirit:format="long">95</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_3</spirit:name>
+      <spirit:displayName>LMB_Sl_03</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">96</spirit:left>
+              <spirit:right spirit:format="long">127</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_4</spirit:name>
+      <spirit:displayName>LMB_Sl_04</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">128</spirit:left>
+              <spirit:right spirit:format="long">159</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_5</spirit:name>
+      <spirit:displayName>LMB_Sl_05</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">160</spirit:left>
+              <spirit:right spirit:format="long">191</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_6</spirit:name>
+      <spirit:displayName>LMB_Sl_06</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">192</spirit:left>
+              <spirit:right spirit:format="long">223</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_6" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_7</spirit:name>
+      <spirit:displayName>LMB_Sl_07</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">224</spirit:left>
+              <spirit:right spirit:format="long">255</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_7" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_8</spirit:name>
+      <spirit:displayName>LMB_Sl_08</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">256</spirit:left>
+              <spirit:right spirit:format="long">287</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_8" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_9</spirit:name>
+      <spirit:displayName>LMB_Sl_09</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">288</spirit:left>
+              <spirit:right spirit:format="long">319</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_10</spirit:name>
+      <spirit:displayName>LMB_Sl_10</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">320</spirit:left>
+              <spirit:right spirit:format="long">351</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_10" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_11</spirit:name>
+      <spirit:displayName>LMB_Sl_11</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">352</spirit:left>
+              <spirit:right spirit:format="long">383</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_11" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_12</spirit:name>
+      <spirit:displayName>LMB_Sl_12</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">384</spirit:left>
+              <spirit:right spirit:format="long">415</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_13</spirit:name>
+      <spirit:displayName>LMB_Sl_13</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">416</spirit:left>
+              <spirit:right spirit:format="long">447</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_14</spirit:name>
+      <spirit:displayName>LMB_Sl_14</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">448</spirit:left>
+              <spirit:right spirit:format="long">479</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_14" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_15</spirit:name>
+      <spirit:displayName>LMB_Sl_15</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">480</spirit:left>
+              <spirit:right spirit:format="long">511</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_15" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_M</spirit:name>
+      <spirit:displayName>LMB_M</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Master interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredMaster/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">SYS_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.SYS_Rst</spirit:name>
+      <spirit:displayName>SYS_Rst</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>SYS_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:channels>
+    <spirit:channel>
+      <spirit:name>LMB_Channel</spirit:name>
+      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_0</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_2</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
+    </spirit:channel>
+  </spirit:channels>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>SYS_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;))) - 1)">63</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        <spirit:wire>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_ReadDBus</spirit:name>
+        <spirit:wire>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
+        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Awidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>C Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
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+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
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+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
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+  </spirit:choices>
+  <spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Awidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1300" spirit:configGroups="1 LMB" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
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+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
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+      <spirit:displayName>C Ext Reset High</spirit:displayName>
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+      <spirit:displayName>LMB Number of Slaves</spirit:displayName>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_ilmb_0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="751c672a"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci
new file mode 100644
index 0000000..48e424f
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xci
@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:library>xci</spirit:library>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_9f2c_dlmb_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;SYS_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;95&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;2&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;}},&quot;interfaces&quot;:{&quot;LMB_Sl_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_W
+IDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_
+rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBU
+S&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;63&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_2&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:
+lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right
+&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;64&quot;,&quot;physical_right&quot;:&quot;95&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_r
+ight&quot;:&quot;0&quot;}}},&quot;LMB_M&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredMaster&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;M_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;M_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_
+name&quot;:&quot;LMB_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;LMB_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;LMB_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;LMB_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;M_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;M_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;SYS_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permiss
+ion&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.SYS_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;SYS_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml
new file mode 100644
index 0000000..8982102
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/bd_9f2c_dlmb_0.xml
@@ -0,0 +1,3536 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_dlmb_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_0</spirit:name>
+      <spirit:displayName>LMB_Sl_00</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">31</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_0" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_1</spirit:name>
+      <spirit:displayName>LMB_Sl_01</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">32</spirit:left>
+              <spirit:right spirit:format="long">63</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_2</spirit:name>
+      <spirit:displayName>LMB_Sl_02</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">64</spirit:left>
+              <spirit:right spirit:format="long">95</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_3</spirit:name>
+      <spirit:displayName>LMB_Sl_03</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">96</spirit:left>
+              <spirit:right spirit:format="long">127</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_4</spirit:name>
+      <spirit:displayName>LMB_Sl_04</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">128</spirit:left>
+              <spirit:right spirit:format="long">159</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_5</spirit:name>
+      <spirit:displayName>LMB_Sl_05</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">160</spirit:left>
+              <spirit:right spirit:format="long">191</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_6</spirit:name>
+      <spirit:displayName>LMB_Sl_06</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">192</spirit:left>
+              <spirit:right spirit:format="long">223</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_6" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_7</spirit:name>
+      <spirit:displayName>LMB_Sl_07</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">224</spirit:left>
+              <spirit:right spirit:format="long">255</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_7" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_8</spirit:name>
+      <spirit:displayName>LMB_Sl_08</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">256</spirit:left>
+              <spirit:right spirit:format="long">287</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_8" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_9</spirit:name>
+      <spirit:displayName>LMB_Sl_09</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">288</spirit:left>
+              <spirit:right spirit:format="long">319</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_10</spirit:name>
+      <spirit:displayName>LMB_Sl_10</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">320</spirit:left>
+              <spirit:right spirit:format="long">351</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_10" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_11</spirit:name>
+      <spirit:displayName>LMB_Sl_11</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">352</spirit:left>
+              <spirit:right spirit:format="long">383</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_11" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_12</spirit:name>
+      <spirit:displayName>LMB_Sl_12</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">384</spirit:left>
+              <spirit:right spirit:format="long">415</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_13</spirit:name>
+      <spirit:displayName>LMB_Sl_13</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">416</spirit:left>
+              <spirit:right spirit:format="long">447</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_14</spirit:name>
+      <spirit:displayName>LMB_Sl_14</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">448</spirit:left>
+              <spirit:right spirit:format="long">479</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_14" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_15</spirit:name>
+      <spirit:displayName>LMB_Sl_15</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">480</spirit:left>
+              <spirit:right spirit:format="long">511</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_15" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_M</spirit:name>
+      <spirit:displayName>LMB_M</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Master interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredMaster/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">SYS_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.SYS_Rst</spirit:name>
+      <spirit:displayName>SYS_Rst</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>SYS_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:channels>
+    <spirit:channel>
+      <spirit:name>LMB_Channel</spirit:name>
+      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_0</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_2</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
+    </spirit:channel>
+  </spirit:channels>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>SYS_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;))) - 1)">95</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
+        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Awidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>C Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1200" spirit:configGroups="1 LMB">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Awidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1300" spirit:configGroups="1 LMB" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci
new file mode 100644
index 0000000..c92a973
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml
new file mode 100644
index 0000000..72e6605
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/bd_9f2c_dlmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_dlmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">65536</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) / 8) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WSTRB" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
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+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci
new file mode 100644
index 0000000..6a6de07
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CE_COUNTER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CE_FAILING_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_ONOFF_REGISTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_STATUS_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAULT_INJECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x000000000000FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERCONNECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK">0x0000000080010000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK1">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK2">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK3">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_LMB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UE_FAILING_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_WRITE_ACCESS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_9f2c_ilmb_cntlr_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml
new file mode 100644
index 0000000..432322b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/bd_9f2c_ilmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_ilmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">65536</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteDBus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_AddrStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ReadStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_BE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_DBus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_Ready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_Wait" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4100" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_PROTOCOL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Protocol</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL" spirit:order="4300" spirit:configGroups="4 S AXI CTRL">AXI4LITE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_PROTOCOL" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_ilmb_cntlr_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>LMB BRAM Controller</xilinx:displayName>
+      <xilinx:coreRevision>19</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6b8a9ed6"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ff7e9a63"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="80dd29e4"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="a2db68b7"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ce681c4"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f6139c3b"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci
new file mode 100644
index 0000000..6a64a19
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xci
@@ -0,0 +1,298 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>bd_9f2c_lmb_bram_I_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     19.660986 mW</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_9f2c_lmb_bram_I_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">BRAM_Controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;web&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dinb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta_busy&quot;:{&quot;direction&quot;:&quot;ou
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_V
+IP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;
+},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rsta&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_lef
+t&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dinb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rstb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;web&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml
new file mode 100644
index 0000000..bb42e99
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/bd_9f2c_lmb_bram_I_0.xml
@@ -0,0 +1,4151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_lmb_bram_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">65536</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">65536</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
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+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">bd_9f2c_lmb_bram_I_0.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     19.660986 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0132492a</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_302d3091</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f9a6a28b</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1f270a52</spirit:name>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_246d8066</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a6697bba</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_lmb_bram_I_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_f9a6a28b" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_a6697bba" spirit:order="8">True_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_302d3091" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="32" spirit:maximum="1024" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">16384</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_6fc15197" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0132492a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_6fc15197" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_1f270a52" spirit:order="3">BRAM_Controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">bd_9f2c_lmb_bram_I_0.mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci
new file mode 100644
index 0000000..93d3055
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml
new file mode 100644
index 0000000..7bdfc1b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/bd_9f2c_second_dlmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_second_dlmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">32768</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
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+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
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+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
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+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci
new file mode 100644
index 0000000..68f93dd
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_9f2c_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml
new file mode 100644
index 0000000..00569c8
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/bd_9f2c_second_ilmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_second_ilmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">32768</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) / 8) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WSTRB" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
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+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_second_ilmb_cntlr_0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci
new file mode 100644
index 0000000..c69c392
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xci
@@ -0,0 +1,298 @@
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+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;web&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dinb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta_busy&quot;:{&quot;direction&quot;:&quot;ou
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_V
+IP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;
+},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rsta&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_lef
+t&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dinb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rstb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;web&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml
new file mode 100644
index 0000000..b398710
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/bd_9f2c_second_lmb_bram_I_0.xml
@@ -0,0 +1,4151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_9f2c_second_lmb_bram_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">32768</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
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+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
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+      </spirit:portMaps>
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+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">32768</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
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+      </spirit:vendorExtensions>
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+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
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+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_READ_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rstb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rstb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>enb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.enb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and(spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>regceb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regceb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        <spirit:name>web</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>eccpipece</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>rdaddrecc</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rdaddrecc" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) != 0) and id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;) != &apos;virtex5&apos;)) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)))">false</xilinx:isEnabled>
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+        <spirit:name>sleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sleep" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;artixu&apos;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplushbm&apos;  or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus58g&apos;or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;zynquplus&apos;))and spirit:decode(id(&apos;MODELPARAM_VALUE.C_EN_SLEEP_PIN&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>deepsleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">bd_9f2c_second_lmb_bram_I_0.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     17.246228 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0132492a</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_302d3091</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f9a6a28b</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1f270a52</spirit:name>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_246d8066</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a6697bba</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_9f2c_second_lmb_bram_I_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_f9a6a28b" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_a6697bba" spirit:order="8">True_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_302d3091" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="32" spirit:maximum="1024" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_6fc15197" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0132492a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_6fc15197" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
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+          <xilinx:enablement>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    </spirit:parameter>
+    <spirit:parameter>
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+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_1f270a52" spirit:order="3">BRAM_Controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">bd_9f2c_second_lmb_bram_I_0.mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
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+    <xilinx:packagingInfo>
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+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
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+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
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+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci
new file mode 100644
index 0000000..24e8fe8
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xci
@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>phy_ddr4_microblaze_mcs</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze_mcs" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET">Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM">CLK_BOARD_INTERFACE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVOID_PRIMITIVES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BSCANID">76547328</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_ddr4_microblaze_mcs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEBUG_ENABLED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI1_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO3_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO2_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO3_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_ASYNC_INTR">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_INTR_SIZE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_LEVEL_EDGE">0x0000</spirit:configurableElementValue>
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+solve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;Reset&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;CLK_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.Reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;gene
+rated&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;IO&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mcsio_bus:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mcsio_bus_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_addr_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;IO_address&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;IO_byte_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_read_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_read_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IO_ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_righ
+t&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_write_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_write_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;TRACE&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbtrace:2.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbtrace_rtl:2.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;DATA_ACCESS&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_ADDRESS&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DATA_BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_byte_enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;DATA_READ&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;
+},&quot;DATA_WRITE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE_VALUE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_write_value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DCACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_READ&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DELAY_SLOT&quot;:{&quot;physical_name&quot;:&quot;TRACE_delay_slot&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EX_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_ex_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;p
+hysical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EXCEPTION_KIND&quot;:{&quot;physical_name&quot;:&quot;TRACE_exception_kind&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;EXCEPTION_TAKEN&quot;:{&quot;physical_name&quot;:&quot;TRACE_exception_taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;INSTRUCTION&quot;:{&quot;physical_name&quot;:&quot;TRACE_instruction&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;JUMP_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_jump_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;JUMP_TAKEN&quot;
+:{&quot;physical_name&quot;:&quot;TRACE_jump_taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MB_HALTED&quot;:{&quot;physical_name&quot;:&quot;TRACE_mb_halted&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MEM_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_mem_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MSR_REG&quot;:{&quot;physical_name&quot;:&quot;TRACE_msr_reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;14&quot;},&quot;NEW_REG_VALUE&quot;:{&quot;physical_name&quot;:&quot;TRACE_new_reg_value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;OF_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_of_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PC&quot;:{&quot;physical_name&quot;:&quot;TRACE_pc&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;PID_REG&quot;:{&quot;physical_name&quot;:&quot;TRACE_pid_reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical
+_right&quot;:&quot;7&quot;},&quot;REG_ADDR&quot;:{&quot;physical_name&quot;:&quot;TRACE_reg_addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;REG_WRITE&quot;:{&quot;physical_name&quot;:&quot;TRACE_reg_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;VALID_INSTR&quot;:{&quot;physical_name&quot;:&quot;TRACE_valid_instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml
new file mode 100644
index 0000000..a58f21e
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_0/phy_ddr4_microblaze_mcs.xml
@@ -0,0 +1,2235 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_ddr4_microblaze_mcs</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.Clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_9f2c_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET">Reset</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM">CLK_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.Reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>IO</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mcsio_bus" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mcsio_bus_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR_STROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_addr_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_STROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_read_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_ready</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_DATA</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_write_data</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>WRITE_STROBE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_write_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace" spirit:version="2.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace_rtl" spirit:version="2.0"/>
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+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_access</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_address</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_write_value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DELAY_SLOT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_delay_slot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EX_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_ex_piperun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_KIND</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_exception_kind</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_exception_taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INSTRUCTION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_instruction</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_jump_hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_jump_taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MB_HALTED</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_mb_halted</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MEM_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_mem_piperun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MSR_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_msr_reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NEW_REG_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_new_reg_value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>OF_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_of_piperun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PC</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_pc</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PID_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_pid_reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_reg_addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_reg_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_INSTR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_valid_instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_elaborateports</spirit:name>
+        <spirit:displayName>Elaborate Ports</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaborateports_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Mar 07 16:27:13 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:a6727c9e</spirit:value>
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+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_elaboratebd</spirit:name>
+        <spirit:displayName>Elaborate BD</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.bd</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaboratebd_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Mon Mar 07 16:27:13 UTC 2022</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:d9c40649</spirit:value>
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+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_data_access</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
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+      <spirit:port>
+        <spirit:name>TRACE_data_address</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_data_byte_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">3</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_data_read</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_data_write</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_data_write_value</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_rdy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_read</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_req</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_delay_slot</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_ex_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_exception_kind</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">4</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_exception_taken</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_rdy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_req</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_instruction</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_jump_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_jump_taken</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_mb_halted</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_mem_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
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+        <spirit:name>TRACE_msr_reg</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">14</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_new_reg_value</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_of_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_pc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_pid_reg</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">7</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_reg_addr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">4</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_reg_write</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_valid_instr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_addr_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_byte_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_read_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_read_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_write_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_write_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+    <spirit:fileSet>
+      <spirit:name>xilinx_elaborateports_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../bd_0/bd_9f2c.bd</spirit:name>
+        <spirit:userFileType>block_diagram</spirit:userFileType>
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+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratebd_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../bd_0/bd_9f2c.bd</spirit:name>
+        <spirit:userFileType>block_diagram</spirit:userFileType>
+      </spirit:file>
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+  <spirit:description>MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger.
+The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs.
+</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>JTAG_CHAIN</spirit:name>
+      <spirit:displayName>Debug JTAG User-defined Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.JTAG_CHAIN" spirit:choiceRef="choice_pairs_5502e96b" spirit:order="1065" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.JTAG_CHAIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MICROBLAZE_INSTANCE</spirit:name>
+      <spirit:displayName>MicroBlaze Instance Name</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MICROBLAZE_INSTANCE" spirit:order="1010" spirit:configGroups="1 NoDisplay">microblaze_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AVOID_PRIMITIVES" spirit:order="1015" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PATH</spirit:name>
+      <spirit:displayName>Instance Hierarchical Design Name</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PATH" spirit:order="1020" spirit:configGroups="1 NoDisplay">mcs_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FREQ</spirit:name>
+      <spirit:displayName>Input Clock Frequency (MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ" spirit:order="1030" spirit:configGroups="1 System">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OPTIMIZATION</spirit:name>
+      <spirit:displayName>Select MicroBlaze Optimization</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZATION" spirit:choiceRef="choice_pairs_563648c8" spirit:order="1025" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DEBUG_ENABLED</spirit:name>
+      <spirit:displayName>Enable Debug Support</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEBUG_ENABLED" spirit:choiceRef="choice_pairs_0d2d32a8" spirit:order="1060" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BSCAN</spirit:name>
+      <spirit:displayName>Select BSCAN location</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BSCAN" spirit:choiceRef="choice_pairs_366c5f3d" spirit:order="1062" spirit:configGroups="1 System">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_BSCAN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BSCANID</spirit:name>
+      <spirit:displayName>Define BSCAN id</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BSCANID" spirit:order="1064" spirit:configGroups="1 System">76547328</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.BSCANID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:displayName>Enable MicroBlaze Trace Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1070" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1035" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEMSIZE</spirit:name>
+      <spirit:displayName>Memory Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEMSIZE" spirit:choiceRef="choice_pairs_f7e0b771" spirit:order="1040" spirit:configGroups="1 System">98304</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEMTYPE</spirit:name>
+      <spirit:displayName>Memory Type</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEMTYPE" spirit:choiceRef="choice_pairs_9de6ed99" spirit:order="1045" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_IO_BUS</spirit:name>
+      <spirit:displayName>Enable IO Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_IO_BUS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1050" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_UART_RX</spirit:name>
+      <spirit:displayName>Enable Receiver</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_UART_RX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_UART_RX">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_UART_TX</spirit:name>
+      <spirit:displayName>Enable Transmitter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_UART_TX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_UART_TX">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BAUDRATE</spirit:name>
+      <spirit:displayName>Define Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BAUDRATE" spirit:choiceRef="choice_list_f585525a" spirit:order="2200" spirit:configGroups="2 UART">9600</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_BAUDRATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_PROG_BAUDRATE</spirit:name>
+      <spirit:displayName>Programmable Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_PROG_BAUDRATE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_PROG_BAUDRATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_DATA_BITS</spirit:name>
+      <spirit:displayName>Number of Data Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_DATA_BITS" spirit:order="2400" spirit:configGroups="2 UART" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_DATA_BITS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_USE_PARITY</spirit:name>
+      <spirit:displayName>Use Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_USE_PARITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_USE_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_ODD_PARITY</spirit:name>
+      <spirit:displayName>Even or Odd Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_ODD_PARITY" spirit:choiceRef="choice_pairs_ffa336e4" spirit:order="2600" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_ODD_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_RX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Receive Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_RX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2700" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_RX_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_TX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Transmit Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_TX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2800" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_TX_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_ERROR_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Error Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_ERROR_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2900" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_ERROR_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT1</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3001" spirit:configGroups="3 FIT1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT1_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT1_No_CLOCKS" spirit:order="3002" spirit:configGroups="3 FIT1" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT1_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3005" spirit:configGroups="3 FIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT2</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3101" spirit:configGroups="3 FIT2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT2_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT2_No_CLOCKS" spirit:order="3102" spirit:configGroups="3 FIT2" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT2_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3105" spirit:configGroups="3 FIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT3</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3201" spirit:configGroups="3 FIT3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT3_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT3_No_CLOCKS" spirit:order="3202" spirit:configGroups="3 FIT3" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT3_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3205" spirit:configGroups="3 FIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT4</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3301" spirit:configGroups="3 FIT4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT4_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT4_No_CLOCKS" spirit:order="3302" spirit:configGroups="3 FIT4" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT4_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3305" spirit:configGroups="3 FIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT1</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4001" spirit:configGroups="4 PIT1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_SIZE" spirit:order="4002" spirit:configGroups="4 PIT1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4003" spirit:configGroups="4 PIT1">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_PRESCALER" spirit:choiceRef="choice_pairs_f0f6eb36" spirit:order="4004" spirit:configGroups="4 PIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4008" spirit:configGroups="4 PIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT2</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4101" spirit:configGroups="4 PIT2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_SIZE" spirit:order="4102" spirit:configGroups="4 PIT2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4103" spirit:configGroups="4 PIT2">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_PRESCALER" spirit:choiceRef="choice_pairs_007f01e9" spirit:order="4104" spirit:configGroups="4 PIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4108" spirit:configGroups="4 PIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT3</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4201" spirit:configGroups="4 PIT3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_SIZE" spirit:order="4202" spirit:configGroups="4 PIT3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4203" spirit:configGroups="4 PIT3">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_PRESCALER" spirit:choiceRef="choice_pairs_4847022f" spirit:order="4204" spirit:configGroups="4 PIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4208" spirit:configGroups="4 PIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT4</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4301" spirit:configGroups="4 PIT4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_SIZE" spirit:order="4302" spirit:configGroups="4 PIT4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4303" spirit:configGroups="4 PIT4">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_PRESCALER" spirit:choiceRef="choice_pairs_5f1e379e" spirit:order="4304" spirit:configGroups="4 PIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4308" spirit:configGroups="4 PIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO1</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5000" spirit:configGroups="5 GPO1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO1_SIZE" spirit:order="5001" spirit:configGroups="5 GPO1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO1_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO1_INIT" spirit:order="5002" spirit:configGroups="5 GPO1" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO1_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO2</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5100" spirit:configGroups="5 GPO2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO2_SIZE" spirit:order="5101" spirit:configGroups="5 GPO2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO2_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO2_INIT" spirit:order="5102" spirit:configGroups="5 GPO2" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO2_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO3</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5200" spirit:configGroups="5 GPO3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO3">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO3_SIZE" spirit:order="5201" spirit:configGroups="5 GPO3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO3_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO3_INIT" spirit:order="5202" spirit:configGroups="5 GPO3" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO3_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO4</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5300" spirit:configGroups="5 GPO4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO4_SIZE" spirit:order="5301" spirit:configGroups="5 GPO4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO4_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO4_INIT" spirit:order="5302" spirit:configGroups="5 GPO4" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO4_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI1</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6000" spirit:configGroups="6 GPI1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI1_SIZE" spirit:order="6001" spirit:configGroups="6 GPI1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI1_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6002" spirit:configGroups="6 GPI1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI2</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 GPI2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI2_SIZE" spirit:order="6101" spirit:configGroups="6 GPI2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI2_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6102" spirit:configGroups="6 GPI2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI3</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6200" spirit:configGroups="6 GPI3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI3">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI3_SIZE" spirit:order="6201" spirit:configGroups="6 GPI3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI3_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6202" spirit:configGroups="6 GPI3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI4</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6300" spirit:configGroups="6 GPI4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI4_SIZE" spirit:order="6301" spirit:configGroups="6 GPI4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI4_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6302" spirit:configGroups="6 GPI4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_USE_EXT_INTR</spirit:name>
+      <spirit:displayName>Use External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_USE_EXT_INTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7000" spirit:configGroups="7 Interrupt">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_INTR_SIZE</spirit:name>
+      <spirit:displayName>Number of External Inputs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_INTR_SIZE" spirit:order="7100" spirit:configGroups="7 Interrupt" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_INTR_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_LEVEL_EDGE</spirit:name>
+      <spirit:displayName>Level or Edge of External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_LEVEL_EDGE" spirit:order="7200" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0x0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_LEVEL_EDGE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_POSITIVE</spirit:name>
+      <spirit:displayName>Positive or Negative External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_POSITIVE" spirit:order="7300" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_POSITIVE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_ASYNC_INTR</spirit:name>
+      <spirit:displayName>Interrupts asynchronous</spirit:displayName>
+      <spirit:description>The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous.</spirit:description>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_ASYNC_INTR" spirit:order="7400" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_ASYNC_INTR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_NUM_SYNC_FF</spirit:name>
+      <spirit:displayName>Number of synchronization flip-flops</spirit:displayName>
+      <spirit:description>Number of synchronization flip-flops used to synchronize asynchronous interupt inputs</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_NUM_SYNC_FF" spirit:order="7500" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_ddr4_microblaze_mcs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="100" spirit:configGroups="0 Board">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="103" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CLK_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_30de7c39" spirit:order="106" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RESET_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO1_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="110" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO1_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO2_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="120" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO2_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO3_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO3_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="130" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO3_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO4_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="140" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO4_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:choiceRef="choice_list_0739ee39" spirit:order="150" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>MicroBlaze MCS</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>14</xilinx:coreRevision>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="bd_viewable">true</xilinx:tag>
+        <xilinx:tag xilinx:name="driver_mode">subcore</xilinx:tag>
+      </xilinx:tags>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEMSIZE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OPTIMIZATION" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TRACE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_IO_BUS" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6ddedfe4"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="08e90b19"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="3d2f3b86"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci
new file mode 100644
index 0000000..6b0e807
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xci
@@ -0,0 +1,667 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>phy_ddr4_phy</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4_phy" spirit:version="2.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ADDR_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_ADDR_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_DATA_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_GROUP_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_TYPE">HP_IO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_DIV_LOC_1">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_DIV_LOC_2">X0Y10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_LOC_1">X0Y70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_LOC_2">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BYTES">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CA_MIRROR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CENTER_BANK_CLOCK_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKIN_PERIOD">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COLUMN_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATABITS_PER_STROBE">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_BUF_ADDR_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DBYTES">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DM_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQS_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQ_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_OTHER_PN_CLOCK_PARAM">{12{2&apos;b00}} </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.INIT">{                            15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111011,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111                                                                                }</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IOBTYPE">                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b
+000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                  
+                                                39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_000_000_000_000_000_001_000_001_001_001_001_001,                                                                                  39&apos;b001_001_001_000_000_001_001_001_00
+1_001_001_001_001,                                                                                  39&apos;b000_001_001_001_001_101_101_001_001_001_001_001_001  </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_CUSTOM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_COMP_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_DEVICE_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_IDX_BANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MR0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MR2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_SLICE_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_SLICE_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PHY_BYTE_ALLOC_PARAM">{{9{2&apos;b11}}, {3{2&apos;b00}}} </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_CH1_BYTES_MAP">12&apos;b000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RANK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RXTX_BITSLICE_EN">{13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b01111
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+                                                                               13&apos;b0111101111111                                                                                }</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RX_DATA_TYPE">{ 15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                               
+                 15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b000000_11_01111_11,                                                
+                                15&apos;b111001_11_11111_11,                                                                                15&apos;b011111_11_11111_11                                                                                }</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELF_CALIBRATE">{12{2&apos;b11}} </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_CENTER_INFO">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Slot">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_OUTPUT_PHASE_90">{ 13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000
+011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000001011111,                                                                                13&apos;b1110011111111,
+                                                                                13&apos;b0111111111111                                                                                }</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_DM_PORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nCK_PER_CLK">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tCK">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tMRD">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tRTP">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tWR">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tXPR">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tZQINIT">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasLatency">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">64GB</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">RDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_customPartAbsPath">no_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES">CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom
+Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom
+Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_ddr4_phy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Phy_Only_Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_act_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cas_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_data_compare_error">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_100">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_101">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_102">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_103">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_104">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_105">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_106">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_107">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_108">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_109">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_2">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_23">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_26">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_33">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_36">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_40">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_41">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_44">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_45">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_46">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_47">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_50">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_57">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_58">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_59">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_60">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_61">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_62">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_63">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_64">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_65">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_66">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_67">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_68">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_69">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_70">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_71">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_79">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_80">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_81">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_82">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_85">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_88">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_90">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_91">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_92">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_98">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_99">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_init_calib_complete">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_parity">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ras_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_reset_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_sys_clk_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_sys_clk_p">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_we_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_rst">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ControllerType" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Clamshell" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Ecc" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Slot" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_StackHeight" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Debug_Signal" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_FROM_PHY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Simulation_Mode" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.System_Clock" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml
new file mode 100644
index 0000000..5fd5b9d
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/ip_1/phy_ddr4_phy.xml
@@ -0,0 +1,4899 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_ddr4_phy</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>sys_clk_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_p" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_n" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk_i</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_i" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;No_Buffer&quot; )">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mmcm_lock</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mmcm_lock" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>pllGate</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pllGate" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>div_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.div_clk" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>div_clk_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        <spirit:displayName>Bank Type</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_TYPE">HP_IO</spirit:value>
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+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CS_WIDTH</spirit:name>
+        <spirit:displayName>CS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CS_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>ODT_WIDTH</spirit:name>
+        <spirit:displayName>ODT WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ODT_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DQ_WIDTH</spirit:name>
+        <spirit:displayName>DQ WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQ_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DQS_WIDTH</spirit:name>
+        <spirit:displayName>DQS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQS_WIDTH">18</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DM_WIDTH</spirit:name>
+        <spirit:displayName>DM WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DM_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MR0</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MR0">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MR2</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MR2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tCK</spirit:name>
+        <spirit:displayName>tCK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tCK">1500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tXPR</spirit:name>
+        <spirit:displayName>tXPR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tXPR">60</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>nCK_PER_CLK</spirit:name>
+        <spirit:displayName>nCK PER CLK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nCK_PER_CLK">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tMRD</spirit:name>
+        <spirit:displayName>tMRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tMRD">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tZQINIT</spirit:name>
+        <spirit:displayName>tZQINIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tZQINIT">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_COMP_WIDTH</spirit:name>
+        <spirit:displayName>MEM COMP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_COMP_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_DEVICE_WIDTH</spirit:name>
+        <spirit:displayName>MEMORY DEVICE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_DEVICE_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PLL_WIDTH</spirit:name>
+        <spirit:displayName>PLL WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PLL_WIDTH">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>IOBTYPE</spirit:name>
+        <spirit:displayName>IOBTYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IOBTYPE">                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b
+000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                  
+                                                39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_111_111,                                                                                  39&apos;b000_000_000_000_000_000_001_000_001_001_001_001_001,                                                                                  39&apos;b001_001_001_000_000_001_001_001_00
+1_001_001_001_001,                                                                                  39&apos;b000_001_001_001_001_101_101_001_001_001_001_001_001  </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BYTES</spirit:name>
+        <spirit:displayName>BYTES</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BYTES">12</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DBYTES</spirit:name>
+        <spirit:displayName>DBYTES</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DBYTES">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_CH1_BYTES_MAP</spirit:name>
+        <spirit:displayName>PING_PONG_CH1_BYTES_MAP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_CH1_BYTES_MAP">12&apos;b000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_PHY</spirit:name>
+        <spirit:displayName>PING PONG PHY</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RX_DATA_TYPE</spirit:name>
+        <spirit:displayName>RX DATA TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_DATA_TYPE">{ 15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                               
+                 15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b011110_11_11110_11,                                                                                15&apos;b000000_11_01111_11,                                                
+                                15&apos;b111001_11_11111_11,                                                                                15&apos;b011111_11_11111_11                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>INIT</spirit:name>
+        <spirit:displayName>INIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INIT">{                            15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111011,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>SELF_CALIBRATE</spirit:name>
+        <spirit:displayName>SELF CALIBRATE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELF_CALIBRATE">{12{2&apos;b11}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>TX_OUTPUT_PHASE_90</spirit:name>
+        <spirit:displayName>TX OUTPUT PHASE 90</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_OUTPUT_PHASE_90">{ 13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000
+011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000011000011,                                                                                13&apos;b0000001011111,                                                                                13&apos;b1110011111111,
+                                                                                13&apos;b0111111111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RXTX_BITSLICE_EN</spirit:name>
+        <spirit:displayName>RXTX BITSLICE EN</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXTX_BITSLICE_EN">{13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b01111
+01111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0000001011111,                                                                                13&apos;b1110011111111, 
+                                                                               13&apos;b0111101111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>EN_OTHER_PN_CLOCK_PARAM</spirit:name>
+        <spirit:displayName>EN OTHER PN CLOCK PARAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_OTHER_PN_CLOCK_PARAM">{12{2&apos;b00}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PHY_BYTE_ALLOC_PARAM</spirit:name>
+        <spirit:displayName>PHY BYTE ALLOC PARAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PHY_BYTE_ALLOC_PARAM">{{9{2&apos;b11}}, {3{2&apos;b00}}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DATA_BUF_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>DATA BUF ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_BUF_ADDR_WIDTH">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKIN_PERIOD</spirit:name>
+        <spirit:displayName>CLKIN PERIOD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_TYPE</spirit:name>
+        <spirit:displayName>MEM TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_ID_WIDTH</spirit:name>
+        <spirit:displayName>AXI ID WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ID_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI DATA WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_DATA_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ADDR_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>USE_DM_PORT</spirit:name>
+        <spirit:displayName>USE DM PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_DM_PORT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_LOC_1</spirit:name>
+        <spirit:displayName>BUFG LOC 1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_LOC_1">X0Y70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_LOC_2</spirit:name>
+        <spirit:displayName>BUFG LOC 2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_LOC_2">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_DIV_LOC_1</spirit:name>
+        <spirit:displayName>BUFG DIV LOC 1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_DIV_LOC_1">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_DIV_LOC_2</spirit:name>
+        <spirit:displayName>BUFG DIV LOC 2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_DIV_LOC_2">X0Y10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_SLICE_LOC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_SLICE_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB36_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB18_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_SLICE_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_SLICE_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB36_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB18_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MMCM_IDX_BANK</spirit:name>
+        <spirit:displayName>MMCM IDX BANK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_IDX_BANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CENTER_BANK_CLOCK_REGION</spirit:name>
+        <spirit:displayName>CENTER BANK CLOCK REGION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CENTER_BANK_CLOCK_REGION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CENTER_BANK_MMCME3_ADV_SITE</spirit:name>
+        <spirit:displayName>CENTER BANK MMCME3 ADV SITE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>SYSCLK_CENTER_INFO</spirit:name>
+        <spirit:displayName>SYSCLK_CENTER_INFO</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYSCLK_CENTER_INFO">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tWR</spirit:name>
+        <spirit:displayName>tWR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tWR">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tRTP</spirit:name>
+        <spirit:displayName>tRTP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tRTP">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RANK_WIDTH</spirit:name>
+        <spirit:displayName>RANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RANK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CK_WIDTH</spirit:name>
+        <spirit:displayName>CK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DATABITS_PER_STROBE</spirit:name>
+        <spirit:displayName>DATABITS PER STROBE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATABITS_PER_STROBE">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>USE_CS_PORT</spirit:name>
+        <spirit:displayName>USE CS PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_CS_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CA_MIRROR</spirit:name>
+        <spirit:displayName>CA MIRROR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CA_MIRROR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>IS_CUSTOM</spirit:name>
+        <spirit:displayName>IS CUSTOM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_CUSTOM">true</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Slot</spirit:name>
+        <spirit:displayName>Slot</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Slot">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>phy_ddr4_phy</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="dummy"/>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>PHY for DDR4 interfaces for Ultrascale Architecture</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C0.ControllerType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ControllerType" spirit:order="2">DDR4_SDRAM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_FROM_PHY</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IS_FROM_PHY" spirit:order="3">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Phy_Only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Phy_Only" spirit:order="4">Phy_Only_Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>No_Controller</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.No_Controller" spirit:order="5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Default_Bank_Selections</spirit:name>
+      <spirit:displayName>Default Bank Selections</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Default_Bank_Selections" spirit:order="6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Debug_Signal</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Debug_Signal" spirit:order="7">Disable</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Simulation_Mode</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Simulation_Mode" spirit:order="8">BFM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PARTIAL_RECONFIG_FLOW_MIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" spirit:order="9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DIVIDE" spirit:order="10">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DIVIDE" spirit:order="11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DIVIDE" spirit:order="12">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DIVIDE" spirit:order="13">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>System_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.System_Clock" spirit:order="14">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RECONFIG_XSDB_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" spirit:order="15">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_TERM_SYSCLK</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_TERM_SYSCLK" spirit:order="16">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TimePeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TimePeriod" spirit:order="17">1500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_InputClockPeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_InputClockPeriod" spirit:order="18">3333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" spirit:order="19">5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" spirit:order="20">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" spirit:order="21">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PhyClockRatio</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PhyClockRatio" spirit:order="22">4:1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryType" spirit:order="23">RDIMMs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryPart</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryPart" spirit:order="24">64GB</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Slot</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Slot" spirit:order="25">Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryVoltage</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryVoltage" spirit:order="26">1.2V</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataWidth" spirit:order="27">72</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataMask</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataMask" spirit:order="28">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ecc" spirit:order="29">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasLatency" spirit:order="30">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasWriteLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasWriteLatency" spirit:order="31">14</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ChipSelect</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ChipSelect" spirit:order="32">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCKEShared</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCKEShared" spirit:order="33">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name>
+      <spirit:displayName>CLKOUTPHY MODE</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" spirit:order="34">VCO</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name>
+      <spirit:displayName>High Range Supported frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" spirit:order="35">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name>
+      <spirit:displayName>Memory Min Period</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MIN_PERIOD" spirit:order="36">833</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name>
+      <spirit:displayName>Indicates Faster Speed RAM Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" spirit:order="37">No</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_VrefVoltage</spirit:name>
+      <spirit:displayName>Vref Voltage</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_VrefVoltage" spirit:order="38">0.84</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_customPartAbsPath</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_customPartAbsPath" spirit:order="39">no_file_loaded</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_StackHeight</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_StackHeight" spirit:order="40">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CUSTOM_PART_ATTRIBUTES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" spirit:order="41">CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom
+Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom
+Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SELF_REFRESH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SELF_REFRESH" spirit:order="42">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" spirit:order="43">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Clamshell</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Clamshell" spirit:order="44">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Enable_LVAUX</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Enable_LVAUX" spirit:order="45">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_EN_PARITY</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_EN_PARITY" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_EN_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_0" spirit:order="47">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_1" spirit:order="48">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_2" spirit:order="49">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_3" spirit:order="50">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_4" spirit:order="51">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_5" spirit:order="52">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_6" spirit:order="53">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_7" spirit:order="54">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_8" spirit:order="55">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_9" spirit:order="56">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_10" spirit:order="57">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_11" spirit:order="58">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_12" spirit:order="59">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_13" spirit:order="60">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_14" spirit:order="61">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_15" spirit:order="62">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_16" spirit:order="63">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_17" spirit:order="64">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_18" spirit:order="65">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_19" spirit:order="66">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_20" spirit:order="67">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_21" spirit:order="68">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_22" spirit:order="69">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_23" spirit:order="70">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_24" spirit:order="71">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_25" spirit:order="72">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_26" spirit:order="73">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_27" spirit:order="74">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_28" spirit:order="75">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_29" spirit:order="76">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_30" spirit:order="77">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_31" spirit:order="78">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_32" spirit:order="79">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_33" spirit:order="80">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_34" spirit:order="81">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_35" spirit:order="82">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_36</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_36" spirit:order="83">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_37</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_37" spirit:order="84">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_38</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_38" spirit:order="85">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_39</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_39" spirit:order="86">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_40</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_40" spirit:order="87">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_41</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_41" spirit:order="88">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_42</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_42" spirit:order="89">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_43</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_43" spirit:order="90">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_44</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_44" spirit:order="91">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_45</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_45" spirit:order="92">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_46</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_46" spirit:order="93">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_47</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_47" spirit:order="94">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_48</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_48" spirit:order="95">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_49</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_49" spirit:order="96">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_50</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_50" spirit:order="97">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_51</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_51" spirit:order="98">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_52</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_52" spirit:order="99">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_53</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_53" spirit:order="100">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_54</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_54" spirit:order="101">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_55</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_55" spirit:order="102">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_56</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_56" spirit:order="103">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_57</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_57" spirit:order="104">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_58</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_58" spirit:order="105">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_59</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_59" spirit:order="106">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_60</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_60" spirit:order="107">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_61</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_61" spirit:order="108">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_62</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_62" spirit:order="109">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_63</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_63" spirit:order="110">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_64</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_64" spirit:order="111">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_65</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_65" spirit:order="112">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_66</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_66" spirit:order="113">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_67</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_67" spirit:order="114">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_68</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_68" spirit:order="115">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_69</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_69" spirit:order="116">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_70</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_70" spirit:order="117">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_71</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_71" spirit:order="118">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_72</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_72" spirit:order="119">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_73</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_73" spirit:order="120">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_74</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_74" spirit:order="121">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_75</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_75" spirit:order="122">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_76</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_76" spirit:order="123">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_77</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_77" spirit:order="124">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_78</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_78" spirit:order="125">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_79</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_79" spirit:order="126">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_80</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_80" spirit:order="127">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_81</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_81" spirit:order="128">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_82</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_82" spirit:order="129">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_83</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_83" spirit:order="130">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_84</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_84" spirit:order="131">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_85</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_85" spirit:order="132">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_86</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_86" spirit:order="133">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_87</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_87" spirit:order="134">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_88</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_88" spirit:order="135">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_89</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_89" spirit:order="136">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_90</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_90" spirit:order="137">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_91</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_91" spirit:order="138">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_92</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_92" spirit:order="139">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_93</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_93" spirit:order="140">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_94</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_94" spirit:order="141">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_95</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_95" spirit:order="142">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_96</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_96" spirit:order="143">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_97</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_97" spirit:order="144">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_98</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_98" spirit:order="145">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_99</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_99" spirit:order="146">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_100</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_100" spirit:order="147">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_101</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_101" spirit:order="148">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_102</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_102" spirit:order="149">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_103</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_103" spirit:order="150">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_104</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_104" spirit:order="151">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_105</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_105" spirit:order="152">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_106</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_106" spirit:order="153">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_107</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_107" spirit:order="154">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_108</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_108" spirit:order="155">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_109</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_109" spirit:order="156">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_110</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_110" spirit:order="157">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_111</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_111" spirit:order="158">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_112</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_112" spirit:order="159">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_113</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_113" spirit:order="160">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_114</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_114" spirit:order="161">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_115</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_115" spirit:order="162">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_116</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_116" spirit:order="163">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_117</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_117" spirit:order="164">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_118</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_118" spirit:order="165">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_119</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_119" spirit:order="166">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_120</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_120" spirit:order="167">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_121</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_121" spirit:order="168">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_122</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_122" spirit:order="169">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_123</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_123" spirit:order="170">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_124</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_124" spirit:order="171">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_125</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_125" spirit:order="172">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_126</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_126" spirit:order="173">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_127</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_127" spirit:order="174">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_128</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_128" spirit:order="175">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_129</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_129" spirit:order="176">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_130</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_130" spirit:order="177">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_131</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_131" spirit:order="178">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_132</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_132" spirit:order="179">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_133</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_133" spirit:order="180">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_134</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_134" spirit:order="181">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_135</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_135" spirit:order="182">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_136</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_136" spirit:order="183">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_137</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_137" spirit:order="184">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_138</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_138" spirit:order="185">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_139</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_139" spirit:order="186">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_140</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_140" spirit:order="187">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_141</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_141" spirit:order="188">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_142</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_142" spirit:order="189">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_143</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_143" spirit:order="190">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_0" spirit:order="191">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_1" spirit:order="192">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_2" spirit:order="193">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_3" spirit:order="194">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_4" spirit:order="195">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_5" spirit:order="196">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_6" spirit:order="197">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_7" spirit:order="198">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_8" spirit:order="199">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_9" spirit:order="200">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_10" spirit:order="201">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_11" spirit:order="202">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_12" spirit:order="203">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_13" spirit:order="204">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_14" spirit:order="205">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_15" spirit:order="206">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_16" spirit:order="207">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_17" spirit:order="208">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_18" spirit:order="209">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_19" spirit:order="210">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_20" spirit:order="211">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_21" spirit:order="212">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_0" spirit:order="213">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_1" spirit:order="214">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_2" spirit:order="215">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_3" spirit:order="216">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_4" spirit:order="217">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_5" spirit:order="218">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_6" spirit:order="219">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_7" spirit:order="220">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_8" spirit:order="221">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_9" spirit:order="222">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_10" spirit:order="223">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_11" spirit:order="224">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_12" spirit:order="225">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_13" spirit:order="226">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_14" spirit:order="227">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_15" spirit:order="228">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_16" spirit:order="229">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_17" spirit:order="230">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_18" spirit:order="231">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_19" spirit:order="232">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_20" spirit:order="233">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_21" spirit:order="234">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_0" spirit:order="235">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_1" spirit:order="236">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_2" spirit:order="237">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_3" spirit:order="238">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_4" spirit:order="239">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_5" spirit:order="240">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_6" spirit:order="241">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_7" spirit:order="242">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_8" spirit:order="243">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_9" spirit:order="244">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_10" spirit:order="245">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_11" spirit:order="246">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_12" spirit:order="247">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_13" spirit:order="248">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_14" spirit:order="249">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_15" spirit:order="250">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_16" spirit:order="251">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_17" spirit:order="252">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_18" spirit:order="253">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_19" spirit:order="254">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_20" spirit:order="255">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_21" spirit:order="256">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_22" spirit:order="257">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_23" spirit:order="258">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_24" spirit:order="259">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_25" spirit:order="260">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_26" spirit:order="261">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_27" spirit:order="262">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_28" spirit:order="263">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_29" spirit:order="264">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_30" spirit:order="265">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_31" spirit:order="266">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_32" spirit:order="267">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_33" spirit:order="268">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_34" spirit:order="269">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_35" spirit:order="270">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_0" spirit:order="271">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_1" spirit:order="272">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_2" spirit:order="273">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_3" spirit:order="274">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_4" spirit:order="275">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_5" spirit:order="276">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_6" spirit:order="277">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_7" spirit:order="278">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_8" spirit:order="279">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_9" spirit:order="280">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_10" spirit:order="281">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_11" spirit:order="282">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_12" spirit:order="283">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_13" spirit:order="284">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_14" spirit:order="285">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_15" spirit:order="286">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_16" spirit:order="287">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_17" spirit:order="288">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_18" spirit:order="289">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_19" spirit:order="290">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_20" spirit:order="291">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_21" spirit:order="292">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_22" spirit:order="293">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_23" spirit:order="294">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_24" spirit:order="295">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_25" spirit:order="296">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_26" spirit:order="297">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_27" spirit:order="298">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_28" spirit:order="299">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_29" spirit:order="300">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_30" spirit:order="301">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_31" spirit:order="302">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_32" spirit:order="303">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_33" spirit:order="304">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_34" spirit:order="305">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_35" spirit:order="306">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_0" spirit:order="307">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_1" spirit:order="308">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_2" spirit:order="309">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_3" spirit:order="310">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_4" spirit:order="311">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_5" spirit:order="312">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_6" spirit:order="313">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_7" spirit:order="314">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_8" spirit:order="315">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_9" spirit:order="316">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_10" spirit:order="317">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_11" spirit:order="318">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_12" spirit:order="319">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_13" spirit:order="320">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_14" spirit:order="321">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_15" spirit:order="322">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_16" spirit:order="323">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_17" spirit:order="324">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_18" spirit:order="325">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_19" spirit:order="326">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_20" spirit:order="327">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_21" spirit:order="328">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_22" spirit:order="329">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_23" spirit:order="330">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_24" spirit:order="331">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_25" spirit:order="332">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_26" spirit:order="333">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_27" spirit:order="334">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_28" spirit:order="335">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_29" spirit:order="336">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_30" spirit:order="337">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_31" spirit:order="338">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_32" spirit:order="339">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_33" spirit:order="340">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_34" spirit:order="341">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_35" spirit:order="342">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_0" spirit:order="343">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_1" spirit:order="344">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_2" spirit:order="345">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_3" spirit:order="346">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_4" spirit:order="347">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_5" spirit:order="348">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_6" spirit:order="349">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_7" spirit:order="350">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_8" spirit:order="351">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_9" spirit:order="352">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_10" spirit:order="353">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_11" spirit:order="354">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_12" spirit:order="355">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_13" spirit:order="356">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_14" spirit:order="357">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_15" spirit:order="358">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_16" spirit:order="359">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_17" spirit:order="360">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_18" spirit:order="361">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_19" spirit:order="362">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_20" spirit:order="363">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_21" spirit:order="364">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_22" spirit:order="365">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_23" spirit:order="366">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_24" spirit:order="367">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_25" spirit:order="368">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_26" spirit:order="369">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_27" spirit:order="370">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_28" spirit:order="371">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_29" spirit:order="372">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_30" spirit:order="373">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_31" spirit:order="374">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_32" spirit:order="375">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_33" spirit:order="376">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_34" spirit:order="377">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_35" spirit:order="378">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_0" spirit:order="379">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_1" spirit:order="380">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_2" spirit:order="381">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_3" spirit:order="382">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_4" spirit:order="383">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_5" spirit:order="384">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_6" spirit:order="385">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_7" spirit:order="386">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_8" spirit:order="387">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_9" spirit:order="388">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_10" spirit:order="389">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_11" spirit:order="390">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_12" spirit:order="391">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_13" spirit:order="392">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_14" spirit:order="393">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_15" spirit:order="394">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_16" spirit:order="395">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_17" spirit:order="396">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_18" spirit:order="397">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_19" spirit:order="398">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_20" spirit:order="399">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_21" spirit:order="400">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_22" spirit:order="401">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_23" spirit:order="402">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_24" spirit:order="403">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_25" spirit:order="404">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_26" spirit:order="405">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_27" spirit:order="406">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_28" spirit:order="407">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_29" spirit:order="408">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_30" spirit:order="409">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_31" spirit:order="410">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_32" spirit:order="411">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_33" spirit:order="412">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_34" spirit:order="413">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_35" spirit:order="414">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_0" spirit:order="415">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_1" spirit:order="416">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_2" spirit:order="417">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_3" spirit:order="418">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_4" spirit:order="419">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_5" spirit:order="420">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_6" spirit:order="421">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_7" spirit:order="422">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_8" spirit:order="423">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_9" spirit:order="424">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_10" spirit:order="425">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_11" spirit:order="426">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_12" spirit:order="427">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_13" spirit:order="428">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_14" spirit:order="429">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_15" spirit:order="430">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_16" spirit:order="431">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_17" spirit:order="432">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_18" spirit:order="433">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_19" spirit:order="434">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_20" spirit:order="435">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_21" spirit:order="436">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_22" spirit:order="437">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_23" spirit:order="438">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_24" spirit:order="439">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_25" spirit:order="440">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_26" spirit:order="441">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_27" spirit:order="442">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_28" spirit:order="443">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_29" spirit:order="444">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_30" spirit:order="445">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_31" spirit:order="446">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_32" spirit:order="447">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_33" spirit:order="448">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_34" spirit:order="449">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_35" spirit:order="450">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_0" spirit:order="451">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_1" spirit:order="452">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_2" spirit:order="453">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_3" spirit:order="454">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_0" spirit:order="455">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_1" spirit:order="456">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_2" spirit:order="457">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_0" spirit:order="458">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_1" spirit:order="459">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_2" spirit:order="460">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_0" spirit:order="461">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_1" spirit:order="462">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_2" spirit:order="463">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_3" spirit:order="464">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_0" spirit:order="465">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_1" spirit:order="466">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_2" spirit:order="467">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_3" spirit:order="468">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_0" spirit:order="469">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_1" spirit:order="470">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_2" spirit:order="471">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_3" spirit:order="472">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_0" spirit:order="473">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_1" spirit:order="474">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_2" spirit:order="475">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_3" spirit:order="476">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_4" spirit:order="477">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_5" spirit:order="478">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_6" spirit:order="479">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_7" spirit:order="480">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_0" spirit:order="481">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_1" spirit:order="482">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_2" spirit:order="483">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_3" spirit:order="484">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_0" spirit:order="485">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_1" spirit:order="486">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_2" spirit:order="487">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_3" spirit:order="488">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_0" spirit:order="489">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_1" spirit:order="490">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_2" spirit:order="491">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_3" spirit:order="492">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_reset_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_reset_n" spirit:order="493">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_act_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_act_n" spirit:order="494">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ras_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ras_n" spirit:order="495">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cas_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cas_n" spirit:order="496">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_we_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_we_n" spirit:order="497">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_parity</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_parity" spirit:order="498">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p" spirit:order="499">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n" spirit:order="500">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n" spirit:order="501">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>sys_rst</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sys_rst" spirit:order="502">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_sys_clk_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_sys_clk_n" spirit:order="503">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_sys_clk_p</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_sys_clk_p" spirit:order="504">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_data_compare_error</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_data_compare_error" spirit:order="505">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_init_calib_complete</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_init_calib_complete" spirit:order="506">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_ddr4_phy</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>DDR4 SDRAM PHY IP</xilinx:displayName>
+      <xilinx:coreRevision>0</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ControllerType" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Clamshell" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Ecc" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Slot" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_StackHeight" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Debug_Signal" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_FROM_PHY" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Simulation_Mode" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.System_Clock" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="422f3c11"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="75959f5e"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5f78b9ec"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="c74d2af3"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci
new file mode 100644
index 0000000..f857867
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xci
@@ -0,0 +1,500 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>phy_ddr4</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4" spirit:version="2.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">576</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_MASK_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_1">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_2">X0Y10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_1">X0Y70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.CENTER_BANK_CLOCK_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ADDR_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BANK_GROUP_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">16Gb</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_ADDR">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">64GB</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">RDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">64GB</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">34359738368</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">83</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">166500000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCK">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRAS">22</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRCD">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tREFI">5200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC">234</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">74</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRP">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_L">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_S">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRTP">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWR">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_L">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_S">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tXPR">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT1_DIVIDE">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom
+Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom
+Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AL_SEL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ADDR_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ACT_SKEW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_11">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_12">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AutoPrecharge">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth">34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme">RD_PRI_REG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiIDWidth">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiNarrowBurst">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstLength">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstType">Sequential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Capacity">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasLatency">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CustomParts">../../../../custom_parts_ddr4_2016_4_and_above.csv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MCS_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">64GB</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">RDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC_DLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TXPR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TREFI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TXPR">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.LR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.MIGRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_ddr4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCI_Cascade">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_PP_4R_MIR">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Power_Reduction">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Phy_Only_Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reference_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SET_DW_TO_40">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_3DS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ADDR_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CKE_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CK_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CS_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CustomParts" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Ecc" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Slot" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_isCustom" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.LR_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ODT_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.StackHeight" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;c0_init_calib_complete&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dbg_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_sys_clk_p&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_sys_clk_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dbg_bus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_parity&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_ui_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_ui_clk_sync_rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addn_ui_clkout1&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataEn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataEnd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;per_rd_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;0&quot;},&quot;rmw_rd_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataEn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_ACT_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcCasSlot&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcCasSlot2&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcRdCAS&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcWrCAS&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winInjTxn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winRmw&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;gt_data_ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winRank&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;tCWL&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrData&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;575&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdData&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;575&quot;,&quot;p
+hysical_right&quot;:&quot;0&quot;},&quot;mc_ADR&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;143&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_BA&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_CKE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_CS_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_ODT&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dBufAdr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataAddr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataAddr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winBuf&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_act_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_adr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;17&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ba&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_bg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_par&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phys
+ical_right&quot;:&quot;0&quot;},&quot;ddr4_cke&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_odt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_cs_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ck_t&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ck_c&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_reset_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_parity&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dq&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dqs_c&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;17&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dqs_t&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;17&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_BG&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;C0_SYS_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:diff_clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:diff_clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.
+ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;C0_CLOCK_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;CLK_N&quot;:{&quot;physical_name&quot;:&quot;c0_sys_clk_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK_P&quot;:{&quot;physical_name&quot;:&quot;c0_sys_clk_p&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;C0_DDR4_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:
+{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk_sync_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;C0_DDR4_CLOCK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1.665e+08&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.00&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;reso
+lve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ADDN_UI_CLKOUT1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1e+08&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;c0_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[
+{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;addn_ui_clkout1&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;SYSTEM_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;sys_rs
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml
new file mode 100644
index 0000000..5bcc81b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml
@@ -0,0 +1,8749 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_ddr4</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>C0_SYS_CLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.BOARD.ASSOCIATED_PARAM">C0_CLOCK_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; (spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_SYS_CLK_I</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_i</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK_I" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;No_Buffer&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACT_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_act_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_adr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ba</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_bg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>C_ID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CK_C</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ck_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CK_T</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ck_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CKE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_cke</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CS_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_cs_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DM_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dm_dbi_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dq</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQS_C</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dqs_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQS_T</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dqs_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ODT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_odt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_parity</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RESET_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4.BOARD.ASSOCIATED_PARAM">C0_DDR4_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TIMEPERIOD_PS</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEMORY_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEMORY_PART</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CS_ENABLED</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_MASK_ENABLED</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SLOT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CUSTOM_PARTS</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ADDR_MAP</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAS_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4" xilinx:dependency="( ( spirit:decode(id(&apos;PARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_CTRL</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="C0_DDR4_MEMORY_MAP_CTRL"/>
+      </spirit:slave>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_S_AXI_CTRL" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_ECC&apos;)) = true()() ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="C0_DDR4_MEMORY_MAP"/>
+      </spirit:slave>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_S_AXI" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_ARESETN</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_ARESETN" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_RESET</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ui_clk_sync_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_RESET" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_CLOCK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ui_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.PHASE">0.00</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.ASSOCIATED_BUSIF">C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.ASSOCIATED_RESET">c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_CLOCK" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT1</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ&apos;))*1000000)">1e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT1" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ&apos;)) != &quot;NONE&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT2</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT2" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT3</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT3" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT4</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT4" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SYSTEM_RESET</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_CTRL_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_CTRL_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_CTRL_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>C0_DDR4_MEMORY_MAP</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>C0_DDR4_ADDRESS_BLOCK</spirit:name>
+        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_MEM_SIZE&apos;))">34359738368</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:vendorExtensions>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:name>dBufAdr</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+        <spirit:name>ddr4_bg</spirit:name>
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+        <spirit:description>AXIMM Socket for Write</spirit:description>
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+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
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+        <spirit:transactional>
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+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
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+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
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+      <spirit:modelParameter>
+        <spirit:name>System_Clock</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.System_Clock" spirit:choiceRef="choice_list_2b96b8de">Differential</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.ControllerType</spirit:name>
+        <spirit:displayName>ControllerType</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>App Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.MEM_TYPE</spirit:name>
+        <spirit:displayName>MEM TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_LOC_1</spirit:name>
+        <spirit:displayName>BUFG LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_LOC_1">X0Y70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_LOC_2</spirit:name>
+        <spirit:displayName>BUFG LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_DIV_LOC_1</spirit:name>
+        <spirit:displayName>BUFG DIV LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_1">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_DIV_LOC_2</spirit:name>
+        <spirit:displayName>BUFG DIV LOC2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_2">X0Y10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_SLICE_LOC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB36_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB18_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_SLICE_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB36_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB18_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.MMCM_IDX_BANK</spirit:name>
+        <spirit:displayName>MMCM IDX BANK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.CENTER_BANK_CLOCK_REGION</spirit:name>
+        <spirit:displayName>CENTER BANK CLOCK REGION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.CENTER_BANK_CLOCK_REGION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.CENTER_BANK_MMCME3_ADV_SITE</spirit:name>
+        <spirit:displayName>CENTER BANK MMCME3 ADV SITE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.SYSCLK_CENTER_INFO</spirit:name>
+        <spirit:displayName>SYSCLK CENTER INFO</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_PHY</spirit:name>
+        <spirit:displayName>Ping Pong Phy</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CS_ADDR</spirit:name>
+        <spirit:displayName>CS Width Check</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CS_ADDR">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_VrefVoltage</spirit:name>
+        <spirit:displayName>Vref Voltage</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AL</spirit:name>
+        <spirit:displayName>Additive Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DQ_WIDTH</spirit:name>
+        <spirit:displayName>DQ WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nCK_PER_CLK</spirit:name>
+        <spirit:displayName>nCK PER CLK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DM_WIDTH</spirit:name>
+        <spirit:displayName>DM WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DQS_WIDTH</spirit:name>
+        <spirit:displayName>DQS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">18</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nCS_PER_RANK</spirit:name>
+        <spirit:displayName>nCS PER RANK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DEVICE_WIDTH</spirit:name>
+        <spirit:displayName>MEM DEVICE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_USE_DM_PORT</spirit:name>
+        <spirit:displayName>USE DM PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_USE_CS_PORT</spirit:name>
+        <spirit:displayName>USE CS PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ROW_WIDTH</spirit:name>
+        <spirit:displayName>ROW WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">18</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ADDR_WIDTH">18</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BANK_WIDTH</spirit:name>
+        <spirit:displayName>BANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BANK_WIDTH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BANK_GROUP_WIDTH</spirit:name>
+        <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BANK_GROUP_WIDTH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>LR_WIDTH</spirit:name>
+        <spirit:displayName>LR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LR_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CK_WIDTH</spirit:name>
+        <spirit:displayName>CK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CKE_WIDTH</spirit:name>
+        <spirit:displayName>CKE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CKE_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CS_WIDTH</spirit:name>
+        <spirit:displayName>CS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ODT_WIDTH</spirit:name>
+        <spirit:displayName>ODT WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEMORY_TYPE</spirit:name>
+        <spirit:displayName>MEMORY TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">RDIMMs</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEMORY_PART</spirit:name>
+        <spirit:displayName>MEMORY PART</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">64GB</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DATA_MASK</spirit:name>
+        <spirit:displayName>DATA MASK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_COLUMN_WIDTH</spirit:name>
+        <spirit:displayName>COLUMN WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_SPEED_GRADE</spirit:name>
+        <spirit:displayName>SPEED GRADE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">83</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY</spirit:name>
+        <spirit:displayName>MEM DENSITY</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">64GB</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY_MB</spirit:name>
+        <spirit:displayName>MEM DENSITY MB</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY_GB</spirit:name>
+        <spirit:displayName>MEM DENSITY GB</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_COMP_DENSITY</spirit:name>
+        <spirit:displayName>COMP DENSITY</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">16Gb</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_COMP_WIDTH</spirit:name>
+        <spirit:displayName>MEM COMP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DATABITS_PER_STROBE</spirit:name>
+        <spirit:displayName>DATABITS PER STROBE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MODEL_SPEED_GRADE</spirit:name>
+        <spirit:displayName>MODEL SPEED GRADE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RANK_WIDTH</spirit:name>
+        <spirit:displayName>RANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IO_VOLTAGE</spirit:name>
+        <spirit:displayName>IO VOLTAGE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name>
+        <spirit:displayName>MIN PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MAX_PERIOD</spirit:name>
+        <spirit:displayName>MAX PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MR0</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MR2</spirit:name>
+        <spirit:displayName>Mode register_2 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nAL</spirit:name>
+        <spirit:displayName>Additive Latency in number of clock</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BURST_MODE</spirit:name>
+        <spirit:displayName>Burst Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BURST_TYPE</spirit:name>
+        <spirit:displayName>Burst Type</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CL</spirit:name>
+        <spirit:displayName>Cas Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CWL</spirit:name>
+        <spirit:displayName>Cas Write Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_OUTPUT_DRV</spirit:name>
+        <spirit:displayName>Output drive Strength</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RTT_NOM</spirit:name>
+        <spirit:displayName>RTT Nominal</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RTT_WR</spirit:name>
+        <spirit:displayName>RTT WR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM</spirit:name>
+        <spirit:displayName>Memory Name</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DBAW</spirit:name>
+        <spirit:displayName>DBAW</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCK</spirit:name>
+        <spirit:displayName>tCK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCK">1500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Configuration</spirit:name>
+        <spirit:displayName>Configuration</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCKE</spirit:name>
+        <spirit:displayName>tCKE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tFAW</spirit:name>
+        <spirit:displayName>tFAW</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tFAW_dlr</spirit:name>
+        <spirit:displayName>tFAW_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tMRD</spirit:name>
+        <spirit:displayName>tMRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRAS</spirit:name>
+        <spirit:displayName>tRAS</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRAS">22</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRCD</spirit:name>
+        <spirit:displayName>tRCD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRCD">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tREFI</spirit:name>
+        <spirit:displayName>tREFI</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tREFI">5200</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRFC</spirit:name>
+        <spirit:displayName>tRFC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC">234</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRFC_dlr</spirit:name>
+        <spirit:displayName>tRFC_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">74</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRP</spirit:name>
+        <spirit:displayName>tRP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRP">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWR</spirit:name>
+        <spirit:displayName>tWR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWR">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD</spirit:name>
+        <spirit:displayName>tRRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRTP</spirit:name>
+        <spirit:displayName>tRTP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRTP">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_S</spirit:name>
+        <spirit:displayName>tRRD_S</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_S">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_L</spirit:name>
+        <spirit:displayName>tRRD_L</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_L">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_dlr</spirit:name>
+        <spirit:displayName>tRRD_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR</spirit:name>
+        <spirit:displayName>tWTR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR_S</spirit:name>
+        <spirit:displayName>tWTR_S</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_S">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR_L</spirit:name>
+        <spirit:displayName>tWTR_L</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_L">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tXPR</spirit:name>
+        <spirit:displayName>tXPR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tXPR">60</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQI</spirit:name>
+        <spirit:displayName>tZQI</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQCS</spirit:name>
+        <spirit:displayName>tZQCS</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQINIT</spirit:name>
+        <spirit:displayName>tZQINIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCCD_3ds</spirit:name>
+        <spirit:displayName>tCCD_3ds</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name>
+        <spirit:displayName>CLKOUTPHY_MODE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT0_DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUT1_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT1_DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+        <spirit:displayName>CLKFBOUT_MULT</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+        <spirit:displayName>DIVCLK DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CAL_INPUT_CLK_PERIOD</spirit:name>
+        <spirit:displayName>Calculated Input Clock Period</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKIN_PERIOD</spirit:name>
+        <spirit:displayName>CLKIN_PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name>
+        <spirit:displayName>High Range Supported frequency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DCI_CASCADE_CUTOFF</spirit:name>
+        <spirit:displayName>DCI Cascade Cutoff</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name>
+        <spirit:displayName>Is Faster Speed RAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_ID_WIDTH</spirit:name>
+        <spirit:displayName>AXI ID Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">34</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_SIZE</spirit:name>
+        <spirit:displayName>Memory Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">34359738368</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_UI_CLOCK</spirit:name>
+        <spirit:displayName>DDR4 UI CLOCK</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">166500000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CA_MIRROR</spirit:name>
+        <spirit:displayName>CA MIRROR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IS_CUSTOM</spirit:name>
+        <spirit:displayName>IS CUSTOM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">true</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name>
+        <spirit:displayName>AUTO AP COL A3</spirit:displayName>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">true</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MCS_ECC</spirit:name>
+        <spirit:displayName>MCS ECC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Slot</spirit:name>
+        <spirit:displayName>Slot Type</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_DATA_WIDTH</spirit:name>
+        <spirit:displayName>APP Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">576</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_MASK_WIDTH</spirit:name>
+        <spirit:displayName>APP Mask Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_MASK_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_StackHeight</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CUSTOM_PART_ATTRIBUTES</spirit:name>
+        <spirit:displayName>custom_part_attributes</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">CustomPart_Address__width 18$CustomPart_Bank__group__width 2$CustomPart_Bank__width 2$CustomPart_CA__Mirror 0$CustomPart_CKE__width 1$CustomPart_CK__width 1$CustomPart_CS__width 1$CustomPart_Column__width 10$CustomPart_Component__density 16Gb$CustomPart_Data__bits__per__strobe 4$CustomPart_Data__mask 0$CustomPart_Data__widths 72$CustomPart_IO__Voltages 1.2V$CustomPart_Max__period 1600$CustomPart_Memory__component__width 4$CustomPart_Memory__density 64GB$CustomPart_Memory__device__width 72$Custom
+Part_Memory__speed__grade 83$CustomPart_Min__period 833$CustomPart_ODT__width 1$CustomPart_Part__name 64GB$CustomPart_Part__type RDIMMs$CustomPart_Rank 1$CustomPart_Row__width 18$CustomPart_StackHeight 1$CustomPart_burst__length 8$CustomPart_cas__latency 24$CustomPart_cas__write__latency 22$CustomPart_tCCD_3ds 5 tck$CustomPart_tCKE 5000 ps$CustomPart_tFAW 13000 ps$CustomPart_tFAW_dlr 16 tck$CustomPart_tMRD 8 tck$CustomPart_tRAS 32000 ps$CustomPart_tRCD 14160 ps$CustomPart_tREFI 7800000 ps$Custom
+Part_tRFC 350000 ps$CustomPart_tRFC_dlr 110000 ps$CustomPart_tRP 14160 ps$CustomPart_tRRD_L 4900 ps$CustomPart_tRRD_S 3300 ps$CustomPart_tRRD_dlr 4 tck$CustomPart_tRTP 7500 ps$CustomPart_tWR 15000 ps$CustomPart_tWTR_L 7500 ps$CustomPart_tWTR_S 2500 ps$CustomPart_tXPR 360 ns$CustomPart_tZQCS 128 tck$CustomPart_tZQINIT 1024 tck$</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT1_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT1 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">100</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT2_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT2 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT3_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT3 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT4_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT4 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT1_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT1 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT2_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT2 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT3_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT3 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT4_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT4 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT0_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT0 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT1_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT1 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT1_DIVIDE">15</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT2_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT2 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT3_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT3 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT4_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT4 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT6_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT6 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Debug_Signal</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Simulation_Mode</spirit:name>
+        <spirit:displayName>Simulation Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Ecc</spirit:name>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_09ec3310</spirit:name>
+      <spirit:enumeration>Single</spirit:enumeration>
+      <spirit:enumeration>Dual</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_157065e4</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+      <spirit:enumeration>10</spirit:enumeration>
+      <spirit:enumeration>11</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_266493f0</spirit:name>
+      <spirit:enumeration>DDR4_SDRAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_28391b73</spirit:name>
+      <spirit:enumeration>1.2V</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_29a21725</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk0</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk1</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk2</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_2b96b8de</spirit:name>
+      <spirit:enumeration>Differential</spirit:enumeration>
+      <spirit:enumeration>No_Buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_301b19dd</spirit:name>
+      <spirit:enumeration>ON</spirit:enumeration>
+      <spirit:enumeration>OFF</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_30636008</spirit:name>
+      <spirit:enumeration>4:1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_30de7c39</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pcie_perstn</spirit:enumeration>
+      <spirit:enumeration>resetn</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_34c5244e</spirit:name>
+      <spirit:enumeration>Components</spirit:enumeration>
+      <spirit:enumeration>UDIMMs</spirit:enumeration>
+      <spirit:enumeration>SODIMMs</spirit:enumeration>
+      <spirit:enumeration>RDIMMs</spirit:enumeration>
+      <spirit:enumeration>LRDIMMs</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_3d7b6424</spirit:name>
+      <spirit:enumeration>500</spirit:enumeration>
+      <spirit:enumeration>375</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>250</spirit:enumeration>
+      <spirit:enumeration>214</spirit:enumeration>
+      <spirit:enumeration>188</spirit:enumeration>
+      <spirit:enumeration>167</spirit:enumeration>
+      <spirit:enumeration>150</spirit:enumeration>
+      <spirit:enumeration>136</spirit:enumeration>
+      <spirit:enumeration>125</spirit:enumeration>
+      <spirit:enumeration>115</spirit:enumeration>
+      <spirit:enumeration>107</spirit:enumeration>
+      <spirit:enumeration>100</spirit:enumeration>
+      <spirit:enumeration>94</spirit:enumeration>
+      <spirit:enumeration>88</spirit:enumeration>
+      <spirit:enumeration>83</spirit:enumeration>
+      <spirit:enumeration>79</spirit:enumeration>
+      <spirit:enumeration>75</spirit:enumeration>
+      <spirit:enumeration>71</spirit:enumeration>
+      <spirit:enumeration>68</spirit:enumeration>
+      <spirit:enumeration>65</spirit:enumeration>
+      <spirit:enumeration>63</spirit:enumeration>
+      <spirit:enumeration>60</spirit:enumeration>
+      <spirit:enumeration>58</spirit:enumeration>
+      <spirit:enumeration>56</spirit:enumeration>
+      <spirit:enumeration>54</spirit:enumeration>
+      <spirit:enumeration>52</spirit:enumeration>
+      <spirit:enumeration>50</spirit:enumeration>
+      <spirit:enumeration>48</spirit:enumeration>
+      <spirit:enumeration>47</spirit:enumeration>
+      <spirit:enumeration>45</spirit:enumeration>
+      <spirit:enumeration>44</spirit:enumeration>
+      <spirit:enumeration>43</spirit:enumeration>
+      <spirit:enumeration>42</spirit:enumeration>
+      <spirit:enumeration>41</spirit:enumeration>
+      <spirit:enumeration>39</spirit:enumeration>
+      <spirit:enumeration>38</spirit:enumeration>
+      <spirit:enumeration>37</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+      <spirit:enumeration>35</spirit:enumeration>
+      <spirit:enumeration>34</spirit:enumeration>
+      <spirit:enumeration>33</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>None</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4665eb01</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4bba4966</spirit:name>
+      <spirit:enumeration>22</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4e3dbc0a</spirit:name>
+      <spirit:enumeration>SIMPLE_TG</spirit:enumeration>
+      <spirit:enumeration>ADVANCED_TG</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_66456a11</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c0</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c1</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c2</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_67b045e5</spirit:name>
+      <spirit:enumeration>BFM</spirit:enumeration>
+      <spirit:enumeration>Unisim</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_687ca1a5</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>500</spirit:enumeration>
+      <spirit:enumeration>375</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>250</spirit:enumeration>
+      <spirit:enumeration>214</spirit:enumeration>
+      <spirit:enumeration>188</spirit:enumeration>
+      <spirit:enumeration>167</spirit:enumeration>
+      <spirit:enumeration>150</spirit:enumeration>
+      <spirit:enumeration>136</spirit:enumeration>
+      <spirit:enumeration>125</spirit:enumeration>
+      <spirit:enumeration>115</spirit:enumeration>
+      <spirit:enumeration>107</spirit:enumeration>
+      <spirit:enumeration>100</spirit:enumeration>
+      <spirit:enumeration>94</spirit:enumeration>
+      <spirit:enumeration>88</spirit:enumeration>
+      <spirit:enumeration>83</spirit:enumeration>
+      <spirit:enumeration>79</spirit:enumeration>
+      <spirit:enumeration>75</spirit:enumeration>
+      <spirit:enumeration>71</spirit:enumeration>
+      <spirit:enumeration>68</spirit:enumeration>
+      <spirit:enumeration>65</spirit:enumeration>
+      <spirit:enumeration>63</spirit:enumeration>
+      <spirit:enumeration>60</spirit:enumeration>
+      <spirit:enumeration>58</spirit:enumeration>
+      <spirit:enumeration>56</spirit:enumeration>
+      <spirit:enumeration>54</spirit:enumeration>
+      <spirit:enumeration>52</spirit:enumeration>
+      <spirit:enumeration>50</spirit:enumeration>
+      <spirit:enumeration>48</spirit:enumeration>
+      <spirit:enumeration>47</spirit:enumeration>
+      <spirit:enumeration>45</spirit:enumeration>
+      <spirit:enumeration>44</spirit:enumeration>
+      <spirit:enumeration>43</spirit:enumeration>
+      <spirit:enumeration>42</spirit:enumeration>
+      <spirit:enumeration>41</spirit:enumeration>
+      <spirit:enumeration>39</spirit:enumeration>
+      <spirit:enumeration>38</spirit:enumeration>
+      <spirit:enumeration>37</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+      <spirit:enumeration>35</spirit:enumeration>
+      <spirit:enumeration>34</spirit:enumeration>
+      <spirit:enumeration>33</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_87b2b38f</spirit:name>
+      <spirit:enumeration>24</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8b4f223f</spirit:name>
+      <spirit:enumeration>Strict</spirit:enumeration>
+      <spirit:enumeration>Normal</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_98f5c8fa</spirit:name>
+      <spirit:enumeration>RZQ/6</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a187d5e4</spirit:name>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ad101c66</spirit:name>
+      <spirit:enumeration>RZQ/7</spirit:enumeration>
+      <spirit:enumeration>RZQ/6</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c89503c8</spirit:name>
+      <spirit:enumeration>ROW_BANK_COLUMN</spirit:enumeration>
+      <spirit:enumeration>BANK_ROW_COLUMN</spirit:enumeration>
+      <spirit:enumeration>ROW_COLUMN_BANK</spirit:enumeration>
+      <spirit:enumeration>ROW_COLUMN_BANK_INTLV</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8951bc1</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d1ecf361</spirit:name>
+      <spirit:enumeration>MTA18ASF1G72PDZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA9ASF51272PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF2G72PDZ-2G3</spirit:enumeration>
+      <spirit:enumeration>MTA9ASF1G72PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>M393A1G43DB1-CRC</spirit:enumeration>
+      <spirit:enumeration>MTA9ASF51272PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>DDR4_CUSTOM3</spirit:enumeration>
+      <spirit:enumeration>DDR4_CUSTOM4</spirit:enumeration>
+      <spirit:enumeration>MTA18ADF1G72PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF1G72PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA36ASF2G72PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF2G72PZ-2G9</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF2G72PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>MTA36ASF4G72PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>M393A2G40DB1-CRC</spirit:enumeration>
+      <spirit:enumeration>M393A8K40B21-CTC</spirit:enumeration>
+      <spirit:enumeration>M393AAK40B41-CTC</spirit:enumeration>
+      <spirit:enumeration>M393A2K40BB1-CRC</spirit:enumeration>
+      <spirit:enumeration>DDR4_CUSTOM5</spirit:enumeration>
+      <spirit:enumeration>64GB</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d6556846</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d8920bdd</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_df7e3f8b</spirit:name>
+      <spirit:enumeration>Sequential</spirit:enumeration>
+      <spirit:enumeration>Interleaved</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e7093afb</spirit:name>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>33</spirit:enumeration>
+      <spirit:enumeration>34</spirit:enumeration>
+      <spirit:enumeration>35</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ed30197c</spirit:name>
+      <spirit:enumeration>TDM</spirit:enumeration>
+      <spirit:enumeration>ROUND_ROBIN</spirit:enumeration>
+      <spirit:enumeration>RD_PRI_REG</spirit:enumeration>
+      <spirit:enumeration>RD_PRI_REG_STARVE_LIMIT</spirit:enumeration>
+      <spirit:enumeration>WRITE_PRIORITY_REG</spirit:enumeration>
+      <spirit:enumeration>WRITE_PRIORITY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ef319ec8</spirit:name>
+      <spirit:enumeration>Differential</spirit:enumeration>
+      <spirit:enumeration>Single_Ended</spirit:enumeration>
+      <spirit:enumeration>No_Buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f3cd92fb</spirit:name>
+      <spirit:enumeration>Disable</spirit:enumeration>
+      <spirit:enumeration>Enable</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fe2d3253</spirit:name>
+      <spirit:enumeration>72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ff0950bb</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>CL-1</spirit:enumeration>
+      <spirit:enumeration>CL-2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_01257c99</spirit:name>
+      <spirit:enumeration spirit:text="Controller_and_physical_layer">Complete_Memory_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Physical_Layer_Only">Phy_Only_Single</spirit:enumeration>
+      <spirit:enumeration spirit:text="Physical_Layer_PingPong">Phy_Only_PingPong</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_05415bea</spirit:name>
+      <spirit:enumeration spirit:text="14000 (71.4286Mhz)">14000</spirit:enumeration>
+      <spirit:enumeration spirit:text="13999 (71.4286Mhz)">13999</spirit:enumeration>
+      <spirit:enumeration spirit:text="13200 (75.7576Mhz)">13200</spirit:enumeration>
+      <spirit:enumeration spirit:text="13199 (75.7576Mhz)">13199</spirit:enumeration>
+      <spirit:enumeration spirit:text="12000 (83.3333Mhz)">12000</spirit:enumeration>
+      <spirit:enumeration spirit:text="11999 (83.3333Mhz)">11999</spirit:enumeration>
+      <spirit:enumeration spirit:text="10801 (92.5926Mhz)">10801</spirit:enumeration>
+      <spirit:enumeration spirit:text="10800 (92.5926Mhz)">10800</spirit:enumeration>
+      <spirit:enumeration spirit:text="10500 (95.2381Mhz)">10500</spirit:enumeration>
+      <spirit:enumeration spirit:text="10499 (95.2381Mhz)">10499</spirit:enumeration>
+      <spirit:enumeration spirit:text="10000 (100Mhz)">10000</spirit:enumeration>
+      <spirit:enumeration spirit:text="9601 (104.167Mhz)">9601</spirit:enumeration>
+      <spirit:enumeration spirit:text="9600 (104.167Mhz)">9600</spirit:enumeration>
+      <spirit:enumeration spirit:text="9599 (104.167Mhz)">9599</spirit:enumeration>
+      <spirit:enumeration spirit:text="9000 (111.111Mhz)">9000</spirit:enumeration>
+      <spirit:enumeration spirit:text="8999 (111.111Mhz)">8999</spirit:enumeration>
+      <spirit:enumeration spirit:text="8572 (116.667Mhz)">8572</spirit:enumeration>
+      <spirit:enumeration spirit:text="8571 (116.667Mhz)">8571</spirit:enumeration>
+      <spirit:enumeration spirit:text="8400 (119.048Mhz)">8400</spirit:enumeration>
+      <spirit:enumeration spirit:text="8399 (119.048Mhz)">8399</spirit:enumeration>
+      <spirit:enumeration spirit:text="8000 (125Mhz)">8000</spirit:enumeration>
+      <spirit:enumeration spirit:text="7715 (129.618Mhz)">7715</spirit:enumeration>
+      <spirit:enumeration spirit:text="7714 (129.618Mhz)">7714</spirit:enumeration>
+      <spirit:enumeration spirit:text="7501 (133.333Mhz)">7501</spirit:enumeration>
+      <spirit:enumeration spirit:text="7500 (133.333Mhz)">7500</spirit:enumeration>
+      <spirit:enumeration spirit:text="7499 (133.333Mhz)">7499</spirit:enumeration>
+      <spirit:enumeration spirit:text="7201 (138.889Mhz)">7201</spirit:enumeration>
+      <spirit:enumeration spirit:text="7200 (138.889Mhz)">7200</spirit:enumeration>
+      <spirit:enumeration spirit:text="7000 (142.857Mhz)">7000</spirit:enumeration>
+      <spirit:enumeration spirit:text="6999 (142.857Mhz)">6999</spirit:enumeration>
+      <spirit:enumeration spirit:text="6858 (145.815Mhz)">6858</spirit:enumeration>
+      <spirit:enumeration spirit:text="6857 (145.815Mhz)">6857</spirit:enumeration>
+      <spirit:enumeration spirit:text="6500 (153.846Mhz)">6500</spirit:enumeration>
+      <spirit:enumeration spirit:text="6499 (153.846Mhz)">6499</spirit:enumeration>
+      <spirit:enumeration spirit:text="6000 (166.667Mhz)">6000</spirit:enumeration>
+      <spirit:enumeration spirit:text="5999 (166.667Mhz)">5999</spirit:enumeration>
+      <spirit:enumeration spirit:text="5573 (179.469Mhz)">5573</spirit:enumeration>
+      <spirit:enumeration spirit:text="5572 (179.469Mhz)">5572</spirit:enumeration>
+      <spirit:enumeration spirit:text="5571 (179.487Mhz)">5571</spirit:enumeration>
+      <spirit:enumeration spirit:text="5401 (185.185Mhz)">5401</spirit:enumeration>
+      <spirit:enumeration spirit:text="5400 (185.185Mhz)">5400</spirit:enumeration>
+      <spirit:enumeration spirit:text="5335 (187.477Mhz)">5335</spirit:enumeration>
+      <spirit:enumeration spirit:text="5334 (187.5Mhz)">5334</spirit:enumeration>
+      <spirit:enumeration spirit:text="5333 (187.5Mhz)">5333</spirit:enumeration>
+      <spirit:enumeration spirit:text="5000 (200Mhz)">5000</spirit:enumeration>
+      <spirit:enumeration spirit:text="4876 (205.128Mhz)">4876</spirit:enumeration>
+      <spirit:enumeration spirit:text="4875 (205.128Mhz)">4875</spirit:enumeration>
+      <spirit:enumeration spirit:text="4801 (208.333Mhz)">4801</spirit:enumeration>
+      <spirit:enumeration spirit:text="4800 (208.333Mhz)">4800</spirit:enumeration>
+      <spirit:enumeration spirit:text="4715 (212.089Mhz)">4715</spirit:enumeration>
+      <spirit:enumeration spirit:text="4714 (212.089Mhz)">4714</spirit:enumeration>
+      <spirit:enumeration spirit:text="4667 (214.286Mhz)">4667</spirit:enumeration>
+      <spirit:enumeration spirit:text="4666 (214.286Mhz)">4666</spirit:enumeration>
+      <spirit:enumeration spirit:text="4573 (218.723Mhz)">4573</spirit:enumeration>
+      <spirit:enumeration spirit:text="4572 (218.723Mhz)">4572</spirit:enumeration>
+      <spirit:enumeration spirit:text="4571 (218.75Mhz)">4571</spirit:enumeration>
+      <spirit:enumeration spirit:text="4500 (222.222Mhz)">4500</spirit:enumeration>
+      <spirit:enumeration spirit:text="4499 (222.222Mhz)">4499</spirit:enumeration>
+      <spirit:enumeration spirit:text="4446 (224.972Mhz)">4446</spirit:enumeration>
+      <spirit:enumeration spirit:text="4445 (224.972Mhz)">4445</spirit:enumeration>
+      <spirit:enumeration spirit:text="4444 (225Mhz)">4444</spirit:enumeration>
+      <spirit:enumeration spirit:text="4401 (227.273Mhz)">4401</spirit:enumeration>
+      <spirit:enumeration spirit:text="4400 (227.273Mhz)">4400</spirit:enumeration>
+      <spirit:enumeration spirit:text="4286 (233.333Mhz)">4286</spirit:enumeration>
+      <spirit:enumeration spirit:text="4285 (233.333Mhz)">4285</spirit:enumeration>
+      <spirit:enumeration spirit:text="4223 (236.842Mhz)">4223</spirit:enumeration>
+      <spirit:enumeration spirit:text="4222 (236.842Mhz)">4222</spirit:enumeration>
+      <spirit:enumeration spirit:text="4126 (242.424Mhz)">4126</spirit:enumeration>
+      <spirit:enumeration spirit:text="4125 (242.424Mhz)">4125</spirit:enumeration>
+      <spirit:enumeration spirit:text="4124 (242.424Mhz)">4124</spirit:enumeration>
+      <spirit:enumeration spirit:text="4000 (250Mhz)">4000</spirit:enumeration>
+      <spirit:enumeration spirit:text="3858 (259.202Mhz)">3858</spirit:enumeration>
+      <spirit:enumeration spirit:text="3857 (259.202Mhz)">3857</spirit:enumeration>
+      <spirit:enumeration spirit:text="3779 (264.69Mhz)">3779</spirit:enumeration>
+      <spirit:enumeration spirit:text="3778 (264.706Mhz)">3778</spirit:enumeration>
+      <spirit:enumeration spirit:text="3777 (264.706Mhz)">3777</spirit:enumeration>
+      <spirit:enumeration spirit:text="3715 (269.231Mhz)">3715</spirit:enumeration>
+      <spirit:enumeration spirit:text="3714 (269.231Mhz)">3714</spirit:enumeration>
+      <spirit:enumeration spirit:text="3601 (277.778Mhz)">3601</spirit:enumeration>
+      <spirit:enumeration spirit:text="3600 (277.778Mhz)">3600</spirit:enumeration>
+      <spirit:enumeration spirit:text="3563 (280.702Mhz)">3563</spirit:enumeration>
+      <spirit:enumeration spirit:text="3562 (280.702Mhz)">3562</spirit:enumeration>
+      <spirit:enumeration spirit:text="3557 (281.215Mhz)">3557</spirit:enumeration>
+      <spirit:enumeration spirit:text="3556 (281.215Mhz)">3556</spirit:enumeration>
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+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratesubcores_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>ip_0/phy_ddr4_microblaze_mcs.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_0/phy_ddr4_microblaze_mcs.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/phy_ddr4_phy.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/phy_ddr4_phy.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>phy_ddr4</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="dummy"/>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>instance_path</spirit:name>
+          <spirit:value>inst/u_ddr_cal_riu/mcs0/inst/microblaze_I</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bootloop_file</spirit:name>
+          <spirit:value>sw/calibration_0/Debug/calibration_ddr.elf</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>endian</spirit:name>
+          <spirit:value>little</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>processor_type</spirit:name>
+          <spirit:value>MICROBLAZE-LE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>is_visible</spirit:name>
+          <spirit:value>false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>DDR4 Interface Generator for Ultrascale Architecture</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C0.ControllerType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ControllerType" spirit:choiceRef="choice_list_266493f0" spirit:order="2">DDR4_SDRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.ControllerType">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IOPowerReduction</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IOPowerReduction" spirit:choiceRef="choice_list_301b19dd" spirit:order="3">OFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_SysPorts</spirit:name>
+      <spirit:displayName>Auto assign static ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_SysPorts" spirit:order="4">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Phy_Only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Phy_Only" spirit:choiceRef="choice_pairs_01257c99" spirit:order="5">Phy_Only_Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_30de7c39" spirit:order="6">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RESET_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0_CLOCK_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE" spirit:choiceRef="choice_list_29a21725" spirit:order="7">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C0_CLOCK_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_FROM_PHY</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IS_FROM_PHY" spirit:order="8">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RECONFIG_XSDB_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" spirit:order="9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AL_SEL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AL_SEL" spirit:choiceRef="choice_list_ff0950bb" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Example_TG</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Example_TG" spirit:choiceRef="choice_list_4e3dbc0a" spirit:order="11">SIMPLE_TG</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.Example_TG">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Clamshell</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Clamshell" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_Clamshell">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.MIGRATION</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.MIGRATION" spirit:order="13">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_OP1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_OP1" spirit:order="14">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_OP2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_OP2" spirit:order="15">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_3DS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_3DS" spirit:order="16">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SET_DW_TO_40</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SET_DW_TO_40" spirit:order="17">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_TERM_SYSCLK</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_TERM_SYSCLK" spirit:order="18">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0_DDR4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE" spirit:choiceRef="choice_list_66456a11" spirit:order="19">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C0_DDR4_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TimePeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TimePeriod" spirit:order="20" spirit:minimum="750" spirit:maximum="1600" spirit:rangeType="long">1500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_InputClockPeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_InputClockPeriod" spirit:choiceRef="choice_pairs_05415bea" spirit:order="21">3333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Specify_MandD</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Specify_MandD" spirit:order="22">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" spirit:order="23" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CLKFBOUT_MULT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" spirit:order="24" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_DIVCLK_DIVIDE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" spirit:order="25" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CLKOUT0_DIVIDE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PhyClockRatio</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PhyClockRatio" spirit:choiceRef="choice_list_30636008" spirit:order="26">4:1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryType" spirit:choiceRef="choice_list_34c5244e" spirit:order="27">RDIMMs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryPart</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryPart" spirit:choiceRef="choice_list_d1ecf361" spirit:order="28">64GB</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Slot</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Slot" spirit:choiceRef="choice_list_09ec3310" spirit:order="29">Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryVoltage</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryVoltage" spirit:choiceRef="choice_list_28391b73" spirit:order="30">1.2V</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataWidth" spirit:choiceRef="choice_list_fe2d3253" spirit:order="31">72</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataMask</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataMask" spirit:choiceRef="choice_list_c8951bc1" spirit:order="32">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_DataMask">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ecc" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_Ecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MCS_ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MCS_ECC" spirit:order="34">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiSelection</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiSelection" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_AxiSelection">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3" spirit:order="36">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ordering</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ordering" spirit:choiceRef="choice_list_8b4f223f" spirit:order="37">Normal</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BurstLength</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BurstLength" spirit:choiceRef="choice_list_d8920bdd" spirit:order="38">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_BurstLength">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BurstType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BurstType" spirit:choiceRef="choice_list_df7e3f8b" spirit:order="39">Sequential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_OutputDriverImpedenceControl</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl" spirit:choiceRef="choice_list_ad101c66" spirit:order="40">RZQ/7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_OnDieTermination</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_OnDieTermination" spirit:choiceRef="choice_list_98f5c8fa" spirit:order="41">RZQ/6</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasLatency" spirit:choiceRef="choice_list_87b2b38f" spirit:order="42">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasWriteLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasWriteLatency" spirit:choiceRef="choice_list_4bba4966" spirit:order="43">14</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ChipSelect</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ChipSelect" spirit:order="44">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_ChipSelect">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCKEShared</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCKEShared" spirit:order="45">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiDataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiDataWidth" spirit:choiceRef="choice_list_d6556846" spirit:order="46">512</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiArbitrationScheme</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme" spirit:choiceRef="choice_list_ed30197c" spirit:order="47">RD_PRI_REG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiNarrowBurst</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiNarrowBurst" spirit:order="48">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiAddressWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiAddressWidth" spirit:choiceRef="choice_list_e7093afb" spirit:order="49">34</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiIDWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiIDWidth" spirit:choiceRef="choice_list_157065e4" spirit:order="50">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Capacity</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Capacity" spirit:choiceRef="choice_list_a187d5e4" spirit:order="51">512</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Mem_Add_Map</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Mem_Add_Map" spirit:choiceRef="choice_list_c89503c8" spirit:order="52">ROW_COLUMN_BANK</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryName</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryName" spirit:order="53">MainMemory</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AutoPrecharge</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AutoPrecharge" spirit:order="54">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_AutoPrecharge">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_UserRefresh_ZQCS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS" spirit:order="55">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_UserRefresh_ZQCS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CustomParts</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CustomParts" spirit:order="56">../../../../custom_parts_ddr4_2016_4_and_above.csv</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:parameterType>file_csv</xilinx:parameterType>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCustom</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCustom" spirit:order="57">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SELF_REFRESH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SELF_REFRESH" spirit:order="58">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_SELF_REFRESH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" spirit:order="59">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_RESTORE_CRC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_RESTORE_CRC" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_RESTORE_CRC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT1_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ" spirit:choiceRef="choice_list_3d7b6424" spirit:order="61">100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT2_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="62">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT3_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="63">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT4_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="64">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6" spirit:order="65">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_ddr4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>No_Controller</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.No_Controller" spirit:choiceRef="choice_list_4665eb01" spirit:order="100">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>System_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.System_Clock" spirit:choiceRef="choice_list_2b96b8de" spirit:order="200">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reference_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reference_Clock" spirit:choiceRef="choice_list_ef319ec8" spirit:order="300">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Debug_Signal</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Debug_Signal" spirit:choiceRef="choice_list_f3cd92fb" spirit:order="400">Disable</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IO_Power_Reduction</spirit:name>
+      <spirit:displayName>IO_Power_Reduction</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.IO_Power_Reduction" spirit:order="500">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DCI_Cascade</spirit:name>
+      <spirit:displayName>DCI Cascade</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DCI_Cascade" spirit:order="600">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Default_Bank_Selections</spirit:name>
+      <spirit:displayName>Default Bank Selections</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Default_Bank_Selections" spirit:order="700">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Simulation_Mode</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Simulation_Mode" spirit:choiceRef="choice_list_67b045e5" spirit:order="800">BFM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PARTIAL_RECONFIG_FLOW_MIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" spirit:order="801">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PARTIAL_RECONFIG_FLOW_MIG">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MCS_DBG_EN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MCS_DBG_EN" spirit:order="802">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_0" spirit:order="803" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_1" spirit:order="804" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_2" spirit:order="805" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_3" spirit:order="806" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0" spirit:order="807" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1" spirit:order="808" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2" spirit:order="809" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3" spirit:order="810" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_4</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4" spirit:order="811" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_5</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5" spirit:order="812" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_6</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6" spirit:order="813" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_7</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7" spirit:order="814" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_8</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8" spirit:order="815" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_9</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9" spirit:order="816" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_10</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10" spirit:order="817" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_11</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_11" spirit:order="818" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_12</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_12" spirit:order="819" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_13</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13" spirit:order="820" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_14</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14" spirit:order="821" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_15</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15" spirit:order="822" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_16</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16" spirit:order="823" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_17</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17" spirit:order="824" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BA_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BA_SKEW_0" spirit:order="825" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BA_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BA_SKEW_1" spirit:order="826" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BG_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BG_SKEW_0" spirit:order="827" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BG_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BG_SKEW_1" spirit:order="828" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_0" spirit:order="829" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_1" spirit:order="830" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_2" spirit:order="831" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_3" spirit:order="832" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_0" spirit:order="833" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_1" spirit:order="834" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_2" spirit:order="835" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_3" spirit:order="836" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ACT_SKEW</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ACT_SKEW" spirit:order="837" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PAR_SKEW</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PAR_SKEW" spirit:order="838" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_0" spirit:order="839" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_1" spirit:order="840" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_2" spirit:order="841" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_3" spirit:order="842" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_LR_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_LR_SKEW_0" spirit:order="843" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_LR_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_LR_SKEW_1" spirit:order="844" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TREFI</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TREFI" spirit:order="845">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TRFC</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TRFC" spirit:order="846">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TRFC_DLR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TRFC_DLR" spirit:order="847">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TXPR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TXPR" spirit:order="848">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TREFI</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TREFI" spirit:order="849">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TRFC</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TRFC" spirit:order="850">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TRFC_DLR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR" spirit:order="851">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TXPR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TXPR" spirit:order="852">5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.ADDR_WIDTH</spirit:name>
+      <spirit:displayName>ADDR WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ADDR_WIDTH" spirit:order="853">18</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.BANK_GROUP_WIDTH</spirit:name>
+      <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.BANK_GROUP_WIDTH" spirit:order="854">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.LR_WIDTH</spirit:name>
+      <spirit:displayName>LR WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.LR_WIDTH" spirit:order="855">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.CK_WIDTH</spirit:name>
+      <spirit:displayName>CK WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CK_WIDTH" spirit:order="856">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.CKE_WIDTH</spirit:name>
+      <spirit:displayName>CKE WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CKE_WIDTH" spirit:order="857">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.CS_WIDTH</spirit:name>
+      <spirit:displayName>CS WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CS_WIDTH" spirit:order="858">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.ODT_WIDTH</spirit:name>
+      <spirit:displayName>ODT WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ODT_WIDTH" spirit:order="859">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.StackHeight</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.StackHeight" spirit:order="860">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PING_PONG_PHY</spirit:name>
+      <spirit:displayName>Ping Pong Phy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PING_PONG_PHY" spirit:order="861">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Enable_LVAUX</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Enable_LVAUX" spirit:order="862">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_EN_PARITY</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_EN_PARITY" spirit:order="863">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_PP_4R_MIR</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_PP_4R_MIR" spirit:order="864">false</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>DDR4 SDRAM (MIG)</xilinx:displayName>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+        <xilinx:systemCLibrary>protobuf</xilinx:systemCLibrary>
+        <xilinx:systemCLibrary>sim_ddr_v1_0</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>10</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ADDR_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CKE_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CK_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CS_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CustomParts" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Ecc" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Slot" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_isCustom" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.LR_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ODT_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.StackHeight" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="a30be5a7"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="9078aaf7"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f0948f98"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="f28b4942"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="832b23d8"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="553d828a"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig
new file mode 100644
index 0000000..698f7e5
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig
@@ -0,0 +1,313 @@
+/******************************************************************************
+// (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
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+******************************************************************************/
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor             : Xilinx
+// \   \   \/     Version            : 1.1
+//  \   \         Application        : MIG
+//  /   /         Filename           : ddr4_v2_2_10_cal_rd_en.sv
+// /___/   /\     Date Last Modified : $Date: 2015/04/23 $
+// \   \  /  \    Date Created       : Thu Apr 18 2013
+//  \___\/\___\
+//
+// Device           : UltraScale
+// Design Name      : DDR4 SDRAM & DDR3 SDRAM
+// Purpose          :
+//                   ddr4_v2_2_10_cal_rd_en module
+// Reference        :
+// Revision History :
+//*****************************************************************************
+
+`timescale 1ns/100ps
+
+module ddr4_v2_2_10_cal_rd_en #(parameter
+    RANKS = 1
+   ,RL  = 11
+   ,EXTRA_CMD_DELAY  = 0
+   ,TCQ = 0.1
+)(
+    input clk
+   ,input rst
+
+   ,output [3:0] mc_clb2phy_rden
+   ,output [3:0] mc_clb2phy_rdcs0
+   ,output [3:0] mc_clb2phy_rdcs1
+
+   ,input [1:0] casSlot       // spyglass disable W498
+   ,input       mccasSlot2
+   ,input       rdCAS
+   ,input       calrdCAS
+   ,input       mcrdCAS
+   ,input [5:0] mCL0
+   ,input [5:0] mCL1
+   ,input [5:0] mCL2
+   ,input [5:0] mCL3
+   ,input [1:0] winRank
+   ,input [1:0] calRank
+   ,input [1:0] mcwinRank
+   ,input       calDone
+);
+
+wire [5:0] mCL[0:3];
+assign mCL[0] = mCL0;
+assign mCL[1] = mCL1;
+assign mCL[2] = mCL2;
+assign mCL[3] = mCL3;
+
+// This section generates the Gate enable mc_clb2phy_rden.
+// This logic is used in calibration and during normal operation.
+// Case 4'b0110 defines nominal timing where the trained mCL value equals RL.
+// This logic supports mCL = RL - 3, to enable the Gate 3tCK earlier than nominal RL.
+// Early gate enable is needed in Gate training, during normal operation
+// if command delays are very low, and to compensate for extra Gate delay
+// in the XiPhy that is allocated for VT tracking.  The logic also supports Gate
+// enable 4tCK later than nominal to allow for command fly-by routing.
+// The Gate enable can be further delayed to allow for extra command pipeline delays.
+// The Gate enable supports RL as low as 7 with no extra command delays, but other
+// blocks have higher low limits, so the minimum RL without extra command delays
+// is expected to be RL=8.
+
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+(* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+reg                      [18:0]                        rsMask[0:7];
+
+function [18:0] rs2mask;
+   input [3:0] diff;
+   input       slot2;
+case ({diff, slot2})
+   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
+     default: rs2mask = 19'b000_0000_1000_0000_1111;
+endcase
+endfunction
+
+always @(posedge clk) begin: blk1
+   reg [3:0] rsNdx;
+   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
+end
+
+always @(*) if (rst) begin
+   rdEn_nxt = 'b0;
+end else begin
+   rdEn_nxt =   (rdEn >> 4)
+                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                : 'b0);
+end
+
+always @(posedge clk)
+   rdEn <= #TCQ rdEn_nxt;
+
+assign mc_clb2phy_rden = rdEn[3:0];
+
+///////////////////////////////////////////////////////////////////
+// This logic is used during normal, multi-rank operation only. Durring cal or single
+// rank operation this logic is bypassed and the output of this section is static.
+// This section generates the read rank signals used by the XiPhy to select per rank
+// cal values during read operations.
+
+integer tck_index;
+localparam rdcs_msb = RL + 8 + 4*EXTRA_CMD_DELAY;
+
+reg  [rdcs_msb :0] rdcs0;
+reg  [rdcs_msb :0] rdcs0_mc;
+reg  [rdcs_msb :0] rdcs1;
+reg  [rdcs_msb :0] rdcs1_mc;
+reg  [6:0]           rdcs_rdcas_lsb_slot0;
+reg                  calDone_dly;
+
+// Extend newest cs (MSB) and shift out the oldest (low 4 LSBs)
+wire [rdcs_msb :0] rdcs0_shift  = { { 4 { rdcs0[rdcs_msb] } }, rdcs0[ rdcs_msb : 4] };
+wire [rdcs_msb :0] rdcs1_shift  = { { 4 { rdcs1[rdcs_msb] } }, rdcs1[ rdcs_msb : 4] };
+
+// Create rdcs mask for the current rdcas
+wire [6:0]         rdcs_rdcas_lsb_slot0_nxt  = { 1'b0, mCL0 } + 4*EXTRA_CMD_DELAY - 7'd7;
+wire [rdcs_msb :0] rdcs_rdcas_mask_slot0     = { ( rdcs_msb + 1 ) { 1'b1 } } << rdcs_rdcas_lsb_slot0;
+wire [rdcs_msb :0] rdcs_rdcas_mask           = rdcs_rdcas_mask_slot0 << 2*mccasSlot2;
+
+// Merge the shifted rdcs and winRank based on the rdcs mask for the current rdcas
+always @(*) begin
+   for (tck_index = 0; tck_index <= rdcs_msb; tck_index = tck_index + 1) begin
+     rdcs0_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[0] : rdcs0_shift[tck_index];
+     rdcs1_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[1] : rdcs1_shift[tck_index];
+   end
+end
+
+// Select mc or cal rdcs
+wire [rdcs_msb :0] rdcs0_nxt = calDone_dly ? rdcs0_mc : { rdcs_msb+1 { calRank[0] } };
+wire [rdcs_msb :0] rdcs1_nxt = calDone_dly ? rdcs1_mc : { rdcs_msb+1 { calRank[1] } };
+
+// Final 4 bit rdcs output
+assign mc_clb2phy_rdcs0 = rdcs0[3:0] & ~{ 4 { RANKS == 1 } };
+assign mc_clb2phy_rdcs1 = rdcs1[3:0] & ~{ 4 { RANKS == 1 } };
+
+// Flops
+always @(posedge clk) begin
+  rdcs_rdcas_lsb_slot0 <= #TCQ rdcs_rdcas_lsb_slot0_nxt;
+  calDone_dly          <= #TCQ calDone;
+end
+
+// Reset flops
+always @(posedge clk) if (rst) begin
+  rdcs0 <= #TCQ '0;
+  rdcs1 <= #TCQ '0;
+end else begin
+  rdcs0 <= #TCQ rdcs0_nxt;
+  rdcs1 <= #TCQ rdcs1_nxt;
+end
+
+
+//synopsys translate_off
+
+`ifdef MEM_INTERNAL
+// Events - When asserted high in a test that passes all verification checks, these coverage
+//          properties indicate that a functional coverage event has been hit.
+// ---------------------------------------------------------------------------------------------
+
+// Minimum mCL in normal operation
+//wire   e_mc_rd_en_000 = ( ( mCL0 + 4*EXTRA_CMD_DELAY ) == 13 ) & calDone & ~( RANKS == 1 ) & rdCAS;
+//always @(posedge clk) mc_rd_en_000: if (~rst) cover property (e_mc_rd_en_000);
+
+
+// Asserts - When asserted high, an illegal condition has been detected and the test has failed.
+// ---------------------------------------------------------------------------------------------
+
+// Check for illegal rank switch in rdEn and rdcs.  rdEn gap must be at least 2tCK wide.  rdcs must be stable for 2tCK after rdEn de-assertion.
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdEn;
+reg                      [rdcs_msb :0]                 a_rdcs0_dly;
+reg                      [rdcs_msb :0]                 a_rdcs1_dly;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0;
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0_nxt = { rdcs0, a_rdcs0_dly[3:0] };
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1;
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1_nxt = { rdcs1, a_rdcs1_dly[3:0] };
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY -1 :0] a_rdEn_falling_edge = ~a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY :1] & a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY -1 :0];
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold0_fail;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold1_fail;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_gap_fail;
+always @(*) begin
+   for (tck_index = 0; tck_index < RL+12 + 4*EXTRA_CMD_DELAY -2; tck_index = tck_index + 1) begin
+     a_rdEn_hold0_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+1] ) | ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+2] ) );
+     a_rdEn_hold1_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+1] ) | ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+2] ) );
+     a_rdEn_gap_fail[tck_index]   = calDone & a_rdEn_falling_edge[tck_index] & a_rdEn[tck_index+2];
+   end
+end
+always @(posedge clk) if (rst) begin
+         a_rdEn      <= #TCQ '0;
+         a_rdcs0_dly <= #TCQ '0;
+         a_rdcs1_dly <= #TCQ '0;
+         a_rdcs0     <= #TCQ '0;
+         a_rdcs1     <= #TCQ '0;
+end else begin
+         a_rdEn      <= #TCQ rdEn;
+         a_rdcs0_dly <= #TCQ rdcs0;
+         a_rdcs1_dly <= #TCQ rdcs1;
+         a_rdcs0     <= #TCQ a_rdcs0_nxt;
+         a_rdcs1     <= #TCQ a_rdcs1_nxt;
+end
+
+// rdcs0 not held for 2tCK after end of burst
+wire a_mc_rd_en_000_hld = calDone & ( | a_rdEn_hold0_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_000_hld);
+
+// rdcs1 not held for 2tCK after end of burst
+wire a_mc_rd_en_001_hld = calDone & ( | a_rdEn_hold1_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_001_hld);
+
+// rdEn not held low for 2tCK after end of burst
+wire a_mc_rd_en_002_hld = calDone & ( | a_rdEn_gap_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_002_hld);
+
+// mCL0 is less than RL-3
+wire a_mc_rd_en_003_ovf = ( mCL0 < (RL - 3) ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_003_ovf);
+
+// mCL1 is less than RL-3
+wire a_mc_rd_en_004_ovf = ( mCL1 < (RL - 3) ) & ( mCL1 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_004_ovf);
+
+// mCL2 is less than RL-3
+wire a_mc_rd_en_005_ovf = ( mCL2 < (RL - 3) ) & ( mCL2 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_005_ovf);
+
+// mCL3 is less than RL-3
+wire a_mc_rd_en_006_ovf = ( mCL3 < (RL - 3) ) & ( mCL3 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_006_ovf);
+
+
+`endif
+//synopsys translate_on
+
+endmodule
+
+
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej
new file mode 100644
index 0000000..29c4462
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej
@@ -0,0 +1,124 @@
+--- U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv
++++ /dev/null
+@@ -114,55 +114,86 @@
+ 
+ reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg                      [18:0]                        rsMask[0:7];
++reg                      [19:0]                        rsMask[0:15];
+ 
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+    input [3:0] diff;
+    input       slot2;
+-case ({diff, slot2})
+-   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+-   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+-   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+-   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++   input       slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++    6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++   6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++    6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++   6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++    6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++   6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++    6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+      default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+ 
+ always @(posedge clk) begin: blk1
+-   reg [3:0] rsNdx;
+-   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+-      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++   reg [4:0] rsNdx;
++   for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+ 
+ always @(*) if (rst) begin
+    rdEn_nxt = 'b0;
+ end else begin
+    rdEn_nxt =   (rdEn >> 4)
+-                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++                | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                 : 'b0);
+ end
+ 
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej
new file mode 100644
index 0000000..76c333f
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv.rej
@@ -0,0 +1,31 @@
+--- U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv
++++ /dev/null
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register.  These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = (   ALL_WR_LATENCY       / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 =   ( ALL_WR_LATENCY     ) % 4;
++localparam OFFSET_CASSLOT1 =   ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 =   ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 =   ( ALL_WR_LATENCY + 3 ) % 4;
+ 
+ integer i;
+ 
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc.  mccasSlot2 is timing critical.
+ reg  [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone    ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric        = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric        = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++                         (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+ 
+ // tCK offset for mc.  mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++                         (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+ 
+ // Output enable shift register load value for cal and mc.  mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf,   calRank, OFFSET_CASSLOT2[1:0], 1'b1};
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd
new file mode 100644
index 0000000..88c7541
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bd
@@ -0,0 +1,513 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0xBCE55F3980178BC9",
+      "design_src": "SBD",
+      "device": "xcu200-fsgd2104-2-e",
+      "name": "bd_ba6a",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "scoped": "true",
+      "synth_flow_mode": "None",
+      "tool_version": "2020.2",
+      "validated": "true"
+    },
+    "design_tree": {
+      "microblaze_I": "",
+      "rst_0": "",
+      "ilmb": "",
+      "dlmb": "",
+      "dlmb_cntlr": "",
+      "ilmb_cntlr": "",
+      "lmb_bram_I": "",
+      "second_dlmb_cntlr": "",
+      "second_ilmb_cntlr": "",
+      "second_lmb_bram_I": "",
+      "iomodule_0": ""
+    },
+    "interface_ports": {
+      "IO": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:mcsio_bus_rtl:1.0"
+      },
+      "TRACE": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:mbtrace_rtl:2.0"
+      }
+    },
+    "ports": {
+      "Clk": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "ASSOCIATED_ASYNC_RESET": {
+            "value": "Reset"
+          },
+          "CLK_DOMAIN": {
+            "value": "bd_ba6a_Clk",
+            "value_src": "constant"
+          },
+          "FREQ_HZ": {
+            "value": "100000000"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.000",
+            "value_src": "default"
+          }
+        }
+      },
+      "Reset": {
+        "type": "rst",
+        "direction": "I",
+        "parameters": {
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "POLARITY": {
+            "value": "ACTIVE_HIGH"
+          }
+        }
+      }
+    },
+    "components": {
+      "microblaze_I": {
+        "vlnv": "xilinx.com:ip:microblaze:11.0",
+        "xci_name": "bd_ba6a_microblaze_I_0",
+        "parameters": {
+          "C_ASYNC_WAKEUP": {
+            "value": "3"
+          },
+          "C_DEBUG_ENABLED": {
+            "value": "0"
+          },
+          "C_FAULT_TOLERANT": {
+            "value": "0"
+          },
+          "C_INSTANCE": {
+            "value": "mb_microblaze_0"
+          },
+          "C_PC_WIDTH": {
+            "value": "17"
+          },
+          "C_TRACE": {
+            "value": "1"
+          },
+          "C_USE_BARREL": {
+            "value": "1"
+          },
+          "C_USE_DIV": {
+            "value": "1"
+          },
+          "C_USE_EXT_BRK": {
+            "value": "0"
+          },
+          "C_USE_EXT_NM_BRK": {
+            "value": "0"
+          },
+          "C_USE_HW_MUL": {
+            "value": "1"
+          },
+          "C_USE_PCMP_INSTR": {
+            "value": "1"
+          },
+          "C_USE_REORDER_INSTR": {
+            "value": "0"
+          }
+        },
+        "addressing": {
+          "address_spaces": {
+            "Data": {
+              "range": "4G",
+              "width": "32"
+            },
+            "Instruction": {
+              "range": "4G",
+              "width": "32"
+            }
+          }
+        },
+        "interface_ports": {
+          "DLMB": {
+            "mode": "Master",
+            "address_space_ref": "Data",
+            "base_address": {
+              "minimum": "0x00000000",
+              "maximum": "0xFFFFFFFF",
+              "width": "32"
+            }
+          },
+          "ILMB": {
+            "mode": "Master",
+            "address_space_ref": "Instruction",
+            "base_address": {
+              "minimum": "0x00000000",
+              "maximum": "0xFFFFFFFF",
+              "width": "32"
+            }
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_PROCESSOR": {
+            "value": "microblaze-le > bd_ba6a dlmb_cntlr",
+            "value_src": "default"
+          },
+          "KEEP_HIERARCHY": {
+            "value": "yes",
+            "value_src": "default"
+          }
+        }
+      },
+      "rst_0": {
+        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
+        "xci_name": "bd_ba6a_rst_0_0"
+      },
+      "ilmb": {
+        "vlnv": "xilinx.com:ip:lmb_v10:3.0",
+        "xci_name": "bd_ba6a_ilmb_0",
+        "parameters": {
+          "C_LMB_NUM_SLAVES": {
+            "value": "2"
+          }
+        },
+        "interface_ports": {
+          "LMB_M": {
+            "mode": "MirroredMaster",
+            "bridges": [
+              "LMB_Sl_0",
+              "LMB_Sl_1"
+            ]
+          }
+        }
+      },
+      "dlmb": {
+        "vlnv": "xilinx.com:ip:lmb_v10:3.0",
+        "xci_name": "bd_ba6a_dlmb_0",
+        "parameters": {
+          "C_LMB_NUM_SLAVES": {
+            "value": "3"
+          }
+        },
+        "interface_ports": {
+          "LMB_M": {
+            "mode": "MirroredMaster",
+            "bridges": [
+              "LMB_Sl_0",
+              "LMB_Sl_1",
+              "LMB_Sl_2"
+            ]
+          }
+        }
+      },
+      "dlmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_ba6a_dlmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000000000FFFF"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0010000"
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_ADDRESS_SPACE": {
+            "value": "byte  0x00000000 32 >  bd_ba6a lmb_bram_I bd_ba6a second_lmb_bram_I",
+            "value_src": "default"
+          },
+          "KEEP_HIERARCHY": {
+            "value": "yes",
+            "value_src": "default"
+          }
+        }
+      },
+      "ilmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_ba6a_ilmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000000000FFFF"
+          },
+          "C_MASK": {
+            "value": "0x0000000080010000"
+          }
+        }
+      },
+      "lmb_bram_I": {
+        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
+        "xci_name": "bd_ba6a_lmb_bram_I_0",
+        "parameters": {
+          "Memory_Type": {
+            "value": "True_Dual_Port_RAM"
+          }
+        }
+      },
+      "second_dlmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_ba6a_second_dlmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000010000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x0000000000017FFF"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0010000"
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_ADDRESS_RANGE": {
+            "value": " ",
+            "value_src": "default"
+          }
+        }
+      },
+      "second_ilmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_ba6a_second_ilmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000010000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x0000000000017FFF"
+          },
+          "C_MASK": {
+            "value": "0x0000000080010000"
+          }
+        }
+      },
+      "second_lmb_bram_I": {
+        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
+        "xci_name": "bd_ba6a_second_lmb_bram_I_0",
+        "parameters": {
+          "Memory_Type": {
+            "value": "True_Dual_Port_RAM"
+          }
+        }
+      },
+      "iomodule_0": {
+        "vlnv": "xilinx.com:ip:iomodule:3.1",
+        "xci_name": "bd_ba6a_iomodule_0_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000080000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000008000FFFF"
+          },
+          "C_INSTANCE": {
+            "value": "iomodule"
+          },
+          "C_INTC_ADDR_WIDTH": {
+            "value": "17"
+          },
+          "C_INTC_HAS_FAST": {
+            "value": "1"
+          },
+          "C_INTC_USE_IRQ_OUT": {
+            "value": "1"
+          },
+          "C_IO_BASEADDR": {
+            "value": "0x00000000C0000000"
+          },
+          "C_IO_HIGHADDR": {
+            "value": "0x00000000FFFFFFFF"
+          },
+          "C_IO_MASK": {
+            "value": "0x00000000C0000000"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0000000"
+          },
+          "C_USE_IO_BUS": {
+            "value": "1"
+          }
+        }
+      }
+    },
+    "interface_nets": {
+      "dlmb_port": {
+        "interface_ports": [
+          "dlmb_cntlr/BRAM_PORT",
+          "lmb_bram_I/BRAM_PORTA"
+        ]
+      },
+      "dlmb_sl_0": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_0",
+          "dlmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb_sl_2": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_2",
+          "second_dlmb_cntlr/SLMB"
+        ]
+      },
+      "ilmb_port": {
+        "interface_ports": [
+          "ilmb_cntlr/BRAM_PORT",
+          "lmb_bram_I/BRAM_PORTB"
+        ]
+      },
+      "dlmb_sl_1": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_1",
+          "iomodule_0/SLMB"
+        ]
+      },
+      "microblaze_I_Trace": {
+        "interface_ports": [
+          "TRACE",
+          "microblaze_I/TRACE"
+        ]
+      },
+      "ilmb_port_2": {
+        "interface_ports": [
+          "second_ilmb_cntlr/BRAM_PORT",
+          "second_lmb_bram_I/BRAM_PORTB"
+        ]
+      },
+      "ilmb": {
+        "interface_ports": [
+          "microblaze_I/ILMB",
+          "ilmb/LMB_M"
+        ]
+      },
+      "ilmb_sl_0": {
+        "interface_ports": [
+          "ilmb/LMB_Sl_0",
+          "ilmb_cntlr/SLMB"
+        ]
+      },
+      "ilmb_sl_1": {
+        "interface_ports": [
+          "ilmb/LMB_Sl_1",
+          "second_ilmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb_port_2": {
+        "interface_ports": [
+          "second_dlmb_cntlr/BRAM_PORT",
+          "second_lmb_bram_I/BRAM_PORTA"
+        ]
+      },
+      "dlmb": {
+        "interface_ports": [
+          "microblaze_I/DLMB",
+          "dlmb/LMB_M"
+        ]
+      },
+      "iomodule_0_IO": {
+        "interface_ports": [
+          "IO",
+          "iomodule_0/IO_BUS"
+        ]
+      }
+    },
+    "nets": {
+      "Clk2": {
+        "ports": [
+          "Clk",
+          "microblaze_I/Clk",
+          "ilmb/LMB_Clk",
+          "dlmb/LMB_Clk",
+          "dlmb_cntlr/LMB_Clk",
+          "ilmb_cntlr/LMB_Clk",
+          "second_dlmb_cntlr/LMB_Clk",
+          "second_ilmb_cntlr/LMB_Clk",
+          "iomodule_0/Clk",
+          "rst_0/slowest_sync_clk"
+        ]
+      },
+      "Reset": {
+        "ports": [
+          "Reset",
+          "rst_0/ext_reset_in"
+        ]
+      },
+      "MB_Reset": {
+        "ports": [
+          "rst_0/mb_reset",
+          "microblaze_I/Reset"
+        ]
+      },
+      "LMB_Rst2": {
+        "ports": [
+          "rst_0/bus_struct_reset",
+          "ilmb/SYS_Rst",
+          "dlmb/SYS_Rst",
+          "ilmb_cntlr/LMB_Rst",
+          "dlmb_cntlr/LMB_Rst",
+          "second_ilmb_cntlr/LMB_Rst",
+          "second_dlmb_cntlr/LMB_Rst"
+        ]
+      },
+      "IO_Rst": {
+        "ports": [
+          "rst_0/peripheral_reset",
+          "iomodule_0/Rst"
+        ]
+      }
+    },
+    "addressing": {
+      "/microblaze_I": {
+        "address_spaces": {
+          "Data": {
+            "segments": {
+              "SEG_dlmb_cntlr_Mem": {
+                "address_block": "/dlmb_cntlr/SLMB/Mem",
+                "offset": "0x00000000",
+                "range": "64K"
+              },
+              "SEG_iomodule_0_IO": {
+                "address_block": "/iomodule_0/SLMB/IO",
+                "offset": "0xC0000000",
+                "range": "1G"
+              },
+              "SEG_iomodule_0_Reg": {
+                "address_block": "/iomodule_0/SLMB/Reg",
+                "offset": "0x80000000",
+                "range": "64K"
+              },
+              "SEG_second_dlmb_cntlr_Mem": {
+                "address_block": "/second_dlmb_cntlr/SLMB/Mem",
+                "offset": "0x00010000",
+                "range": "32K"
+              }
+            }
+          },
+          "Instruction": {
+            "segments": {
+              "SEG_ilmb_cntlr_Mem": {
+                "address_block": "/ilmb_cntlr/SLMB/Mem",
+                "offset": "0x00000000",
+                "range": "64K"
+              },
+              "SEG_second_ilmb_cntlr_Mem": {
+                "address_block": "/second_ilmb_cntlr/SLMB/Mem",
+                "offset": "0x00010000",
+                "range": "32K"
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml
new file mode 100644
index 0000000..dddba12
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/bd_ba6a.bxml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="39">
+  <CompositeFile CompositeFileTopName="bd_ba6a" CanBeSetAsTop="true" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="RESET" Timestamp="1646750778"/>
+    <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1646750778"/>
+    <Generation Name="SIMULATION" State="RESET" Timestamp="1646750778"/>
+    <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1646750778"/>
+    <FileCollection Name="SOURCES" Type="SOURCES">
+      <File Name="ip/ip_0/bd_ba6a_microblaze_I_0.xci" Type="IP">
+        <Instance HierarchyPath="microblaze_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_1/bd_ba6a_rst_0_0.xci" Type="IP">
+        <Instance HierarchyPath="rst_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_2/bd_ba6a_ilmb_0.xci" Type="IP">
+        <Instance HierarchyPath="ilmb"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_3/bd_ba6a_dlmb_0.xci" Type="IP">
+        <Instance HierarchyPath="dlmb"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="dlmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="ilmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_6/bd_ba6a_lmb_bram_I_0.xci" Type="IP">
+        <Instance HierarchyPath="lmb_bram_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="second_dlmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="second_ilmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci" Type="IP">
+        <Instance HierarchyPath="second_lmb_bram_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_10/bd_ba6a_iomodule_0_0.xci" Type="IP">
+        <Instance HierarchyPath="iomodule_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+    </FileCollection>
+  </CompositeFile>
+</Root>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v
new file mode 100644
index 0000000..62aef3f
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/hdl/bd_ba6a_wrapper.v
@@ -0,0 +1,173 @@
+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Command: generate_target bd_ba6a_wrapper.bd
+//Design : bd_ba6a_wrapper
+//Purpose: IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module bd_ba6a_wrapper
+   (Clk,
+    IO_addr_strobe,
+    IO_address,
+    IO_byte_enable,
+    IO_read_data,
+    IO_read_strobe,
+    IO_ready,
+    IO_write_data,
+    IO_write_strobe,
+    Reset,
+    TRACE_data_access,
+    TRACE_data_address,
+    TRACE_data_byte_enable,
+    TRACE_data_read,
+    TRACE_data_write,
+    TRACE_data_write_value,
+    TRACE_dcache_hit,
+    TRACE_dcache_rdy,
+    TRACE_dcache_read,
+    TRACE_dcache_req,
+    TRACE_delay_slot,
+    TRACE_ex_piperun,
+    TRACE_exception_kind,
+    TRACE_exception_taken,
+    TRACE_icache_hit,
+    TRACE_icache_rdy,
+    TRACE_icache_req,
+    TRACE_instruction,
+    TRACE_jump_hit,
+    TRACE_jump_taken,
+    TRACE_mb_halted,
+    TRACE_mem_piperun,
+    TRACE_msr_reg,
+    TRACE_new_reg_value,
+    TRACE_of_piperun,
+    TRACE_pc,
+    TRACE_pid_reg,
+    TRACE_reg_addr,
+    TRACE_reg_write,
+    TRACE_valid_instr);
+  input Clk;
+  output IO_addr_strobe;
+  output [31:0]IO_address;
+  output [3:0]IO_byte_enable;
+  input [31:0]IO_read_data;
+  output IO_read_strobe;
+  input IO_ready;
+  output [31:0]IO_write_data;
+  output IO_write_strobe;
+  input Reset;
+  output TRACE_data_access;
+  output [0:31]TRACE_data_address;
+  output [0:3]TRACE_data_byte_enable;
+  output TRACE_data_read;
+  output TRACE_data_write;
+  output [0:31]TRACE_data_write_value;
+  output TRACE_dcache_hit;
+  output TRACE_dcache_rdy;
+  output TRACE_dcache_read;
+  output TRACE_dcache_req;
+  output TRACE_delay_slot;
+  output TRACE_ex_piperun;
+  output [0:4]TRACE_exception_kind;
+  output TRACE_exception_taken;
+  output TRACE_icache_hit;
+  output TRACE_icache_rdy;
+  output TRACE_icache_req;
+  output [0:31]TRACE_instruction;
+  output TRACE_jump_hit;
+  output TRACE_jump_taken;
+  output TRACE_mb_halted;
+  output TRACE_mem_piperun;
+  output [0:14]TRACE_msr_reg;
+  output [0:31]TRACE_new_reg_value;
+  output TRACE_of_piperun;
+  output [0:31]TRACE_pc;
+  output [0:7]TRACE_pid_reg;
+  output [0:4]TRACE_reg_addr;
+  output TRACE_reg_write;
+  output TRACE_valid_instr;
+
+  wire Clk;
+  wire IO_addr_strobe;
+  wire [31:0]IO_address;
+  wire [3:0]IO_byte_enable;
+  wire [31:0]IO_read_data;
+  wire IO_read_strobe;
+  wire IO_ready;
+  wire [31:0]IO_write_data;
+  wire IO_write_strobe;
+  wire Reset;
+  wire TRACE_data_access;
+  wire [0:31]TRACE_data_address;
+  wire [0:3]TRACE_data_byte_enable;
+  wire TRACE_data_read;
+  wire TRACE_data_write;
+  wire [0:31]TRACE_data_write_value;
+  wire TRACE_dcache_hit;
+  wire TRACE_dcache_rdy;
+  wire TRACE_dcache_read;
+  wire TRACE_dcache_req;
+  wire TRACE_delay_slot;
+  wire TRACE_ex_piperun;
+  wire [0:4]TRACE_exception_kind;
+  wire TRACE_exception_taken;
+  wire TRACE_icache_hit;
+  wire TRACE_icache_rdy;
+  wire TRACE_icache_req;
+  wire [0:31]TRACE_instruction;
+  wire TRACE_jump_hit;
+  wire TRACE_jump_taken;
+  wire TRACE_mb_halted;
+  wire TRACE_mem_piperun;
+  wire [0:14]TRACE_msr_reg;
+  wire [0:31]TRACE_new_reg_value;
+  wire TRACE_of_piperun;
+  wire [0:31]TRACE_pc;
+  wire [0:7]TRACE_pid_reg;
+  wire [0:4]TRACE_reg_addr;
+  wire TRACE_reg_write;
+  wire TRACE_valid_instr;
+
+  bd_ba6a bd_ba6a_i
+       (.Clk(Clk),
+        .IO_addr_strobe(IO_addr_strobe),
+        .IO_address(IO_address),
+        .IO_byte_enable(IO_byte_enable),
+        .IO_read_data(IO_read_data),
+        .IO_read_strobe(IO_read_strobe),
+        .IO_ready(IO_ready),
+        .IO_write_data(IO_write_data),
+        .IO_write_strobe(IO_write_strobe),
+        .Reset(Reset),
+        .TRACE_data_access(TRACE_data_access),
+        .TRACE_data_address(TRACE_data_address),
+        .TRACE_data_byte_enable(TRACE_data_byte_enable),
+        .TRACE_data_read(TRACE_data_read),
+        .TRACE_data_write(TRACE_data_write),
+        .TRACE_data_write_value(TRACE_data_write_value),
+        .TRACE_dcache_hit(TRACE_dcache_hit),
+        .TRACE_dcache_rdy(TRACE_dcache_rdy),
+        .TRACE_dcache_read(TRACE_dcache_read),
+        .TRACE_dcache_req(TRACE_dcache_req),
+        .TRACE_delay_slot(TRACE_delay_slot),
+        .TRACE_ex_piperun(TRACE_ex_piperun),
+        .TRACE_exception_kind(TRACE_exception_kind),
+        .TRACE_exception_taken(TRACE_exception_taken),
+        .TRACE_icache_hit(TRACE_icache_hit),
+        .TRACE_icache_rdy(TRACE_icache_rdy),
+        .TRACE_icache_req(TRACE_icache_req),
+        .TRACE_instruction(TRACE_instruction),
+        .TRACE_jump_hit(TRACE_jump_hit),
+        .TRACE_jump_taken(TRACE_jump_taken),
+        .TRACE_mb_halted(TRACE_mb_halted),
+        .TRACE_mem_piperun(TRACE_mem_piperun),
+        .TRACE_msr_reg(TRACE_msr_reg),
+        .TRACE_new_reg_value(TRACE_new_reg_value),
+        .TRACE_of_piperun(TRACE_of_piperun),
+        .TRACE_pc(TRACE_pc),
+        .TRACE_pid_reg(TRACE_pid_reg),
+        .TRACE_reg_addr(TRACE_reg_addr),
+        .TRACE_reg_write(TRACE_reg_write),
+        .TRACE_valid_instr(TRACE_valid_instr));
+endmodule
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci
new file mode 100644
index 0000000..7bd31b9
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xci
@@ -0,0 +1,1032 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>bd_ba6a_microblaze_I_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze" spirit:version="11.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_HZ">30000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_INTR.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M0_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M0_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPCODE_0x0_ILLEGAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPTIMIZATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PC_WIDTH">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PVR">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PVR_USER2">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_BIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_DCE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_EE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_EIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_ICE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RESET_MSR_IE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S0_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S0_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S10_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S10_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S11_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S11_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S12_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S12_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S13_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S13_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S14_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S14_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S15_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S15_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S1_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S1_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S2_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S2_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S3_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S3_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S4_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S4_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S5_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S5_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S6_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S6_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S7_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S7_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S8_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S8_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S9_AXIS_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S9_AXIS_PROTOCOL">GENERIC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCO">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRACE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UNALIGNED_EXCEPTIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BARREL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BRANCH_TARGET_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_DCACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_DIV">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXTENDED_FSL_INSTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXT_BRK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FPU">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_HW_MUL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_ICACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_MMU">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_MSR_INSTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_NON_SECURE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PCMP_INSTR">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STACK_PROTECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_ba6a_microblaze_I_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.G_TEMPLATE_LIST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.G_USE_EXCEPTIONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ASYNC_WAKEUP" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DEBUG_ENABLED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_D_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EDGE_IS_POSITIVE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FAULT_TOLERANT" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_IS_EDGE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_I_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUMBER_OF_PC_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PC_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TRACE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_BARREL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_DIV" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_HW_MUL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_INTERRUPT" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_NON_SECURE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_PCMP_INSTR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
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+l_right&quot;:&quot;31&quot;},&quot;Data_Read&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Data_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;D_AS&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Read_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Write_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DReady&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DWait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DCE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DUE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Trace_Instruction&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Valid_Instr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_PC&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Reg_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,
+&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Reg_Addr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;},&quot;Trace_MSR_Reg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;},&quot;Trace_PID_Reg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;},&quot;Trace_New_Reg_Value&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Exception_Taken&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Exception_Kind&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;},&quot;Trace_Jump_Taken&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Delay_Slot&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Address&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Data_Write_Value&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Data_Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Trace_Data_Access&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:
+&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Read&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Rdy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Read&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Rdy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_OF_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_EX_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_MEM_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_MB_Ha
+lted&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Jump_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;Reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;
+value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:
+[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;INTERRUPT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbinterrupt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbinterrupt_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;SENSITIVITY&quot;:[{&quot;value&quot;:&quot;LEVEL_HIGH&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LOW_LATENCY&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ACK&quot;:{&quot;physical_name&quot;:&quot;Interrupt_Ack&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;1&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;Interrupt_Address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;INTERRUPT&quot;:{&quot;physical_name&quot;:&quot;Interrupt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;DLMB&quot;:{&quot;vl
+nv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;Data_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;D_AS&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;Byte_Enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;DCE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical
+_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Data_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;Read_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;DReady&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;DUE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;DWait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;Data_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;Write_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ILMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;
+master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_ONLY&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;Instr_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;I_AS&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;ICE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;IFetch&quot;,&quot;phy
+sical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IReady&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;IUE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;IWAIT&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;TRACE&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbtrace:2.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbtrace_rtl:2.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;DATA_ACCESS&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_ADDRESS&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DATA_BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Byte_Enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;DATA_READ&quot;:{&quot;physi
+cal_name&quot;:&quot;Trace_Data_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE_VALUE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Write_Value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DCACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_READ&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DELAY_SLOT&quot;:{&quot;physical_name&quot;:&quot;Trace_Delay_Slot&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;log
+ical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EX_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_EX_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EXCEPTION_KIND&quot;:{&quot;physical_name&quot;:&quot;Trace_Exception_Kind&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;EXCEPTION_TAKEN&quot;:{&quot;physical_name&quot;:&quot;Trace_Exception_Taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;INSTRUCTION&quot;:{&quot;physical_name&quot;:&quot;Trace_Instruction&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;JUMP_HIT&quot;:{&quot;physical_name&quot;:&quot;Tr
+ace_Jump_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;JUMP_TAKEN&quot;:{&quot;physical_name&quot;:&quot;Trace_Jump_Taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MB_HALTED&quot;:{&quot;physical_name&quot;:&quot;Trace_MB_Halted&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MEM_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_MEM_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MSR_REG&quot;:{&quot;physical_name&quot;:&quot;Trace_MSR_Reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;14&quot;},&quot;NEW_REG_VALUE&quot;:{&quot;physical_name&quot;:&quot;Trace_New_Reg_Value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;OF_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_OF_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PC&quot;:{&quot;physical_name&quot;:&quot;Trace_PC&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;PID
+_REG&quot;:{&quot;physical_name&quot;:&quot;Trace_PID_Reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;7&quot;},&quot;REG_ADDR&quot;:{&quot;physical_name&quot;:&quot;Trace_Reg_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;REG_WRITE&quot;:{&quot;physical_name&quot;:&quot;Trace_Reg_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;VALID_INSTR&quot;:{&quot;physical_name&quot;:&quot;Trace_Valid_Instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml
new file mode 100644
index 0000000..1b8c2d1
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/bd_ba6a_microblaze_I_0.xml
@@ -0,0 +1,27445 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_microblaze_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.CLK</spirit:name>
+      <spirit:displayName>Clk</spirit:displayName>
+      <spirit:description>Clock input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF">M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET">Reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Clk frequency</spirit:displayName>
+          <spirit:description>Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.RESET</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.RESET.TYPE">PROCESSOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT</spirit:name>
+      <spirit:displayName>INTERRUPT</spirit:displayName>
+      <spirit:description>Interrupt Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 0))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_INTERRUPT</spirit:name>
+      <spirit:displayName>INTERRUPT</spirit:displayName>
+      <spirit:description>Interrupt Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_INTERRUPT.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DLMB</spirit:name>
+      <spirit:displayName>DLMB</spirit:displayName>
+      <spirit:description>Data Local Memory Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>D_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DCE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Read_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DWait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Write_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.DLMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.DLMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DLMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB_MON&apos;)) = 0)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_DLMB</spirit:name>
+      <spirit:displayName>DLMB</spirit:displayName>
+      <spirit:description>Data Local Memory Bus Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>D_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DCE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Read_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DWait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Write_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_DLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_DLMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ILMB</spirit:name>
+      <spirit:displayName>ILMB</spirit:displayName>
+      <spirit:description>Instruction Local Memory Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>I_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ICE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IFetch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IWAIT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ILMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.ILMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ILMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ILMB.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ILMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB_MON&apos;)) = 0)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ILMB</spirit:name>
+      <spirit:displayName>ILMB</spirit:displayName>
+      <spirit:description>Instruction Local Memory Bus Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>I_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ICE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IFetch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IWAIT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ILMB.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ILMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_DP</spirit:name>
+      <spirit:displayName>M_AXI_DP</spirit:displayName>
+      <spirit:description>Master AXI4 Data Peripheral Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.PROTOCOL" spirit:dependency="substring(&quot;AXI4LITE&quot;, 1, 4 + 4 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) &lt; 2) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 0)))">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_DP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_DP</spirit:name>
+      <spirit:displayName>M_AXI_DP</spirit:displayName>
+      <spirit:description>Master AXI4 Data Peripheral Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.PROTOCOL" spirit:dependency="substring(&quot;AXI4LITE&quot;, 1, 4 + 4 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) &lt; 2) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 0)))">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_DP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_IP</spirit:name>
+      <spirit:displayName>M_AXI_IP</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Peripheral Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_IP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_IP</spirit:name>
+      <spirit:displayName>M_AXI_IP</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Peripheral Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_IP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IP_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M0_AXIS</spirit:name>
+      <spirit:displayName>M0_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M0_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S0_AXIS</spirit:name>
+      <spirit:displayName>S0_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S0_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M1_AXIS</spirit:name>
+      <spirit:displayName>M1_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M1_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S1_AXIS</spirit:name>
+      <spirit:displayName>S1_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S1_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M2_AXIS</spirit:name>
+      <spirit:displayName>M2_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M2_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S2_AXIS</spirit:name>
+      <spirit:displayName>S2_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S2_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M3_AXIS</spirit:name>
+      <spirit:displayName>M3_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M3_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S3_AXIS</spirit:name>
+      <spirit:displayName>S3_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S3_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M4_AXIS</spirit:name>
+      <spirit:displayName>M4_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M4_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S4_AXIS</spirit:name>
+      <spirit:displayName>S4_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S4_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M5_AXIS</spirit:name>
+      <spirit:displayName>M5_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M5_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S5_AXIS</spirit:name>
+      <spirit:displayName>S5_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S5_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M6_AXIS</spirit:name>
+      <spirit:displayName>M6_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M6_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S6_AXIS</spirit:name>
+      <spirit:displayName>S6_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S6_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M7_AXIS</spirit:name>
+      <spirit:displayName>M7_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M7_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S7_AXIS</spirit:name>
+      <spirit:displayName>S7_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S7_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M8_AXIS</spirit:name>
+      <spirit:displayName>M8_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M8_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S8_AXIS</spirit:name>
+      <spirit:displayName>S8_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S8_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M9_AXIS</spirit:name>
+      <spirit:displayName>M9_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M9_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S9_AXIS</spirit:name>
+      <spirit:displayName>S9_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S9_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M10_AXIS</spirit:name>
+      <spirit:displayName>M10_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M10_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S10_AXIS</spirit:name>
+      <spirit:displayName>S10_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S10_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M11_AXIS</spirit:name>
+      <spirit:displayName>M11_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M11_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S11_AXIS</spirit:name>
+      <spirit:displayName>S11_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S11_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M12_AXIS</spirit:name>
+      <spirit:displayName>M12_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M12_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S12_AXIS</spirit:name>
+      <spirit:displayName>S12_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S12_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M13_AXIS</spirit:name>
+      <spirit:displayName>M13_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M13_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S13_AXIS</spirit:name>
+      <spirit:displayName>S13_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S13_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M14_AXIS</spirit:name>
+      <spirit:displayName>M14_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M14_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S14_AXIS</spirit:name>
+      <spirit:displayName>S14_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S14_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M15_AXIS</spirit:name>
+      <spirit:displayName>M15_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M15_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S15_AXIS</spirit:name>
+      <spirit:displayName>S15_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S15_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_DC</spirit:name>
+      <spirit:displayName>M_AXI_DC</spirit:displayName>
+      <spirit:description>Master AXI4 Data Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_DC</spirit:name>
+      <spirit:displayName>M_AXI_DC</spirit:displayName>
+      <spirit:description>Master AXI4 Data Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_ACE_DC</spirit:name>
+      <spirit:displayName>M_ACE_DC</spirit:displayName>
+      <spirit:description>Master ACE Data Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_ACE_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ACE_DC</spirit:name>
+      <spirit:displayName>M_ACE_DC</spirit:displayName>
+      <spirit:description>Master ACE Data Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ACE_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_IC</spirit:name>
+      <spirit:displayName>M_AXI_IC</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_IC</spirit:name>
+      <spirit:displayName>M_AXI_IC</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_ACE_IC</spirit:name>
+      <spirit:displayName>M_ACE_IC</spirit:displayName>
+      <spirit:description>Master ACE Instruction Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_ACE_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ACE_IC</spirit:name>
+      <spirit:displayName>M_ACE_IC</spirit:displayName>
+      <spirit:description>Master ACE Instruction Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ACE_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DEBUG</spirit:name>
+      <spirit:displayName>DEBUG</spirit:displayName>
+      <spirit:description>MicroBlaze Debug Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbdebug" spirit:version="3.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbdebug_rtl" spirit:version="3.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CAPTURE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Capture</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DISABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Disable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Reg_En</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Debug_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SHIFT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Shift</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDI</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_TDI</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDO</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_TDO</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRCLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_ACK_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Ack_In</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_ACK_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Ack_Out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_In</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UPDATE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Update</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DEBUG" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) &lt; 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_DEBUG</spirit:name>
+      <spirit:displayName>DEBUG</spirit:displayName>
+      <spirit:description>AXI4-Lite Debug</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_DEBUG"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_DEBUG" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.DEBUG_ACLK</spirit:name>
+      <spirit:displayName>DEBUG_ACLK</spirit:displayName>
+      <spirit:description>Parallel Debug Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DEBUG_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.ASSOCIATED_BUSIF">DEBUG:S_AXI_DEBUG</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.ASSOCIATED_RESET">DEBUG_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>DEBUG_ACLK frequency</spirit:displayName>
+          <spirit:description>DEBUG_ACLK frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_HZ">30000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.DEBUG_ACLK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) > 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.DEBUG_ARESETN</spirit:name>
+      <spirit:displayName>DEBUG_ARESETN</spirit:displayName>
+      <spirit:description>Parallel Debug Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DEBUG_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.DEBUG_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.DEBUG_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.DEBUG_ARESETN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) > 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DBG_INTR</spirit:name>
+      <spirit:displayName>Dbg_Intr</spirit:displayName>
+      <spirit:description>Debug Interrupt Output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Intr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_INTR.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DBG_INTR.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DBG_INTR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_ENABLE_DISCRETE_PORTS&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:displayName>TRACE</spirit:displayName>
+      <spirit:description>MicroBlaze Trace Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace" spirit:version="2.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace_rtl" spirit:version="2.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Access</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Write_Value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DELAY_SLOT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Delay_Slot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EX_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_EX_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_KIND</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Exception_Kind</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Exception_Taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INSTRUCTION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Instruction</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Jump_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Jump_Taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MB_HALTED</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MB_Halted</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MEM_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MEM_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MSR_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MSR_Reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NEW_REG_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_New_Reg_Value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>OF_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_OF_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PC</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_PC</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PID_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_PID_Reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Reg_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Reg_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_INSTR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Valid_Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.TRACE" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_TRACE&apos;)) = 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:width>
+      <spirit:localMemoryMap>
+        <spirit:name>local_memory_map</spirit:name>
+        <spirit:addressBlock>
+          <spirit:name>microblaze_0</spirit:name>
+          <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+          <spirit:range spirit:format="long">98304</spirit:range>
+          <spirit:width spirit:format="long">32</spirit:width>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>lsb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.lsb">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>msb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.msb">31</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>workflow</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.workflow">simulation</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>controlpaths</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.controlpaths">dlmb_cntlr=lmb_bram_I,second_dlmb_cntlr=second_lmb_bram_I</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>memorytypename</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.memorytypename"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>simmemfile</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.simmemfile"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>combined</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.combined">{&quot;AddressBlocks&quot;:[{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:0,&quot;AddrEnd&quot;:65535,&quot;Workflow&quot;:&quot;simulation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot; bd_ba6a lmb_bram_I_MEM_DEVICE&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:65536,&quot;MemFile&quot;:&quot;bd_ba6a_lmb_bram_I_0.mem&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;dlmb_cntlr&quot;,&quot;Val&quot;:&quot;lmb_bram_I&quot;}]},{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:65536,&quot;AddrEnd&quot;:98303,&quot;Workflow&quot;:&quot;simulation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot; bd_ba6a lmb_bram_I bd_ba6a
+ second_lmb_bram_I_MEM_DEVICE&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:32768,&quot;MemFile&quot;:&quot;bd_ba6a_second_lmb_bram_I_0.mem&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;second_dlmb_cntlr&quot;,&quot;Val&quot;:&quot;second_lmb_bram_I&quot;}]}]}</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </spirit:addressBlock>
+        <spirit:addressBlock>
+          <spirit:name>microblaze_1</spirit:name>
+          <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+          <spirit:range spirit:format="long">98304</spirit:range>
+          <spirit:width spirit:format="long">32</spirit:width>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>lsb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.lsb">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>msb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.msb">31</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>workflow</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.workflow">implementation</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>controlpaths</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.controlpaths">dlmb_cntlr=lmb_bram_I,second_dlmb_cntlr=second_lmb_bram_I</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>memorytypename</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.memorytypename"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>simmemfile</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.simmemfile"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>combined</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.combined">{&quot;AddressBlocks&quot;:[{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:0,&quot;AddrEnd&quot;:65535,&quot;Workflow&quot;:&quot;implementation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot;&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:65536,&quot;MemFile&quot;:&quot;&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;dlmb_cntlr&quot;,&quot;Val&quot;:&quot;lmb_bram_I&quot;}]},{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:65536,&quot;AddrEnd&quot;:98303,&quot;Workflow&quot;:&quot;implementation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot;&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:32768,&quot;MemFile&quot;:&quot;&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;second_d
+lmb_cntlr&quot;,&quot;Val&quot;:&quot;second_lmb_bram_I&quot;}]}]}</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </spirit:addressBlock>
+      </spirit:localMemoryMap>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Instruction</spirit:name>
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+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:width>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_DEBUG</spirit:name>
+      <spirit:description>AXI debug memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Debug Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="32768" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Mb_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Mb_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Config_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Scan_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_Reset_Sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_En</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
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+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>RAM_To</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">255</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.RAM_To" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>RAM_From</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">255</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
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+        <spirit:name>Interrupt</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt_Address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_IADDR_SIZE&apos;)) - 1)">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+      <spirit:port>
+        <spirit:name>Interrupt_Ack</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">1</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt_Ack" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 0))">true</xilinx:isEnabled>
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+        <spirit:name>Ext_BRK</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:name>Ext_NM_BRK</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>Byte_Enable</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        <spirit:name>M_AXI_DP_AWADDR</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_AWADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_WVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_CRRESP</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_CRREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_CDVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>M_AXI_IC_CDDATA</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_CDDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_CDLAST</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>M_AXI_IC_CDREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DC_AWID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_AWADDR</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+        <spirit:name>M_AXI_DC_BUSER</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_WACK</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_WACK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARLEN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARSIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARBURST</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARBURST" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARLOCK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARCACHE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DC_ARPROT</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARPROT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_ARQOS</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARQOS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_ARVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_ARREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DC_ARUSER</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_CDREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_SCO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SCO">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREQ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CONFIG_RESET" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK_IRQ</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region for interrupt input</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK_DEBUG</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region in debug module</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_DBG_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Dbg_Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_DBG_TRACE_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Dbg_Trace_Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_TOLERANT</spirit:name>
+        <spirit:displayName>Enable Fault Tolerance Support</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_TOLERANT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_USE_CE_EXCEPTION</spirit:name>
+        <spirit:displayName>Correctable Error Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_USE_CE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCKSTEP_SLAVE</spirit:name>
+        <spirit:displayName>Lockstep Slave</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKSTEP_SLAVE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCKSTEP_MASTER</spirit:name>
+        <spirit:displayName>Lockstep Master</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKSTEP_MASTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ENDIANNESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENDIANNESS" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DATA_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_SIZE" spirit:choiceRef="choice_list_99ba8646">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DATA_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_LMB_DATA_SIZE">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INSTR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_INSTR_SIZE">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_INSTANCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INSTANCE">bd_ba6a_microblaze_I_0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AVOID_PRIMITIVES" spirit:choiceRef="choice_pairs_22d9f392">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AREA_OPTIMIZED</spirit:name>
+        <spirit:displayName>Select implementation optimization</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AREA_OPTIMIZED" spirit:choiceRef="choice_pairs_3eb333f8">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPTIMIZATION</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Bus Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_ff364cce">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASE_VECTORS</spirit:name>
+        <spirit:displayName>Vector Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASE_VECTORS" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_DATA_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_EXCLUSIVE_ACCESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_EXCLUSIVE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_D_BUS_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Data-side AXI Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_D_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_D_BUS_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_DATA_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_I_BUS_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Instruction-side AXI Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_I_BUS_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_LMB</spirit:name>
+        <spirit:displayName>Enable Local Memory Bus Data Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_LMB" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>Local Memory Bus Data Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_AXI</spirit:name>
+        <spirit:displayName>Enable Peripheral AXI Data Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_AXI" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_LMB</spirit:name>
+        <spirit:displayName>Enable Local Memory Bus Instruction Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_LMB" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>Local Memory Bus Instruction Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_AXI</spirit:name>
+        <spirit:displayName>Enable Peripheral AXI Instruction Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_AXI" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>G_TEMPLATE_LIST</spirit:name>
+        <spirit:displayName>Select Configuration</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.G_TEMPLATE_LIST" spirit:choiceRef="choice_pairs_7dd2834f">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_MSR_INSTR</spirit:name>
+        <spirit:displayName>Enable Additional Machine Status Register Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MSR_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PCMP_INSTR</spirit:name>
+        <spirit:displayName>Enable Pattern Comparator</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PCMP_INSTR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_BARREL</spirit:name>
+        <spirit:displayName>Enable Barrel Shifter</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BARREL" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DIV</spirit:name>
+        <spirit:displayName>Enable Integer Divider</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DIV" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_HW_MUL</spirit:name>
+        <spirit:displayName>Enable Integer Multiplier</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_HW_MUL" spirit:choiceRef="choice_pairs_1075faf2">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FPU</spirit:name>
+        <spirit:displayName>Enable Floating Point Unit</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FPU" spirit:choiceRef="choice_pairs_7bfd418d">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_REORDER_INSTR</spirit:name>
+        <spirit:displayName>Enable Reversed Load/Store and Swap Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_REORDER_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UNALIGNED_EXCEPTIONS</spirit:name>
+        <spirit:displayName>Enable Unaligned Data Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UNALIGNED_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ILL_OPCODE_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Illegal Instruction Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ILL_OPCODE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIV_ZERO_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Integer Divide Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIV_ZERO_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DIV_ZERO_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DIV&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FPU_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Floating Point Unit Exceptions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FPU_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FPU_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FPU&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FSL_LINKS</spirit:name>
+        <spirit:displayName>Number of Stream Links</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FSL_LINKS" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXTENDED_FSL_INSTR</spirit:name>
+        <spirit:displayName>Enable Additional Stream Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXTENDED_FSL_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FSL_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Stream Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FSL_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FSL_EXCEPTION" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_EXTENDED_FSL_INSTR&apos;)) > 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_STACK_PROTECTION</spirit:name>
+        <spirit:displayName>Enable stack protection</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STACK_PROTECTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_STACK_PROTECTION" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) = 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) = 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPRECISE_EXCEPTIONS</spirit:name>
+        <spirit:displayName>Allow Imprecise Exceptions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPRECISE_EXCEPTIONS" spirit:choiceRef="choice_pairs_2058dc69">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INTERRUPT" spirit:choiceRef="choice_pairs_db57ca32">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXT_BRK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXT_BRK" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXT_NM_BRK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXT_NM_BRK" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_NON_SECURE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_NON_SECURE" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_MMU</spirit:name>
+        <spirit:displayName>Memory Management</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MMU" spirit:choiceRef="choice_pairs_0000a26c">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_MMU" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_DTLB_SIZE</spirit:name>
+        <spirit:displayName>Data Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_DTLB_SIZE" spirit:choiceRef="choice_list_dd2843c6">4</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_DTLB_SIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_ITLB_SIZE</spirit:name>
+        <spirit:displayName>Instruction Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_ITLB_SIZE" spirit:choiceRef="choice_list_dd2843c6">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_ITLB_SIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_TLB_ACCESS</spirit:name>
+        <spirit:displayName>Enable Access to Memory Management Special Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_TLB_ACCESS" spirit:choiceRef="choice_pairs_7ad6afc0">3</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_TLB_ACCESS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_ZONES</spirit:name>
+        <spirit:displayName>Number of Memory Protection Zones</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_ZONES" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">16</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_ZONES" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_PRIVILEGED_INSTR</spirit:name>
+        <spirit:displayName>Privileged Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_PRIVILEGED_INSTR" spirit:choiceRef="choice_pairs_443ae6cc">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_PRIVILEGED_INSTR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_BRANCH_TARGET_CACHE</spirit:name>
+        <spirit:displayName>Enable Branch Target Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRANCH_TARGET_CACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_BRANCH_TARGET_CACHE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRANCH_TARGET_CACHE_SIZE</spirit:name>
+        <spirit:displayName>Branch Target Cache Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRANCH_TARGET_CACHE_SIZE" spirit:choiceRef="choice_pairs_e7a1eb81">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_BRANCH_TARGET_CACHE_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PC_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PC_WIDTH" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PVR</spirit:name>
+        <spirit:displayName>Specifies Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR" spirit:choiceRef="choice_pairs_5ab38e91">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 7)">
+        <spirit:name>C_PVR_USER1</spirit:name>
+        <spirit:displayName>Specify USER1 Bits in Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR_USER1" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 31)">
+        <spirit:name>C_PVR_USER2</spirit:name>
+        <spirit:displayName>Specify USER2 Bits in Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR_USER2" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DYNAMIC_BUS_SIZING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DYNAMIC_BUS_SIZING">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 31)">
+        <spirit:name>C_RESET_MSR</spirit:name>
+        <spirit:displayName>Specify Reset Value for Select MSR Bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_MSR" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPCODE_0x0_ILLEGAL</spirit:name>
+        <spirit:displayName>Generate Illegal Instruction Exception for NULL Instruction</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPCODE_0x0_ILLEGAL" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_ENABLED</spirit:name>
+        <spirit:displayName>MicroBlaze Debug Module Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_ENABLED" spirit:choiceRef="choice_pairs_7bfd418d">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_INTERFACE</spirit:name>
+        <spirit:displayName>MicroBlaze Debug Connection</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_INTERFACE" spirit:choiceRef="choice_pairs_56d5ba32">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_PC_BRK</spirit:name>
+        <spirit:displayName>Number of PC Breakpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_PC_BRK" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_RD_ADDR_BRK</spirit:name>
+        <spirit:displayName>Number of Read Address Watchpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_WR_ADDR_BRK</spirit:name>
+        <spirit:displayName>Number of Write Address Watchpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_EVENT_COUNTERS</spirit:name>
+        <spirit:displayName>Number of Performance Monitor Event Counters</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_EVENT_COUNTERS" spirit:minimum="0" spirit:maximum="48" spirit:rangeType="long">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_LATENCY_COUNTERS</spirit:name>
+        <spirit:displayName>Number of Performance Monitor Latency Counters</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_LATENCY_COUNTERS" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Performance Monitor Counter Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_COUNTER_WIDTH" spirit:choiceRef="choice_list_b1aff63c">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_TRACE_SIZE</spirit:name>
+        <spirit:displayName>Trace Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_TRACE_SIZE" spirit:choiceRef="choice_pairs_13d40c7c">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_EXTERNAL_TRACE</spirit:name>
+        <spirit:displayName>External Trace</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_TRACE_ASYNC_RESET</spirit:name>
+        <spirit:displayName>Use Asynchrnous Reset for External Trace</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_TRACE_ASYNC_RESET" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_PROFILE_SIZE</spirit:name>
+        <spirit:displayName>Profile Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_PROFILE_SIZE" spirit:choiceRef="choice_pairs_5b1842a1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERRUPT_IS_EDGE</spirit:name>
+        <spirit:displayName>Sense Interrupt on Edge vs. Level</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERRUPT_IS_EDGE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EDGE_IS_POSITIVE</spirit:name>
+        <spirit:displayName>Sense Interrupt on Rising vs. Falling Edge</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EDGE_IS_POSITIVE" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ASYNC_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ASYNC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ASYNC_WAKEUP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ASYNC_WAKEUP" spirit:choiceRef="choice_list_6e3ded9c">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M0_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M0_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S0_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S0_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M1_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M1_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S1_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S1_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M2_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M2_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S2_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S2_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M3_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M3_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S3_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S3_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M4_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M4_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S4_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S4_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M5_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M5_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S5_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S5_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M6_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M6_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S6_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S6_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M7_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M7_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S7_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S7_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M8_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M8_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S8_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S8_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M9_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M9_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S9_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S9_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M10_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M10_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S10_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S10_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M11_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M11_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S11_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S11_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M12_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M12_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S12_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S12_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M13_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M13_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S13_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S13_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M14_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M14_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S14_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S14_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M15_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M15_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S15_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S15_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ICACHE_BASEADDR</spirit:name>
+        <spirit:displayName>Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ICACHE_HIGHADDR</spirit:name>
+        <spirit:displayName>High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_HIGHADDR" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ICACHE</spirit:name>
+        <spirit:displayName>Enable Instruction Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ICACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ALLOW_ICACHE_WR</spirit:name>
+        <spirit:displayName>Enable Writes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALLOW_ICACHE_WR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ADDR_TAG_BITS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDR_TAG_BITS" spirit:minimum="0" spirit:maximum="26" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CACHE_BYTE_SIZE</spirit:name>
+        <spirit:displayName>Size in Bytes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_LINE_LEN</spirit:name>
+        <spirit:displayName>Line Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_ALWAYS_USED</spirit:name>
+        <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_STREAMS</spirit:name>
+        <spirit:displayName>Number of Streams</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_STREAMS" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_STREAMS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_VICTIMS</spirit:name>
+        <spirit:displayName>Number of Victims</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_VICTIMS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_FORCE_TAG_LUTRAM</spirit:name>
+        <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_FORCE_TAG_LUTRAM" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CACHE_BYTE_SIZE&apos;)) &lt;= (2048 * spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;))))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_DATA_WIDTH" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_TOLERANT&apos;)) = 0)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CACHE_BYTE_SIZE&apos;)) > ((2048 * spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;))) - 1)))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_USER_VALUE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_USER_VALUE" spirit:minimum="0" spirit:maximum="31" spirit:rangeType="long">31</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_USER_VALUE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_AWUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_AWUSER_WIDTH">5</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_AWUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_ARUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_ARUSER_WIDTH">5</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_ARUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_WUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_WUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_RUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_RUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_RUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_BUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_BUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_BUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_DCACHE_BASEADDR</spirit:name>
+        <spirit:displayName>Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_DCACHE_HIGHADDR</spirit:name>
+        <spirit:displayName>High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_HIGHADDR" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DCACHE</spirit:name>
+        <spirit:displayName>Enable Data Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DCACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ALLOW_DCACHE_WR</spirit:name>
+        <spirit:displayName>Enable Writes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALLOW_DCACHE_WR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_ADDR_TAG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_ADDR_TAG" spirit:minimum="0" spirit:maximum="58" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_BYTE_SIZE</spirit:name>
+        <spirit:displayName>Size in Bytes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_LINE_LEN</spirit:name>
+        <spirit:displayName>Line Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_ALWAYS_USED</spirit:name>
+        <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_USE_WRITEBACK</spirit:name>
+        <spirit:displayName>Enable Write-back Storage Policy</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DCACHE_USE_WRITEBACK" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_TOLERANT&apos;)) = 0">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DCACHE_VICTIMS</spirit:name>
+        <spirit:displayName>Number of Victims</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DCACHE_VICTIMS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>C_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FREQ" spirit:order="1130" spirit:configGroups="1 NoDisplay">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FREQ">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DATA_SIZE</spirit:name>
+      <spirit:displayName>Select Processor Implementation</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_SIZE" spirit:choiceRef="choice_list_99ba8646" spirit:order="1160" spirit:configGroups="1 Instructions">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DATA_SIZE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ADDR_SIZE</spirit:name>
+      <spirit:displayName>Select Extended Addressing</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_SIZE" spirit:choiceRef="choice_pairs_c471ed24" spirit:order="1165" spirit:configGroups="1 Instructions">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ADDR_SIZE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DYNAMIC_BUS_SIZING</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DYNAMIC_BUS_SIZING" spirit:order="1220" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DYNAMIC_BUS_SIZING">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PC_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PC_WIDTH" spirit:order="1200" spirit:configGroups="1 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PC_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INSTANCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="1140" spirit:configGroups="1 NoDisplay">mb_microblaze_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INSTANCE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AVOID_PRIMITIVES" spirit:order="1170" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_AVOID_PRIMITIVES">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_TOLERANT</spirit:name>
+      <spirit:displayName>Enable Fault Tolerance Support</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_TOLERANT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1110" spirit:configGroups="1 Fault Tolerance">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_TOLERANT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_USE_CE_EXCEPTION</spirit:name>
+      <spirit:displayName>Correctable Error Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_USE_CE_EXCEPTION" spirit:order="1150" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_USE_CE_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LOCKSTEP_SLAVE</spirit:name>
+      <spirit:displayName>Lockstep Slave</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LOCKSTEP_SLAVE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1230" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LOCKSTEP_SLAVE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ENDIANNESS</spirit:name>
+      <spirit:displayName>Endianness</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ENDIANNESS" spirit:order="1235" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ENDIANNESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AREA_OPTIMIZED</spirit:name>
+      <spirit:displayName>Select implementation optimization</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AREA_OPTIMIZED" spirit:choiceRef="choice_pairs_3eb333f8" spirit:order="1080" spirit:configGroups="1 Optimization">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_AREA_OPTIMIZED">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPTIMIZATION</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPTIMIZATION" spirit:order="1180" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_OPTIMIZATION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Bus Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_ff364cce" spirit:order="2036" spirit:configGroups="8 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_BASE_VECTORS</spirit:name>
+      <spirit:displayName>Vector Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASE_VECTORS" spirit:order="1190" spirit:configGroups="1 NoDisplay" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASE_VECTORS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CONFIG_RESET" spirit:order="1210" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CONFIG_RESET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK" spirit:order="1220" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK_IRQ</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region for interrupt input</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ" spirit:order="1230" spirit:configGroups="1 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK_IRQ">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK_DEBUG</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region in debug module</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG" spirit:order="1240" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK_DEBUG">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_DBG_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Dbg_Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK" spirit:order="1250" spirit:configGroups="1 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_DBG_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_DBG_TRACE_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Dbg_Trace_Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK" spirit:order="1260" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_DBG_TRACE_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_THREAD_ID_WIDTH" spirit:order="8120" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_DATA_WIDTH" spirit:order="8130" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH" spirit:order="8140" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_EXCLUSIVE_ACCESS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS" spirit:order="8150" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_EXCLUSIVE_ACCESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_AXI</spirit:name>
+      <spirit:displayName>Enable Peripheral AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_AXI" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8030" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DP_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Peripheral AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DP_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8032" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DP_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DC_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Cache AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DC_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8034" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DC_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB</spirit:name>
+      <spirit:displayName>Enable Local Memory Bus Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8050" spirit:configGroups="8 Buses">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>Local Memory Bus Data Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="8052" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Local Memory Bus Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8055" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH" spirit:order="8200" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_DATA_WIDTH" spirit:order="8210" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH" spirit:order="8220" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_AXI</spirit:name>
+      <spirit:displayName>Enable Peripheral AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_AXI" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8060" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IP_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Peripheral AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IP_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8062" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IP_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IC_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Cache AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IC_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8064" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IC_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB</spirit:name>
+      <spirit:displayName>Enable Local Memory Bus Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8080" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>Local Memory Bus Instruction Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="8082" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Local Memory Bus Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8085" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_TRACE</spirit:name>
+      <spirit:displayName>Enable Trace Bus Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8090" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_TRACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LOCKSTEP_SELECT</spirit:name>
+      <spirit:displayName>Lockstep Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LOCKSTEP_SELECT" spirit:choiceRef="choice_pairs_75c71b2b" spirit:order="8100" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LOCKSTEP_SELECT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ENABLE_DISCRETE_PORTS</spirit:name>
+      <spirit:displayName>Enable Discrete Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ENABLE_DISCRETE_PORTS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8470" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ENABLE_DISCRETE_PORTS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_USER_SIGNALS</spirit:name>
+      <spirit:displayName>Enable M_AXI_DC User Signals</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8370" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_USER_SIGNALS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_USER_SIGNALS</spirit:name>
+      <spirit:displayName>Enable M_AXI_IC User Signals</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8460" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_USER_SIGNALS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>G_TEMPLATE_LIST</spirit:name>
+      <spirit:displayName>Select Configuration</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_TEMPLATE_LIST" spirit:choiceRef="choice_pairs_7dd2834f" spirit:order="10" spirit:configGroups="9 GUI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.G_TEMPLATE_LIST">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>G_USE_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Enable Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_USE_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="50" spirit:configGroups="9 GUI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.G_USE_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_MSR_INSTR</spirit:name>
+      <spirit:displayName>Enable Additional Machine Status Register Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_MSR_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1040" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_MSR_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PCMP_INSTR</spirit:name>
+      <spirit:displayName>Enable Pattern Comparator</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PCMP_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1050" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_PCMP_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_REORDER_INSTR</spirit:name>
+      <spirit:displayName>Enable Reversed Load/Store and Swap Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_REORDER_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1060" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_REORDER_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_BARREL</spirit:name>
+      <spirit:displayName>Enable Barrel Shifter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_BARREL" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1000" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_BARREL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_DIV</spirit:name>
+      <spirit:displayName>Enable Integer Divider</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_DIV" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1030" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_DIV">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_HW_MUL</spirit:name>
+      <spirit:displayName>Enable Integer Multiplier</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_HW_MUL" spirit:choiceRef="choice_pairs_1075faf2" spirit:order="1020" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_HW_MUL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FPU</spirit:name>
+      <spirit:displayName>Enable Floating Point Unit</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FPU" spirit:choiceRef="choice_pairs_7bfd418d" spirit:order="1010" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_FPU">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UNALIGNED_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Enable Unaligned Data Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UNALIGNED_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2090" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UNALIGNED_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ILL_OPCODE_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Illegal Instruction Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ILL_OPCODE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2060" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ILL_OPCODE_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_I_BUS_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Instruction-side AXI Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2040" spirit:configGroups="2 Bus Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_I_BUS_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_D_BUS_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Data-side AXI Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_D_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2050" spirit:configGroups="2 Bus Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_D_BUS_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DIV_ZERO_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Integer Divide Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DIV_ZERO_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 Math Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DIV_ZERO_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FPU_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Floating Point Unit Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FPU_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2010" spirit:configGroups="2 Math Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FPU_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FSL_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Stream Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FSL_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8008" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FSL_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_STACK_PROTECTION</spirit:name>
+      <spirit:displayName>Enable stack protection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_STACK_PROTECTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4004" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_STACK_PROTECTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IMPRECISE_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Allow Imprecise Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IMPRECISE_EXCEPTIONS" spirit:choiceRef="choice_pairs_2058dc69" spirit:order="2090" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IMPRECISE_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR</spirit:name>
+      <spirit:displayName>Specifies Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR" spirit:choiceRef="choice_pairs_5ab38e91" spirit:order="7000" spirit:configGroups="7 Processor Version Registers">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR_USER1</spirit:name>
+      <spirit:displayName>Specify USER1 Bits in Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR_USER1" spirit:order="7100" spirit:configGroups="7 Processor Version Registers" spirit:bitStringLength="8">0x00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR_USER1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR_USER2</spirit:name>
+      <spirit:displayName>Specify USER2 Bits in Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR_USER2" spirit:order="7200" spirit:configGroups="7 Processor Version Registers" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR_USER2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_ENABLED</spirit:name>
+      <spirit:displayName>MicroBlaze Debug Module Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_ENABLED" spirit:choiceRef="choice_pairs_7bfd418d" spirit:order="5000" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_ENABLED">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_INTERFACE</spirit:name>
+      <spirit:displayName>MicroBlaze Debug Connection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_INTERFACE" spirit:choiceRef="choice_pairs_56d5ba32" spirit:order="5010" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_INTERFACE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_PC_BRK</spirit:name>
+      <spirit:displayName>Number of PC Breakpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_PC_BRK" spirit:order="5100" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_PC_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_RD_ADDR_BRK</spirit:name>
+      <spirit:displayName>Number of Read Address Watchpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK" spirit:order="5300" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_RD_ADDR_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_WR_ADDR_BRK</spirit:name>
+      <spirit:displayName>Number of Write Address Watchpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK" spirit:order="5200" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_WR_ADDR_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_EVENT_COUNTERS</spirit:name>
+      <spirit:displayName>Number of Performance Monitor Event Counters</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_EVENT_COUNTERS" spirit:order="5400" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="48" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_EVENT_COUNTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_LATENCY_COUNTERS</spirit:name>
+      <spirit:displayName>Number of Performance Monitor Latency Counters</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_LATENCY_COUNTERS" spirit:order="5500" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_LATENCY_COUNTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Performance Monitor Counter Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_COUNTER_WIDTH" spirit:choiceRef="choice_list_b1aff63c" spirit:order="5600" spirit:configGroups="5 Hardware Breakpoints">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_TRACE_SIZE</spirit:name>
+      <spirit:displayName>Trace Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_TRACE_SIZE" spirit:choiceRef="choice_pairs_126baff7" spirit:order="5700" spirit:configGroups="5 Hardware Breakpoints">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_TRACE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_EXTERNAL_TRACE</spirit:name>
+      <spirit:displayName>External Trace</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5650" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_EXTERNAL_TRACE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_TRACE_ASYNC_RESET</spirit:name>
+      <spirit:displayName>Use Asynchrnous Reset for External Trace</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_TRACE_ASYNC_RESET" spirit:order="5655" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_TRACE_ASYNC_RESET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_PROFILE_SIZE</spirit:name>
+      <spirit:displayName>Profile Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_PROFILE_SIZE" spirit:choiceRef="choice_pairs_5b1842a1" spirit:order="5800" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_PROFILE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERRUPT_IS_EDGE</spirit:name>
+      <spirit:displayName>Sense Interrupt on Edge vs. Level</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERRUPT_IS_EDGE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6000" spirit:configGroups="6 Interrupt">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERRUPT_IS_EDGE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EDGE_IS_POSITIVE</spirit:name>
+      <spirit:displayName>Sense Interrupt on Rising vs. Falling Edge</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EDGE_IS_POSITIVE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 Interrupt">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_EDGE_IS_POSITIVE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ASYNC_INTERRUPT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ASYNC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703" spirit:order="6600" spirit:configGroups="6 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ASYNC_INTERRUPT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ASYNC_WAKEUP</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ASYNC_WAKEUP" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="6650" spirit:configGroups="6 NoDisplay">3</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ASYNC_WAKEUP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_IE</spirit:name>
+      <spirit:displayName>IE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_IE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6201" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_IE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_BIP</spirit:name>
+      <spirit:displayName>BIP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_BIP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6202" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_BIP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_ICE</spirit:name>
+      <spirit:displayName>ICE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_ICE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6203" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_ICE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_DCE</spirit:name>
+      <spirit:displayName>DCE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_DCE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6204" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_DCE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_EE</spirit:name>
+      <spirit:displayName>EE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_EE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6205" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_EE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_EIP</spirit:name>
+      <spirit:displayName>EIP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_EIP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6206" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_EIP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPCODE_0x0_ILLEGAL</spirit:name>
+      <spirit:displayName>Generate Illegal Instruction Exception for NULL Instruction</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPCODE_0x0_ILLEGAL" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2070" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_OPCODE_0x0_ILLEGAL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FSL_LINKS</spirit:name>
+      <spirit:displayName>Number of Stream Links</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FSL_LINKS" spirit:order="8000" spirit:configGroups="8 NoDisplay" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FSL_LINKS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_EXTENDED_FSL_INSTR</spirit:name>
+      <spirit:displayName>Enable Additional Stream Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_EXTENDED_FSL_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8004" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_EXTENDED_FSL_INSTR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M0_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M0_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8520" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M0_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S0_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S0_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8530" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S0_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M1_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M1_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8560" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M1_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S1_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S1_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8570" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S1_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M2_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M2_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8600" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M2_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S2_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S2_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8610" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S2_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M3_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M3_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8640" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M3_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S3_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S3_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8650" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S3_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M4_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M4_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8680" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M4_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S4_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S4_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8690" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S4_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M5_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M5_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8720" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M5_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S5_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S5_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8730" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S5_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M6_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M6_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8760" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M6_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S6_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S6_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8770" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S6_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M7_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M7_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8800" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M7_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S7_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S7_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8810" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S7_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M8_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M8_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8840" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M8_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S8_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S8_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8850" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S8_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M9_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M9_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8880" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M9_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S9_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S9_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8890" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S9_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M10_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M10_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8920" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M10_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S10_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S10_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8930" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S10_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M11_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M11_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8960" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M11_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S11_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S11_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8970" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S11_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M12_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M12_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9000" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M12_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S12_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S12_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9010" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S12_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M13_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M13_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9040" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M13_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S13_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S13_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9050" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S13_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M14_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M14_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9080" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M14_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S14_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S14_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9090" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S14_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M15_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M15_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9120" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M15_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S15_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S15_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9130" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S15_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M0_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M0_AXIS_DATA_WIDTH" spirit:order="8500" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M0_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S0_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S0_AXIS_DATA_WIDTH" spirit:order="8510" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S0_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M1_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M1_AXIS_DATA_WIDTH" spirit:order="8540" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M1_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S1_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S1_AXIS_DATA_WIDTH" spirit:order="8550" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S1_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M2_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M2_AXIS_DATA_WIDTH" spirit:order="8580" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M2_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S2_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S2_AXIS_DATA_WIDTH" spirit:order="8590" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S2_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M3_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M3_AXIS_DATA_WIDTH" spirit:order="8620" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M3_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S3_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S3_AXIS_DATA_WIDTH" spirit:order="8630" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S3_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M4_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M4_AXIS_DATA_WIDTH" spirit:order="8660" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M4_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S4_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S4_AXIS_DATA_WIDTH" spirit:order="8670" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S4_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M5_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M5_AXIS_DATA_WIDTH" spirit:order="8700" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M5_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S5_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S5_AXIS_DATA_WIDTH" spirit:order="8710" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S5_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M6_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M6_AXIS_DATA_WIDTH" spirit:order="8740" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M6_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S6_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S6_AXIS_DATA_WIDTH" spirit:order="8750" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S6_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M7_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M7_AXIS_DATA_WIDTH" spirit:order="8780" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M7_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S7_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S7_AXIS_DATA_WIDTH" spirit:order="8790" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S7_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M8_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M8_AXIS_DATA_WIDTH" spirit:order="8820" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M8_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S8_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S8_AXIS_DATA_WIDTH" spirit:order="8830" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S8_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M9_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M9_AXIS_DATA_WIDTH" spirit:order="8860" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M9_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S9_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S9_AXIS_DATA_WIDTH" spirit:order="8870" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S9_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M10_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M10_AXIS_DATA_WIDTH" spirit:order="8900" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M10_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S10_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S10_AXIS_DATA_WIDTH" spirit:order="8910" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S10_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M11_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M11_AXIS_DATA_WIDTH" spirit:order="8940" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M11_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S11_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S11_AXIS_DATA_WIDTH" spirit:order="8950" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S11_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M12_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M12_AXIS_DATA_WIDTH" spirit:order="8980" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M12_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S12_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S12_AXIS_DATA_WIDTH" spirit:order="8990" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S12_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M13_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M13_AXIS_DATA_WIDTH" spirit:order="9020" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M13_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S13_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S13_AXIS_DATA_WIDTH" spirit:order="9030" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S13_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M14_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M14_AXIS_DATA_WIDTH" spirit:order="9060" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M14_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S14_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S14_AXIS_DATA_WIDTH" spirit:order="9070" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S14_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M15_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M15_AXIS_DATA_WIDTH" spirit:order="9100" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M15_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S15_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S15_AXIS_DATA_WIDTH" spirit:order="9110" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S15_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_BASEADDR</spirit:name>
+      <spirit:displayName>Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_BASEADDR" spirit:order="3040" spirit:configGroups="3 Instruction Cache Feature" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_HIGHADDR</spirit:name>
+      <spirit:displayName>High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_HIGHADDR" spirit:order="3030" spirit:configGroups="3 Instruction Cache Feature" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_ICACHE</spirit:name>
+      <spirit:displayName>Enable Instruction Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_ICACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3000" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_ICACHE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ALLOW_ICACHE_WR</spirit:name>
+      <spirit:displayName>Enable Writes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALLOW_ICACHE_WR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3050" spirit:configGroups="3 Instruction Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ALLOW_ICACHE_WR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ADDR_TAG_BITS</spirit:name>
+      <spirit:displayName>Set number of I-cache address tag bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_TAG_BITS" spirit:order="3200" spirit:configGroups="3 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ADDR_TAG_BITS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CACHE_BYTE_SIZE</spirit:name>
+      <spirit:displayName>Size in Bytes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448" spirit:order="3010" spirit:configGroups="3 Instruction Cache Feature">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CACHE_BYTE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_LINE_LEN</spirit:name>
+      <spirit:displayName>Line Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf" spirit:order="3020" spirit:configGroups="3 Instruction Cache Feature">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_LINE_LEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_ALWAYS_USED</spirit:name>
+      <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3060" spirit:configGroups="3 Instruction Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_ALWAYS_USED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_VICTIMS</spirit:name>
+      <spirit:displayName>Number of Victims</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab" spirit:order="3090" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_VICTIMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_STREAMS</spirit:name>
+      <spirit:displayName>Number of Streams</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_STREAMS" spirit:choiceRef="choice_list_8af5a703" spirit:order="3080" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_STREAMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_FORCE_TAG_LUTRAM</spirit:name>
+      <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3070" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_FORCE_TAG_LUTRAM">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9" spirit:order="3220" spirit:configGroups="3 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_THREAD_ID_WIDTH" spirit:order="8380" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH" spirit:order="8390" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_AWUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_AWUSER_WIDTH" spirit:order="8400" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_AWUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_ARUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_ARUSER_WIDTH" spirit:order="8410" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_ARUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_WUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH" spirit:order="8420" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_WUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_RUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_RUSER_WIDTH" spirit:order="8430" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_RUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_BUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_BUSER_WIDTH" spirit:order="8440" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_BUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_USER_VALUE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_USER_VALUE" spirit:order="8450" spirit:configGroups="8 NoDisplay">31</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_USER_VALUE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_BASEADDR</spirit:name>
+      <spirit:displayName>Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_BASEADDR" spirit:order="3140" spirit:configGroups="3 Data Cache Feature" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_HIGHADDR</spirit:name>
+      <spirit:displayName>High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_HIGHADDR" spirit:order="3130" spirit:configGroups="3 Data Cache Feature" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_DCACHE</spirit:name>
+      <spirit:displayName>Enable Data Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_DCACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3100" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_DCACHE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ALLOW_DCACHE_WR</spirit:name>
+      <spirit:displayName>Enable Writes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALLOW_DCACHE_WR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3150" spirit:configGroups="3 Data Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ALLOW_DCACHE_WR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_ADDR_TAG</spirit:name>
+      <spirit:displayName>Set number of D-cache address tag bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_ADDR_TAG" spirit:order="3230" spirit:configGroups="3 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_ADDR_TAG">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_BYTE_SIZE</spirit:name>
+      <spirit:displayName>Size in Bytes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448" spirit:order="3110" spirit:configGroups="3 Data Cache Feature">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_BYTE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_LINE_LEN</spirit:name>
+      <spirit:displayName>Line Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf" spirit:order="3120" spirit:configGroups="3 Data Cache Feature">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_LINE_LEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_ALWAYS_USED</spirit:name>
+      <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3160" spirit:configGroups="3 Data Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_ALWAYS_USED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_USE_WRITEBACK</spirit:name>
+      <spirit:displayName>Enable Write-back Storage Policy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_USE_WRITEBACK" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3180" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_USE_WRITEBACK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_VICTIMS</spirit:name>
+      <spirit:displayName>Number of Victims</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab" spirit:order="3190" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_VICTIMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_FORCE_TAG_LUTRAM</spirit:name>
+      <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3170" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_FORCE_TAG_LUTRAM">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9" spirit:order="3250" spirit:configGroups="3 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_THREAD_ID_WIDTH" spirit:order="8280" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH" spirit:order="8290" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_AWUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_AWUSER_WIDTH" spirit:order="8300" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_AWUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_ARUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_ARUSER_WIDTH" spirit:order="8310" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_ARUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_WUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_WUSER_WIDTH" spirit:order="8320" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_WUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_RUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_RUSER_WIDTH" spirit:order="8330" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_RUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_BUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_BUSER_WIDTH" spirit:order="8340" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_BUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_EXCLUSIVE_ACCESS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS" spirit:order="8350" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_EXCLUSIVE_ACCESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_USER_VALUE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_USER_VALUE" spirit:order="8360" spirit:configGroups="8 NoDisplay">31</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_USER_VALUE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_MMU</spirit:name>
+      <spirit:displayName>Memory Management</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_MMU" spirit:choiceRef="choice_pairs_0000a26c" spirit:order="4000" spirit:configGroups="4 Memory Management Unit">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_MMU">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MMU_DTLB_SIZE</spirit:name>
+      <spirit:displayName>Data Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_DTLB_SIZE" spirit:choiceRef="choice_list_dd2843c6" spirit:order="4100" spirit:configGroups="4 Memory Management Unit">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MMU_DTLB_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MMU_ITLB_SIZE</spirit:name>
+      <spirit:displayName>Instruction Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_ITLB_SIZE" spirit:choiceRef="choice_list_dd2843c6" spirit:order="4200" spirit:configGroups="4 Memory Management Unit">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MMU_ITLB_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
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+      <spirit:name>C_MMU_PRIVILEGED_INSTR</spirit:name>
+      <spirit:displayName>Privileged Instructions</spirit:displayName>
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+      <spirit:displayName>Use Interrupt</spirit:displayName>
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+      <spirit:displayName>Use Monitor Interface for Interrupt</spirit:displayName>
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+      <spirit:name>C_USE_NON_SECURE</spirit:name>
+      <spirit:displayName>Use Non-Secure AXI access permission</spirit:displayName>
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+      <spirit:displayName>Enable Branch Target Cache</spirit:displayName>
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+      <spirit:displayName>Branch Target Cache Size</spirit:displayName>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_microblaze_I_0</spirit:value>
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+      <xilinx:displayName>MicroBlaze</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EDGE_IS_POSITIVE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_BRK" xilinx:valueSource="user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_NON_SECURE" xilinx:valueSource="propagated"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR" xilinx:valueSource="user"/>
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+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cf8c578c"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="33347ad3"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci
new file mode 100644
index 0000000..97c4643
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xci
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:library>xci</spirit:library>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;slowest_sync_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ext_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;aux_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mb_debug_sys_rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dcm_locked&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mb_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;bus_struct_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;peripheral_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;interconnect_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;peripheral_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;clock&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;mb_reset:bus_struct_re
+set:interconnect_aresetn:peripheral_aresetn:peripheral_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;slowest_sync_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ext_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:res
+et:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;ext_reset_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;aux_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;aux_reset_in&quot;,&quot;ph
+ysical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;dbg_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;mb_debug_sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;mb_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissi
+on&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;mb_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;bus_struct_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;bus_struct_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;interconnect_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_perm
+ission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;interconnect_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;peripheral_high_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;peripheral_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,
+&quot;logical_right&quot;:&quot;0&quot;}}},&quot;peripheral_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;peripheral_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml
new file mode 100644
index 0000000..f9728f9
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/bd_ba6a_rst_0_0.xml
@@ -0,0 +1,691 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_rst_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>clock</spirit:name>
+      <spirit:displayName>Clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>slowest_sync_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
+          <spirit:description>Slowest Synchronous clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ext_reset</spirit:name>
+      <spirit:displayName>Ext_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>aux_reset</spirit:name>
+      <spirit:displayName>aux_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aux_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>dbg_reset</spirit:name>
+      <spirit:displayName>DBG_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>mb_debug_sys_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>mb_rst</spirit:name>
+      <spirit:displayName>MB_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mb_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>bus_struct_reset</spirit:name>
+      <spirit:displayName>bus_struct_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>bus_struct_reset</spirit:name>
+          </spirit:physicalPort>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interconnect_low_rst</spirit:name>
+      <spirit:displayName>interconnect_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interconnect_aresetn</spirit:name>
+          </spirit:physicalPort>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>peripheral_high_rst</spirit:name>
+      <spirit:displayName>peripheral_high_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>peripheral_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>peripheral_low_rst</spirit:name>
+      <spirit:displayName>peripheral_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>peripheral_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>slowest_sync_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_reset_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>aux_reset_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mb_debug_sys_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dcm_locked</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mb_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>bus_struct_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_BUS_RST&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>peripheral_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_RST&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>interconnect_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>peripheral_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_ARESETN&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+        <spirit:displayName>Ext Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+        <spirit:displayName>Aux Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+        <spirit:displayName>Aux Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_BUS_RST</spirit:name>
+        <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_RST</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+        <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_caf95c77</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>resetn</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Processor Reset System</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+      <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_RST</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_BUS_RST</spirit:name>
+      <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+      <spirit:displayName>Aux Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+      <spirit:displayName>Ext Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+      <spirit:displayName>Aux Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+      <spirit:displayName>Ext Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_rst_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_caf95c77" spirit:order="3">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Processor System Reset</xilinx:displayName>
+      <xilinx:coreRevision>13</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci
new file mode 100644
index 0000000..9dacbc7
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xci
@@ -0,0 +1,309 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
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+      <spirit:instanceName>bd_ba6a_iomodule_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="iomodule" spirit:version="3.1"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO1_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO2_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO3_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPO4_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x000000008000FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">iomodule</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS">0x0000000000000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_NUM_SYNC_FF">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_POSITIVE">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_USE_EXT_INTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IO_BASEADDR">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IO_HIGHADDR">0x00000000FFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IO_MASK">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PIT4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TMR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_BAUDRATE">9600</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_DATA_BITS">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_ERROR_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_ODD_PARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_PROG_BAUDRATE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_RX_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_TX_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UART_USE_PARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_FIT4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPI4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_GPO4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_IO_BUS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PIT4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TMR_DISABLE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_UART_RX">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_UART_TX">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_ba6a_iomodule_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO3_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_HAS_FAST" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_INTR_SIZE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_LEVEL_EDGE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_POSITIVE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_IO_BUS" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Addr_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Read_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Write_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Address&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Write_Data&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Read_Data&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LM
+B_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_s
+rc&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,
+&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;Rst:TMR_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{
+&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.TMR_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;IO_BUS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mcsio_bus:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mcsio_bus_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Addr_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;IO_Address&quot;,&quot;phy
+sical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;IO_Byte_Enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_Read_Data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Read_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IO_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_Write_Data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Write_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml
new file mode 100644
index 0000000..545119a
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/bd_ba6a_iomodule_0_0.xml
@@ -0,0 +1,8812 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_iomodule_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.CLK</spirit:name>
+      <spirit:displayName>Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF">SLMB</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET">Rst:TMR_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Clk frequency</spirit:displayName>
+          <spirit:description>Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.Rst</spirit:name>
+      <spirit:displayName>Rst</spirit:displayName>
+      <spirit:description>Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
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+      <spirit:displayName>UART_Interrupt</spirit:displayName>
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+          <spirit:vendorExtensions>
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+      <spirit:displayName>FIT1_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>FIT1_Interrupt</spirit:name>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+          <spirit:vendorExtensions>
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+      <spirit:displayName>FIT2_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>FIT2_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+          <spirit:name>PortWidth</spirit:name>
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+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:displayName>FIT3_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>FIT3_Interrupt</spirit:name>
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+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <xilinx:enablement>
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+      <spirit:name>INTERRUPT.FIT4_Interrupt</spirit:name>
+      <spirit:displayName>FIT4_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+            <spirit:name>FIT4_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <xilinx:enablement>
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+      <spirit:displayName>PIT1_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>PIT1_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT1_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:displayName>PIT2_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+            <spirit:name>PIT2_Interrupt</spirit:name>
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+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT2_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
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+      <spirit:name>INTERRUPT.PIT3_Interrupt</spirit:name>
+      <spirit:displayName>PIT3_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>INTERRUPT</spirit:name>
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+            <spirit:name>PIT3_Interrupt</spirit:name>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT3_INTERRUPT.PortWidth">1</spirit:value>
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+      <spirit:name>INTERRUPT.PIT4_Interrupt</spirit:name>
+      <spirit:displayName>PIT4_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+            <spirit:name>PIT4_Interrupt</spirit:name>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.PIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI1_Interrupt</spirit:name>
+      <spirit:displayName>GPI1_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI1_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI2_Interrupt</spirit:name>
+      <spirit:displayName>GPI2_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI2_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI3_Interrupt</spirit:name>
+      <spirit:displayName>GPI3_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI3_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI4_Interrupt</spirit:name>
+      <spirit:displayName>GPI4_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI4_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Interrupt</spirit:name>
+      <spirit:displayName>INTC_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Interrupt" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Irq_Single</spirit:name>
+      <spirit:displayName>INTC_IRQ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Irq_Single" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Irq</spirit:name>
+      <spirit:displayName>INTC_IRQ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Processor_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTC_IRQ.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_IRQ.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Irq" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTC_Irq_Out</spirit:name>
+      <spirit:displayName>INTC_IRQ_OUT</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ_OUT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTC_Irq_Out" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_USE_IRQ_OUT&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART</spirit:name>
+      <spirit:displayName>UART</spirit:displayName>
+      <spirit:description>UART TX/RX</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RxD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TxD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART.BOARD.ASSOCIATED_PARAM">UART_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART_CLK.CLK</spirit:name>
+      <spirit:displayName>UART_Clk</spirit:displayName>
+      <spirit:description>Asynchronous UART Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.ASSOCIATED_BUSIF">SLMB</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.ASSOCIATED_RESET">UART_Rst:TMR_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>UART Clk frequency</spirit:displayName>
+          <spirit:description>UART Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART_CLK.CLK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART_RST.Rst</spirit:name>
+      <spirit:displayName>UART_Rst</spirit:displayName>
+      <spirit:description>Asynchronous UART Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART_RST.Rst" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO1</spirit:name>
+      <spirit:displayName>GPIO1</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO1</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_USE_GPO1" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_USE_GPO1" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO1_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPO1_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPO1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO1_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPO1_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPO1_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI1</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_USE_GPI1" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_USE_GPI1" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI1_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPI1_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPI1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPI1_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPI1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO1.BOARD.ASSOCIATED_PARAM">GPIO1_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO2</spirit:name>
+      <spirit:displayName>GPIO2</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO2</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_USE_GPO2" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_USE_GPO2" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO2_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPO2_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPO2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO2_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPO2_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPO2_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI2</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_USE_GPI2" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_USE_GPI2" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI2_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPI2_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPI2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPI2_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPI2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO2.BOARD.ASSOCIATED_PARAM">GPIO2_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO3</spirit:name>
+      <spirit:displayName>GPIO3</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO3</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_USE_GPO3" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_USE_GPO3" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO3_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPO3_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPO3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO3_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPO3_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPO3_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI3</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_USE_GPI3" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_USE_GPI3" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI3_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPI3_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPI3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPI3_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPI3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO3.BOARD.ASSOCIATED_PARAM">GPIO3_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO4</spirit:name>
+      <spirit:displayName>GPIO4</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO4</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_USE_GPO4" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_USE_GPO4" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO4_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPO4_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPO4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO4_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPO4_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPO4_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI4</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_USE_GPI4" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_USE_GPI4" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI4_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPI4_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPI4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPI4_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPI4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO4.BOARD.ASSOCIATED_PARAM">GPIO4_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>LMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="2048" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.REG.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.REG.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>UART_RX</spirit:name>
+          <spirit:displayName>UART Receive Data Register</spirit:displayName>
+          <spirit:description>UART Receive Data Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>Receive Data</spirit:displayName>
+            <spirit:description>Data received by the UART.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_RX" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_TX</spirit:name>
+          <spirit:displayName>UART Transmit Data Register</spirit:displayName>
+          <spirit:description>UART Transmit Data Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>Transmit Data</spirit:displayName>
+            <spirit:description>Data to be transmitted by the UART.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_TX" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_Status</spirit:name>
+          <spirit:displayName>UART Status Register</spirit:displayName>
+          <spirit:description>UART Status Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Rx_Valid_Data</spirit:name>
+            <spirit:displayName>Rx Valid Data</spirit:displayName>
+            <spirit:description>Indicates if the receive register has valid data:
+  0 - Receive register is empty.
+  1 - Receive register has valid data.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Tx_Used</spirit:name>
+            <spirit:displayName>Tx Used</spirit:displayName>
+            <spirit:description>Indicates if the transmit register is in use:
+  0 - Transmit register is not in use.
+  1 - Transmit register is in use.
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Overrun_Error</spirit:name>
+            <spirit:displayName>Overrun Error</spirit:displayName>
+            <spirit:description>Indicates that an overrun error has occurred:
+  0 - No overrun has occurred.
+  1 - An overrun has occurred.
+</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Frame_Error</spirit:name>
+            <spirit:displayName>Frame Error</spirit:displayName>
+            <spirit:description>Indicates that an frame error has occurred:
+  0 - No frame error has occurred.
+  1 - A frame error has occurred.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Parity_Error</spirit:name>
+            <spirit:displayName>Parity Error</spirit:displayName>
+            <spirit:description>Indicates that a parity error has occurred:
+  0 - No parity error has occurred.
+  1 - A parity error occurred.
+</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_MODE</spirit:name>
+          <spirit:displayName>Interrupt Mode Register</spirit:displayName>
+          <spirit:description>Interrupt Mode Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Mode</spirit:name>
+            <spirit:displayName>IRQ Mode</spirit:displayName>
+            <spirit:description>Interrupt Mode.
+For each bit:
+  W - When written with 1 the corresponding interrupt will use fast mode.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_MODE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_1</spirit:name>
+          <spirit:displayName>General Purpose Output 1 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 1 Register</spirit:description>
+          <spirit:addressOffset>0x10</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_2</spirit:name>
+          <spirit:displayName>General Purpose Output 2 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 2 Register</spirit:description>
+          <spirit:addressOffset>0x14</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_3</spirit:name>
+          <spirit:displayName>General Purpose Output 3 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 3 Register</spirit:description>
+          <spirit:addressOffset>0x18</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_4</spirit:name>
+          <spirit:displayName>General Purpose Output 4 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 4 Register</spirit:description>
+          <spirit:addressOffset>0x1C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_1</spirit:name>
+          <spirit:displayName>General Purpose Input 1 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 1 Register</spirit:description>
+          <spirit:addressOffset>0x20</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_2</spirit:name>
+          <spirit:displayName>General Purpose Input 2 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 2 Register</spirit:description>
+          <spirit:addressOffset>0x24</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_3</spirit:name>
+          <spirit:displayName>General Purpose Input 3 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 3 Register</spirit:description>
+          <spirit:addressOffset>0x28</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_4</spirit:name>
+          <spirit:displayName>General Purpose Input 4 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 4 Register</spirit:description>
+          <spirit:addressOffset>0x2C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_STATUS</spirit:name>
+          <spirit:displayName>Interrupt Status Register</spirit:displayName>
+          <spirit:description>Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>0x30</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 lapsed.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 lapsed.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 lapsed.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 lapsed.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 strobe.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 strobe.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 strobe.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 strobe.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 changed.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 changed.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 changed.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 changed.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>External interrupt input signal</spirit:displayName>
+            <spirit:description>Interrupt Status Register.
+For each bit:
+  R - Reads active interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_STATUS" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_PENDING</spirit:name>
+          <spirit:displayName>Interrupt Pending Register</spirit:displayName>
+          <spirit:description>Interrupt Pending Register</spirit:description>
+          <spirit:addressOffset>0x34</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 lapsed.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 lapsed.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 lapsed.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 lapsed.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 strobe.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 strobe.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 strobe.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 strobe.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 changed.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 changed.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 changed.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 changed.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>Enabled interrupt events that have occurred</spirit:displayName>
+            <spirit:description>Interrupt Pending.
+For each bit:
+  R - Reads enabled interrupt event that has occurred.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_PENDING" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_ENABLE</spirit:name>
+          <spirit:displayName>Interrupt Enable Register</spirit:displayName>
+          <spirit:description>Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x38</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt enabled.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>Enable external interrupt input signals</spirit:displayName>
+            <spirit:description>Interrupt Enable.
+For each bit:
+  W - Enable external interrupt input signal.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_ENABLE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_ACK</spirit:name>
+          <spirit:displayName>Interrupt Acknowledge Register</spirit:displayName>
+          <spirit:description>Interrupt Acknowledge Register</spirit:description>
+          <spirit:addressOffset>0x3C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Acknowledge</spirit:name>
+            <spirit:displayName>IRQ Acknowledge</spirit:displayName>
+            <spirit:description>Interrupt Acknowledge.
+For each bit:
+  W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_ACK" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 1 Preload Register</spirit:displayName>
+          <spirit:description>PIT 1 Preload Register</spirit:description>
+          <spirit:addressOffset>0x40</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT1_Preload</spirit:name>
+            <spirit:displayName>PIT1 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_COUNTER</spirit:name>
+          <spirit:displayName>PIT 1 Counter Register</spirit:displayName>
+          <spirit:description>PIT 1 Counter Register</spirit:description>
+          <spirit:addressOffset>0x44</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT1_Counter</spirit:name>
+            <spirit:displayName>PIT1 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_CONTROL</spirit:name>
+          <spirit:displayName>PIT 1 Control Register</spirit:displayName>
+          <spirit:description>PIT 1 Control Register</spirit:description>
+          <spirit:addressOffset>0x48</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT1_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_BAUD</spirit:name>
+          <spirit:displayName>UART Programmable Baud Rate</spirit:displayName>
+          <spirit:description>UART Programmable Baud Rate</spirit:description>
+          <spirit:addressOffset>0x4C</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_BAUD</spirit:name>
+            <spirit:displayName>Baud Rate</spirit:displayName>
+            <spirit:description>Programmable UART Baud Rate.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">20</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_BAUD" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_PROG_BAUDRATE&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 2 Preload Register</spirit:displayName>
+          <spirit:description>PIT 2 Preload Register</spirit:description>
+          <spirit:addressOffset>0x50</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT2_Preload</spirit:name>
+            <spirit:displayName>PIT2 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_COUNTER</spirit:name>
+          <spirit:displayName>PIT 2 Counter Register</spirit:displayName>
+          <spirit:description>PIT 2 Counter Register</spirit:description>
+          <spirit:addressOffset>0x54</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT2_Counter</spirit:name>
+            <spirit:displayName>PIT2 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_CONTROL</spirit:name>
+          <spirit:displayName>PIT 2 Control Register</spirit:displayName>
+          <spirit:description>PIT 2 Control Register</spirit:description>
+          <spirit:addressOffset>0x58</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT2_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 3 Preload Register</spirit:displayName>
+          <spirit:description>PIT 3 Preload Register</spirit:description>
+          <spirit:addressOffset>0x60</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT3_Preload</spirit:name>
+            <spirit:displayName>PIT3 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_COUNTER</spirit:name>
+          <spirit:displayName>PIT 3 Counter Register</spirit:displayName>
+          <spirit:description>PIT 3 Counter Register</spirit:description>
+          <spirit:addressOffset>0x64</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT3_Counter</spirit:name>
+            <spirit:displayName>PIT3 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_CONTROL</spirit:name>
+          <spirit:displayName>PIT 3 Control Register</spirit:displayName>
+          <spirit:description>PIT 3 Control Register</spirit:description>
+          <spirit:addressOffset>0x68</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT3_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 4 Preload Register</spirit:displayName>
+          <spirit:description>PIT 4 Preload Register</spirit:description>
+          <spirit:addressOffset>0x70</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT4_Preload</spirit:name>
+            <spirit:displayName>PIT4 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_COUNTER</spirit:name>
+          <spirit:displayName>PIT 4 Counter Register</spirit:displayName>
+          <spirit:description>PIT 4 Counter Register</spirit:description>
+          <spirit:addressOffset>0x74</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT4_Counter</spirit:name>
+            <spirit:displayName>PIT4 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_CONTROL</spirit:name>
+          <spirit:displayName>PIT 4 Control Register</spirit:displayName>
+          <spirit:description>PIT 4 Control Register</spirit:description>
+          <spirit:addressOffset>0x78</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT4_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_0</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 0</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 0</spirit:description>
+          <spirit:addressOffset>0x80</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 0 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_1</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 1</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 1</spirit:description>
+          <spirit:addressOffset>0x84</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 1 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_2</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 2</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 2</spirit:description>
+          <spirit:addressOffset>0x88</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 2 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_3</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 3</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 3</spirit:description>
+          <spirit:addressOffset>0x8C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 3 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_4</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 4</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 4</spirit:description>
+          <spirit:addressOffset>0x90</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 4 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_5</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 5</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 5</spirit:description>
+          <spirit:addressOffset>0x94</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 5 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_6</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 6</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 6</spirit:description>
+          <spirit:addressOffset>0x98</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 6 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_7</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 7</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 7</spirit:description>
+          <spirit:addressOffset>0x9C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 7 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_8</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 8</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 8</spirit:description>
+          <spirit:addressOffset>0xA0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 8 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_9</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 9</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 9</spirit:description>
+          <spirit:addressOffset>0xA4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 9 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_10</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 10</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 10</spirit:description>
+          <spirit:addressOffset>0xA8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 10 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_11</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 11</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 11</spirit:description>
+          <spirit:addressOffset>0xAC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 11 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_12</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 12</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 12</spirit:description>
+          <spirit:addressOffset>0xB0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 12 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_13</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 13</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 13</spirit:description>
+          <spirit:addressOffset>0xB4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 13 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_14</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 14</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 14</spirit:description>
+          <spirit:addressOffset>0xB8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 14 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_14" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_16</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 16</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 16</spirit:description>
+          <spirit:addressOffset>0xC0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 16 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_16" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_17</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 17</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 17</spirit:description>
+          <spirit:addressOffset>0xC4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 17 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_17" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 2)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_18</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 18</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 18</spirit:description>
+          <spirit:addressOffset>0xC8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 18 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_18" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 3)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_19</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 19</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 19</spirit:description>
+          <spirit:addressOffset>0xCC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 19 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_19" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 4)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_20</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 20</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 20</spirit:description>
+          <spirit:addressOffset>0xD0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 20 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_20" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 5)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_21</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 21</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 21</spirit:description>
+          <spirit:addressOffset>0xD4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 21 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_21" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 6)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_22</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 22</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 22</spirit:description>
+          <spirit:addressOffset>0xD8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 22 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_22" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 7)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_23</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 23</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 23</spirit:description>
+          <spirit:addressOffset>0xDC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 23 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_23" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 8)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_24</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 24</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 24</spirit:description>
+          <spirit:addressOffset>0xE0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 24 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_24" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 9)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_25</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 25</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 25</spirit:description>
+          <spirit:addressOffset>0xE4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 25 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_25" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 10)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_26</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 26</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 26</spirit:description>
+          <spirit:addressOffset>0xE8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 26 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_26" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 11)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_27</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 27</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 27</spirit:description>
+          <spirit:addressOffset>0xEC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 27 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_27" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 12)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_28</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 28</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 28</spirit:description>
+          <spirit:addressOffset>0xF0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 28 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_28" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 13)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_29</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 29</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 29</spirit:description>
+          <spirit:addressOffset>0xF4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 29 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_29" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 14)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_30</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 30</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 30</spirit:description>
+          <spirit:addressOffset>0xF8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 30 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_30" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 15)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_31</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 31</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 31</spirit:description>
+          <spirit:addressOffset>0xFC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 31 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_31" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 16)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_0</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 0</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 0</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 0 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_1</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 1</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 1</spirit:description>
+          <spirit:addressOffset>0x108</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 1 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_2</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 2</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 2</spirit:description>
+          <spirit:addressOffset>0x110</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 2 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_3</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 3</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 3</spirit:description>
+          <spirit:addressOffset>0x118</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 3 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_4</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 4</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 4</spirit:description>
+          <spirit:addressOffset>0x120</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 4 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_5</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 5</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 5</spirit:description>
+          <spirit:addressOffset>0x128</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 5 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_6</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 6</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 6</spirit:description>
+          <spirit:addressOffset>0x130</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 6 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_7</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 7</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 7</spirit:description>
+          <spirit:addressOffset>0x138</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 7 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_8</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 8</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 8</spirit:description>
+          <spirit:addressOffset>0x140</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 8 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_9</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 9</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 9</spirit:description>
+          <spirit:addressOffset>0x148</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 9 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_10</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 10</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 10</spirit:description>
+          <spirit:addressOffset>0x150</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 10 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_11</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 11</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 11</spirit:description>
+          <spirit:addressOffset>0x158</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 11 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_12</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 12</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 12</spirit:description>
+          <spirit:addressOffset>0x160</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 12 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_13</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 13</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 13</spirit:description>
+          <spirit:addressOffset>0x168</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 13 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_14</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 14</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 14</spirit:description>
+          <spirit:addressOffset>0x170</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 14 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_14" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_16</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 16</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 16</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 16 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_16" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_17</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 17</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 17</spirit:description>
+          <spirit:addressOffset>0x188</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 17 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_17" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 2)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_18</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 18</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 18</spirit:description>
+          <spirit:addressOffset>0x190</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 18 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_18" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 3)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_19</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 19</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 19</spirit:description>
+          <spirit:addressOffset>0x198</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 19 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_19" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 4)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_20</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 20</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 20</spirit:description>
+          <spirit:addressOffset>0x1A0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 20 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_20" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 5)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_21</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 21</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 21</spirit:description>
+          <spirit:addressOffset>0x1A8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 21 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_21" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 6)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_22</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 22</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 22</spirit:description>
+          <spirit:addressOffset>0x1B0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 22 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_22" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 7)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_23</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 23</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 23</spirit:description>
+          <spirit:addressOffset>0x1B8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 23 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_23" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 8)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_24</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 24</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 24</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 24 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_24" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 9)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_25</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 25</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 25</spirit:description>
+          <spirit:addressOffset>0x1C8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 25 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_25" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 10)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_26</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 26</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 26</spirit:description>
+          <spirit:addressOffset>0x1D0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 26 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_26" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 11)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_27</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 27</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 27</spirit:description>
+          <spirit:addressOffset>0x1D8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 27 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_27" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 12)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_28</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 28</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 28</spirit:description>
+          <spirit:addressOffset>0x1E0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 28 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_28" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 13)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_29</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 29</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 29</spirit:description>
+          <spirit:addressOffset>0x1E8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 29 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_29" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 14)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_30</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 30</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 30</spirit:description>
+          <spirit:addressOffset>0x1F0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 30 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_30" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 15)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_31</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 31</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 31</spirit:description>
+          <spirit:addressOffset>0x1F8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 31 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>IO_Read_Strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>IO_Write_Strobe</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Write_Strobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Byte_Enable" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:displayName>Serial Data In</spirit:displayName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UART_Rx" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT1_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT1_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT2_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT2_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>FIT3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT3_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT3_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT4_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT4_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT4_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT3_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT3_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT4_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        <spirit:name>PIT4_Interrupt</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
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+        <spirit:name>PIT4_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>GPO1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPO1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPO2</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI4</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI4_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Interrupt</spirit:name>
+        <spirit:displayName>Interrupt Inputs</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Interrupt" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_IRQ</spirit:name>
+        <spirit:displayName>Interrupt Request Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Processor_Ack</spirit:name>
+        <spirit:displayName>Interrupt Acknowledgement Input</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Processor_Ack" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Interrupt_Address</spirit:name>
+        <spirit:displayName>Interrupt Vector Address Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(( ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) + 31) / 64) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) - 32) + 32) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Interrupt_Address" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_IRQ_OUT</spirit:name>
+        <spirit:displayName>Interrupt Request Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_IRQ_OUT" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_USE_IRQ_OUT&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREQ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_INSTANCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INSTANCE">iomodule</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AVOID_PRIMITIVES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TMR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TMR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_TMR_DISABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_TMR_DISABLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000008000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_HIGHADDR" spirit:bitStringLength="64">0x00000000FFFFFFFF</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_HIGHADDR" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_BASEADDR" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_BASEADDR" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_MASK</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_MASK" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_MASK" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_IO_BUS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_IO_BUS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_UART_RX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_UART_RX">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_UART_TX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_UART_TX">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_BAUDRATE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_BAUDRATE">9600</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_BAUDRATE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_DATA_BITS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_DATA_BITS" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_DATA_BITS" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_USE_PARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_USE_PARITY">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_USE_PARITY" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ODD_PARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ODD_PARITY">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_ODD_PARITY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_USE_PARITY&apos;)) >= 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_RX_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_RX_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_RX_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_TX_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_TX_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_TX_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ERROR_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_ERROR_INTERRUPT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_PROG_BAUDRATE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_PROG_BAUDRATE">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_PROG_BAUDRATE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_FREQ" spirit:minimum="0" spirit:rangeType="long">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ASYNC</spirit:name>
+        <spirit:displayName>Asynchronous Clock</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ASYNC" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_NUM_SYNC_FF</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_NUM_SYNC_FF" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT1_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT1_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT1_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT1_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT2_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT2_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT2_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT2_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT3_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT3_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT3_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT3_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT4_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT4_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT4_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT4_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO1_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO1_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO1_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO2_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO2_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO2_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO3_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO3_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO3_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO4_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO4_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO4_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI1_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI2_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI3_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI4_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_USE_EXT_INTR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_USE_EXT_INTR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_INTR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_INTR_SIZE" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_INTR_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_LEVEL_EDGE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_LEVEL_EDGE" spirit:bitStringLength="16">0x0000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_LEVEL_EDGE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_POSITIVE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_POSITIVE" spirit:bitStringLength="16">0xFFFF</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_POSITIVE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_HAS_FAST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_HAS_FAST" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_ADDR_WIDTH" spirit:minimum="5" spirit:maximum="64" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_INTC_BASE_VECTORS</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_BASE_VECTORS" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_ASYNC_INTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_ASYNC_INTR" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_NUM_SYNC_FF</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_NUM_SYNC_FF" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0739ee39</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>rs232_uart</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_38e5a9f1</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>dip_switches_4bits</spirit:enumeration>
+      <spirit:enumeration>led_3bits</spirit:enumeration>
+      <spirit:enumeration>qsfp0_lowspeed</spirit:enumeration>
+      <spirit:enumeration>qsfp1_lowspeed</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8af5a703</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f585525a</spirit:name>
+      <spirit:enumeration>110</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>1200</spirit:enumeration>
+      <spirit:enumeration>2400</spirit:enumeration>
+      <spirit:enumeration>4800</spirit:enumeration>
+      <spirit:enumeration>9600</spirit:enumeration>
+      <spirit:enumeration>19200</spirit:enumeration>
+      <spirit:enumeration>38400</spirit:enumeration>
+      <spirit:enumeration>57600</spirit:enumeration>
+      <spirit:enumeration>115200</spirit:enumeration>
+      <spirit:enumeration>128000</spirit:enumeration>
+      <spirit:enumeration>230400</spirit:enumeration>
+      <spirit:enumeration>460800</spirit:enumeration>
+      <spirit:enumeration>921600</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_007f01e9</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4847022f</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_5f1e379e</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_7ba91213</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Both Edges">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Rising Edge">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="Falling Edge">3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_d4609148</spirit:name>
+      <spirit:enumeration spirit:text="Bus">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f0f6eb36</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ffa336e4</spirit:name>
+      <spirit:enumeration spirit:text="Even">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Odd">1</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>LMB module which includes plenty of I/O peripherals</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CONFIG_RESET" spirit:order="1110" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AVOID_PRIMITIVES" spirit:order="1120" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_TMR</spirit:name>
+      <spirit:displayName>Use Triple Modular Redundancy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TMR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1125" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_TMR_DISABLE</spirit:name>
+      <spirit:displayName>Activate TMR Disable Input</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_TMR_DISABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1128" spirit:configGroups="1 System">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_TMR_DISABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FREQ" spirit:order="1090" spirit:configGroups="1 System">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INSTANCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="1100" spirit:configGroups="1 System">iomodule</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_BASE_VECTORS</spirit:name>
+      <spirit:displayName>MicroBlaze Relocatable Base Vector Value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_BASE_VECTORS" spirit:order="1130" spirit:configGroups="1 NoDisplay" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>I/O Module Register Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1000" spirit:configGroups="1 System" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>I/O Module Register High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1010" spirit:configGroups="1 System" spirit:bitStringLength="64">0x000000008000FFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>I/O Module Register Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1020" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_IO_BUS</spirit:name>
+      <spirit:displayName>Enable IO Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_IO_BUS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1030" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_BASEADDR</spirit:name>
+      <spirit:displayName>I/O Module IO Bus Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_BASEADDR" spirit:order="1040" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_BASEADDR" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_HIGHADDR</spirit:name>
+      <spirit:displayName>I/O Module IO Bus High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_HIGHADDR" spirit:order="1050" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000FFFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_HIGHADDR" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_MASK</spirit:name>
+      <spirit:displayName>I/O Module IO Bus Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_MASK" spirit:order="1060" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_MASK" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1070" spirit:configGroups="1 System" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1080" spirit:configGroups="1 System">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1085" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_UART_RX</spirit:name>
+      <spirit:displayName>Enable Receiver</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_UART_RX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 UART">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_UART_TX</spirit:name>
+      <spirit:displayName>Enable Transmitter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_UART_TX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100" spirit:configGroups="2 UART">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_BAUDRATE</spirit:name>
+      <spirit:displayName>Define Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_BAUDRATE" spirit:choiceRef="choice_list_f585525a" spirit:order="2200" spirit:configGroups="2 UART">9600</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_BAUDRATE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_PROG_BAUDRATE</spirit:name>
+      <spirit:displayName>Programmable Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_PROG_BAUDRATE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_PROG_BAUDRATE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_DATA_BITS</spirit:name>
+      <spirit:displayName>Number of Data Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_DATA_BITS" spirit:order="2400" spirit:configGroups="2 UART" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_DATA_BITS" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_USE_PARITY</spirit:name>
+      <spirit:displayName>Use Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_USE_PARITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_USE_PARITY" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_ODD_PARITY</spirit:name>
+      <spirit:displayName>Even or Odd Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_ODD_PARITY" spirit:choiceRef="choice_pairs_ffa336e4" spirit:order="2600" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_ODD_PARITY" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_RX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Receive Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_RX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2700" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_RX_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_TX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Transmit Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_TX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2800" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_TX_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_ERROR_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Error Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_ERROR_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2900" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_ERROR_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT1</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3010" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT1_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT1_No_CLOCKS" spirit:order="3020" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT1_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3030" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT2</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3040" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT2_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT2_No_CLOCKS" spirit:order="3050" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT2_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3060" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT3</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3070" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT3_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT3_No_CLOCKS" spirit:order="3080" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT3_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3090" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT4</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3100" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT4_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT4_No_CLOCKS" spirit:order="3110" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT4_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3120" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT1</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4010" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_SIZE" spirit:order="4020" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4030" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_PRESCALER" spirit:choiceRef="choice_pairs_f0f6eb36" spirit:order="4040" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4050" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT2</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4060" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_SIZE" spirit:order="4070" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4080" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_PRESCALER" spirit:choiceRef="choice_pairs_007f01e9" spirit:order="4090" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4100" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT3</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4110" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_SIZE" spirit:order="4120" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4130" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_PRESCALER" spirit:choiceRef="choice_pairs_4847022f" spirit:order="4140" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4150" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT4</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4160" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_SIZE" spirit:order="4170" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4180" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_PRESCALER" spirit:choiceRef="choice_pairs_5f1e379e" spirit:order="4190" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4200" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO1</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5010" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO1_SIZE" spirit:order="5020" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO1_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO1_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO1_INIT" spirit:order="5030" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO1_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO2</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5040" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO2_SIZE" spirit:order="5050" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO2_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO2_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO2_INIT" spirit:order="5060" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO2_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO3</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5070" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO3_SIZE" spirit:order="5080" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO3_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO3_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO3_INIT" spirit:order="5090" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO3_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO4</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5100" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO4_SIZE" spirit:order="5110" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO4_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO4_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO4_INIT" spirit:order="5120" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO4_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI1</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6010" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI1_SIZE" spirit:order="6020" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI1_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI1_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6030" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI1_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI2</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6040" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI2_SIZE" spirit:order="6050" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI2_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI2_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6060" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI2_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI3</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6070" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI3_SIZE" spirit:order="6080" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI3_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI3_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6090" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI3_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI4</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI4_SIZE" spirit:order="6110" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI4_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI4_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6120" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI4_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_HAS_FAST</spirit:name>
+      <spirit:displayName>Use Low-latency Interrupt Handling</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_HAS_FAST" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7100" spirit:configGroups="7 Interrupt">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_USE_EXT_INTR</spirit:name>
+      <spirit:displayName>Use External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_USE_EXT_INTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7200" spirit:configGroups="7 Interrupt">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_USE_IRQ_OUT</spirit:name>
+      <spirit:displayName>Use Separate Interrupt Output</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_USE_IRQ_OUT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7250" spirit:configGroups="7 Interrupt">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_IRQ_CONNECTION</spirit:name>
+      <spirit:displayName>Interrupt Output Connection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_IRQ_CONNECTION" spirit:choiceRef="choice_pairs_d4609148" spirit:order="7280">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_IRQ_CONNECTION" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_INTR_SIZE</spirit:name>
+      <spirit:displayName>Number of External Inputs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_INTR_SIZE" spirit:order="7300" spirit:configGroups="7 Interrupt" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_INTR_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_LEVEL_EDGE</spirit:name>
+      <spirit:displayName>Level or Edge of External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_LEVEL_EDGE" spirit:order="7400" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0x0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_LEVEL_EDGE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_POSITIVE</spirit:name>
+      <spirit:displayName>Positive or Negative External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_POSITIVE" spirit:order="7500" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_POSITIVE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Interrupt Address Width</spirit:displayName>
+      <spirit:description>Interrupt address width with Fast Mode Interrupt.</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_ADDR_WIDTH" spirit:order="7600" spirit:configGroups="7 Interrupt" spirit:minimum="5" spirit:maximum="64" spirit:rangeType="long">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_ADDR_WIDTH" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_ASYNC_INTR</spirit:name>
+      <spirit:displayName>Interrupts asynchronous</spirit:displayName>
+      <spirit:description>The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous.</spirit:description>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_ASYNC_INTR" spirit:order="7700" spirit:bitStringLength="16">0xFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_NUM_SYNC_FF</spirit:name>
+      <spirit:displayName>Number of synchronization flip-flops</spirit:displayName>
+      <spirit:description>Number of synchronization flip-flops used to synchronize asynchronous interupt inputs</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_NUM_SYNC_FF" spirit:order="7800" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_iomodule_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="100" spirit:configGroups="0 Board">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO1_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="110" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO2_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="120" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO3_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO3_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="130" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO4_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="140" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:choiceRef="choice_list_0739ee39" spirit:order="150" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>IOModule</xilinx:displayName>
+      <xilinx:coreRevision>6</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_HAS_FAST" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_INTR_SIZE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_LEVEL_EDGE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_POSITIVE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_IO_BUS" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3e38f1f1"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="00000000"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="08f03615"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="8aacb230"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="53aec875"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="4fae1825"/>
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+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci
new file mode 100644
index 0000000..a5df74b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xci
@@ -0,0 +1,159 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_v10" spirit:version="3.0"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_ba6a_ilmb_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;SYS_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;63&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;1&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;}},&quot;interfaces&quot;:{&quot;LMB_Sl_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_W
+IDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_
+rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBU
+S&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;63&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_M&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb
+:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredMaster&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_ONLY&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;M_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;M_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;LMB_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;
+,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;LMB_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;LMB_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;LMB_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;M_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;M_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;SYS_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[
+{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.SYS_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;SYS_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml
new file mode 100644
index 0000000..fd650dd
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/bd_ba6a_ilmb_0.xml
@@ -0,0 +1,3532 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_ilmb_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_0</spirit:name>
+      <spirit:displayName>LMB_Sl_00</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">31</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_0" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_1</spirit:name>
+      <spirit:displayName>LMB_Sl_01</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">32</spirit:left>
+              <spirit:right spirit:format="long">63</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_2</spirit:name>
+      <spirit:displayName>LMB_Sl_02</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">64</spirit:left>
+              <spirit:right spirit:format="long">95</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_3</spirit:name>
+      <spirit:displayName>LMB_Sl_03</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">96</spirit:left>
+              <spirit:right spirit:format="long">127</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_4</spirit:name>
+      <spirit:displayName>LMB_Sl_04</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">128</spirit:left>
+              <spirit:right spirit:format="long">159</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_5</spirit:name>
+      <spirit:displayName>LMB_Sl_05</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">160</spirit:left>
+              <spirit:right spirit:format="long">191</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_6</spirit:name>
+      <spirit:displayName>LMB_Sl_06</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">192</spirit:left>
+              <spirit:right spirit:format="long">223</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_6" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_7</spirit:name>
+      <spirit:displayName>LMB_Sl_07</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">224</spirit:left>
+              <spirit:right spirit:format="long">255</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_7" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_8</spirit:name>
+      <spirit:displayName>LMB_Sl_08</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">256</spirit:left>
+              <spirit:right spirit:format="long">287</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_8" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_9</spirit:name>
+      <spirit:displayName>LMB_Sl_09</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">288</spirit:left>
+              <spirit:right spirit:format="long">319</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_10</spirit:name>
+      <spirit:displayName>LMB_Sl_10</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">320</spirit:left>
+              <spirit:right spirit:format="long">351</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_10" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_11</spirit:name>
+      <spirit:displayName>LMB_Sl_11</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">352</spirit:left>
+              <spirit:right spirit:format="long">383</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_11" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_12</spirit:name>
+      <spirit:displayName>LMB_Sl_12</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">384</spirit:left>
+              <spirit:right spirit:format="long">415</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_13</spirit:name>
+      <spirit:displayName>LMB_Sl_13</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">416</spirit:left>
+              <spirit:right spirit:format="long">447</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_14</spirit:name>
+      <spirit:displayName>LMB_Sl_14</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">448</spirit:left>
+              <spirit:right spirit:format="long">479</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_14" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_15</spirit:name>
+      <spirit:displayName>LMB_Sl_15</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">480</spirit:left>
+              <spirit:right spirit:format="long">511</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_15" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_M</spirit:name>
+      <spirit:displayName>LMB_M</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Master interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredMaster/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">SYS_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.SYS_Rst</spirit:name>
+      <spirit:displayName>SYS_Rst</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>SYS_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:channels>
+    <spirit:channel>
+      <spirit:name>LMB_Channel</spirit:name>
+      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_0</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_2</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
+    </spirit:channel>
+  </spirit:channels>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>SYS_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;))) - 1)">63</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">1</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:wire>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:wire>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
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+        <spirit:wire>
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+        <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
+        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Awidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>C Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
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+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
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+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
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+  <spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
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+      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
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+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Awidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1300" spirit:configGroups="1 LMB" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_ilmb_0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci
new file mode 100644
index 0000000..9d1dda8
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xci
@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_ba6a_dlmb_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;SYS_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;95&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;2&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;}},&quot;interfaces&quot;:{&quot;LMB_Sl_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_W
+IDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_
+rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBU
+S&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;63&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_2&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:
+lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right
+&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;64&quot;,&quot;physical_right&quot;:&quot;95&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_r
+ight&quot;:&quot;0&quot;}}},&quot;LMB_M&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredMaster&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;M_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;M_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_
+name&quot;:&quot;LMB_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;LMB_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;LMB_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;LMB_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;M_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;M_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;SYS_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permiss
+ion&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.SYS_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;SYS_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml
new file mode 100644
index 0000000..ae40117
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/bd_ba6a_dlmb_0.xml
@@ -0,0 +1,3536 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_dlmb_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_0</spirit:name>
+      <spirit:displayName>LMB_Sl_00</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">31</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_0" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_1</spirit:name>
+      <spirit:displayName>LMB_Sl_01</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">32</spirit:left>
+              <spirit:right spirit:format="long">63</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_2</spirit:name>
+      <spirit:displayName>LMB_Sl_02</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">64</spirit:left>
+              <spirit:right spirit:format="long">95</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_3</spirit:name>
+      <spirit:displayName>LMB_Sl_03</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">96</spirit:left>
+              <spirit:right spirit:format="long">127</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_4</spirit:name>
+      <spirit:displayName>LMB_Sl_04</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">128</spirit:left>
+              <spirit:right spirit:format="long">159</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_5</spirit:name>
+      <spirit:displayName>LMB_Sl_05</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">160</spirit:left>
+              <spirit:right spirit:format="long">191</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_6</spirit:name>
+      <spirit:displayName>LMB_Sl_06</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">192</spirit:left>
+              <spirit:right spirit:format="long">223</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_6" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_7</spirit:name>
+      <spirit:displayName>LMB_Sl_07</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">224</spirit:left>
+              <spirit:right spirit:format="long">255</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_7" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_8</spirit:name>
+      <spirit:displayName>LMB_Sl_08</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">256</spirit:left>
+              <spirit:right spirit:format="long">287</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_8" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_9</spirit:name>
+      <spirit:displayName>LMB_Sl_09</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">288</spirit:left>
+              <spirit:right spirit:format="long">319</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_10</spirit:name>
+      <spirit:displayName>LMB_Sl_10</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">320</spirit:left>
+              <spirit:right spirit:format="long">351</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_10" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_11</spirit:name>
+      <spirit:displayName>LMB_Sl_11</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">352</spirit:left>
+              <spirit:right spirit:format="long">383</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_11" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_12</spirit:name>
+      <spirit:displayName>LMB_Sl_12</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">384</spirit:left>
+              <spirit:right spirit:format="long">415</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_13</spirit:name>
+      <spirit:displayName>LMB_Sl_13</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">416</spirit:left>
+              <spirit:right spirit:format="long">447</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_14</spirit:name>
+      <spirit:displayName>LMB_Sl_14</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">448</spirit:left>
+              <spirit:right spirit:format="long">479</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_14" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_15</spirit:name>
+      <spirit:displayName>LMB_Sl_15</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">480</spirit:left>
+              <spirit:right spirit:format="long">511</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_15" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_M</spirit:name>
+      <spirit:displayName>LMB_M</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Master interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredMaster/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">SYS_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.SYS_Rst</spirit:name>
+      <spirit:displayName>SYS_Rst</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>SYS_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:channels>
+    <spirit:channel>
+      <spirit:name>LMB_Channel</spirit:name>
+      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_0</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_2</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
+    </spirit:channel>
+  </spirit:channels>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>SYS_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;))) - 1)">95</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
+        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Awidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>C Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1200" spirit:configGroups="1 LMB">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Awidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1300" spirit:configGroups="1 LMB" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci
new file mode 100644
index 0000000..3345ed9
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml
new file mode 100644
index 0000000..f502ac2
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/bd_ba6a_dlmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_dlmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">65536</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) / 8) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WSTRB" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
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+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci
new file mode 100644
index 0000000..0a3df28
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CE_COUNTER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CE_FAILING_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_ONOFF_REGISTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_STATUS_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAULT_INJECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x000000000000FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERCONNECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK">0x0000000080010000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK1">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK2">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK3">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_LMB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UE_FAILING_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_WRITE_ACCESS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_ba6a_ilmb_cntlr_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml
new file mode 100644
index 0000000..8c8d9f8
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/bd_ba6a_ilmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_ilmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">65536</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteDBus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_AddrStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ReadStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_BE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_DBus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_Ready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_Wait" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Sl1_UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl1_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4100" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_PROTOCOL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Protocol</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL" spirit:order="4300" spirit:configGroups="4 S AXI CTRL">AXI4LITE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_PROTOCOL" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_ilmb_cntlr_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>LMB BRAM Controller</xilinx:displayName>
+      <xilinx:coreRevision>19</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6b8a9ed6"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ff7e9a63"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="80dd29e4"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="a2db68b7"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ce681c4"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f6139c3b"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci
new file mode 100644
index 0000000..0e3e0b9
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xci
@@ -0,0 +1,298 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>bd_ba6a_lmb_bram_I_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     19.660986 mW</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">BRAM_Controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;web&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dinb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta_busy&quot;:{&quot;direction&quot;:&quot;ou
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_V
+IP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;
+},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rsta&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_lef
+t&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dinb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rstb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;web&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml
new file mode 100644
index 0000000..bdf7b98
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/bd_ba6a_lmb_bram_I_0.xml
@@ -0,0 +1,4151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_lmb_bram_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">65536</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">65536</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
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+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">bd_ba6a_lmb_bram_I_0.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     19.660986 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0132492a</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_302d3091</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f9a6a28b</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1f270a52</spirit:name>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_246d8066</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a6697bba</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_lmb_bram_I_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_f9a6a28b" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_a6697bba" spirit:order="8">True_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_302d3091" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="32" spirit:maximum="1024" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">16384</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_6fc15197" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0132492a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_6fc15197" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_1f270a52" spirit:order="3">BRAM_Controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">bd_ba6a_lmb_bram_I_0.mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci
new file mode 100644
index 0000000..d6fe9d7
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml
new file mode 100644
index 0000000..70c890f
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/bd_ba6a_second_dlmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_second_dlmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">32768</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
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+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
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+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
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+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci
new file mode 100644
index 0000000..92861b3
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_ba6a_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml
new file mode 100644
index 0000000..d8cd6cb
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/bd_ba6a_second_ilmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_second_ilmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">32768</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) / 8) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WSTRB" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci
new file mode 100644
index 0000000..40c231e
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xci
@@ -0,0 +1,298 @@
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+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;web&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dinb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta_busy&quot;:{&quot;direction&quot;:&quot;ou
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_V
+IP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;
+},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rsta&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_lef
+t&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dinb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rstb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;web&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml
new file mode 100644
index 0000000..4c0a36a
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/bd_ba6a_second_lmb_bram_I_0.xml
@@ -0,0 +1,4151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_ba6a_second_lmb_bram_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">32768</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
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+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
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+      </spirit:portMaps>
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+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">32768</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
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+      </spirit:vendorExtensions>
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+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
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+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_READ_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rstb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rstb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>enb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.enb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and(spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>regceb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regceb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        <spirit:name>web</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>eccpipece</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>rdaddrecc</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rdaddrecc" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) != 0) and id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;) != &apos;virtex5&apos;)) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)))">false</xilinx:isEnabled>
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+        <spirit:name>sleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sleep" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;artixu&apos;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplushbm&apos;  or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus58g&apos;or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;zynquplus&apos;))and spirit:decode(id(&apos;MODELPARAM_VALUE.C_EN_SLEEP_PIN&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>deepsleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">bd_ba6a_second_lmb_bram_I_0.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     17.246228 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0132492a</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_302d3091</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f9a6a28b</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1f270a52</spirit:name>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_246d8066</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a6697bba</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_ba6a_second_lmb_bram_I_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_f9a6a28b" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_a6697bba" spirit:order="8">True_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_302d3091" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="32" spirit:maximum="1024" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_6fc15197" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0132492a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_6fc15197" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    <spirit:parameter>
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+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
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+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_1f270a52" spirit:order="3">BRAM_Controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">bd_ba6a_second_lmb_bram_I_0.mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
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+    <xilinx:packagingInfo>
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+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9c3516e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
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+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/phy_ddr4_udimm_microblaze_mcs.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/phy_ddr4_udimm_microblaze_mcs.xci
new file mode 100644
index 0000000..298b68c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/phy_ddr4_udimm_microblaze_mcs.xci
@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
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+      <spirit:instanceName>phy_ddr4_udimm_microblaze_mcs</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze_mcs" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET">Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM">CLK_BOARD_INTERFACE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVOID_PRIMITIVES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BSCANID">76547328</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_ddr4_udimm_microblaze_mcs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEBUG_ENABLED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI1_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO3_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO2_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO3_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_ASYNC_INTR">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_INTR_SIZE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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+solve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;Reset&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;CLK_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.Reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;gene
+rated&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;IO&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mcsio_bus:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mcsio_bus_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_addr_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;IO_address&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;IO_byte_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_read_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_read_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IO_ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_righ
+t&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_write_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_write_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;TRACE&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbtrace:2.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbtrace_rtl:2.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;DATA_ACCESS&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_ADDRESS&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DATA_BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_byte_enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;DATA_READ&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;
+},&quot;DATA_WRITE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE_VALUE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_write_value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DCACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_READ&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DELAY_SLOT&quot;:{&quot;physical_name&quot;:&quot;TRACE_delay_slot&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EX_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_ex_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;p
+hysical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EXCEPTION_KIND&quot;:{&quot;physical_name&quot;:&quot;TRACE_exception_kind&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;EXCEPTION_TAKEN&quot;:{&quot;physical_name&quot;:&quot;TRACE_exception_taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;INSTRUCTION&quot;:{&quot;physical_name&quot;:&quot;TRACE_instruction&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;JUMP_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_jump_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;JUMP_TAKEN&quot;
+:{&quot;physical_name&quot;:&quot;TRACE_jump_taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MB_HALTED&quot;:{&quot;physical_name&quot;:&quot;TRACE_mb_halted&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MEM_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_mem_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MSR_REG&quot;:{&quot;physical_name&quot;:&quot;TRACE_msr_reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;14&quot;},&quot;NEW_REG_VALUE&quot;:{&quot;physical_name&quot;:&quot;TRACE_new_reg_value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;OF_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_of_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PC&quot;:{&quot;physical_name&quot;:&quot;TRACE_pc&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;PID_REG&quot;:{&quot;physical_name&quot;:&quot;TRACE_pid_reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical
+_right&quot;:&quot;7&quot;},&quot;REG_ADDR&quot;:{&quot;physical_name&quot;:&quot;TRACE_reg_addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;REG_WRITE&quot;:{&quot;physical_name&quot;:&quot;TRACE_reg_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;VALID_INSTR&quot;:{&quot;physical_name&quot;:&quot;TRACE_valid_instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/phy_ddr4_udimm_microblaze_mcs.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/phy_ddr4_udimm_microblaze_mcs.xml
new file mode 100644
index 0000000..877f67c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/phy_ddr4_udimm_microblaze_mcs.xml
@@ -0,0 +1,2227 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_ddr4_udimm_microblaze_mcs</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.Clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_ba6a_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET">Reset</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM">CLK_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.Reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>IO</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mcsio_bus" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mcsio_bus_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR_STROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_addr_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_STROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_read_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
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+            <spirit:name>READY</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_ready</spirit:name>
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+            <spirit:name>WRITE_DATA</spirit:name>
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+          <spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>WRITE_STROBE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_write_strobe</spirit:name>
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+        </spirit:portMap>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace_rtl" spirit:version="2.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>DATA_ACCESS</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_access</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ADDRESS</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_address</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DATA_BYTE_ENABLE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_byte_enable</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_READ</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_read</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_write</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE_VALUE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_write_value</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DCACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_rdy</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+          <spirit:logicalPort>
+            <spirit:name>DCACHE_REQ</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_req</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DELAY_SLOT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_delay_slot</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>EX_PIPERUN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_ex_piperun</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_KIND</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_exception_kind</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_exception_taken</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_HIT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_hit</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_RDY</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_rdy</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_REQ</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INSTRUCTION</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_instruction</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>JUMP_HIT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_jump_hit</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_TAKEN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_jump_taken</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>MB_HALTED</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_mb_halted</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MEM_PIPERUN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_mem_piperun</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>MSR_REG</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_msr_reg</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NEW_REG_VALUE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_new_reg_value</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>OF_PIPERUN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_of_piperun</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>PC</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_pc</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PID_REG</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_pid_reg</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>REG_ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_reg_addr</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_WRITE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_reg_write</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>VALID_INSTR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_valid_instr</spirit:name>
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+        </spirit:portMap>
+      </spirit:portMaps>
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+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_elaborateports</spirit:name>
+        <spirit:displayName>Elaborate Ports</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaborateports_view_fileset</spirit:localName>
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+      <spirit:view>
+        <spirit:name>xilinx_elaboratebd</spirit:name>
+        <spirit:displayName>Elaborate BD</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.bd</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaboratebd_view_fileset</spirit:localName>
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+            <spirit:name>outputProductCRC</spirit:name>
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+        <spirit:name>Clk</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>Reset</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_access</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_address</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:name>TRACE_data_byte_enable</spirit:name>
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+            <spirit:left spirit:format="long">0</spirit:left>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_read</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_write</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_write_value</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_rdy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_read</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_req</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_delay_slot</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_ex_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_exception_kind</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">4</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_exception_taken</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_rdy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_req</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_instruction</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_jump_hit</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_jump_taken</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      <spirit:port>
+        <spirit:name>TRACE_mb_halted</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_mem_piperun</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:name>TRACE_msr_reg</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_new_reg_value</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_of_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_pc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_pid_reg</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_reg_addr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_valid_instr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      <spirit:port>
+        <spirit:name>IO_byte_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_read_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
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+      <spirit:port>
+        <spirit:name>IO_read_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          </spirit:driver>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_write_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>IO_write_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+    <spirit:fileSet>
+      <spirit:name>xilinx_elaborateports_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../bd_0/bd_ba6a.bd</spirit:name>
+        <spirit:userFileType>block_diagram</spirit:userFileType>
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+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratebd_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../bd_0/bd_ba6a.bd</spirit:name>
+        <spirit:userFileType>block_diagram</spirit:userFileType>
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+  <spirit:description>MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger.
+The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs.
+</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>JTAG_CHAIN</spirit:name>
+      <spirit:displayName>Debug JTAG User-defined Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.JTAG_CHAIN" spirit:choiceRef="choice_pairs_5502e96b" spirit:order="1065" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MICROBLAZE_INSTANCE</spirit:name>
+      <spirit:displayName>MicroBlaze Instance Name</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MICROBLAZE_INSTANCE" spirit:order="1010" spirit:configGroups="1 NoDisplay">microblaze_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AVOID_PRIMITIVES" spirit:order="1015" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PATH</spirit:name>
+      <spirit:displayName>Instance Hierarchical Design Name</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PATH" spirit:order="1020" spirit:configGroups="1 NoDisplay">mcs_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FREQ</spirit:name>
+      <spirit:displayName>Input Clock Frequency (MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ" spirit:order="1030" spirit:configGroups="1 System">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OPTIMIZATION</spirit:name>
+      <spirit:displayName>Select MicroBlaze Optimization</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZATION" spirit:choiceRef="choice_pairs_563648c8" spirit:order="1025" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DEBUG_ENABLED</spirit:name>
+      <spirit:displayName>Enable Debug Support</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEBUG_ENABLED" spirit:choiceRef="choice_pairs_0d2d32a8" spirit:order="1060" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BSCAN</spirit:name>
+      <spirit:displayName>Select BSCAN location</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BSCAN" spirit:choiceRef="choice_pairs_366c5f3d" spirit:order="1062" spirit:configGroups="1 System">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_BSCAN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BSCANID</spirit:name>
+      <spirit:displayName>Define BSCAN id</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BSCANID" spirit:order="1064" spirit:configGroups="1 System">76547328</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.BSCANID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:displayName>Enable MicroBlaze Trace Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1070" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1035" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEMSIZE</spirit:name>
+      <spirit:displayName>Memory Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEMSIZE" spirit:choiceRef="choice_pairs_f7e0b771" spirit:order="1040" spirit:configGroups="1 System">98304</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEMTYPE</spirit:name>
+      <spirit:displayName>Memory Type</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEMTYPE" spirit:choiceRef="choice_pairs_9de6ed99" spirit:order="1045" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_IO_BUS</spirit:name>
+      <spirit:displayName>Enable IO Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_IO_BUS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1050" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_UART_RX</spirit:name>
+      <spirit:displayName>Enable Receiver</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_UART_RX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_UART_RX">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_UART_TX</spirit:name>
+      <spirit:displayName>Enable Transmitter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_UART_TX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_UART_TX">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BAUDRATE</spirit:name>
+      <spirit:displayName>Define Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BAUDRATE" spirit:choiceRef="choice_list_f585525a" spirit:order="2200" spirit:configGroups="2 UART">9600</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_BAUDRATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_PROG_BAUDRATE</spirit:name>
+      <spirit:displayName>Programmable Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_PROG_BAUDRATE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_PROG_BAUDRATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_DATA_BITS</spirit:name>
+      <spirit:displayName>Number of Data Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_DATA_BITS" spirit:order="2400" spirit:configGroups="2 UART" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_DATA_BITS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_USE_PARITY</spirit:name>
+      <spirit:displayName>Use Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_USE_PARITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_USE_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_ODD_PARITY</spirit:name>
+      <spirit:displayName>Even or Odd Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_ODD_PARITY" spirit:choiceRef="choice_pairs_ffa336e4" spirit:order="2600" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_ODD_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_RX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Receive Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_RX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2700" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_RX_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_TX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Transmit Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_TX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2800" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_TX_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_ERROR_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Error Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_ERROR_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2900" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_ERROR_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT1</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3001" spirit:configGroups="3 FIT1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT1_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT1_No_CLOCKS" spirit:order="3002" spirit:configGroups="3 FIT1" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT1_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3005" spirit:configGroups="3 FIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT2</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3101" spirit:configGroups="3 FIT2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT2_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT2_No_CLOCKS" spirit:order="3102" spirit:configGroups="3 FIT2" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT2_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3105" spirit:configGroups="3 FIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT3</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3201" spirit:configGroups="3 FIT3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT3_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT3_No_CLOCKS" spirit:order="3202" spirit:configGroups="3 FIT3" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT3_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3205" spirit:configGroups="3 FIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT4</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3301" spirit:configGroups="3 FIT4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT4_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT4_No_CLOCKS" spirit:order="3302" spirit:configGroups="3 FIT4" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT4_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3305" spirit:configGroups="3 FIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT1</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4001" spirit:configGroups="4 PIT1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_SIZE" spirit:order="4002" spirit:configGroups="4 PIT1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4003" spirit:configGroups="4 PIT1">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_PRESCALER" spirit:choiceRef="choice_pairs_f0f6eb36" spirit:order="4004" spirit:configGroups="4 PIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4008" spirit:configGroups="4 PIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT2</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4101" spirit:configGroups="4 PIT2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_SIZE" spirit:order="4102" spirit:configGroups="4 PIT2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4103" spirit:configGroups="4 PIT2">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_PRESCALER" spirit:choiceRef="choice_pairs_007f01e9" spirit:order="4104" spirit:configGroups="4 PIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4108" spirit:configGroups="4 PIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT3</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4201" spirit:configGroups="4 PIT3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_SIZE" spirit:order="4202" spirit:configGroups="4 PIT3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4203" spirit:configGroups="4 PIT3">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_PRESCALER" spirit:choiceRef="choice_pairs_4847022f" spirit:order="4204" spirit:configGroups="4 PIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4208" spirit:configGroups="4 PIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT4</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4301" spirit:configGroups="4 PIT4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_SIZE" spirit:order="4302" spirit:configGroups="4 PIT4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4303" spirit:configGroups="4 PIT4">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_PRESCALER" spirit:choiceRef="choice_pairs_5f1e379e" spirit:order="4304" spirit:configGroups="4 PIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4308" spirit:configGroups="4 PIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO1</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5000" spirit:configGroups="5 GPO1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO1_SIZE" spirit:order="5001" spirit:configGroups="5 GPO1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO1_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO1_INIT" spirit:order="5002" spirit:configGroups="5 GPO1" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO1_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO2</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5100" spirit:configGroups="5 GPO2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO2_SIZE" spirit:order="5101" spirit:configGroups="5 GPO2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO2_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO2_INIT" spirit:order="5102" spirit:configGroups="5 GPO2" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO2_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO3</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5200" spirit:configGroups="5 GPO3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO3">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO3_SIZE" spirit:order="5201" spirit:configGroups="5 GPO3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO3_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO3_INIT" spirit:order="5202" spirit:configGroups="5 GPO3" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO3_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO4</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5300" spirit:configGroups="5 GPO4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO4_SIZE" spirit:order="5301" spirit:configGroups="5 GPO4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO4_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO4_INIT" spirit:order="5302" spirit:configGroups="5 GPO4" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO4_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI1</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6000" spirit:configGroups="6 GPI1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI1_SIZE" spirit:order="6001" spirit:configGroups="6 GPI1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI1_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6002" spirit:configGroups="6 GPI1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI2</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 GPI2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI2_SIZE" spirit:order="6101" spirit:configGroups="6 GPI2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI2_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6102" spirit:configGroups="6 GPI2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI3</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6200" spirit:configGroups="6 GPI3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI3">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI3_SIZE" spirit:order="6201" spirit:configGroups="6 GPI3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI3_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6202" spirit:configGroups="6 GPI3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI4</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6300" spirit:configGroups="6 GPI4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI4_SIZE" spirit:order="6301" spirit:configGroups="6 GPI4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI4_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6302" spirit:configGroups="6 GPI4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_USE_EXT_INTR</spirit:name>
+      <spirit:displayName>Use External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_USE_EXT_INTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7000" spirit:configGroups="7 Interrupt">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_INTR_SIZE</spirit:name>
+      <spirit:displayName>Number of External Inputs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_INTR_SIZE" spirit:order="7100" spirit:configGroups="7 Interrupt" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_INTR_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_LEVEL_EDGE</spirit:name>
+      <spirit:displayName>Level or Edge of External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_LEVEL_EDGE" spirit:order="7200" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0x0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_LEVEL_EDGE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_POSITIVE</spirit:name>
+      <spirit:displayName>Positive or Negative External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_POSITIVE" spirit:order="7300" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_POSITIVE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_ASYNC_INTR</spirit:name>
+      <spirit:displayName>Interrupts asynchronous</spirit:displayName>
+      <spirit:description>The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous.</spirit:description>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_ASYNC_INTR" spirit:order="7400" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_ASYNC_INTR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_NUM_SYNC_FF</spirit:name>
+      <spirit:displayName>Number of synchronization flip-flops</spirit:displayName>
+      <spirit:description>Number of synchronization flip-flops used to synchronize asynchronous interupt inputs</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_NUM_SYNC_FF" spirit:order="7500" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_ddr4_udimm_microblaze_mcs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="100" spirit:configGroups="0 Board">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="103" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CLK_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_30de7c39" spirit:order="106" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RESET_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO1_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="110" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO1_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO2_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="120" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO2_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO3_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO3_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="130" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO3_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO4_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="140" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO4_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:choiceRef="choice_list_0739ee39" spirit:order="150" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>MicroBlaze MCS</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>14</xilinx:coreRevision>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="bd_viewable">true</xilinx:tag>
+        <xilinx:tag xilinx:name="driver_mode">subcore</xilinx:tag>
+      </xilinx:tags>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEMSIZE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OPTIMIZATION" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TRACE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_IO_BUS" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6ddedfe4"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="08e90b19"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="3d2f3b86"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci
new file mode 100644
index 0000000..855a261
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xci
@@ -0,0 +1,665 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>phy_ddr4_udimm_phy</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4_phy" spirit:version="2.2"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_ADDR_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_DATA_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_GROUP_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_TYPE">HP_IO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_DIV_LOC_1">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_DIV_LOC_2">X0Y10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_LOC_1">X0Y70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_LOC_2">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BYTES">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CA_MIRROR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CENTER_BANK_CLOCK_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKIN_PERIOD">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COLUMN_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATABITS_PER_STROBE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_BUF_ADDR_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DBYTES">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DM_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQS_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQ_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_OTHER_PN_CLOCK_PARAM">{{8{2&apos;b01}}, {3{2&apos;b00}}} </spirit:configurableElementValue>
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+1_001_001_001_001  </spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_COMP_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_DEVICE_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_IDX_BANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MR0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MR2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_CH1_BYTES_MAP">11&apos;b00000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RANK_WIDTH">1</spirit:configurableElementValue>
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+                                                                              }</spirit:configurableElementValue>
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+                                15&apos;b011111_11_11111_11                                                                                }</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELF_CALIBRATE">{11{2&apos;b11}} </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_CENTER_INFO">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Slot">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_OUTPUT_PHASE_90">{ 13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000
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+                                                                               }</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tCK">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tMRD">2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tWR">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tXPR">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tZQINIT">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasLatency">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MTA8ATF1G64AZ-2G3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">UDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_customPartAbsPath">no_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_ddr4_udimm_phy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Phy_Only_Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_act_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cas_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_data_compare_error">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_100">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_101">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_102">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_103">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_104">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_105">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_106">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_107">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_108">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_109">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_110">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_111">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_112">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_113">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_114">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_115">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_116">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_117">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_118">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_119">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_120">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_121">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_122">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_123">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_124">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_36">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_37">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_38">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_39">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_40">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_41">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_42">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_43">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_44">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_45">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_46">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_47">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_48">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_49">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_50">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_51">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_52">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_53">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_54">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_55">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_56">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_57">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_58">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_59">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_60">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_61">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_62">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_63">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_64">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_65">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_66">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_67">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_68">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_69">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_70">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_71">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_72">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_73">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_74">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_75">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_76">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_77">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_78">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_79">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_80">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_81">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_82">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_83">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_84">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_85">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_86">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_87">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_88">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_89">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_90">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_91">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_92">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_93">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_94">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_95">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_96">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_97">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_98">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_99">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_init_calib_complete">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_parity">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ras_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_reset_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_sys_clk_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_sys_clk_p">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_we_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_rst">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ControllerType" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Clamshell" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Ecc" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Slot" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_StackHeight" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Debug_Signal" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_FROM_PHY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Simulation_Mode" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.System_Clock" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml
new file mode 100644
index 0000000..45c8a5e
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/phy_ddr4_udimm_phy.xml
@@ -0,0 +1,4890 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_ddr4_udimm_phy</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>sys_clk_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_p" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_n" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk_i</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_i" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;No_Buffer&quot; )">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mmcm_lock</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mmcm_lock" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>pllGate</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pllGate" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>div_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.div_clk" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>div_clk_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.div_clk_rst" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>riu_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.riu_clk" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>riu_clk_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>ddr4_odt</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>ddr4_cs_n</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>ddr4_ck_c</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>ddr4_reset_n</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>ddr4_dm_dbi_n</spirit:name>
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+          <spirit:direction>inout</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>mcal_CK_c</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcal_CK_c" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mcal_CK_t</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcal_CK_t" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dq</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr4_dq" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>ddr4_dqs_c</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr4_dqs_c" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+        <spirit:name>ddr4_dqs_t</spirit:name>
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+          <spirit:direction>inout</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr4_dqs_t" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+        <spirit:name>mcal_BG</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcal_BG" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType">
+        <spirit:name>C0.ControllerType</spirit:name>
+        <spirit:displayName>ControllerType</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>BANK_TYPE</spirit:name>
+        <spirit:displayName>Bank Type</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_TYPE">HP_IO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>ADDR_WIDTH</spirit:name>
+        <spirit:displayName>ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADDR_WIDTH">17</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>BANK_WIDTH</spirit:name>
+        <spirit:displayName>BANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_WIDTH">2</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>BANK_GROUP_WIDTH</spirit:name>
+        <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_GROUP_WIDTH">2</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>LR_WIDTH</spirit:name>
+        <spirit:displayName>LR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LR_WIDTH">1</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>CKE_WIDTH</spirit:name>
+        <spirit:displayName>CKE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CKE_WIDTH">1</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>COLUMN_WIDTH</spirit:name>
+        <spirit:displayName>COLUMN WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COLUMN_WIDTH">10</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>CS_WIDTH</spirit:name>
+        <spirit:displayName>CS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CS_WIDTH">1</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>ODT_WIDTH</spirit:name>
+        <spirit:displayName>ODT WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ODT_WIDTH">1</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>DQ_WIDTH</spirit:name>
+        <spirit:displayName>DQ WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQ_WIDTH">64</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>DQS_WIDTH</spirit:name>
+        <spirit:displayName>DQS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQS_WIDTH">8</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>DM_WIDTH</spirit:name>
+        <spirit:displayName>DM WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DM_WIDTH">8</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>MR0</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MR0">0</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>MR2</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MR2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tCK</spirit:name>
+        <spirit:displayName>tCK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tCK">1500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tXPR</spirit:name>
+        <spirit:displayName>tXPR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tXPR">60</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>nCK_PER_CLK</spirit:name>
+        <spirit:displayName>nCK PER CLK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nCK_PER_CLK">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tMRD</spirit:name>
+        <spirit:displayName>tMRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tMRD">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tZQINIT</spirit:name>
+        <spirit:displayName>tZQINIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tZQINIT">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_COMP_WIDTH</spirit:name>
+        <spirit:displayName>MEM COMP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_COMP_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_DEVICE_WIDTH</spirit:name>
+        <spirit:displayName>MEMORY DEVICE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_DEVICE_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PLL_WIDTH</spirit:name>
+        <spirit:displayName>PLL WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PLL_WIDTH">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>IOBTYPE</spirit:name>
+        <spirit:displayName>IOBTYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IOBTYPE">                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b
+000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                  
+                                                39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_000_000_000_000_000_000_000_000_001_001_001_001,                                                                                  39&apos;b001_001_001_000_000_001_001_001_001_001_001_001_001,                                                                                  39&apos;b000_001_001_001_001_101_101_001_00
+1_001_001_001_001  </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BYTES</spirit:name>
+        <spirit:displayName>BYTES</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BYTES">11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DBYTES</spirit:name>
+        <spirit:displayName>DBYTES</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DBYTES">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_CH1_BYTES_MAP</spirit:name>
+        <spirit:displayName>PING_PONG_CH1_BYTES_MAP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_CH1_BYTES_MAP">11&apos;b00000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_PHY</spirit:name>
+        <spirit:displayName>PING PONG PHY</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RX_DATA_TYPE</spirit:name>
+        <spirit:displayName>RX DATA TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_DATA_TYPE">{ 15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                               
+                 15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b000000_00_00111_11,                                                                                15&apos;b111001_11_11111_11,                                                
+                                15&apos;b011111_11_11111_11                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>INIT</spirit:name>
+        <spirit:displayName>INIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INIT">{                            15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111101,                                                                                15&apos;b111111111111111,                                                   
+                             15&apos;b111111111111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>SELF_CALIBRATE</spirit:name>
+        <spirit:displayName>SELF CALIBRATE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELF_CALIBRATE">{11{2&apos;b11}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>TX_OUTPUT_PHASE_90</spirit:name>
+        <spirit:displayName>TX OUTPUT PHASE 90</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_OUTPUT_PHASE_90">{ 13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000
+011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000000001111,                                                                                13&apos;b1110011111111,                                                                                13&apos;b0111111111111 
+                                                                               }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RXTX_BITSLICE_EN</spirit:name>
+        <spirit:displayName>RXTX BITSLICE EN</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXTX_BITSLICE_EN">{13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b01111
+01111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0000000001111,                                                                                13&apos;b1110011111111,                                                                                13&apos;b0111101111111  
+                                                                              }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>EN_OTHER_PN_CLOCK_PARAM</spirit:name>
+        <spirit:displayName>EN OTHER PN CLOCK PARAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_OTHER_PN_CLOCK_PARAM">{{8{2&apos;b01}}, {3{2&apos;b00}}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PHY_BYTE_ALLOC_PARAM</spirit:name>
+        <spirit:displayName>PHY BYTE ALLOC PARAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PHY_BYTE_ALLOC_PARAM">{{8{2&apos;b11}}, {3{2&apos;b00}}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DATA_BUF_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>DATA BUF ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_BUF_ADDR_WIDTH">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKIN_PERIOD</spirit:name>
+        <spirit:displayName>CLKIN PERIOD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_TYPE</spirit:name>
+        <spirit:displayName>MEM TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_ID_WIDTH</spirit:name>
+        <spirit:displayName>AXI ID WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ID_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI DATA WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_DATA_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ADDR_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>USE_DM_PORT</spirit:name>
+        <spirit:displayName>USE DM PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_DM_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_LOC_1</spirit:name>
+        <spirit:displayName>BUFG LOC 1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_LOC_1">X0Y70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_LOC_2</spirit:name>
+        <spirit:displayName>BUFG LOC 2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_LOC_2">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_DIV_LOC_1</spirit:name>
+        <spirit:displayName>BUFG DIV LOC 1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_DIV_LOC_1">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_DIV_LOC_2</spirit:name>
+        <spirit:displayName>BUFG DIV LOC 2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_DIV_LOC_2">X0Y10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_SLICE_LOC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_SLICE_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB36_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB18_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_SLICE_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_SLICE_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB36_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB18_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MMCM_IDX_BANK</spirit:name>
+        <spirit:displayName>MMCM IDX BANK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_IDX_BANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CENTER_BANK_CLOCK_REGION</spirit:name>
+        <spirit:displayName>CENTER BANK CLOCK REGION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CENTER_BANK_CLOCK_REGION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CENTER_BANK_MMCME3_ADV_SITE</spirit:name>
+        <spirit:displayName>CENTER BANK MMCME3 ADV SITE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>SYSCLK_CENTER_INFO</spirit:name>
+        <spirit:displayName>SYSCLK_CENTER_INFO</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYSCLK_CENTER_INFO">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tWR</spirit:name>
+        <spirit:displayName>tWR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tWR">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tRTP</spirit:name>
+        <spirit:displayName>tRTP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tRTP">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RANK_WIDTH</spirit:name>
+        <spirit:displayName>RANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RANK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CK_WIDTH</spirit:name>
+        <spirit:displayName>CK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DATABITS_PER_STROBE</spirit:name>
+        <spirit:displayName>DATABITS PER STROBE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATABITS_PER_STROBE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>USE_CS_PORT</spirit:name>
+        <spirit:displayName>USE CS PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_CS_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CA_MIRROR</spirit:name>
+        <spirit:displayName>CA MIRROR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CA_MIRROR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>IS_CUSTOM</spirit:name>
+        <spirit:displayName>IS CUSTOM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_CUSTOM">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Slot</spirit:name>
+        <spirit:displayName>Slot</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Slot">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>phy_ddr4_udimm_phy</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="dummy"/>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>PHY for DDR4 interfaces for Ultrascale Architecture</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C0.ControllerType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ControllerType" spirit:order="2">DDR4_SDRAM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_FROM_PHY</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IS_FROM_PHY" spirit:order="3">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Phy_Only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Phy_Only" spirit:order="4">Phy_Only_Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>No_Controller</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.No_Controller" spirit:order="5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Default_Bank_Selections</spirit:name>
+      <spirit:displayName>Default Bank Selections</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Default_Bank_Selections" spirit:order="6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Debug_Signal</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Debug_Signal" spirit:order="7">Disable</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Simulation_Mode</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Simulation_Mode" spirit:order="8">BFM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PARTIAL_RECONFIG_FLOW_MIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" spirit:order="9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DIVIDE" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DIVIDE" spirit:order="11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DIVIDE" spirit:order="12">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DIVIDE" spirit:order="13">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>System_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.System_Clock" spirit:order="14">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RECONFIG_XSDB_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" spirit:order="15">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_TERM_SYSCLK</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_TERM_SYSCLK" spirit:order="16">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TimePeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TimePeriod" spirit:order="17">1500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_InputClockPeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_InputClockPeriod" spirit:order="18">3333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" spirit:order="19">5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" spirit:order="20">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" spirit:order="21">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PhyClockRatio</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PhyClockRatio" spirit:order="22">4:1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryType" spirit:order="23">UDIMMs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryPart</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryPart" spirit:order="24">MTA8ATF1G64AZ-2G3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Slot</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Slot" spirit:order="25">Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryVoltage</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryVoltage" spirit:order="26">1.2V</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataWidth" spirit:order="27">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataMask</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataMask" spirit:order="28">DM_NO_DBI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ecc" spirit:order="29">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasLatency" spirit:order="30">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasWriteLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasWriteLatency" spirit:order="31">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ChipSelect</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ChipSelect" spirit:order="32">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCKEShared</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCKEShared" spirit:order="33">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name>
+      <spirit:displayName>CLKOUTPHY MODE</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" spirit:order="34">VCO</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name>
+      <spirit:displayName>High Range Supported frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" spirit:order="35">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name>
+      <spirit:displayName>Memory Min Period</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MIN_PERIOD" spirit:order="36">833</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name>
+      <spirit:displayName>Indicates Faster Speed RAM Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" spirit:order="37">No</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_VrefVoltage</spirit:name>
+      <spirit:displayName>Vref Voltage</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_VrefVoltage" spirit:order="38">0.84</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_customPartAbsPath</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_customPartAbsPath" spirit:order="39">no_file_loaded</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_StackHeight</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_StackHeight" spirit:order="40">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CUSTOM_PART_ATTRIBUTES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" spirit:order="41">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SELF_REFRESH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SELF_REFRESH" spirit:order="42">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" spirit:order="43">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Clamshell</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Clamshell" spirit:order="44">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Enable_LVAUX</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Enable_LVAUX" spirit:order="45">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_EN_PARITY</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_EN_PARITY" spirit:order="46">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_0" spirit:order="47">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_1" spirit:order="48">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_2" spirit:order="49">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_3" spirit:order="50">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_4" spirit:order="51">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_5" spirit:order="52">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_6" spirit:order="53">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_7" spirit:order="54">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_8" spirit:order="55">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_9" spirit:order="56">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_10" spirit:order="57">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_11" spirit:order="58">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_12" spirit:order="59">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_13" spirit:order="60">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_14" spirit:order="61">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_15" spirit:order="62">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_16" spirit:order="63">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_17" spirit:order="64">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_18" spirit:order="65">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_19" spirit:order="66">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_20" spirit:order="67">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_21" spirit:order="68">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_22" spirit:order="69">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_23" spirit:order="70">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_24" spirit:order="71">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_25" spirit:order="72">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_26" spirit:order="73">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_27" spirit:order="74">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_28" spirit:order="75">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_29" spirit:order="76">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_30" spirit:order="77">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_31" spirit:order="78">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_32" spirit:order="79">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_33" spirit:order="80">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_34" spirit:order="81">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_35" spirit:order="82">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_36</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_36" spirit:order="83">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_37</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_37" spirit:order="84">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_38</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_38" spirit:order="85">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_39</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_39" spirit:order="86">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_40</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_40" spirit:order="87">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_41</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_41" spirit:order="88">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_42</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_42" spirit:order="89">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_43</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_43" spirit:order="90">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_44</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_44" spirit:order="91">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_45</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_45" spirit:order="92">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_46</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_46" spirit:order="93">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_47</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_47" spirit:order="94">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_48</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_48" spirit:order="95">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_49</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_49" spirit:order="96">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_50</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_50" spirit:order="97">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_51</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_51" spirit:order="98">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_52</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_52" spirit:order="99">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_53</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_53" spirit:order="100">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_54</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_54" spirit:order="101">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_55</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_55" spirit:order="102">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_56</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_56" spirit:order="103">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_57</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_57" spirit:order="104">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_58</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_58" spirit:order="105">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_59</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_59" spirit:order="106">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_60</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_60" spirit:order="107">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_61</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_61" spirit:order="108">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_62</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_62" spirit:order="109">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_63</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_63" spirit:order="110">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_64</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_64" spirit:order="111">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_65</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_65" spirit:order="112">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_66</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_66" spirit:order="113">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_67</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_67" spirit:order="114">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_68</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_68" spirit:order="115">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_69</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_69" spirit:order="116">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_70</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_70" spirit:order="117">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_71</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_71" spirit:order="118">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_72</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_72" spirit:order="119">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_73</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_73" spirit:order="120">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_74</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_74" spirit:order="121">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_75</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_75" spirit:order="122">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_76</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_76" spirit:order="123">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_77</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_77" spirit:order="124">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_78</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_78" spirit:order="125">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_79</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_79" spirit:order="126">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_80</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_80" spirit:order="127">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_81</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_81" spirit:order="128">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_82</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_82" spirit:order="129">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_83</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_83" spirit:order="130">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_84</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_84" spirit:order="131">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_85</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_85" spirit:order="132">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_86</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_86" spirit:order="133">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_87</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_87" spirit:order="134">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_88</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_88" spirit:order="135">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_89</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_89" spirit:order="136">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_90</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_90" spirit:order="137">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_91</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_91" spirit:order="138">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_92</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_92" spirit:order="139">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_93</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_93" spirit:order="140">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_94</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_94" spirit:order="141">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_95</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_95" spirit:order="142">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_96</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_96" spirit:order="143">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_97</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_97" spirit:order="144">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_98</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_98" spirit:order="145">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_99</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_99" spirit:order="146">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_100</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_100" spirit:order="147">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_101</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_101" spirit:order="148">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_102</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_102" spirit:order="149">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_103</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_103" spirit:order="150">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_104</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_104" spirit:order="151">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_105</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_105" spirit:order="152">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_106</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_106" spirit:order="153">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_107</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_107" spirit:order="154">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_108</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_108" spirit:order="155">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_109</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_109" spirit:order="156">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_110</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_110" spirit:order="157">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_111</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_111" spirit:order="158">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_112</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_112" spirit:order="159">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_113</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_113" spirit:order="160">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_114</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_114" spirit:order="161">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_115</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_115" spirit:order="162">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_116</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_116" spirit:order="163">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_117</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_117" spirit:order="164">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_118</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_118" spirit:order="165">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_119</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_119" spirit:order="166">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_120</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_120" spirit:order="167">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_121</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_121" spirit:order="168">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_122</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_122" spirit:order="169">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_123</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_123" spirit:order="170">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_124</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_124" spirit:order="171">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_125</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_125" spirit:order="172">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_126</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_126" spirit:order="173">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_127</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_127" spirit:order="174">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_128</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_128" spirit:order="175">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_129</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_129" spirit:order="176">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_130</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_130" spirit:order="177">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_131</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_131" spirit:order="178">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_132</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_132" spirit:order="179">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_133</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_133" spirit:order="180">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_134</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_134" spirit:order="181">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_135</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_135" spirit:order="182">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_136</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_136" spirit:order="183">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_137</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_137" spirit:order="184">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_138</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_138" spirit:order="185">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_139</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_139" spirit:order="186">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_140</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_140" spirit:order="187">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_141</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_141" spirit:order="188">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_142</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_142" spirit:order="189">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_143</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_143" spirit:order="190">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_0" spirit:order="191">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_1" spirit:order="192">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_2" spirit:order="193">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_3" spirit:order="194">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_4" spirit:order="195">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_5" spirit:order="196">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_6" spirit:order="197">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_7" spirit:order="198">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_8" spirit:order="199">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_9" spirit:order="200">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_10" spirit:order="201">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_11" spirit:order="202">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_12" spirit:order="203">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_13" spirit:order="204">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_14" spirit:order="205">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_15" spirit:order="206">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_16" spirit:order="207">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_17" spirit:order="208">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_18" spirit:order="209">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_19" spirit:order="210">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_20" spirit:order="211">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_21" spirit:order="212">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_0" spirit:order="213">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_1" spirit:order="214">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_2" spirit:order="215">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_3" spirit:order="216">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_4" spirit:order="217">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_5" spirit:order="218">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_6" spirit:order="219">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_7" spirit:order="220">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_8" spirit:order="221">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_9" spirit:order="222">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_10" spirit:order="223">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_11" spirit:order="224">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_12" spirit:order="225">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_13" spirit:order="226">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_14" spirit:order="227">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_15" spirit:order="228">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_16" spirit:order="229">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_17" spirit:order="230">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_18" spirit:order="231">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_19" spirit:order="232">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_20" spirit:order="233">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_21" spirit:order="234">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_0" spirit:order="235">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_1" spirit:order="236">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_2" spirit:order="237">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_3" spirit:order="238">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_4" spirit:order="239">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_5" spirit:order="240">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_6" spirit:order="241">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_7" spirit:order="242">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_8" spirit:order="243">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_9" spirit:order="244">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_10" spirit:order="245">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_11" spirit:order="246">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_12" spirit:order="247">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_13" spirit:order="248">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_14" spirit:order="249">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_15" spirit:order="250">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_16" spirit:order="251">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_17" spirit:order="252">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_18" spirit:order="253">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_19" spirit:order="254">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_20" spirit:order="255">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_21" spirit:order="256">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_22" spirit:order="257">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_23" spirit:order="258">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_24" spirit:order="259">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_25" spirit:order="260">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_26" spirit:order="261">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_27" spirit:order="262">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_28" spirit:order="263">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_29" spirit:order="264">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_30" spirit:order="265">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_31" spirit:order="266">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_32" spirit:order="267">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_33" spirit:order="268">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_34" spirit:order="269">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_35" spirit:order="270">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_0" spirit:order="271">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_1" spirit:order="272">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_2" spirit:order="273">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_3" spirit:order="274">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_4" spirit:order="275">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_5" spirit:order="276">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_6" spirit:order="277">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_7" spirit:order="278">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_8" spirit:order="279">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_9" spirit:order="280">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_10" spirit:order="281">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_11" spirit:order="282">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_12" spirit:order="283">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_13" spirit:order="284">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_14" spirit:order="285">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_15" spirit:order="286">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_16" spirit:order="287">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_17" spirit:order="288">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_18" spirit:order="289">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_19" spirit:order="290">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_20" spirit:order="291">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_21" spirit:order="292">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_22" spirit:order="293">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_23" spirit:order="294">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_24" spirit:order="295">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_25" spirit:order="296">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_26" spirit:order="297">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_27" spirit:order="298">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_28" spirit:order="299">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_29" spirit:order="300">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_30" spirit:order="301">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_31" spirit:order="302">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_32" spirit:order="303">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_33" spirit:order="304">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_34" spirit:order="305">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_35" spirit:order="306">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_0" spirit:order="307">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_1" spirit:order="308">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_2" spirit:order="309">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_3" spirit:order="310">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_4" spirit:order="311">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_5" spirit:order="312">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_6" spirit:order="313">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_7" spirit:order="314">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_8" spirit:order="315">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_9" spirit:order="316">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_10" spirit:order="317">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_11" spirit:order="318">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_12" spirit:order="319">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_13" spirit:order="320">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_14" spirit:order="321">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_15" spirit:order="322">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_16" spirit:order="323">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_17" spirit:order="324">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_18" spirit:order="325">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_19" spirit:order="326">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_20" spirit:order="327">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_21" spirit:order="328">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_22" spirit:order="329">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_23" spirit:order="330">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_24" spirit:order="331">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_25" spirit:order="332">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_26" spirit:order="333">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_27" spirit:order="334">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_28" spirit:order="335">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_29" spirit:order="336">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_30" spirit:order="337">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_31" spirit:order="338">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_32" spirit:order="339">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_33" spirit:order="340">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_34" spirit:order="341">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_35" spirit:order="342">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_0" spirit:order="343">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_1" spirit:order="344">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_2" spirit:order="345">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_3" spirit:order="346">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_4" spirit:order="347">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_5" spirit:order="348">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_6" spirit:order="349">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_7" spirit:order="350">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_8" spirit:order="351">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_9" spirit:order="352">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_10" spirit:order="353">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_11" spirit:order="354">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_12" spirit:order="355">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_13" spirit:order="356">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_14" spirit:order="357">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_15" spirit:order="358">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_16" spirit:order="359">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_17" spirit:order="360">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_18" spirit:order="361">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_19" spirit:order="362">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_20" spirit:order="363">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_21" spirit:order="364">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_22" spirit:order="365">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_23" spirit:order="366">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_24" spirit:order="367">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_25" spirit:order="368">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_26" spirit:order="369">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_27" spirit:order="370">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_28" spirit:order="371">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_29" spirit:order="372">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_30" spirit:order="373">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_31" spirit:order="374">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_32" spirit:order="375">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_33" spirit:order="376">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_34" spirit:order="377">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_35" spirit:order="378">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_0" spirit:order="379">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_1" spirit:order="380">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_2" spirit:order="381">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_3" spirit:order="382">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_4" spirit:order="383">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_5" spirit:order="384">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_6" spirit:order="385">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_7" spirit:order="386">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_8" spirit:order="387">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_9" spirit:order="388">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_10" spirit:order="389">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_11" spirit:order="390">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_12" spirit:order="391">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_13" spirit:order="392">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_14" spirit:order="393">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_15" spirit:order="394">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_16" spirit:order="395">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_17" spirit:order="396">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_18" spirit:order="397">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_19" spirit:order="398">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_20" spirit:order="399">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_21" spirit:order="400">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_22" spirit:order="401">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_23" spirit:order="402">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_24" spirit:order="403">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_25" spirit:order="404">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_26" spirit:order="405">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_27" spirit:order="406">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_28" spirit:order="407">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_29" spirit:order="408">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_30" spirit:order="409">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_31" spirit:order="410">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_32" spirit:order="411">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_33" spirit:order="412">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_34" spirit:order="413">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_35" spirit:order="414">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_0" spirit:order="415">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_1" spirit:order="416">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_2" spirit:order="417">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_3" spirit:order="418">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_4" spirit:order="419">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_5" spirit:order="420">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_6" spirit:order="421">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_7" spirit:order="422">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_8" spirit:order="423">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_9" spirit:order="424">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_10" spirit:order="425">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_11" spirit:order="426">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_12" spirit:order="427">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_13" spirit:order="428">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_14" spirit:order="429">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_15" spirit:order="430">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_16" spirit:order="431">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_17" spirit:order="432">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_18" spirit:order="433">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_19" spirit:order="434">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_20" spirit:order="435">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_21" spirit:order="436">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_22" spirit:order="437">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_23" spirit:order="438">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_24" spirit:order="439">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_25" spirit:order="440">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_26" spirit:order="441">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_27" spirit:order="442">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_28" spirit:order="443">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_29" spirit:order="444">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_30" spirit:order="445">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_31" spirit:order="446">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_32" spirit:order="447">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_33" spirit:order="448">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_34" spirit:order="449">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_35" spirit:order="450">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_0" spirit:order="451">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_1" spirit:order="452">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_2" spirit:order="453">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_3" spirit:order="454">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_0" spirit:order="455">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_1" spirit:order="456">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_2" spirit:order="457">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_0" spirit:order="458">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_1" spirit:order="459">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_2" spirit:order="460">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_0" spirit:order="461">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_1" spirit:order="462">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_2" spirit:order="463">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_3" spirit:order="464">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_0" spirit:order="465">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_1" spirit:order="466">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_2" spirit:order="467">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_3" spirit:order="468">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_0" spirit:order="469">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_1" spirit:order="470">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_2" spirit:order="471">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_3" spirit:order="472">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_0" spirit:order="473">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_1" spirit:order="474">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_2" spirit:order="475">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_3" spirit:order="476">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_4" spirit:order="477">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_5" spirit:order="478">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_6" spirit:order="479">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_7" spirit:order="480">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_0" spirit:order="481">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_1" spirit:order="482">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_2" spirit:order="483">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_3" spirit:order="484">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_0" spirit:order="485">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_1" spirit:order="486">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_2" spirit:order="487">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_3" spirit:order="488">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_0" spirit:order="489">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_1" spirit:order="490">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_2" spirit:order="491">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_3" spirit:order="492">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_reset_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_reset_n" spirit:order="493">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_act_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_act_n" spirit:order="494">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ras_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ras_n" spirit:order="495">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cas_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cas_n" spirit:order="496">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_we_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_we_n" spirit:order="497">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_parity</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_parity" spirit:order="498">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p" spirit:order="499">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n" spirit:order="500">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n" spirit:order="501">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>sys_rst</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sys_rst" spirit:order="502">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_sys_clk_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_sys_clk_n" spirit:order="503">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_sys_clk_p</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_sys_clk_p" spirit:order="504">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_data_compare_error</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_data_compare_error" spirit:order="505">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_init_calib_complete</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_init_calib_complete" spirit:order="506">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_ddr4_udimm_phy</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>DDR4 SDRAM PHY IP</xilinx:displayName>
+      <xilinx:coreRevision>0</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ControllerType" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Clamshell" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="propagated"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xci b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xci
new file mode 100644
index 0000000..18c0587
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xci
@@ -0,0 +1,474 @@
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">8GB</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">8192</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_833_Timing</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">083</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">166500000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ">None</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MTA8ATF1G64AZ-2G3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">UDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC_DLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TXPR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TREFI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TXPR">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.LR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.MIGRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_ddr4_udimm</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCI_Cascade">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_PP_4R_MIR">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Power_Reduction">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Phy_Only_Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reference_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SET_DW_TO_40">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_3DS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;c0_init_calib_complete&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dbg_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_sys_clk_p&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_sys_clk_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dbg_bus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_ui_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_ui_clk_sync_rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataEn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataEnd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;per_rd_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rmw_rd_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataEn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_righ
+t&quot;:&quot;0&quot;},&quot;mc_ACT_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcCasSlot&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcCasSlot2&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcRdCAS&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcWrCAS&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winInjTxn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winRmw&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;gt_data_ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winRank&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;tCWL&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrData&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataMask&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdData&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_ADR&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;135&quot;,&quot;physical_righ
+t&quot;:&quot;0&quot;},&quot;mc_BA&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_CKE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_CS_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_ODT&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dBufAdr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataAddr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataAddr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winBuf&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_act_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_adr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;16&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ba&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_bg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_par&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_cke&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;
+:&quot;0&quot;},&quot;ddr4_odt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_cs_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ck_t&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ck_c&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_reset_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dm_dbi_n&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dq&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dqs_c&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dqs_t&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_BG&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;C0_SYS_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:diff_clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:diff_clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;C0_CLOCK_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},
+{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;CLK_N&quot;:{&quot;physical_name&quot;:&quot;c0_sys_clk_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK_P&quot;:{&quot;physical_name&quot;:&quot;c0_sys_clk_p&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;C0_DDR4_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk_sync_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_r
+ight&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;C0_DDR4_CLOCK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1.665e+08&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.00&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;val
+ue_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;SYSTEM_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xml b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xml
new file mode 100644
index 0000000..ea283cd
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/phy_ddr4_udimm.xml
@@ -0,0 +1,8655 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_ddr4_udimm</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>C0_SYS_CLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.BOARD.ASSOCIATED_PARAM">C0_CLOCK_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; (spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_SYS_CLK_I</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_i</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK_I" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;No_Buffer&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACT_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_act_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_adr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ba</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_bg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>C_ID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CK_C</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ck_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CK_T</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ck_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CKE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_cke</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CS_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_cs_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DM_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dm_dbi_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dq</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQS_C</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dqs_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQS_T</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dqs_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ODT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_odt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_parity</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RESET_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4.BOARD.ASSOCIATED_PARAM">C0_DDR4_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TIMEPERIOD_PS</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEMORY_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEMORY_PART</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CS_ENABLED</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_MASK_ENABLED</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SLOT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CUSTOM_PARTS</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ADDR_MAP</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAS_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4" xilinx:dependency="( ( spirit:decode(id(&apos;PARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_CTRL</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="C0_DDR4_MEMORY_MAP_CTRL"/>
+      </spirit:slave>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_S_AXI_CTRL" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_ECC&apos;)) = true()() ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="C0_DDR4_MEMORY_MAP"/>
+      </spirit:slave>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_S_AXI" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_ARESETN</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_ARESETN" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_RESET</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ui_clk_sync_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_RESET" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_CLOCK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ui_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.PHASE">0.00</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.ASSOCIATED_BUSIF">C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.ASSOCIATED_RESET">c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_CLOCK" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT1</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT1" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT2</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT2" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT3</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT3" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT4</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT4" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SYSTEM_RESET</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_CTRL_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_CTRL_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_CTRL_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>C0_DDR4_MEMORY_MAP</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>C0_DDR4_ADDRESS_BLOCK</spirit:name>
+        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_MEM_SIZE&apos;))">8589934592</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:vendorExtensions>
+          <xilinx:addressBlockInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C0_DDR4_MEMORY_MAP.C0_DDR4_ADDRESS_BLOCK" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:addressBlockInfo>
+        </spirit:vendorExtensions>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>C0_DDR4_MEMORY_MAP_CTRL</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>C0_REG</spirit:name>
+        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:vendorExtensions>
+          <xilinx:addressBlockInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C0_DDR4_MEMORY_MAP_CTRL.C0_REG" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_ECC&apos;)) = true()() ))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:addressBlockInfo>
+        </spirit:vendorExtensions>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
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+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_elaborateports</spirit:name>
+        <spirit:displayName>Elaborate Ports</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b3e354e4</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_elaboratesubcores</spirit:name>
+        <spirit:displayName>Elaborate Sub-Cores</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.subcores</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaboratesubcores_view_fileset</spirit:localName>
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+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:fafdee37</spirit:value>
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+        <spirit:name>c0_init_calib_complete</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_init_calib_complete" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
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+      <spirit:port>
+        <spirit:name>dbg_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dbg_clk" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
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+      <spirit:port>
+        <spirit:name>c0_sys_clk_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_CS_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_ODT</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dBufAdr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rdDataAddr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wrDataAddr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>winBuf</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_act_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_adr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">16</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_ba</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_bg</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_par</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_cke</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_odt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_cs_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_ck_t</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_ck_c</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_reset_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dm_dbi_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dq</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dqs_c</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dqs_t</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_BG</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_wr_socket</spirit:name>
+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>wr_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_rd_socket</spirit:name>
+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>rd_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_CTRL_wr_socket</spirit:name>
+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>wr_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_CTRL_rd_socket</spirit:name>
+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>rd_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType">
+        <spirit:name>C0.DDR4_Mem_Add_Map</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>System_Clock</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.System_Clock" spirit:choiceRef="choice_list_2b96b8de">Differential</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.ControllerType</spirit:name>
+        <spirit:displayName>ControllerType</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>App Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">30</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.MEM_TYPE</spirit:name>
+        <spirit:displayName>MEM TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_LOC_1</spirit:name>
+        <spirit:displayName>BUFG LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_LOC_1">X0Y70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_LOC_2</spirit:name>
+        <spirit:displayName>BUFG LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_DIV_LOC_1</spirit:name>
+        <spirit:displayName>BUFG DIV LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_1">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_DIV_LOC_2</spirit:name>
+        <spirit:displayName>BUFG DIV LOC2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_2">X0Y10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_SLICE_LOC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB36_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB18_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_SLICE_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB36_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB18_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.MMCM_IDX_BANK</spirit:name>
+        <spirit:displayName>MMCM IDX BANK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.CENTER_BANK_CLOCK_REGION</spirit:name>
+        <spirit:displayName>CENTER BANK CLOCK REGION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.CENTER_BANK_CLOCK_REGION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.CENTER_BANK_MMCME3_ADV_SITE</spirit:name>
+        <spirit:displayName>CENTER BANK MMCME3 ADV SITE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.SYSCLK_CENTER_INFO</spirit:name>
+        <spirit:displayName>SYSCLK CENTER INFO</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_PHY</spirit:name>
+        <spirit:displayName>Ping Pong Phy</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CS_ADDR</spirit:name>
+        <spirit:displayName>CS Width Check</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CS_ADDR">30</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_VrefVoltage</spirit:name>
+        <spirit:displayName>Vref Voltage</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AL</spirit:name>
+        <spirit:displayName>Additive Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DQ_WIDTH</spirit:name>
+        <spirit:displayName>DQ WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nCK_PER_CLK</spirit:name>
+        <spirit:displayName>nCK PER CLK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DM_WIDTH</spirit:name>
+        <spirit:displayName>DM WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DQS_WIDTH</spirit:name>
+        <spirit:displayName>DQS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nCS_PER_RANK</spirit:name>
+        <spirit:displayName>nCS PER RANK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DEVICE_WIDTH</spirit:name>
+        <spirit:displayName>MEM DEVICE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_USE_DM_PORT</spirit:name>
+        <spirit:displayName>USE DM PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_USE_CS_PORT</spirit:name>
+        <spirit:displayName>USE CS PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ROW_WIDTH</spirit:name>
+        <spirit:displayName>ROW WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ADDR_WIDTH">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BANK_WIDTH</spirit:name>
+        <spirit:displayName>BANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BANK_WIDTH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BANK_GROUP_WIDTH</spirit:name>
+        <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BANK_GROUP_WIDTH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>LR_WIDTH</spirit:name>
+        <spirit:displayName>LR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LR_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CK_WIDTH</spirit:name>
+        <spirit:displayName>CK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CKE_WIDTH</spirit:name>
+        <spirit:displayName>CKE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CKE_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CS_WIDTH</spirit:name>
+        <spirit:displayName>CS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ODT_WIDTH</spirit:name>
+        <spirit:displayName>ODT WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEMORY_TYPE</spirit:name>
+        <spirit:displayName>MEMORY TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">UDIMMs</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEMORY_PART</spirit:name>
+        <spirit:displayName>MEMORY PART</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">MTA8ATF1G64AZ-2G3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DATA_MASK</spirit:name>
+        <spirit:displayName>DATA MASK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_COLUMN_WIDTH</spirit:name>
+        <spirit:displayName>COLUMN WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_SPEED_GRADE</spirit:name>
+        <spirit:displayName>SPEED GRADE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">083</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY</spirit:name>
+        <spirit:displayName>MEM DENSITY</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">8GB</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY_MB</spirit:name>
+        <spirit:displayName>MEM DENSITY MB</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY_GB</spirit:name>
+        <spirit:displayName>MEM DENSITY GB</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_COMP_DENSITY</spirit:name>
+        <spirit:displayName>COMP DENSITY</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">8Gb</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_COMP_WIDTH</spirit:name>
+        <spirit:displayName>MEM COMP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DATABITS_PER_STROBE</spirit:name>
+        <spirit:displayName>DATABITS PER STROBE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MODEL_SPEED_GRADE</spirit:name>
+        <spirit:displayName>MODEL SPEED GRADE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_833_Timing</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RANK_WIDTH</spirit:name>
+        <spirit:displayName>RANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IO_VOLTAGE</spirit:name>
+        <spirit:displayName>IO VOLTAGE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name>
+        <spirit:displayName>MIN PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MAX_PERIOD</spirit:name>
+        <spirit:displayName>MAX PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MR0</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MR2</spirit:name>
+        <spirit:displayName>Mode register_2 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nAL</spirit:name>
+        <spirit:displayName>Additive Latency in number of clock</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BURST_MODE</spirit:name>
+        <spirit:displayName>Burst Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BURST_TYPE</spirit:name>
+        <spirit:displayName>Burst Type</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CL</spirit:name>
+        <spirit:displayName>Cas Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CWL</spirit:name>
+        <spirit:displayName>Cas Write Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_OUTPUT_DRV</spirit:name>
+        <spirit:displayName>Output drive Strength</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RTT_NOM</spirit:name>
+        <spirit:displayName>RTT Nominal</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RTT_WR</spirit:name>
+        <spirit:displayName>RTT WR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM</spirit:name>
+        <spirit:displayName>Memory Name</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DBAW</spirit:name>
+        <spirit:displayName>DBAW</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCK</spirit:name>
+        <spirit:displayName>tCK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCK">1500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Configuration</spirit:name>
+        <spirit:displayName>Configuration</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCKE</spirit:name>
+        <spirit:displayName>tCKE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tFAW</spirit:name>
+        <spirit:displayName>tFAW</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW">14</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tFAW_dlr</spirit:name>
+        <spirit:displayName>tFAW_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tMRD</spirit:name>
+        <spirit:displayName>tMRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRAS</spirit:name>
+        <spirit:displayName>tRAS</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRAS">22</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRCD</spirit:name>
+        <spirit:displayName>tRCD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRCD">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tREFI</spirit:name>
+        <spirit:displayName>tREFI</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tREFI">5200</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRFC</spirit:name>
+        <spirit:displayName>tRFC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC">234</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRFC_dlr</spirit:name>
+        <spirit:displayName>tRFC_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">80</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRP</spirit:name>
+        <spirit:displayName>tRP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRP">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWR</spirit:name>
+        <spirit:displayName>tWR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWR">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD</spirit:name>
+        <spirit:displayName>tRRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRTP</spirit:name>
+        <spirit:displayName>tRTP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRTP">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_S</spirit:name>
+        <spirit:displayName>tRRD_S</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_S">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_L</spirit:name>
+        <spirit:displayName>tRRD_L</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_L">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_dlr</spirit:name>
+        <spirit:displayName>tRRD_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR</spirit:name>
+        <spirit:displayName>tWTR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR_S</spirit:name>
+        <spirit:displayName>tWTR_S</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_S">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR_L</spirit:name>
+        <spirit:displayName>tWTR_L</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_L">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tXPR</spirit:name>
+        <spirit:displayName>tXPR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tXPR">60</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQI</spirit:name>
+        <spirit:displayName>tZQI</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQCS</spirit:name>
+        <spirit:displayName>tZQCS</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQINIT</spirit:name>
+        <spirit:displayName>tZQINIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCCD_3ds</spirit:name>
+        <spirit:displayName>tCCD_3ds</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name>
+        <spirit:displayName>CLKOUTPHY_MODE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT0_DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUT1_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT1_DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+        <spirit:displayName>CLKFBOUT_MULT</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+        <spirit:displayName>DIVCLK DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CAL_INPUT_CLK_PERIOD</spirit:name>
+        <spirit:displayName>Calculated Input Clock Period</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKIN_PERIOD</spirit:name>
+        <spirit:displayName>CLKIN_PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name>
+        <spirit:displayName>High Range Supported frequency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DCI_CASCADE_CUTOFF</spirit:name>
+        <spirit:displayName>DCI Cascade Cutoff</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name>
+        <spirit:displayName>Is Faster Speed RAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_ID_WIDTH</spirit:name>
+        <spirit:displayName>AXI ID Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_SIZE</spirit:name>
+        <spirit:displayName>Memory Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">8589934592</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_UI_CLOCK</spirit:name>
+        <spirit:displayName>DDR4 UI CLOCK</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">166500000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CA_MIRROR</spirit:name>
+        <spirit:displayName>CA MIRROR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IS_CUSTOM</spirit:name>
+        <spirit:displayName>IS CUSTOM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name>
+        <spirit:displayName>AUTO AP COL A3</spirit:displayName>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MCS_ECC</spirit:name>
+        <spirit:displayName>MCS ECC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Slot</spirit:name>
+        <spirit:displayName>Slot Type</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_DATA_WIDTH</spirit:name>
+        <spirit:displayName>APP Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_MASK_WIDTH</spirit:name>
+        <spirit:displayName>APP Mask Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_MASK_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_StackHeight</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CUSTOM_PART_ATTRIBUTES</spirit:name>
+        <spirit:displayName>custom_part_attributes</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT1_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT1 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT2_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT2 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT3_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT3 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT4_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT4 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT1_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT1 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT2_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT2 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT3_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT3 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT4_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT4 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT0_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT0 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT1_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT1 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT1_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT2_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT2 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT3_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT3 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT4_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT4 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT6_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT6 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Debug_Signal</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Simulation_Mode</spirit:name>
+        <spirit:displayName>Simulation Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Ecc</spirit:name>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_09ec3310</spirit:name>
+      <spirit:enumeration>Single</spirit:enumeration>
+      <spirit:enumeration>Dual</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_157065e4</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+      <spirit:enumeration>10</spirit:enumeration>
+      <spirit:enumeration>11</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_165ed04b</spirit:name>
+      <spirit:enumeration>64</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_266493f0</spirit:name>
+      <spirit:enumeration>DDR4_SDRAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_28391b73</spirit:name>
+      <spirit:enumeration>1.2V</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_29a21725</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk0</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk1</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk2</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_2b96b8de</spirit:name>
+      <spirit:enumeration>Differential</spirit:enumeration>
+      <spirit:enumeration>No_Buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_301b19dd</spirit:name>
+      <spirit:enumeration>ON</spirit:enumeration>
+      <spirit:enumeration>OFF</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_30636008</spirit:name>
+      <spirit:enumeration>4:1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_30de7c39</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pcie_perstn</spirit:enumeration>
+      <spirit:enumeration>resetn</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_34c5244e</spirit:name>
+      <spirit:enumeration>Components</spirit:enumeration>
+      <spirit:enumeration>UDIMMs</spirit:enumeration>
+      <spirit:enumeration>SODIMMs</spirit:enumeration>
+      <spirit:enumeration>RDIMMs</spirit:enumeration>
+      <spirit:enumeration>LRDIMMs</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4665eb01</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4e3dbc0a</spirit:name>
+      <spirit:enumeration>SIMPLE_TG</spirit:enumeration>
+      <spirit:enumeration>ADVANCED_TG</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6330c9d2</spirit:name>
+      <spirit:enumeration>10</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_66456a11</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c0</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c1</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c2</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_67b045e5</spirit:name>
+      <spirit:enumeration>BFM</spirit:enumeration>
+      <spirit:enumeration>Unisim</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_687ca1a5</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>500</spirit:enumeration>
+      <spirit:enumeration>375</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>250</spirit:enumeration>
+      <spirit:enumeration>214</spirit:enumeration>
+      <spirit:enumeration>188</spirit:enumeration>
+      <spirit:enumeration>167</spirit:enumeration>
+      <spirit:enumeration>150</spirit:enumeration>
+      <spirit:enumeration>136</spirit:enumeration>
+      <spirit:enumeration>125</spirit:enumeration>
+      <spirit:enumeration>115</spirit:enumeration>
+      <spirit:enumeration>107</spirit:enumeration>
+      <spirit:enumeration>100</spirit:enumeration>
+      <spirit:enumeration>94</spirit:enumeration>
+      <spirit:enumeration>88</spirit:enumeration>
+      <spirit:enumeration>83</spirit:enumeration>
+      <spirit:enumeration>79</spirit:enumeration>
+      <spirit:enumeration>75</spirit:enumeration>
+      <spirit:enumeration>71</spirit:enumeration>
+      <spirit:enumeration>68</spirit:enumeration>
+      <spirit:enumeration>65</spirit:enumeration>
+      <spirit:enumeration>63</spirit:enumeration>
+      <spirit:enumeration>60</spirit:enumeration>
+      <spirit:enumeration>58</spirit:enumeration>
+      <spirit:enumeration>56</spirit:enumeration>
+      <spirit:enumeration>54</spirit:enumeration>
+      <spirit:enumeration>52</spirit:enumeration>
+      <spirit:enumeration>50</spirit:enumeration>
+      <spirit:enumeration>48</spirit:enumeration>
+      <spirit:enumeration>47</spirit:enumeration>
+      <spirit:enumeration>45</spirit:enumeration>
+      <spirit:enumeration>44</spirit:enumeration>
+      <spirit:enumeration>43</spirit:enumeration>
+      <spirit:enumeration>42</spirit:enumeration>
+      <spirit:enumeration>41</spirit:enumeration>
+      <spirit:enumeration>39</spirit:enumeration>
+      <spirit:enumeration>38</spirit:enumeration>
+      <spirit:enumeration>37</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+      <spirit:enumeration>35</spirit:enumeration>
+      <spirit:enumeration>34</spirit:enumeration>
+      <spirit:enumeration>33</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
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+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/phy_ddr4_udimm_phy.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>phy_ddr4_udimm</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="dummy"/>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>instance_path</spirit:name>
+          <spirit:value>inst/u_ddr_cal_riu/mcs0/inst/microblaze_I</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bootloop_file</spirit:name>
+          <spirit:value>sw/calibration_0/Debug/calibration_ddr.elf</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>endian</spirit:name>
+          <spirit:value>little</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>processor_type</spirit:name>
+          <spirit:value>MICROBLAZE-LE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>is_visible</spirit:name>
+          <spirit:value>false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>DDR4 Interface Generator for Ultrascale Architecture</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C0.ControllerType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ControllerType" spirit:choiceRef="choice_list_266493f0" spirit:order="2">DDR4_SDRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.ControllerType">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IOPowerReduction</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IOPowerReduction" spirit:choiceRef="choice_list_301b19dd" spirit:order="3">OFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_SysPorts</spirit:name>
+      <spirit:displayName>Auto assign static ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_SysPorts" spirit:order="4">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Phy_Only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Phy_Only" spirit:choiceRef="choice_pairs_01257c99" spirit:order="5">Phy_Only_Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_30de7c39" spirit:order="6">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RESET_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0_CLOCK_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE" spirit:choiceRef="choice_list_29a21725" spirit:order="7">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C0_CLOCK_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_FROM_PHY</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IS_FROM_PHY" spirit:order="8">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RECONFIG_XSDB_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" spirit:order="9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AL_SEL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AL_SEL" spirit:choiceRef="choice_list_ff0950bb" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Example_TG</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Example_TG" spirit:choiceRef="choice_list_4e3dbc0a" spirit:order="11">SIMPLE_TG</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.Example_TG">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Clamshell</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Clamshell" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_Clamshell">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.MIGRATION</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.MIGRATION" spirit:order="13">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_OP1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_OP1" spirit:order="14">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_OP2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_OP2" spirit:order="15">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_3DS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_3DS" spirit:order="16">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SET_DW_TO_40</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SET_DW_TO_40" spirit:order="17">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_TERM_SYSCLK</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_TERM_SYSCLK" spirit:order="18">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0_DDR4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE" spirit:choiceRef="choice_list_66456a11" spirit:order="19">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C0_DDR4_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TimePeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TimePeriod" spirit:order="20" spirit:minimum="750" spirit:maximum="1600" spirit:rangeType="long">1500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_InputClockPeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_InputClockPeriod" spirit:choiceRef="choice_pairs_05415bea" spirit:order="21">3333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Specify_MandD</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Specify_MandD" spirit:order="22">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" spirit:order="23" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CLKFBOUT_MULT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" spirit:order="24" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_DIVCLK_DIVIDE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" spirit:order="25" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CLKOUT0_DIVIDE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PhyClockRatio</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PhyClockRatio" spirit:choiceRef="choice_list_30636008" spirit:order="26">4:1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryType" spirit:choiceRef="choice_list_34c5244e" spirit:order="27">UDIMMs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryPart</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryPart" spirit:choiceRef="choice_list_6a9416ad" spirit:order="28">MTA8ATF1G64AZ-2G3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Slot</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Slot" spirit:choiceRef="choice_list_09ec3310" spirit:order="29">Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryVoltage</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryVoltage" spirit:choiceRef="choice_list_28391b73" spirit:order="30">1.2V</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataWidth" spirit:choiceRef="choice_list_165ed04b" spirit:order="31">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataMask</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataMask" spirit:choiceRef="choice_list_8d3f5284" spirit:order="32">DM_NO_DBI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ecc" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_Ecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MCS_ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MCS_ECC" spirit:order="34">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiSelection</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiSelection" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_AxiSelection">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3" spirit:order="36">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ordering</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ordering" spirit:choiceRef="choice_list_8b4f223f" spirit:order="37">Normal</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BurstLength</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BurstLength" spirit:choiceRef="choice_list_d8920bdd" spirit:order="38">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_BurstLength">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BurstType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BurstType" spirit:choiceRef="choice_list_df7e3f8b" spirit:order="39">Sequential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_OutputDriverImpedenceControl</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl" spirit:choiceRef="choice_list_ad101c66" spirit:order="40">RZQ/7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_OnDieTermination</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_OnDieTermination" spirit:choiceRef="choice_list_98f5c8fa" spirit:order="41">RZQ/6</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasLatency" spirit:choiceRef="choice_list_6330c9d2" spirit:order="42">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasWriteLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasWriteLatency" spirit:choiceRef="choice_list_ae57517c" spirit:order="43">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ChipSelect</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ChipSelect" spirit:order="44">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCKEShared</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCKEShared" spirit:order="45">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiDataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiDataWidth" spirit:choiceRef="choice_list_d6556846" spirit:order="46">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiArbitrationScheme</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme" spirit:choiceRef="choice_list_ed30197c" spirit:order="47">RD_PRI_REG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiNarrowBurst</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiNarrowBurst" spirit:order="48">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiAddressWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiAddressWidth" spirit:choiceRef="choice_list_e7093afb" spirit:order="49">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiIDWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiIDWidth" spirit:choiceRef="choice_list_157065e4" spirit:order="50">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Capacity</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Capacity" spirit:choiceRef="choice_list_a187d5e4" spirit:order="51">512</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Mem_Add_Map</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Mem_Add_Map" spirit:choiceRef="choice_list_c89503c8" spirit:order="52">ROW_COLUMN_BANK</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryName</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryName" spirit:order="53">MainMemory</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AutoPrecharge</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AutoPrecharge" spirit:order="54">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_AutoPrecharge">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_UserRefresh_ZQCS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS" spirit:order="55">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_UserRefresh_ZQCS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CustomParts</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CustomParts" spirit:order="56">no_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:parameterType>file_csv</xilinx:parameterType>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CustomParts">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCustom</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCustom" spirit:order="57">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SELF_REFRESH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SELF_REFRESH" spirit:order="58">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_SELF_REFRESH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" spirit:order="59">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_RESTORE_CRC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_RESTORE_CRC" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_RESTORE_CRC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT1_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="61">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT2_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="62">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT3_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="63">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT4_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="64">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6" spirit:order="65">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_ddr4_udimm</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>No_Controller</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.No_Controller" spirit:choiceRef="choice_list_4665eb01" spirit:order="100">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>System_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.System_Clock" spirit:choiceRef="choice_list_2b96b8de" spirit:order="200">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reference_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reference_Clock" spirit:choiceRef="choice_list_ef319ec8" spirit:order="300">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Debug_Signal</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Debug_Signal" spirit:choiceRef="choice_list_f3cd92fb" spirit:order="400">Disable</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IO_Power_Reduction</spirit:name>
+      <spirit:displayName>IO_Power_Reduction</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.IO_Power_Reduction" spirit:order="500">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DCI_Cascade</spirit:name>
+      <spirit:displayName>DCI Cascade</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DCI_Cascade" spirit:order="600">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Default_Bank_Selections</spirit:name>
+      <spirit:displayName>Default Bank Selections</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Default_Bank_Selections" spirit:order="700">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Simulation_Mode</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Simulation_Mode" spirit:choiceRef="choice_list_67b045e5" spirit:order="800">BFM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PARTIAL_RECONFIG_FLOW_MIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" spirit:order="801">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PARTIAL_RECONFIG_FLOW_MIG">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MCS_DBG_EN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MCS_DBG_EN" spirit:order="802">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_0" spirit:order="803" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_1" spirit:order="804" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_2" spirit:order="805" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_3" spirit:order="806" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0" spirit:order="807" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1" spirit:order="808" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2" spirit:order="809" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3" spirit:order="810" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_4</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4" spirit:order="811" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_5</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5" spirit:order="812" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_6</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6" spirit:order="813" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_7</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7" spirit:order="814" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_8</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8" spirit:order="815" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_9</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9" spirit:order="816" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_10</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10" spirit:order="817" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_11</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_11" spirit:order="818" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_12</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_12" spirit:order="819" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_13</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13" spirit:order="820" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_14</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14" spirit:order="821" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_15</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15" spirit:order="822" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_16</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16" spirit:order="823" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_17</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17" spirit:order="824" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BA_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BA_SKEW_0" spirit:order="825" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BA_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BA_SKEW_1" spirit:order="826" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BG_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BG_SKEW_0" spirit:order="827" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BG_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BG_SKEW_1" spirit:order="828" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_0" spirit:order="829" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_1" spirit:order="830" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_2" spirit:order="831" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_3" spirit:order="832" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_0" spirit:order="833" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_1" spirit:order="834" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_2" spirit:order="835" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_3" spirit:order="836" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ACT_SKEW</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ACT_SKEW" spirit:order="837" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PAR_SKEW</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PAR_SKEW" spirit:order="838" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_0" spirit:order="839" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_1" spirit:order="840" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_2" spirit:order="841" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_3" spirit:order="842" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_LR_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_LR_SKEW_0" spirit:order="843" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_LR_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_LR_SKEW_1" spirit:order="844" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TREFI</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TREFI" spirit:order="845">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TRFC</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TRFC" spirit:order="846">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TRFC_DLR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TRFC_DLR" spirit:order="847">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TXPR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TXPR" spirit:order="848">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TREFI</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TREFI" spirit:order="849">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TRFC</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TRFC" spirit:order="850">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TRFC_DLR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR" spirit:order="851">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TXPR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TXPR" spirit:order="852">5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.ADDR_WIDTH</spirit:name>
+      <spirit:displayName>ADDR WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ADDR_WIDTH" spirit:order="853">17</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.BANK_GROUP_WIDTH</spirit:name>
+      <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.BANK_GROUP_WIDTH" spirit:order="854">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.LR_WIDTH</spirit:name>
+      <spirit:displayName>LR WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.LR_WIDTH" spirit:order="855">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.CK_WIDTH</spirit:name>
+      <spirit:displayName>CK WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CK_WIDTH" spirit:order="856">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.CKE_WIDTH</spirit:name>
+      <spirit:displayName>CKE WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CKE_WIDTH" spirit:order="857">1</spirit:value>
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+      <spirit:displayName>CS WIDTH</spirit:displayName>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig
new file mode 100644
index 0000000..698f7e5
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig
@@ -0,0 +1,313 @@
+/******************************************************************************
+// (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+******************************************************************************/
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor             : Xilinx
+// \   \   \/     Version            : 1.1
+//  \   \         Application        : MIG
+//  /   /         Filename           : ddr4_v2_2_10_cal_rd_en.sv
+// /___/   /\     Date Last Modified : $Date: 2015/04/23 $
+// \   \  /  \    Date Created       : Thu Apr 18 2013
+//  \___\/\___\
+//
+// Device           : UltraScale
+// Design Name      : DDR4 SDRAM & DDR3 SDRAM
+// Purpose          :
+//                   ddr4_v2_2_10_cal_rd_en module
+// Reference        :
+// Revision History :
+//*****************************************************************************
+
+`timescale 1ns/100ps
+
+module ddr4_v2_2_10_cal_rd_en #(parameter
+    RANKS = 1
+   ,RL  = 11
+   ,EXTRA_CMD_DELAY  = 0
+   ,TCQ = 0.1
+)(
+    input clk
+   ,input rst
+
+   ,output [3:0] mc_clb2phy_rden
+   ,output [3:0] mc_clb2phy_rdcs0
+   ,output [3:0] mc_clb2phy_rdcs1
+
+   ,input [1:0] casSlot       // spyglass disable W498
+   ,input       mccasSlot2
+   ,input       rdCAS
+   ,input       calrdCAS
+   ,input       mcrdCAS
+   ,input [5:0] mCL0
+   ,input [5:0] mCL1
+   ,input [5:0] mCL2
+   ,input [5:0] mCL3
+   ,input [1:0] winRank
+   ,input [1:0] calRank
+   ,input [1:0] mcwinRank
+   ,input       calDone
+);
+
+wire [5:0] mCL[0:3];
+assign mCL[0] = mCL0;
+assign mCL[1] = mCL1;
+assign mCL[2] = mCL2;
+assign mCL[3] = mCL3;
+
+// This section generates the Gate enable mc_clb2phy_rden.
+// This logic is used in calibration and during normal operation.
+// Case 4'b0110 defines nominal timing where the trained mCL value equals RL.
+// This logic supports mCL = RL - 3, to enable the Gate 3tCK earlier than nominal RL.
+// Early gate enable is needed in Gate training, during normal operation
+// if command delays are very low, and to compensate for extra Gate delay
+// in the XiPhy that is allocated for VT tracking.  The logic also supports Gate
+// enable 4tCK later than nominal to allow for command fly-by routing.
+// The Gate enable can be further delayed to allow for extra command pipeline delays.
+// The Gate enable supports RL as low as 7 with no extra command delays, but other
+// blocks have higher low limits, so the minimum RL without extra command delays
+// is expected to be RL=8.
+
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+(* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+reg                      [18:0]                        rsMask[0:7];
+
+function [18:0] rs2mask;
+   input [3:0] diff;
+   input       slot2;
+case ({diff, slot2})
+   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
+     default: rs2mask = 19'b000_0000_1000_0000_1111;
+endcase
+endfunction
+
+always @(posedge clk) begin: blk1
+   reg [3:0] rsNdx;
+   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
+end
+
+always @(*) if (rst) begin
+   rdEn_nxt = 'b0;
+end else begin
+   rdEn_nxt =   (rdEn >> 4)
+                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                : 'b0);
+end
+
+always @(posedge clk)
+   rdEn <= #TCQ rdEn_nxt;
+
+assign mc_clb2phy_rden = rdEn[3:0];
+
+///////////////////////////////////////////////////////////////////
+// This logic is used during normal, multi-rank operation only. Durring cal or single
+// rank operation this logic is bypassed and the output of this section is static.
+// This section generates the read rank signals used by the XiPhy to select per rank
+// cal values during read operations.
+
+integer tck_index;
+localparam rdcs_msb = RL + 8 + 4*EXTRA_CMD_DELAY;
+
+reg  [rdcs_msb :0] rdcs0;
+reg  [rdcs_msb :0] rdcs0_mc;
+reg  [rdcs_msb :0] rdcs1;
+reg  [rdcs_msb :0] rdcs1_mc;
+reg  [6:0]           rdcs_rdcas_lsb_slot0;
+reg                  calDone_dly;
+
+// Extend newest cs (MSB) and shift out the oldest (low 4 LSBs)
+wire [rdcs_msb :0] rdcs0_shift  = { { 4 { rdcs0[rdcs_msb] } }, rdcs0[ rdcs_msb : 4] };
+wire [rdcs_msb :0] rdcs1_shift  = { { 4 { rdcs1[rdcs_msb] } }, rdcs1[ rdcs_msb : 4] };
+
+// Create rdcs mask for the current rdcas
+wire [6:0]         rdcs_rdcas_lsb_slot0_nxt  = { 1'b0, mCL0 } + 4*EXTRA_CMD_DELAY - 7'd7;
+wire [rdcs_msb :0] rdcs_rdcas_mask_slot0     = { ( rdcs_msb + 1 ) { 1'b1 } } << rdcs_rdcas_lsb_slot0;
+wire [rdcs_msb :0] rdcs_rdcas_mask           = rdcs_rdcas_mask_slot0 << 2*mccasSlot2;
+
+// Merge the shifted rdcs and winRank based on the rdcs mask for the current rdcas
+always @(*) begin
+   for (tck_index = 0; tck_index <= rdcs_msb; tck_index = tck_index + 1) begin
+     rdcs0_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[0] : rdcs0_shift[tck_index];
+     rdcs1_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[1] : rdcs1_shift[tck_index];
+   end
+end
+
+// Select mc or cal rdcs
+wire [rdcs_msb :0] rdcs0_nxt = calDone_dly ? rdcs0_mc : { rdcs_msb+1 { calRank[0] } };
+wire [rdcs_msb :0] rdcs1_nxt = calDone_dly ? rdcs1_mc : { rdcs_msb+1 { calRank[1] } };
+
+// Final 4 bit rdcs output
+assign mc_clb2phy_rdcs0 = rdcs0[3:0] & ~{ 4 { RANKS == 1 } };
+assign mc_clb2phy_rdcs1 = rdcs1[3:0] & ~{ 4 { RANKS == 1 } };
+
+// Flops
+always @(posedge clk) begin
+  rdcs_rdcas_lsb_slot0 <= #TCQ rdcs_rdcas_lsb_slot0_nxt;
+  calDone_dly          <= #TCQ calDone;
+end
+
+// Reset flops
+always @(posedge clk) if (rst) begin
+  rdcs0 <= #TCQ '0;
+  rdcs1 <= #TCQ '0;
+end else begin
+  rdcs0 <= #TCQ rdcs0_nxt;
+  rdcs1 <= #TCQ rdcs1_nxt;
+end
+
+
+//synopsys translate_off
+
+`ifdef MEM_INTERNAL
+// Events - When asserted high in a test that passes all verification checks, these coverage
+//          properties indicate that a functional coverage event has been hit.
+// ---------------------------------------------------------------------------------------------
+
+// Minimum mCL in normal operation
+//wire   e_mc_rd_en_000 = ( ( mCL0 + 4*EXTRA_CMD_DELAY ) == 13 ) & calDone & ~( RANKS == 1 ) & rdCAS;
+//always @(posedge clk) mc_rd_en_000: if (~rst) cover property (e_mc_rd_en_000);
+
+
+// Asserts - When asserted high, an illegal condition has been detected and the test has failed.
+// ---------------------------------------------------------------------------------------------
+
+// Check for illegal rank switch in rdEn and rdcs.  rdEn gap must be at least 2tCK wide.  rdcs must be stable for 2tCK after rdEn de-assertion.
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdEn;
+reg                      [rdcs_msb :0]                 a_rdcs0_dly;
+reg                      [rdcs_msb :0]                 a_rdcs1_dly;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0;
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0_nxt = { rdcs0, a_rdcs0_dly[3:0] };
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1;
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1_nxt = { rdcs1, a_rdcs1_dly[3:0] };
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY -1 :0] a_rdEn_falling_edge = ~a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY :1] & a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY -1 :0];
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold0_fail;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold1_fail;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_gap_fail;
+always @(*) begin
+   for (tck_index = 0; tck_index < RL+12 + 4*EXTRA_CMD_DELAY -2; tck_index = tck_index + 1) begin
+     a_rdEn_hold0_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+1] ) | ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+2] ) );
+     a_rdEn_hold1_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+1] ) | ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+2] ) );
+     a_rdEn_gap_fail[tck_index]   = calDone & a_rdEn_falling_edge[tck_index] & a_rdEn[tck_index+2];
+   end
+end
+always @(posedge clk) if (rst) begin
+         a_rdEn      <= #TCQ '0;
+         a_rdcs0_dly <= #TCQ '0;
+         a_rdcs1_dly <= #TCQ '0;
+         a_rdcs0     <= #TCQ '0;
+         a_rdcs1     <= #TCQ '0;
+end else begin
+         a_rdEn      <= #TCQ rdEn;
+         a_rdcs0_dly <= #TCQ rdcs0;
+         a_rdcs1_dly <= #TCQ rdcs1;
+         a_rdcs0     <= #TCQ a_rdcs0_nxt;
+         a_rdcs1     <= #TCQ a_rdcs1_nxt;
+end
+
+// rdcs0 not held for 2tCK after end of burst
+wire a_mc_rd_en_000_hld = calDone & ( | a_rdEn_hold0_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_000_hld);
+
+// rdcs1 not held for 2tCK after end of burst
+wire a_mc_rd_en_001_hld = calDone & ( | a_rdEn_hold1_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_001_hld);
+
+// rdEn not held low for 2tCK after end of burst
+wire a_mc_rd_en_002_hld = calDone & ( | a_rdEn_gap_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_002_hld);
+
+// mCL0 is less than RL-3
+wire a_mc_rd_en_003_ovf = ( mCL0 < (RL - 3) ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_003_ovf);
+
+// mCL1 is less than RL-3
+wire a_mc_rd_en_004_ovf = ( mCL1 < (RL - 3) ) & ( mCL1 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_004_ovf);
+
+// mCL2 is less than RL-3
+wire a_mc_rd_en_005_ovf = ( mCL2 < (RL - 3) ) & ( mCL2 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_005_ovf);
+
+// mCL3 is less than RL-3
+wire a_mc_rd_en_006_ovf = ( mCL3 < (RL - 3) ) & ( mCL3 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_006_ovf);
+
+
+`endif
+//synopsys translate_on
+
+endmodule
+
+
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej
new file mode 100644
index 0000000..abf0911
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej
@@ -0,0 +1,124 @@
+--- U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv
++++ /dev/null
+@@ -114,55 +114,86 @@
+ 
+ reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg                      [18:0]                        rsMask[0:7];
++reg                      [19:0]                        rsMask[0:15];
+ 
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+    input [3:0] diff;
+    input       slot2;
+-case ({diff, slot2})
+-   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+-   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+-   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+-   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++   input       slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++    6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++   6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++    6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++   6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++    6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++   6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++    6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+      default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+ 
+ always @(posedge clk) begin: blk1
+-   reg [3:0] rsNdx;
+-   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+-      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++   reg [4:0] rsNdx;
++   for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+ 
+ always @(*) if (rst) begin
+    rdEn_nxt = 'b0;
+ end else begin
+    rdEn_nxt =   (rdEn >> 4)
+-                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++                | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                 : 'b0);
+ end
+ 
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv.rej
new file mode 100644
index 0000000..217d7e9
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv.rej
@@ -0,0 +1,31 @@
+--- U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv
++++ /dev/null
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register.  These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = (   ALL_WR_LATENCY       / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 =   ( ALL_WR_LATENCY     ) % 4;
++localparam OFFSET_CASSLOT1 =   ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 =   ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 =   ( ALL_WR_LATENCY + 3 ) % 4;
+ 
+ integer i;
+ 
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc.  mccasSlot2 is timing critical.
+ reg  [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone    ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric        = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric        = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++                         (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+ 
+ // tCK offset for mc.  mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++                         (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+ 
+ // Output enable shift register load value for cal and mc.  mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf,   calRank, OFFSET_CASSLOT2[1:0], 1'b1};
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd
new file mode 100644
index 0000000..c114c72
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bd
@@ -0,0 +1,513 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0xBCE55F3980178BC9",
+      "design_src": "SBD",
+      "device": "xcu200-fsgd2104-2-e",
+      "name": "bd_afa8",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "scoped": "true",
+      "synth_flow_mode": "None",
+      "tool_version": "2020.2",
+      "validated": "true"
+    },
+    "design_tree": {
+      "microblaze_I": "",
+      "rst_0": "",
+      "ilmb": "",
+      "dlmb": "",
+      "dlmb_cntlr": "",
+      "ilmb_cntlr": "",
+      "lmb_bram_I": "",
+      "second_dlmb_cntlr": "",
+      "second_ilmb_cntlr": "",
+      "second_lmb_bram_I": "",
+      "iomodule_0": ""
+    },
+    "interface_ports": {
+      "IO": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:mcsio_bus_rtl:1.0"
+      },
+      "TRACE": {
+        "mode": "Master",
+        "vlnv": "xilinx.com:interface:mbtrace_rtl:2.0"
+      }
+    },
+    "ports": {
+      "Clk": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "ASSOCIATED_ASYNC_RESET": {
+            "value": "Reset"
+          },
+          "CLK_DOMAIN": {
+            "value": "bd_afa8_Clk",
+            "value_src": "constant"
+          },
+          "FREQ_HZ": {
+            "value": "100000000"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.000",
+            "value_src": "default"
+          }
+        }
+      },
+      "Reset": {
+        "type": "rst",
+        "direction": "I",
+        "parameters": {
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "POLARITY": {
+            "value": "ACTIVE_HIGH"
+          }
+        }
+      }
+    },
+    "components": {
+      "microblaze_I": {
+        "vlnv": "xilinx.com:ip:microblaze:11.0",
+        "xci_name": "bd_afa8_microblaze_I_0",
+        "parameters": {
+          "C_ASYNC_WAKEUP": {
+            "value": "3"
+          },
+          "C_DEBUG_ENABLED": {
+            "value": "0"
+          },
+          "C_FAULT_TOLERANT": {
+            "value": "0"
+          },
+          "C_INSTANCE": {
+            "value": "mb_microblaze_0"
+          },
+          "C_PC_WIDTH": {
+            "value": "17"
+          },
+          "C_TRACE": {
+            "value": "1"
+          },
+          "C_USE_BARREL": {
+            "value": "1"
+          },
+          "C_USE_DIV": {
+            "value": "1"
+          },
+          "C_USE_EXT_BRK": {
+            "value": "0"
+          },
+          "C_USE_EXT_NM_BRK": {
+            "value": "0"
+          },
+          "C_USE_HW_MUL": {
+            "value": "1"
+          },
+          "C_USE_PCMP_INSTR": {
+            "value": "1"
+          },
+          "C_USE_REORDER_INSTR": {
+            "value": "0"
+          }
+        },
+        "addressing": {
+          "address_spaces": {
+            "Data": {
+              "range": "4G",
+              "width": "32"
+            },
+            "Instruction": {
+              "range": "4G",
+              "width": "32"
+            }
+          }
+        },
+        "interface_ports": {
+          "DLMB": {
+            "mode": "Master",
+            "address_space_ref": "Data",
+            "base_address": {
+              "minimum": "0x00000000",
+              "maximum": "0xFFFFFFFF",
+              "width": "32"
+            }
+          },
+          "ILMB": {
+            "mode": "Master",
+            "address_space_ref": "Instruction",
+            "base_address": {
+              "minimum": "0x00000000",
+              "maximum": "0xFFFFFFFF",
+              "width": "32"
+            }
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_PROCESSOR": {
+            "value": "microblaze-le > bd_afa8 dlmb_cntlr",
+            "value_src": "default"
+          },
+          "KEEP_HIERARCHY": {
+            "value": "yes",
+            "value_src": "default"
+          }
+        }
+      },
+      "rst_0": {
+        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
+        "xci_name": "bd_afa8_rst_0_0"
+      },
+      "ilmb": {
+        "vlnv": "xilinx.com:ip:lmb_v10:3.0",
+        "xci_name": "bd_afa8_ilmb_0",
+        "parameters": {
+          "C_LMB_NUM_SLAVES": {
+            "value": "2"
+          }
+        },
+        "interface_ports": {
+          "LMB_M": {
+            "mode": "MirroredMaster",
+            "bridges": [
+              "LMB_Sl_0",
+              "LMB_Sl_1"
+            ]
+          }
+        }
+      },
+      "dlmb": {
+        "vlnv": "xilinx.com:ip:lmb_v10:3.0",
+        "xci_name": "bd_afa8_dlmb_0",
+        "parameters": {
+          "C_LMB_NUM_SLAVES": {
+            "value": "3"
+          }
+        },
+        "interface_ports": {
+          "LMB_M": {
+            "mode": "MirroredMaster",
+            "bridges": [
+              "LMB_Sl_0",
+              "LMB_Sl_1",
+              "LMB_Sl_2"
+            ]
+          }
+        }
+      },
+      "dlmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_afa8_dlmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000000000FFFF"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0010000"
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_ADDRESS_SPACE": {
+            "value": "byte  0x00000000 32 >  bd_afa8 lmb_bram_I bd_afa8 second_lmb_bram_I",
+            "value_src": "default"
+          },
+          "KEEP_HIERARCHY": {
+            "value": "yes",
+            "value_src": "default"
+          }
+        }
+      },
+      "ilmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_afa8_ilmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000000000FFFF"
+          },
+          "C_MASK": {
+            "value": "0x0000000080010000"
+          }
+        }
+      },
+      "lmb_bram_I": {
+        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
+        "xci_name": "bd_afa8_lmb_bram_I_0",
+        "parameters": {
+          "Memory_Type": {
+            "value": "True_Dual_Port_RAM"
+          }
+        }
+      },
+      "second_dlmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_afa8_second_dlmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000010000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x0000000000017FFF"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0010000"
+          }
+        },
+        "hdl_attributes": {
+          "BMM_INFO_ADDRESS_RANGE": {
+            "value": " ",
+            "value_src": "default"
+          }
+        }
+      },
+      "second_ilmb_cntlr": {
+        "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+        "xci_name": "bd_afa8_second_ilmb_cntlr_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000000010000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x0000000000017FFF"
+          },
+          "C_MASK": {
+            "value": "0x0000000080010000"
+          }
+        }
+      },
+      "second_lmb_bram_I": {
+        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
+        "xci_name": "bd_afa8_second_lmb_bram_I_0",
+        "parameters": {
+          "Memory_Type": {
+            "value": "True_Dual_Port_RAM"
+          }
+        }
+      },
+      "iomodule_0": {
+        "vlnv": "xilinx.com:ip:iomodule:3.1",
+        "xci_name": "bd_afa8_iomodule_0_0",
+        "parameters": {
+          "C_BASEADDR": {
+            "value": "0x0000000080000000"
+          },
+          "C_HIGHADDR": {
+            "value": "0x000000008000FFFF"
+          },
+          "C_INSTANCE": {
+            "value": "iomodule"
+          },
+          "C_INTC_ADDR_WIDTH": {
+            "value": "17"
+          },
+          "C_INTC_HAS_FAST": {
+            "value": "1"
+          },
+          "C_INTC_USE_IRQ_OUT": {
+            "value": "1"
+          },
+          "C_IO_BASEADDR": {
+            "value": "0x00000000C0000000"
+          },
+          "C_IO_HIGHADDR": {
+            "value": "0x00000000FFFFFFFF"
+          },
+          "C_IO_MASK": {
+            "value": "0x00000000C0000000"
+          },
+          "C_MASK": {
+            "value": "0x00000000C0000000"
+          },
+          "C_USE_IO_BUS": {
+            "value": "1"
+          }
+        }
+      }
+    },
+    "interface_nets": {
+      "iomodule_0_IO": {
+        "interface_ports": [
+          "IO",
+          "iomodule_0/IO_BUS"
+        ]
+      },
+      "dlmb_sl_0": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_0",
+          "dlmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb_port_2": {
+        "interface_ports": [
+          "second_dlmb_cntlr/BRAM_PORT",
+          "second_lmb_bram_I/BRAM_PORTA"
+        ]
+      },
+      "dlmb_port": {
+        "interface_ports": [
+          "dlmb_cntlr/BRAM_PORT",
+          "lmb_bram_I/BRAM_PORTA"
+        ]
+      },
+      "ilmb_sl_0": {
+        "interface_ports": [
+          "ilmb/LMB_Sl_0",
+          "ilmb_cntlr/SLMB"
+        ]
+      },
+      "ilmb_port_2": {
+        "interface_ports": [
+          "second_ilmb_cntlr/BRAM_PORT",
+          "second_lmb_bram_I/BRAM_PORTB"
+        ]
+      },
+      "microblaze_I_Trace": {
+        "interface_ports": [
+          "TRACE",
+          "microblaze_I/TRACE"
+        ]
+      },
+      "dlmb_sl_1": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_1",
+          "iomodule_0/SLMB"
+        ]
+      },
+      "ilmb_port": {
+        "interface_ports": [
+          "ilmb_cntlr/BRAM_PORT",
+          "lmb_bram_I/BRAM_PORTB"
+        ]
+      },
+      "dlmb_sl_2": {
+        "interface_ports": [
+          "dlmb/LMB_Sl_2",
+          "second_dlmb_cntlr/SLMB"
+        ]
+      },
+      "ilmb_sl_1": {
+        "interface_ports": [
+          "ilmb/LMB_Sl_1",
+          "second_ilmb_cntlr/SLMB"
+        ]
+      },
+      "dlmb": {
+        "interface_ports": [
+          "microblaze_I/DLMB",
+          "dlmb/LMB_M"
+        ]
+      },
+      "ilmb": {
+        "interface_ports": [
+          "microblaze_I/ILMB",
+          "ilmb/LMB_M"
+        ]
+      }
+    },
+    "nets": {
+      "Clk2": {
+        "ports": [
+          "Clk",
+          "microblaze_I/Clk",
+          "ilmb/LMB_Clk",
+          "dlmb/LMB_Clk",
+          "dlmb_cntlr/LMB_Clk",
+          "ilmb_cntlr/LMB_Clk",
+          "second_dlmb_cntlr/LMB_Clk",
+          "second_ilmb_cntlr/LMB_Clk",
+          "iomodule_0/Clk",
+          "rst_0/slowest_sync_clk"
+        ]
+      },
+      "Reset": {
+        "ports": [
+          "Reset",
+          "rst_0/ext_reset_in"
+        ]
+      },
+      "MB_Reset": {
+        "ports": [
+          "rst_0/mb_reset",
+          "microblaze_I/Reset"
+        ]
+      },
+      "LMB_Rst2": {
+        "ports": [
+          "rst_0/bus_struct_reset",
+          "ilmb/SYS_Rst",
+          "dlmb/SYS_Rst",
+          "ilmb_cntlr/LMB_Rst",
+          "dlmb_cntlr/LMB_Rst",
+          "second_ilmb_cntlr/LMB_Rst",
+          "second_dlmb_cntlr/LMB_Rst"
+        ]
+      },
+      "IO_Rst": {
+        "ports": [
+          "rst_0/peripheral_reset",
+          "iomodule_0/Rst"
+        ]
+      }
+    },
+    "addressing": {
+      "/microblaze_I": {
+        "address_spaces": {
+          "Data": {
+            "segments": {
+              "SEG_dlmb_cntlr_Mem": {
+                "address_block": "/dlmb_cntlr/SLMB/Mem",
+                "offset": "0x00000000",
+                "range": "64K"
+              },
+              "SEG_iomodule_0_IO": {
+                "address_block": "/iomodule_0/SLMB/IO",
+                "offset": "0xC0000000",
+                "range": "1G"
+              },
+              "SEG_iomodule_0_Reg": {
+                "address_block": "/iomodule_0/SLMB/Reg",
+                "offset": "0x80000000",
+                "range": "64K"
+              },
+              "SEG_second_dlmb_cntlr_Mem": {
+                "address_block": "/second_dlmb_cntlr/SLMB/Mem",
+                "offset": "0x00010000",
+                "range": "32K"
+              }
+            }
+          },
+          "Instruction": {
+            "segments": {
+              "SEG_ilmb_cntlr_Mem": {
+                "address_block": "/ilmb_cntlr/SLMB/Mem",
+                "offset": "0x00000000",
+                "range": "64K"
+              },
+              "SEG_second_ilmb_cntlr_Mem": {
+                "address_block": "/second_ilmb_cntlr/SLMB/Mem",
+                "offset": "0x00010000",
+                "range": "32K"
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml
new file mode 100644
index 0000000..64d4f45
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/bd_afa8.bxml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="39">
+  <CompositeFile CompositeFileTopName="bd_afa8" CanBeSetAsTop="true" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="RESET" Timestamp="1646750766"/>
+    <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1646750766"/>
+    <Generation Name="SIMULATION" State="RESET" Timestamp="1646750766"/>
+    <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1646750766"/>
+    <FileCollection Name="SOURCES" Type="SOURCES">
+      <File Name="ip/ip_0/bd_afa8_microblaze_I_0.xci" Type="IP">
+        <Instance HierarchyPath="microblaze_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_1/bd_afa8_rst_0_0.xci" Type="IP">
+        <Instance HierarchyPath="rst_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_2/bd_afa8_ilmb_0.xci" Type="IP">
+        <Instance HierarchyPath="ilmb"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_3/bd_afa8_dlmb_0.xci" Type="IP">
+        <Instance HierarchyPath="dlmb"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_4/bd_afa8_dlmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="dlmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_5/bd_afa8_ilmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="ilmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_6/bd_afa8_lmb_bram_I_0.xci" Type="IP">
+        <Instance HierarchyPath="lmb_bram_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="second_dlmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci" Type="IP">
+        <Instance HierarchyPath="second_ilmb_cntlr"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci" Type="IP">
+        <Instance HierarchyPath="second_lmb_bram_I"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip/ip_10/bd_afa8_iomodule_0_0.xci" Type="IP">
+        <Instance HierarchyPath="iomodule_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+    </FileCollection>
+  </CompositeFile>
+</Root>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v
new file mode 100644
index 0000000..2347719
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/hdl/bd_afa8_wrapper.v
@@ -0,0 +1,173 @@
+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Command: generate_target bd_afa8_wrapper.bd
+//Design : bd_afa8_wrapper
+//Purpose: IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module bd_afa8_wrapper
+   (Clk,
+    IO_addr_strobe,
+    IO_address,
+    IO_byte_enable,
+    IO_read_data,
+    IO_read_strobe,
+    IO_ready,
+    IO_write_data,
+    IO_write_strobe,
+    Reset,
+    TRACE_data_access,
+    TRACE_data_address,
+    TRACE_data_byte_enable,
+    TRACE_data_read,
+    TRACE_data_write,
+    TRACE_data_write_value,
+    TRACE_dcache_hit,
+    TRACE_dcache_rdy,
+    TRACE_dcache_read,
+    TRACE_dcache_req,
+    TRACE_delay_slot,
+    TRACE_ex_piperun,
+    TRACE_exception_kind,
+    TRACE_exception_taken,
+    TRACE_icache_hit,
+    TRACE_icache_rdy,
+    TRACE_icache_req,
+    TRACE_instruction,
+    TRACE_jump_hit,
+    TRACE_jump_taken,
+    TRACE_mb_halted,
+    TRACE_mem_piperun,
+    TRACE_msr_reg,
+    TRACE_new_reg_value,
+    TRACE_of_piperun,
+    TRACE_pc,
+    TRACE_pid_reg,
+    TRACE_reg_addr,
+    TRACE_reg_write,
+    TRACE_valid_instr);
+  input Clk;
+  output IO_addr_strobe;
+  output [31:0]IO_address;
+  output [3:0]IO_byte_enable;
+  input [31:0]IO_read_data;
+  output IO_read_strobe;
+  input IO_ready;
+  output [31:0]IO_write_data;
+  output IO_write_strobe;
+  input Reset;
+  output TRACE_data_access;
+  output [0:31]TRACE_data_address;
+  output [0:3]TRACE_data_byte_enable;
+  output TRACE_data_read;
+  output TRACE_data_write;
+  output [0:31]TRACE_data_write_value;
+  output TRACE_dcache_hit;
+  output TRACE_dcache_rdy;
+  output TRACE_dcache_read;
+  output TRACE_dcache_req;
+  output TRACE_delay_slot;
+  output TRACE_ex_piperun;
+  output [0:4]TRACE_exception_kind;
+  output TRACE_exception_taken;
+  output TRACE_icache_hit;
+  output TRACE_icache_rdy;
+  output TRACE_icache_req;
+  output [0:31]TRACE_instruction;
+  output TRACE_jump_hit;
+  output TRACE_jump_taken;
+  output TRACE_mb_halted;
+  output TRACE_mem_piperun;
+  output [0:14]TRACE_msr_reg;
+  output [0:31]TRACE_new_reg_value;
+  output TRACE_of_piperun;
+  output [0:31]TRACE_pc;
+  output [0:7]TRACE_pid_reg;
+  output [0:4]TRACE_reg_addr;
+  output TRACE_reg_write;
+  output TRACE_valid_instr;
+
+  wire Clk;
+  wire IO_addr_strobe;
+  wire [31:0]IO_address;
+  wire [3:0]IO_byte_enable;
+  wire [31:0]IO_read_data;
+  wire IO_read_strobe;
+  wire IO_ready;
+  wire [31:0]IO_write_data;
+  wire IO_write_strobe;
+  wire Reset;
+  wire TRACE_data_access;
+  wire [0:31]TRACE_data_address;
+  wire [0:3]TRACE_data_byte_enable;
+  wire TRACE_data_read;
+  wire TRACE_data_write;
+  wire [0:31]TRACE_data_write_value;
+  wire TRACE_dcache_hit;
+  wire TRACE_dcache_rdy;
+  wire TRACE_dcache_read;
+  wire TRACE_dcache_req;
+  wire TRACE_delay_slot;
+  wire TRACE_ex_piperun;
+  wire [0:4]TRACE_exception_kind;
+  wire TRACE_exception_taken;
+  wire TRACE_icache_hit;
+  wire TRACE_icache_rdy;
+  wire TRACE_icache_req;
+  wire [0:31]TRACE_instruction;
+  wire TRACE_jump_hit;
+  wire TRACE_jump_taken;
+  wire TRACE_mb_halted;
+  wire TRACE_mem_piperun;
+  wire [0:14]TRACE_msr_reg;
+  wire [0:31]TRACE_new_reg_value;
+  wire TRACE_of_piperun;
+  wire [0:31]TRACE_pc;
+  wire [0:7]TRACE_pid_reg;
+  wire [0:4]TRACE_reg_addr;
+  wire TRACE_reg_write;
+  wire TRACE_valid_instr;
+
+  bd_afa8 bd_afa8_i
+       (.Clk(Clk),
+        .IO_addr_strobe(IO_addr_strobe),
+        .IO_address(IO_address),
+        .IO_byte_enable(IO_byte_enable),
+        .IO_read_data(IO_read_data),
+        .IO_read_strobe(IO_read_strobe),
+        .IO_ready(IO_ready),
+        .IO_write_data(IO_write_data),
+        .IO_write_strobe(IO_write_strobe),
+        .Reset(Reset),
+        .TRACE_data_access(TRACE_data_access),
+        .TRACE_data_address(TRACE_data_address),
+        .TRACE_data_byte_enable(TRACE_data_byte_enable),
+        .TRACE_data_read(TRACE_data_read),
+        .TRACE_data_write(TRACE_data_write),
+        .TRACE_data_write_value(TRACE_data_write_value),
+        .TRACE_dcache_hit(TRACE_dcache_hit),
+        .TRACE_dcache_rdy(TRACE_dcache_rdy),
+        .TRACE_dcache_read(TRACE_dcache_read),
+        .TRACE_dcache_req(TRACE_dcache_req),
+        .TRACE_delay_slot(TRACE_delay_slot),
+        .TRACE_ex_piperun(TRACE_ex_piperun),
+        .TRACE_exception_kind(TRACE_exception_kind),
+        .TRACE_exception_taken(TRACE_exception_taken),
+        .TRACE_icache_hit(TRACE_icache_hit),
+        .TRACE_icache_rdy(TRACE_icache_rdy),
+        .TRACE_icache_req(TRACE_icache_req),
+        .TRACE_instruction(TRACE_instruction),
+        .TRACE_jump_hit(TRACE_jump_hit),
+        .TRACE_jump_taken(TRACE_jump_taken),
+        .TRACE_mb_halted(TRACE_mb_halted),
+        .TRACE_mem_piperun(TRACE_mem_piperun),
+        .TRACE_msr_reg(TRACE_msr_reg),
+        .TRACE_new_reg_value(TRACE_new_reg_value),
+        .TRACE_of_piperun(TRACE_of_piperun),
+        .TRACE_pc(TRACE_pc),
+        .TRACE_pid_reg(TRACE_pid_reg),
+        .TRACE_reg_addr(TRACE_reg_addr),
+        .TRACE_reg_write(TRACE_reg_write),
+        .TRACE_valid_instr(TRACE_valid_instr));
+endmodule
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci
new file mode 100644
index 0000000..1c2d623
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xci
@@ -0,0 +1,1032 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>bd_afa8_microblaze_I_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze" spirit:version="11.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S10_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S11_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S12_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S13_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S14_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S15_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S1_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S3_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S4_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S5_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S6_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S7_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S8_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S8_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S8_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S8_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S8_AXIS.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S8_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S9_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S9_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S9_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S9_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_D_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EDGE_IS_POSITIVE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FAULT_TOLERANT" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_IS_EDGE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_I_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUMBER_OF_PC_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PC_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TRACE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_BARREL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_DIV" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_HW_MUL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_INTERRUPT" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_NON_SECURE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_PCMP_INSTR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Interrupt&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Interrupt_Address&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Interrupt_Ack&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Instr_Addr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Instr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;IFetch&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;I_AS&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IReady&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IWAIT&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ICE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IUE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Data_Addr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physica
+l_right&quot;:&quot;31&quot;},&quot;Data_Read&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Data_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;D_AS&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Read_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Write_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DReady&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DWait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DCE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;DUE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Trace_Instruction&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Valid_Instr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_PC&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Reg_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,
+&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Reg_Addr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;},&quot;Trace_MSR_Reg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;},&quot;Trace_PID_Reg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;},&quot;Trace_New_Reg_Value&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Exception_Taken&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Exception_Kind&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;},&quot;Trace_Jump_Taken&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Delay_Slot&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Address&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Data_Write_Value&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Trace_Data_Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Trace_Data_Access&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:
+&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Read&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Data_Write&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Rdy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_DCache_Read&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_ICache_Rdy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_OF_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_EX_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_MEM_PipeRun&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_MB_Ha
+lted&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Trace_Jump_Hit&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;Reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;
+value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:
+[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;INTERRUPT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbinterrupt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbinterrupt_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;SENSITIVITY&quot;:[{&quot;value&quot;:&quot;LEVEL_HIGH&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LOW_LATENCY&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ACK&quot;:{&quot;physical_name&quot;:&quot;Interrupt_Ack&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;1&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;Interrupt_Address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;INTERRUPT&quot;:{&quot;physical_name&quot;:&quot;Interrupt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;DLMB&quot;:{&quot;vl
+nv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;Data_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;D_AS&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;Byte_Enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;DCE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical
+_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Data_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;Read_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;DReady&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;DUE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;DWait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;Data_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;Write_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ILMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;
+master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_ONLY&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;Instr_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;I_AS&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;ICE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;IFetch&quot;,&quot;phy
+sical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IReady&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;IUE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;IWAIT&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;TRACE&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbtrace:2.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbtrace_rtl:2.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;DATA_ACCESS&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_ADDRESS&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DATA_BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Byte_Enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;DATA_READ&quot;:{&quot;physi
+cal_name&quot;:&quot;Trace_Data_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE_VALUE&quot;:{&quot;physical_name&quot;:&quot;Trace_Data_Write_Value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DCACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_READ&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;Trace_DCache_Req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DELAY_SLOT&quot;:{&quot;physical_name&quot;:&quot;Trace_Delay_Slot&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;log
+ical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EX_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_EX_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EXCEPTION_KIND&quot;:{&quot;physical_name&quot;:&quot;Trace_Exception_Kind&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;EXCEPTION_TAKEN&quot;:{&quot;physical_name&quot;:&quot;Trace_Exception_Taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;Trace_ICache_Req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;INSTRUCTION&quot;:{&quot;physical_name&quot;:&quot;Trace_Instruction&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;JUMP_HIT&quot;:{&quot;physical_name&quot;:&quot;Tr
+ace_Jump_Hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;JUMP_TAKEN&quot;:{&quot;physical_name&quot;:&quot;Trace_Jump_Taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MB_HALTED&quot;:{&quot;physical_name&quot;:&quot;Trace_MB_Halted&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MEM_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_MEM_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MSR_REG&quot;:{&quot;physical_name&quot;:&quot;Trace_MSR_Reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;14&quot;},&quot;NEW_REG_VALUE&quot;:{&quot;physical_name&quot;:&quot;Trace_New_Reg_Value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;OF_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;Trace_OF_PipeRun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PC&quot;:{&quot;physical_name&quot;:&quot;Trace_PC&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;PID
+_REG&quot;:{&quot;physical_name&quot;:&quot;Trace_PID_Reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;7&quot;},&quot;REG_ADDR&quot;:{&quot;physical_name&quot;:&quot;Trace_Reg_Addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;REG_WRITE&quot;:{&quot;physical_name&quot;:&quot;Trace_Reg_Write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;VALID_INSTR&quot;:{&quot;physical_name&quot;:&quot;Trace_Valid_Instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xml
new file mode 100644
index 0000000..bd5e92c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/bd_afa8_microblaze_I_0.xml
@@ -0,0 +1,27445 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_microblaze_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.CLK</spirit:name>
+      <spirit:displayName>Clk</spirit:displayName>
+      <spirit:description>Clock input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF">M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET">Reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Clk frequency</spirit:displayName>
+          <spirit:description>Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.RESET</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.RESET.TYPE">PROCESSOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT</spirit:name>
+      <spirit:displayName>INTERRUPT</spirit:displayName>
+      <spirit:description>Interrupt Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 0))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_INTERRUPT</spirit:name>
+      <spirit:displayName>INTERRUPT</spirit:displayName>
+      <spirit:description>Interrupt Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_INTERRUPT.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTERRUPT_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DLMB</spirit:name>
+      <spirit:displayName>DLMB</spirit:displayName>
+      <spirit:description>Data Local Memory Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>D_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DCE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Read_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DWait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Write_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.DLMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.DLMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DLMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB_MON&apos;)) = 0)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_DLMB</spirit:name>
+      <spirit:displayName>DLMB</spirit:displayName>
+      <spirit:description>Data Local Memory Bus Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>D_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DCE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Read_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DWait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Write_Strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_DLMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_D_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_DLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_DLMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_LMB_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ILMB</spirit:name>
+      <spirit:displayName>ILMB</spirit:displayName>
+      <spirit:description>Instruction Local Memory Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>I_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ICE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IFetch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IWAIT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ILMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.ILMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ILMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ILMB.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ILMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB_MON&apos;)) = 0)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ILMB</spirit:name>
+      <spirit:displayName>ILMB</spirit:displayName>
+      <spirit:description>Instruction Local Memory Bus Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>I_AS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ICE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IFetch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IReady</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IUE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IWAIT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ILMB.PROTOCOL" spirit:dependency="substring(&quot;STANDARDFREQUENCY&quot;, 9 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))), 8 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_I_LMB_PROTOCOL&apos;)))) )">STANDARD</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ILMB.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ILMB" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_LMB_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_DP</spirit:name>
+      <spirit:displayName>M_AXI_DP</spirit:displayName>
+      <spirit:description>Master AXI4 Data Peripheral Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.PROTOCOL" spirit:dependency="substring(&quot;AXI4LITE&quot;, 1, 4 + 4 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) &lt; 2) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 0)))">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_DP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_DP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_DP</spirit:name>
+      <spirit:displayName>M_AXI_DP</spirit:displayName>
+      <spirit:description>Master AXI4 Data Peripheral Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.PROTOCOL" spirit:dependency="substring(&quot;AXI4LITE&quot;, 1, 4 + 4 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) &lt; 2) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 0)))">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_DP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_IP</spirit:name>
+      <spirit:displayName>M_AXI_IP</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Peripheral Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_IP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_IP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_IP</spirit:name>
+      <spirit:displayName>M_AXI_IP</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Peripheral Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IP_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.MAX_BURST_LENGTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IP.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_IP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_I_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IP_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M0_AXIS</spirit:name>
+      <spirit:displayName>M0_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M0_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M0_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M0_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S0_AXIS</spirit:name>
+      <spirit:displayName>S0_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S0_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S0_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S0_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M1_AXIS</spirit:name>
+      <spirit:displayName>M1_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M1_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M1_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M1_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S1_AXIS</spirit:name>
+      <spirit:displayName>S1_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S1_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S1_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S1_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M2_AXIS</spirit:name>
+      <spirit:displayName>M2_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M2_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M2_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M2_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S2_AXIS</spirit:name>
+      <spirit:displayName>S2_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S2_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S2_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M3_AXIS</spirit:name>
+      <spirit:displayName>M3_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M3_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M3_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M3_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S3_AXIS</spirit:name>
+      <spirit:displayName>S3_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S3_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S3_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S3_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M4_AXIS</spirit:name>
+      <spirit:displayName>M4_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M4_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M4_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M4_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S4_AXIS</spirit:name>
+      <spirit:displayName>S4_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S4_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S4_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S4_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M5_AXIS</spirit:name>
+      <spirit:displayName>M5_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M5_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M5_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M5_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S5_AXIS</spirit:name>
+      <spirit:displayName>S5_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S5_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S5_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S5_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M6_AXIS</spirit:name>
+      <spirit:displayName>M6_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M6_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M6_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M6_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S6_AXIS</spirit:name>
+      <spirit:displayName>S6_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S6_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S6_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S6_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M7_AXIS</spirit:name>
+      <spirit:displayName>M7_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M7_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M7_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M7_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S7_AXIS</spirit:name>
+      <spirit:displayName>S7_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S7_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S7_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S7_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M8_AXIS</spirit:name>
+      <spirit:displayName>M8_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M8_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M8_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M8_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S8_AXIS</spirit:name>
+      <spirit:displayName>S8_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S8_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S8_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S8_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M9_AXIS</spirit:name>
+      <spirit:displayName>M9_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M9_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M9_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M9_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S9_AXIS</spirit:name>
+      <spirit:displayName>S9_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S9_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S9_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S9_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M10_AXIS</spirit:name>
+      <spirit:displayName>M10_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M10_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M10_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M10_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S10_AXIS</spirit:name>
+      <spirit:displayName>S10_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S10_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S10_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S10_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M11_AXIS</spirit:name>
+      <spirit:displayName>M11_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M11_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M11_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M11_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S11_AXIS</spirit:name>
+      <spirit:displayName>S11_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S11_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S11_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S11_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M12_AXIS</spirit:name>
+      <spirit:displayName>M12_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M12_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M12_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M12_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S12_AXIS</spirit:name>
+      <spirit:displayName>S12_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S12_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S12_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S12_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M13_AXIS</spirit:name>
+      <spirit:displayName>M13_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M13_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M13_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M13_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S13_AXIS</spirit:name>
+      <spirit:displayName>S13_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S13_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S13_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S13_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M14_AXIS</spirit:name>
+      <spirit:displayName>M14_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M14_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M14_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M14_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S14_AXIS</spirit:name>
+      <spirit:displayName>S14_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S14_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S14_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S14_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M15_AXIS</spirit:name>
+      <spirit:displayName>M15_AXIS</spirit:displayName>
+      <spirit:description>Master AXI4 Stream Interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M15_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M15_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M15_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S15_AXIS</spirit:name>
+      <spirit:displayName>S15_AXIS</spirit:displayName>
+      <spirit:description>Slave AXI4 Stream Interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S15_AXIS_TVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TDATA_NUM_BYTES">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S15_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S15_AXIS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_DC</spirit:name>
+      <spirit:displayName>M_AXI_DC</spirit:displayName>
+      <spirit:description>Master AXI4 Data Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_DC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_DC</spirit:name>
+      <spirit:displayName>M_AXI_DC</spirit:displayName>
+      <spirit:description>Master AXI4 Data Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_LOCK" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_EXCLUSIVE_ACCESS&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_DC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_ACE_DC</spirit:name>
+      <spirit:displayName>M_ACE_DC</spirit:displayName>
+      <spirit:description>Master ACE Data Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_DC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_ACE_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ACE_DC</spirit:name>
+      <spirit:displayName>M_ACE_DC</spirit:displayName>
+      <spirit:description>Master ACE Data Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_DC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.NUM_READ_OUTSTANDING" spirit:dependency="2 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.NUM_WRITE_OUTSTANDING">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_DC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ACE_DC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_IC</spirit:name>
+      <spirit:displayName>M_AXI_IC</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_IC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_AXI_IC</spirit:name>
+      <spirit:displayName>M_AXI_IC</spirit:displayName>
+      <spirit:description>Master AXI4 Instruction Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ID_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_BURST" spirit:dependency="number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0)">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_LOCK">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.AWUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.ARUSER_WIDTH" spirit:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) * 5">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.WUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.WUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.RUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.RUSER_BITS_PER_BYTE">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.BUSER_WIDTH">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_WSTRB">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_BRESP">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MON_AXI_IC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_AXI_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_ACE_IC</spirit:name>
+      <spirit:displayName>M_ACE_IC</spirit:displayName>
+      <spirit:description>Master ACE Instruction Cache Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Instruction"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_ACE_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_ACE_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MON_ACE_IC</spirit:name>
+      <spirit:displayName>M_ACE_IC</spirit:displayName>
+      <spirit:description>Master ACE Instruction Cache Interface Monitor</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="acemm_rtl" spirit:version="1.0"/>
+      <spirit:monitor spirit:interfaceMode="slave"/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ACVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBAR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWDOMAIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWDOMAIN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSNOOP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWSNOOP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CDVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CDVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_CRVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WACK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AXI_IC_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ID_WIDTH">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.READ_WRITE_MODE">READ_ONLY</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ADDR_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH&apos;))">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.PROTOCOL">ACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.DATA_WIDTH" spirit:dependency="32 + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 1)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) * 32 - 32)) + (number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 2)) * 480)">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.NUM_READ_OUTSTANDING" spirit:dependency="2 + number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) = 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_STREAMS&apos;)) = 1)) * 6 - number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) > 0)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.MAX_BURST_LENGTH" spirit:dependency="(1 - floor((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH&apos;)) + 1) div 2)) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;)) - 1) + 1">4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MON_ACE_IC.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MON_ACE_IC" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_IC_AXI_MON&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DEBUG</spirit:name>
+      <spirit:displayName>DEBUG</spirit:displayName>
+      <spirit:description>MicroBlaze Debug Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbdebug" spirit:version="3.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbdebug_rtl" spirit:version="3.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CAPTURE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Capture</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DISABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Disable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Reg_En</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Debug_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SHIFT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Shift</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDI</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_TDI</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDO</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_TDO</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRCLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_ACK_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Ack_In</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_ACK_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Ack_Out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_In</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRIG_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trig_Out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Trace_Valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UPDATE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Update</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DEBUG" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) &lt; 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_DEBUG</spirit:name>
+      <spirit:displayName>DEBUG</spirit:displayName>
+      <spirit:description>AXI4-Lite Debug</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_DEBUG"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_DEBUG.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_DEBUG" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.DEBUG_ACLK</spirit:name>
+      <spirit:displayName>DEBUG_ACLK</spirit:displayName>
+      <spirit:description>Parallel Debug Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DEBUG_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.ASSOCIATED_BUSIF">DEBUG:S_AXI_DEBUG</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.ASSOCIATED_RESET">DEBUG_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>DEBUG_ACLK frequency</spirit:displayName>
+          <spirit:description>DEBUG_ACLK frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_HZ">30000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.DEBUG_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.DEBUG_ACLK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) > 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.DEBUG_ARESETN</spirit:name>
+      <spirit:displayName>DEBUG_ARESETN</spirit:displayName>
+      <spirit:description>Parallel Debug Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>DEBUG_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.DEBUG_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.DEBUG_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.DEBUG_ARESETN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_INTERFACE&apos;)) > 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>DBG_INTR</spirit:name>
+      <spirit:displayName>Dbg_Intr</spirit:displayName>
+      <spirit:description>Debug Interrupt Output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Dbg_Intr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_INTR.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DBG_INTR.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DBG_INTR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_DEBUG_ENABLED&apos;)) > 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_ENABLE_DISCRETE_PORTS&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) and (spirit:decode(id(&apos;PARAM_VALUE.C_LOCKSTEP_SELECT&apos;)) &lt; 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:displayName>TRACE</spirit:displayName>
+      <spirit:description>MicroBlaze Trace Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace" spirit:version="2.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace_rtl" spirit:version="2.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Access</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Byte_Enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Data_Write_Value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_DCache_Req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DELAY_SLOT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Delay_Slot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EX_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_EX_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_KIND</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Exception_Kind</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Exception_Taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_ICache_Req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INSTRUCTION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Instruction</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Jump_Hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_TAKEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Jump_Taken</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MB_HALTED</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MB_Halted</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MEM_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MEM_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MSR_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_MSR_Reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NEW_REG_VALUE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_New_Reg_Value</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>OF_PIPERUN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_OF_PipeRun</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PC</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_PC</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PID_REG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_PID_Reg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Reg_Addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_WRITE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Reg_Write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_INSTR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Trace_Valid_Instr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.TRACE" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_TRACE&apos;)) = 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_DADDR_SIZE&apos;))">32</spirit:width>
+      <spirit:localMemoryMap>
+        <spirit:name>local_memory_map</spirit:name>
+        <spirit:addressBlock>
+          <spirit:name>microblaze_0</spirit:name>
+          <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+          <spirit:range spirit:format="long">98304</spirit:range>
+          <spirit:width spirit:format="long">32</spirit:width>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>lsb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.lsb">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>msb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.msb">31</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>workflow</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.workflow">simulation</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>controlpaths</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.controlpaths">dlmb_cntlr=lmb_bram_I,second_dlmb_cntlr=second_lmb_bram_I</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>memorytypename</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.memorytypename"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>simmemfile</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.simmemfile"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>combined</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_0.combined">{&quot;AddressBlocks&quot;:[{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:0,&quot;AddrEnd&quot;:65535,&quot;Workflow&quot;:&quot;simulation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot; bd_afa8 lmb_bram_I_MEM_DEVICE&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:65536,&quot;MemFile&quot;:&quot;bd_afa8_lmb_bram_I_0.mem&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;dlmb_cntlr&quot;,&quot;Val&quot;:&quot;lmb_bram_I&quot;}]},{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:65536,&quot;AddrEnd&quot;:98303,&quot;Workflow&quot;:&quot;simulation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot; bd_afa8 lmb_bram_I bd_afa8
+ second_lmb_bram_I_MEM_DEVICE&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:32768,&quot;MemFile&quot;:&quot;bd_afa8_second_lmb_bram_I_0.mem&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;second_dlmb_cntlr&quot;,&quot;Val&quot;:&quot;second_lmb_bram_I&quot;}]}]}</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </spirit:addressBlock>
+        <spirit:addressBlock>
+          <spirit:name>microblaze_1</spirit:name>
+          <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+          <spirit:range spirit:format="long">98304</spirit:range>
+          <spirit:width spirit:format="long">32</spirit:width>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>lsb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.lsb">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>msb</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.msb">31</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>workflow</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.workflow">implementation</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>controlpaths</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.controlpaths">dlmb_cntlr=lmb_bram_I,second_dlmb_cntlr=second_lmb_bram_I</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>memorytypename</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.memorytypename"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>simmemfile</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.simmemfile"/>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>combined</spirit:name>
+              <spirit:value spirit:id="ADDRSPACE_ADDRBLOCKPARAM_VALUE.DATA.LOCAL_MEMORY_MAP.MICROBLAZE_1.combined">{&quot;AddressBlocks&quot;:[{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:0,&quot;AddrEnd&quot;:65535,&quot;Workflow&quot;:&quot;implementation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot;&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:65536,&quot;MemFile&quot;:&quot;&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;dlmb_cntlr&quot;,&quot;Val&quot;:&quot;lmb_bram_I&quot;}]},{&quot;Width&quot;:32,&quot;LSB&quot;:0,&quot;MSB&quot;:31,&quot;AddrBegin&quot;:65536,&quot;AddrEnd&quot;:98303,&quot;Workflow&quot;:&quot;implementation&quot;,&quot;ECC&quot;:false,&quot;ECCAlgo&quot;:&quot;ECC_NONE&quot;,&quot;ECCLSB&quot;:0,&quot;ECCMSB&quot;:0,&quot;MemType&quot;:&quot;&quot;,&quot;MemWidth&quot;:32,&quot;MemDepth&quot;:32768,&quot;MemFile&quot;:&quot;&quot;,&quot;MemColl&quot;:[{&quot;Key&quot;:&quot;second_d
+lmb_cntlr&quot;,&quot;Val&quot;:&quot;second_lmb_bram_I&quot;}]}]}</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </spirit:addressBlock>
+      </spirit:localMemoryMap>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Instruction</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIADDR_SIZE&apos;))">32</spirit:width>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_DEBUG</spirit:name>
+      <spirit:description>AXI debug memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Debug Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="32768" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Mb_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Mb_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Config_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Config_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Scan_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_Reset_Sel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Scan_Reset_Sel" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Scan_En</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Scan_En" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>RAM_To</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">255</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+      <spirit:port>
+        <spirit:name>M_AXI_DP_AWCACHE</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+        <spirit:name>M_AXI_DP_AWPROT</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_AWVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>M_AXI_DP_AWREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_WDATA</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+      <spirit:port>
+        <spirit:name>M_AXI_DP_WSTRB</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_WSTRB" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DP_WLAST</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_WLAST" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DP_WVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_WVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DP_WREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DP_BID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_BID" xilinx:dependency="false">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_DP_BRESP</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DP_BVALID</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DP_BREADY</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DP_ARID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_ARADDR</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_ARLOCK</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_ARCACHE</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_RDATA</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_RLAST</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_RLAST" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS&apos;)) = 1))">false</xilinx:isEnabled>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DP_RREADY</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DP_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;PARAM_VALUE.C_D_AXI&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DP_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+        <spirit:name>M_AXI_IC_ARSIZE</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_ARLOCK</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_IC_ARCACHE</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>M_AXI_IC_ARPROT</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>M_AXI_IC_ARQOS</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARQOS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_ARVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_ARREADY</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1))">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>M_AXI_IC_ARUSER</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARUSER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_ARDOMAIN</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARDOMAIN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_ARSNOOP</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARSNOOP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_IC_ARBAR</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_IC_ARBAR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ICACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>M_AXI_DC_AWVALID</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWUSER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_AWDOMAIN</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWDOMAIN" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+        <spirit:name>M_AXI_DC_AWSNOOP</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWSNOOP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_AWBAR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+        <spirit:name>M_AXI_DC_CDVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_CDVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_CDDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_DC_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_CDDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_CDLAST</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_CDLAST" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LOCKSTEP_SLAVE&apos;)) = 0) or (spirit:decode(id(&apos;PARAM_VALUE.C_DC_AXI_MON&apos;)) = 0)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AXI_DC_CDREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXI_DC_CDREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DCACHE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_SCO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SCO">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREQ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CONFIG_RESET" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK_IRQ</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region for interrupt input</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_CLK_DEBUG</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region in debug module</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_DBG_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Dbg_Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_SYNC_FF_DBG_TRACE_CLK</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Dbg_Trace_Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_TOLERANT</spirit:name>
+        <spirit:displayName>Enable Fault Tolerance Support</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_TOLERANT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_USE_CE_EXCEPTION</spirit:name>
+        <spirit:displayName>Correctable Error Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_USE_CE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCKSTEP_SLAVE</spirit:name>
+        <spirit:displayName>Lockstep Slave</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKSTEP_SLAVE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCKSTEP_MASTER</spirit:name>
+        <spirit:displayName>Lockstep Master</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKSTEP_MASTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ENDIANNESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENDIANNESS" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DATA_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_SIZE" spirit:choiceRef="choice_list_99ba8646">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DATA_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_LMB_DATA_SIZE">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INSTR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_INSTR_SIZE">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DADDR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_SIZE" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_INSTANCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INSTANCE">bd_afa8_microblaze_I_0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AVOID_PRIMITIVES" spirit:choiceRef="choice_pairs_22d9f392">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AREA_OPTIMIZED</spirit:name>
+        <spirit:displayName>Select implementation optimization</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AREA_OPTIMIZED" spirit:choiceRef="choice_pairs_3eb333f8">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPTIMIZATION</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Bus Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_ff364cce">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASE_VECTORS</spirit:name>
+        <spirit:displayName>Vector Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASE_VECTORS" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_DATA_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_DP_EXCLUSIVE_ACCESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_DP_EXCLUSIVE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_D_BUS_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Data-side AXI Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_D_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_D_BUS_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_DATA_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IP_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IP_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_I_BUS_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Instruction-side AXI Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_I_BUS_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_LMB</spirit:name>
+        <spirit:displayName>Enable Local Memory Bus Data Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_LMB" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>Local Memory Bus Data Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_D_AXI</spirit:name>
+        <spirit:displayName>Enable Peripheral AXI Data Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_AXI" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_LMB</spirit:name>
+        <spirit:displayName>Enable Local Memory Bus Instruction Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_LMB" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>Local Memory Bus Instruction Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_I_AXI</spirit:name>
+        <spirit:displayName>Enable Peripheral AXI Instruction Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_I_AXI" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>G_TEMPLATE_LIST</spirit:name>
+        <spirit:displayName>Select Configuration</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.G_TEMPLATE_LIST" spirit:choiceRef="choice_pairs_7dd2834f">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_MSR_INSTR</spirit:name>
+        <spirit:displayName>Enable Additional Machine Status Register Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MSR_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PCMP_INSTR</spirit:name>
+        <spirit:displayName>Enable Pattern Comparator</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PCMP_INSTR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_BARREL</spirit:name>
+        <spirit:displayName>Enable Barrel Shifter</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BARREL" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DIV</spirit:name>
+        <spirit:displayName>Enable Integer Divider</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DIV" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_HW_MUL</spirit:name>
+        <spirit:displayName>Enable Integer Multiplier</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_HW_MUL" spirit:choiceRef="choice_pairs_1075faf2">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FPU</spirit:name>
+        <spirit:displayName>Enable Floating Point Unit</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FPU" spirit:choiceRef="choice_pairs_7bfd418d">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_REORDER_INSTR</spirit:name>
+        <spirit:displayName>Enable Reversed Load/Store and Swap Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_REORDER_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UNALIGNED_EXCEPTIONS</spirit:name>
+        <spirit:displayName>Enable Unaligned Data Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UNALIGNED_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ILL_OPCODE_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Illegal Instruction Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ILL_OPCODE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIV_ZERO_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Integer Divide Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIV_ZERO_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DIV_ZERO_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_DIV&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FPU_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Floating Point Unit Exceptions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FPU_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FPU_EXCEPTION" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FPU&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FSL_LINKS</spirit:name>
+        <spirit:displayName>Number of Stream Links</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FSL_LINKS" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXTENDED_FSL_INSTR</spirit:name>
+        <spirit:displayName>Enable Additional Stream Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXTENDED_FSL_INSTR" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FSL_EXCEPTION</spirit:name>
+        <spirit:displayName>Enable Stream Exception</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FSL_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FSL_EXCEPTION" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FSL_LINKS&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_EXTENDED_FSL_INSTR&apos;)) > 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_STACK_PROTECTION</spirit:name>
+        <spirit:displayName>Enable stack protection</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STACK_PROTECTION" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_STACK_PROTECTION" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) = 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) = 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPRECISE_EXCEPTIONS</spirit:name>
+        <spirit:displayName>Allow Imprecise Exceptions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPRECISE_EXCEPTIONS" spirit:choiceRef="choice_pairs_2058dc69">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INTERRUPT" spirit:choiceRef="choice_pairs_db57ca32">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXT_BRK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXT_BRK" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EXT_NM_BRK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EXT_NM_BRK" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_NON_SECURE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_NON_SECURE" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_MMU</spirit:name>
+        <spirit:displayName>Memory Management</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MMU" spirit:choiceRef="choice_pairs_0000a26c">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_MMU" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_DTLB_SIZE</spirit:name>
+        <spirit:displayName>Data Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_DTLB_SIZE" spirit:choiceRef="choice_list_dd2843c6">4</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_DTLB_SIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_ITLB_SIZE</spirit:name>
+        <spirit:displayName>Instruction Shadow Translation Look-Aside Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_ITLB_SIZE" spirit:choiceRef="choice_list_dd2843c6">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_ITLB_SIZE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_TLB_ACCESS</spirit:name>
+        <spirit:displayName>Enable Access to Memory Management Special Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_TLB_ACCESS" spirit:choiceRef="choice_pairs_7ad6afc0">3</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_TLB_ACCESS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_ZONES</spirit:name>
+        <spirit:displayName>Number of Memory Protection Zones</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_ZONES" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">16</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_ZONES" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MMU_PRIVILEGED_INSTR</spirit:name>
+        <spirit:displayName>Privileged Instructions</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMU_PRIVILEGED_INSTR" spirit:choiceRef="choice_pairs_443ae6cc">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MMU_PRIVILEGED_INSTR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_MMU&apos;)) > 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_BRANCH_TARGET_CACHE</spirit:name>
+        <spirit:displayName>Enable Branch Target Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRANCH_TARGET_CACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_USE_BRANCH_TARGET_CACHE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRANCH_TARGET_CACHE_SIZE</spirit:name>
+        <spirit:displayName>Branch Target Cache Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRANCH_TARGET_CACHE_SIZE" spirit:choiceRef="choice_pairs_e7a1eb81">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_BRANCH_TARGET_CACHE_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PC_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PC_WIDTH" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PVR</spirit:name>
+        <spirit:displayName>Specifies Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR" spirit:choiceRef="choice_pairs_5ab38e91">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 7)">
+        <spirit:name>C_PVR_USER1</spirit:name>
+        <spirit:displayName>Specify USER1 Bits in Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR_USER1" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 31)">
+        <spirit:name>C_PVR_USER2</spirit:name>
+        <spirit:displayName>Specify USER2 Bits in Processor Version Register</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PVR_USER2" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DYNAMIC_BUS_SIZING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DYNAMIC_BUS_SIZING">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(0 to 31)">
+        <spirit:name>C_RESET_MSR</spirit:name>
+        <spirit:displayName>Specify Reset Value for Select MSR Bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_MSR" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPCODE_0x0_ILLEGAL</spirit:name>
+        <spirit:displayName>Generate Illegal Instruction Exception for NULL Instruction</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPCODE_0x0_ILLEGAL" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_ENABLED</spirit:name>
+        <spirit:displayName>MicroBlaze Debug Module Interface</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_ENABLED" spirit:choiceRef="choice_pairs_7bfd418d">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_INTERFACE</spirit:name>
+        <spirit:displayName>MicroBlaze Debug Connection</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_INTERFACE" spirit:choiceRef="choice_pairs_56d5ba32">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_PC_BRK</spirit:name>
+        <spirit:displayName>Number of PC Breakpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_PC_BRK" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_RD_ADDR_BRK</spirit:name>
+        <spirit:displayName>Number of Read Address Watchpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUMBER_OF_WR_ADDR_BRK</spirit:name>
+        <spirit:displayName>Number of Write Address Watchpoints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_EVENT_COUNTERS</spirit:name>
+        <spirit:displayName>Number of Performance Monitor Event Counters</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_EVENT_COUNTERS" spirit:minimum="0" spirit:maximum="48" spirit:rangeType="long">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_LATENCY_COUNTERS</spirit:name>
+        <spirit:displayName>Number of Performance Monitor Latency Counters</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_LATENCY_COUNTERS" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Performance Monitor Counter Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_COUNTER_WIDTH" spirit:choiceRef="choice_list_b1aff63c">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_TRACE_SIZE</spirit:name>
+        <spirit:displayName>Trace Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_TRACE_SIZE" spirit:choiceRef="choice_pairs_13d40c7c">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_EXTERNAL_TRACE</spirit:name>
+        <spirit:displayName>External Trace</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_TRACE_ASYNC_RESET</spirit:name>
+        <spirit:displayName>Use Asynchrnous Reset for External Trace</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_TRACE_ASYNC_RESET" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DEBUG_PROFILE_SIZE</spirit:name>
+        <spirit:displayName>Profile Buffer Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEBUG_PROFILE_SIZE" spirit:choiceRef="choice_pairs_5b1842a1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERRUPT_IS_EDGE</spirit:name>
+        <spirit:displayName>Sense Interrupt on Edge vs. Level</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERRUPT_IS_EDGE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EDGE_IS_POSITIVE</spirit:name>
+        <spirit:displayName>Sense Interrupt on Rising vs. Falling Edge</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EDGE_IS_POSITIVE" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ASYNC_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ASYNC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ASYNC_WAKEUP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ASYNC_WAKEUP" spirit:choiceRef="choice_list_6e3ded9c">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M0_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M0_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S0_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S0_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M1_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M1_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S1_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S1_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M2_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M2_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S2_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S2_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M3_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M3_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S3_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S3_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M4_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M4_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S4_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S4_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M5_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M5_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S5_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S5_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M6_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M6_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S6_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S6_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M7_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M7_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S7_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S7_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M8_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M8_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S8_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S8_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M9_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M9_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S9_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S9_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M10_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M10_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S10_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S10_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M11_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M11_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S11_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S11_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M12_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M12_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S12_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S12_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M13_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M13_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S13_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S13_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M14_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M14_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S14_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S14_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M15_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M15_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S15_AXIS_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S15_AXIS_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ICACHE_BASEADDR</spirit:name>
+        <spirit:displayName>Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ICACHE_HIGHADDR</spirit:name>
+        <spirit:displayName>High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_HIGHADDR" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ICACHE</spirit:name>
+        <spirit:displayName>Enable Instruction Cache</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ICACHE" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ALLOW_ICACHE_WR</spirit:name>
+        <spirit:displayName>Enable Writes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALLOW_ICACHE_WR" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ADDR_TAG_BITS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDR_TAG_BITS" spirit:minimum="0" spirit:maximum="26" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CACHE_BYTE_SIZE</spirit:name>
+        <spirit:displayName>Size in Bytes</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_LINE_LEN</spirit:name>
+        <spirit:displayName>Line Length</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_ALWAYS_USED</spirit:name>
+        <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_STREAMS</spirit:name>
+        <spirit:displayName>Number of Streams</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_STREAMS" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_STREAMS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_VICTIMS</spirit:name>
+        <spirit:displayName>Number of Victims</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_VICTIMS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_FORCE_TAG_LUTRAM</spirit:name>
+        <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_FORCE_TAG_LUTRAM" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CACHE_BYTE_SIZE&apos;)) &lt;= (2048 * spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;))))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ICACHE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ICACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ICACHE_DATA_WIDTH" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_TOLERANT&apos;)) = 0)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CACHE_BYTE_SIZE&apos;)) > ((2048 * spirit:decode(id(&apos;MODELPARAM_VALUE.C_ICACHE_LINE_LEN&apos;))) - 1)))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_THREAD_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_THREAD_ID_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_THREAD_ID_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_DATA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_USER_VALUE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_USER_VALUE" spirit:minimum="0" spirit:maximum="31" spirit:rangeType="long">31</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_USER_VALUE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_AWUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_AWUSER_WIDTH">5</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_AWUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_ARUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_ARUSER_WIDTH">5</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_ARUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_WUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_WUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_RUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_RUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_RUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_IC_BUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_IC_BUSER_WIDTH">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXI_IC_BUSER_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) >= 2">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_DCACHE_BASEADDR</spirit:name>
+        <spirit:displayName>Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_DCACHE_HIGHADDR</spirit:name>
+        <spirit:displayName>High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCACHE_HIGHADDR" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ALLOW_DCACHE_WR</spirit:name>
+        <spirit:displayName>Enable Writes</spirit:displayName>
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+      <spirit:modelParameter spirit:dataType="integer">
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+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:displayName>Line Length</spirit:displayName>
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+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
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+        <spirit:displayName>Enable Write-back Storage Policy</spirit:displayName>
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+      <spirit:modelParameter spirit:dataType="integer">
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_DCACHE_VICTIMS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AREA_OPTIMIZED&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_DCACHE_USE_WRITEBACK&apos;)) = 1))">false</xilinx:isEnabled>
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+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
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+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:displayName>Data Width</spirit:displayName>
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+      <spirit:name>choice_pairs_c471ed24</spirit:name>
+      <spirit:enumeration spirit:text="NONE">32</spirit:enumeration>
+      <spirit:enumeration spirit:text="64GB">36</spirit:enumeration>
+      <spirit:enumeration spirit:text="1TB">40</spirit:enumeration>
+      <spirit:enumeration spirit:text="16TB">44</spirit:enumeration>
+      <spirit:enumeration spirit:text="256TB">48</spirit:enumeration>
+      <spirit:enumeration spirit:text="4PB">52</spirit:enumeration>
+      <spirit:enumeration spirit:text="16EB">64</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_db57ca32</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="NORMAL">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FAST">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e7a1eb81</spirit:name>
+      <spirit:enumeration spirit:text="DEFAULT">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="8_ENTRIES">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="16_ENTRIES">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="32_ENTRIES">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="64_ENTRIES">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="512_ENTRIES">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="1024_ENTRIES">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="2048_ENTRIES">7</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ff364cce</spirit:name>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ACE">3</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>microblaze</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>endian</spirit:name>
+          <spirit:value>little</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>elf_class</spirit:name>
+          <spirit:value>32-bit</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>instance_path</spirit:name>
+          <spirit:value/>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bootloop_file</spirit:name>
+          <spirit:value>data/mb_bootloop_le.elf</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>processor_type</spirit:name>
+          <spirit:value>MICROBLAZE_LE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>is_visible</spirit:name>
+          <spirit:value>true</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>The MicroBlaze 32 and 64 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support.
+It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development.
+</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_SCO</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SCO" spirit:order="1120" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SCO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FREQ" spirit:order="1130" spirit:configGroups="1 NoDisplay">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FREQ">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DATA_SIZE</spirit:name>
+      <spirit:displayName>Select Processor Implementation</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_SIZE" spirit:choiceRef="choice_list_99ba8646" spirit:order="1160" spirit:configGroups="1 Instructions">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DATA_SIZE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ADDR_SIZE</spirit:name>
+      <spirit:displayName>Select Extended Addressing</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_SIZE" spirit:choiceRef="choice_pairs_c471ed24" spirit:order="1165" spirit:configGroups="1 Instructions">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ADDR_SIZE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DYNAMIC_BUS_SIZING</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DYNAMIC_BUS_SIZING" spirit:order="1220" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DYNAMIC_BUS_SIZING">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PC_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PC_WIDTH" spirit:order="1200" spirit:configGroups="1 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PC_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INSTANCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="1140" spirit:configGroups="1 NoDisplay">mb_microblaze_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INSTANCE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AVOID_PRIMITIVES" spirit:order="1170" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_AVOID_PRIMITIVES">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_TOLERANT</spirit:name>
+      <spirit:displayName>Enable Fault Tolerance Support</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_TOLERANT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1110" spirit:configGroups="1 Fault Tolerance">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_TOLERANT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_USE_CE_EXCEPTION</spirit:name>
+      <spirit:displayName>Correctable Error Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_USE_CE_EXCEPTION" spirit:order="1150" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_USE_CE_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LOCKSTEP_SLAVE</spirit:name>
+      <spirit:displayName>Lockstep Slave</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LOCKSTEP_SLAVE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1230" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LOCKSTEP_SLAVE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ENDIANNESS</spirit:name>
+      <spirit:displayName>Endianness</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ENDIANNESS" spirit:order="1235" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ENDIANNESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AREA_OPTIMIZED</spirit:name>
+      <spirit:displayName>Select implementation optimization</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AREA_OPTIMIZED" spirit:choiceRef="choice_pairs_3eb333f8" spirit:order="1080" spirit:configGroups="1 Optimization">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_AREA_OPTIMIZED">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPTIMIZATION</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPTIMIZATION" spirit:order="1180" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_OPTIMIZATION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Bus Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_ff364cce" spirit:order="2036" spirit:configGroups="8 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_BASE_VECTORS</spirit:name>
+      <spirit:displayName>Vector Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASE_VECTORS" spirit:order="1190" spirit:configGroups="1 NoDisplay" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASE_VECTORS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CONFIG_RESET" spirit:order="1210" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_CONFIG_RESET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK" spirit:order="1220" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK_IRQ</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region for interrupt input</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK_IRQ" spirit:order="1230" spirit:configGroups="1 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK_IRQ">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_CLK_DEBUG</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Clk region in debug module</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_CLK_DEBUG" spirit:order="1240" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_CLK_DEBUG">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_DBG_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Dbg_Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_DBG_CLK" spirit:order="1250" spirit:configGroups="1 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_DBG_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_SYNC_FF_DBG_TRACE_CLK</spirit:name>
+      <spirit:displayName>Synchronizing FFs to Dbg_Trace_Clk region</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SYNC_FF_DBG_TRACE_CLK" spirit:order="1260" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SYNC_FF_DBG_TRACE_CLK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_THREAD_ID_WIDTH" spirit:order="8120" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_DATA_WIDTH" spirit:order="8130" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_ADDR_WIDTH" spirit:order="8140" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DP_EXCLUSIVE_ACCESS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DP_EXCLUSIVE_ACCESS" spirit:order="8150" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DP_EXCLUSIVE_ACCESS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_AXI</spirit:name>
+      <spirit:displayName>Enable Peripheral AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_AXI" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8030" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DP_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Peripheral AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DP_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8032" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DP_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DC_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Cache AXI Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DC_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8034" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DC_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB</spirit:name>
+      <spirit:displayName>Enable Local Memory Bus Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8050" spirit:configGroups="8 Buses">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>Local Memory Bus Data Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="8052" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_D_LMB_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Local Memory Bus Data Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_D_LMB_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8055" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_D_LMB_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_THREAD_ID_WIDTH" spirit:order="8200" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_DATA_WIDTH" spirit:order="8210" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IP_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IP_ADDR_WIDTH" spirit:order="8220" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IP_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_AXI</spirit:name>
+      <spirit:displayName>Enable Peripheral AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_AXI" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8060" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IP_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Peripheral AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IP_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8062" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IP_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IC_AXI_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Cache AXI Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IC_AXI_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8064" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IC_AXI_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB</spirit:name>
+      <spirit:displayName>Enable Local Memory Bus Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8080" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>Local Memory Bus Instruction Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="8082" spirit:configGroups="8 Buses">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_I_LMB_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Local Memory Bus Instruction Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_I_LMB_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8085" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_I_LMB_MON">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_TRACE</spirit:name>
+      <spirit:displayName>Enable Trace Bus Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8090" spirit:configGroups="8 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_TRACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LOCKSTEP_SELECT</spirit:name>
+      <spirit:displayName>Lockstep Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LOCKSTEP_SELECT" spirit:choiceRef="choice_pairs_75c71b2b" spirit:order="8100" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LOCKSTEP_SELECT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ENABLE_DISCRETE_PORTS</spirit:name>
+      <spirit:displayName>Enable Discrete Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ENABLE_DISCRETE_PORTS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8470" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ENABLE_DISCRETE_PORTS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_USER_SIGNALS</spirit:name>
+      <spirit:displayName>Enable M_AXI_DC User Signals</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8370" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_USER_SIGNALS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_USER_SIGNALS</spirit:name>
+      <spirit:displayName>Enable M_AXI_IC User Signals</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8460" spirit:configGroups="8 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_USER_SIGNALS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>G_TEMPLATE_LIST</spirit:name>
+      <spirit:displayName>Select Configuration</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_TEMPLATE_LIST" spirit:choiceRef="choice_pairs_7dd2834f" spirit:order="10" spirit:configGroups="9 GUI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.G_TEMPLATE_LIST">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>G_USE_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Enable Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_USE_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="50" spirit:configGroups="9 GUI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.G_USE_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_MSR_INSTR</spirit:name>
+      <spirit:displayName>Enable Additional Machine Status Register Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_MSR_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1040" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_MSR_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PCMP_INSTR</spirit:name>
+      <spirit:displayName>Enable Pattern Comparator</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PCMP_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1050" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_PCMP_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_REORDER_INSTR</spirit:name>
+      <spirit:displayName>Enable Reversed Load/Store and Swap Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_REORDER_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1060" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_REORDER_INSTR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_BARREL</spirit:name>
+      <spirit:displayName>Enable Barrel Shifter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_BARREL" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1000" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_BARREL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_DIV</spirit:name>
+      <spirit:displayName>Enable Integer Divider</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_DIV" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1030" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_DIV">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_HW_MUL</spirit:name>
+      <spirit:displayName>Enable Integer Multiplier</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_HW_MUL" spirit:choiceRef="choice_pairs_1075faf2" spirit:order="1020" spirit:configGroups="1 Instructions">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_HW_MUL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FPU</spirit:name>
+      <spirit:displayName>Enable Floating Point Unit</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FPU" spirit:choiceRef="choice_pairs_7bfd418d" spirit:order="1010" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_FPU">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UNALIGNED_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Enable Unaligned Data Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UNALIGNED_EXCEPTIONS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2090" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UNALIGNED_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ILL_OPCODE_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Illegal Instruction Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ILL_OPCODE_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2060" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ILL_OPCODE_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_I_BUS_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Instruction-side AXI Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_I_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2040" spirit:configGroups="2 Bus Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_I_BUS_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_D_BUS_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Data-side AXI Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_D_BUS_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2050" spirit:configGroups="2 Bus Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_D_BUS_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DIV_ZERO_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Integer Divide Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DIV_ZERO_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 Math Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DIV_ZERO_EXCEPTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FPU_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Floating Point Unit Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FPU_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2010" spirit:configGroups="2 Math Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FPU_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FSL_EXCEPTION</spirit:name>
+      <spirit:displayName>Enable Stream Exception</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FSL_EXCEPTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8008" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FSL_EXCEPTION">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_STACK_PROTECTION</spirit:name>
+      <spirit:displayName>Enable stack protection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_STACK_PROTECTION" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4004" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_STACK_PROTECTION">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IMPRECISE_EXCEPTIONS</spirit:name>
+      <spirit:displayName>Allow Imprecise Exceptions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IMPRECISE_EXCEPTIONS" spirit:choiceRef="choice_pairs_2058dc69" spirit:order="2090" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IMPRECISE_EXCEPTIONS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR</spirit:name>
+      <spirit:displayName>Specifies Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR" spirit:choiceRef="choice_pairs_5ab38e91" spirit:order="7000" spirit:configGroups="7 Processor Version Registers">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR_USER1</spirit:name>
+      <spirit:displayName>Specify USER1 Bits in Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR_USER1" spirit:order="7100" spirit:configGroups="7 Processor Version Registers" spirit:bitStringLength="8">0x00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR_USER1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PVR_USER2</spirit:name>
+      <spirit:displayName>Specify USER2 Bits in Processor Version Register</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PVR_USER2" spirit:order="7200" spirit:configGroups="7 Processor Version Registers" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PVR_USER2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_ENABLED</spirit:name>
+      <spirit:displayName>MicroBlaze Debug Module Interface</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_ENABLED" spirit:choiceRef="choice_pairs_7bfd418d" spirit:order="5000" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_ENABLED">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_INTERFACE</spirit:name>
+      <spirit:displayName>MicroBlaze Debug Connection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_INTERFACE" spirit:choiceRef="choice_pairs_56d5ba32" spirit:order="5010" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_INTERFACE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_PC_BRK</spirit:name>
+      <spirit:displayName>Number of PC Breakpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_PC_BRK" spirit:order="5100" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_PC_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_RD_ADDR_BRK</spirit:name>
+      <spirit:displayName>Number of Read Address Watchpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_RD_ADDR_BRK" spirit:order="5300" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_RD_ADDR_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUMBER_OF_WR_ADDR_BRK</spirit:name>
+      <spirit:displayName>Number of Write Address Watchpoints</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUMBER_OF_WR_ADDR_BRK" spirit:order="5200" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="4" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUMBER_OF_WR_ADDR_BRK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_EVENT_COUNTERS</spirit:name>
+      <spirit:displayName>Number of Performance Monitor Event Counters</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_EVENT_COUNTERS" spirit:order="5400" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="48" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_EVENT_COUNTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_LATENCY_COUNTERS</spirit:name>
+      <spirit:displayName>Number of Performance Monitor Latency Counters</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_LATENCY_COUNTERS" spirit:order="5500" spirit:configGroups="5 Hardware Breakpoints" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_LATENCY_COUNTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Performance Monitor Counter Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_COUNTER_WIDTH" spirit:choiceRef="choice_list_b1aff63c" spirit:order="5600" spirit:configGroups="5 Hardware Breakpoints">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_TRACE_SIZE</spirit:name>
+      <spirit:displayName>Trace Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_TRACE_SIZE" spirit:choiceRef="choice_pairs_126baff7" spirit:order="5700" spirit:configGroups="5 Hardware Breakpoints">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_TRACE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_EXTERNAL_TRACE</spirit:name>
+      <spirit:displayName>External Trace</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5650" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_EXTERNAL_TRACE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_TRACE_ASYNC_RESET</spirit:name>
+      <spirit:displayName>Use Asynchrnous Reset for External Trace</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_TRACE_ASYNC_RESET" spirit:order="5655" spirit:configGroups="1 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_TRACE_ASYNC_RESET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DEBUG_PROFILE_SIZE</spirit:name>
+      <spirit:displayName>Profile Buffer Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DEBUG_PROFILE_SIZE" spirit:choiceRef="choice_pairs_5b1842a1" spirit:order="5800" spirit:configGroups="5 Hardware Breakpoints">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DEBUG_PROFILE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERRUPT_IS_EDGE</spirit:name>
+      <spirit:displayName>Sense Interrupt on Edge vs. Level</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERRUPT_IS_EDGE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6000" spirit:configGroups="6 Interrupt">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERRUPT_IS_EDGE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EDGE_IS_POSITIVE</spirit:name>
+      <spirit:displayName>Sense Interrupt on Rising vs. Falling Edge</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EDGE_IS_POSITIVE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 Interrupt">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_EDGE_IS_POSITIVE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ASYNC_INTERRUPT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ASYNC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703" spirit:order="6600" spirit:configGroups="6 NoDisplay">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ASYNC_INTERRUPT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ASYNC_WAKEUP</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ASYNC_WAKEUP" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="6650" spirit:configGroups="6 NoDisplay">3</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ASYNC_WAKEUP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_IE</spirit:name>
+      <spirit:displayName>IE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_IE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6201" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_IE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_BIP</spirit:name>
+      <spirit:displayName>BIP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_BIP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6202" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_BIP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_ICE</spirit:name>
+      <spirit:displayName>ICE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_ICE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6203" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_ICE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_DCE</spirit:name>
+      <spirit:displayName>DCE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_DCE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6204" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_DCE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_EE</spirit:name>
+      <spirit:displayName>EE</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_EE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6205" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_EE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_RESET_MSR_EIP</spirit:name>
+      <spirit:displayName>EIP</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_RESET_MSR_EIP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6206" spirit:configGroups="6 Reset">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_RESET_MSR_EIP">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_OPCODE_0x0_ILLEGAL</spirit:name>
+      <spirit:displayName>Generate Illegal Instruction Exception for NULL Instruction</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_OPCODE_0x0_ILLEGAL" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2070" spirit:configGroups="2 Misc Exceptions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_OPCODE_0x0_ILLEGAL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FSL_LINKS</spirit:name>
+      <spirit:displayName>Number of Stream Links</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FSL_LINKS" spirit:order="8000" spirit:configGroups="8 NoDisplay" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FSL_LINKS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_EXTENDED_FSL_INSTR</spirit:name>
+      <spirit:displayName>Enable Additional Stream Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_EXTENDED_FSL_INSTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="8004" spirit:configGroups="1 Instructions">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_EXTENDED_FSL_INSTR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M0_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M0_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8520" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M0_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S0_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S0_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8530" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S0_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M1_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M1_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8560" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M1_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S1_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S1_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8570" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S1_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M2_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M2_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8600" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M2_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S2_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S2_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8610" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S2_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M3_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M3_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8640" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M3_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S3_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S3_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8650" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S3_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M4_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M4_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8680" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M4_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S4_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S4_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8690" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S4_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M5_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M5_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8720" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M5_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S5_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S5_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8730" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S5_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M6_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M6_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8760" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M6_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S6_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S6_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8770" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S6_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M7_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M7_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8800" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M7_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S7_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S7_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8810" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S7_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M8_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M8_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8840" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M8_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S8_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S8_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8850" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S8_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M9_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M9_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8880" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M9_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S9_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S9_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8890" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S9_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M10_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M10_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8920" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M10_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S10_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S10_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8930" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S10_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M11_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M11_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8960" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M11_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S11_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S11_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="8970" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S11_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M12_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M12_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9000" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M12_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S12_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S12_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9010" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S12_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M13_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M13_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9040" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M13_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S13_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S13_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9050" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S13_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M14_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M14_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9080" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M14_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S14_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S14_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9090" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S14_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M15_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_M15_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9120" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M15_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S15_AXIS_PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S15_AXIS_PROTOCOL" spirit:choiceRef="choice_list_29910ba8" spirit:order="9130" spirit:configGroups="8 NoDisplay">GENERIC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S15_AXIS_PROTOCOL">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M0_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M0_AXIS_DATA_WIDTH" spirit:order="8500" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M0_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S0_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S0_AXIS_DATA_WIDTH" spirit:order="8510" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S0_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M1_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M1_AXIS_DATA_WIDTH" spirit:order="8540" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M1_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S1_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S1_AXIS_DATA_WIDTH" spirit:order="8550" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S1_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M2_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M2_AXIS_DATA_WIDTH" spirit:order="8580" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M2_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S2_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S2_AXIS_DATA_WIDTH" spirit:order="8590" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S2_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M3_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M3_AXIS_DATA_WIDTH" spirit:order="8620" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M3_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S3_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S3_AXIS_DATA_WIDTH" spirit:order="8630" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S3_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M4_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M4_AXIS_DATA_WIDTH" spirit:order="8660" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M4_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S4_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S4_AXIS_DATA_WIDTH" spirit:order="8670" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S4_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M5_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M5_AXIS_DATA_WIDTH" spirit:order="8700" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M5_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S5_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S5_AXIS_DATA_WIDTH" spirit:order="8710" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S5_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M6_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M6_AXIS_DATA_WIDTH" spirit:order="8740" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M6_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S6_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S6_AXIS_DATA_WIDTH" spirit:order="8750" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S6_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M7_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M7_AXIS_DATA_WIDTH" spirit:order="8780" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M7_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S7_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S7_AXIS_DATA_WIDTH" spirit:order="8790" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S7_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M8_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M8_AXIS_DATA_WIDTH" spirit:order="8820" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M8_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S8_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S8_AXIS_DATA_WIDTH" spirit:order="8830" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S8_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M9_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M9_AXIS_DATA_WIDTH" spirit:order="8860" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M9_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S9_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S9_AXIS_DATA_WIDTH" spirit:order="8870" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S9_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M10_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M10_AXIS_DATA_WIDTH" spirit:order="8900" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M10_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S10_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S10_AXIS_DATA_WIDTH" spirit:order="8910" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S10_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M11_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M11_AXIS_DATA_WIDTH" spirit:order="8940" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M11_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S11_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S11_AXIS_DATA_WIDTH" spirit:order="8950" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S11_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M12_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M12_AXIS_DATA_WIDTH" spirit:order="8980" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M12_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S12_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S12_AXIS_DATA_WIDTH" spirit:order="8990" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S12_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M13_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M13_AXIS_DATA_WIDTH" spirit:order="9020" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M13_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S13_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S13_AXIS_DATA_WIDTH" spirit:order="9030" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S13_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M14_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M14_AXIS_DATA_WIDTH" spirit:order="9060" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M14_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S14_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S14_AXIS_DATA_WIDTH" spirit:order="9070" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S14_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M15_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M15_AXIS_DATA_WIDTH" spirit:order="9100" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M15_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S15_AXIS_DATA_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S15_AXIS_DATA_WIDTH" spirit:order="9110" spirit:configGroups="8 NoDisplay" spirit:minimum="32" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S15_AXIS_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_BASEADDR</spirit:name>
+      <spirit:displayName>Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_BASEADDR" spirit:order="3040" spirit:configGroups="3 Instruction Cache Feature" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_HIGHADDR</spirit:name>
+      <spirit:displayName>High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_HIGHADDR" spirit:order="3030" spirit:configGroups="3 Instruction Cache Feature" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_ICACHE</spirit:name>
+      <spirit:displayName>Enable Instruction Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_ICACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3000" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_ICACHE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ALLOW_ICACHE_WR</spirit:name>
+      <spirit:displayName>Enable Writes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALLOW_ICACHE_WR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3050" spirit:configGroups="3 Instruction Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ALLOW_ICACHE_WR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ADDR_TAG_BITS</spirit:name>
+      <spirit:displayName>Set number of I-cache address tag bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_TAG_BITS" spirit:order="3200" spirit:configGroups="3 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ADDR_TAG_BITS">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CACHE_BYTE_SIZE</spirit:name>
+      <spirit:displayName>Size in Bytes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448" spirit:order="3010" spirit:configGroups="3 Instruction Cache Feature">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CACHE_BYTE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_LINE_LEN</spirit:name>
+      <spirit:displayName>Line Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf" spirit:order="3020" spirit:configGroups="3 Instruction Cache Feature">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_LINE_LEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_ALWAYS_USED</spirit:name>
+      <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3060" spirit:configGroups="3 Instruction Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_ALWAYS_USED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_VICTIMS</spirit:name>
+      <spirit:displayName>Number of Victims</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab" spirit:order="3090" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_VICTIMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_STREAMS</spirit:name>
+      <spirit:displayName>Number of Streams</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_STREAMS" spirit:choiceRef="choice_list_8af5a703" spirit:order="3080" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_STREAMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_FORCE_TAG_LUTRAM</spirit:name>
+      <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3070" spirit:configGroups="3 Instruction Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_FORCE_TAG_LUTRAM">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ICACHE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ICACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9" spirit:order="3220" spirit:configGroups="3 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ICACHE_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_THREAD_ID_WIDTH" spirit:order="8380" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_ADDR_WIDTH" spirit:order="8390" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_AWUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_AWUSER_WIDTH" spirit:order="8400" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_AWUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_ARUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_ARUSER_WIDTH" spirit:order="8410" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_ARUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_WUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_WUSER_WIDTH" spirit:order="8420" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_WUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_RUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_RUSER_WIDTH" spirit:order="8430" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_RUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_BUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_BUSER_WIDTH" spirit:order="8440" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_BUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IC_USER_VALUE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IC_USER_VALUE" spirit:order="8450" spirit:configGroups="8 NoDisplay">31</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IC_USER_VALUE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_BASEADDR</spirit:name>
+      <spirit:displayName>Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_BASEADDR" spirit:order="3140" spirit:configGroups="3 Data Cache Feature" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_HIGHADDR</spirit:name>
+      <spirit:displayName>High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_HIGHADDR" spirit:order="3130" spirit:configGroups="3 Data Cache Feature" spirit:bitStringLength="64">0x000000003FFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_DCACHE</spirit:name>
+      <spirit:displayName>Enable Data Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_DCACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3100" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_DCACHE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ALLOW_DCACHE_WR</spirit:name>
+      <spirit:displayName>Enable Writes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALLOW_DCACHE_WR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3150" spirit:configGroups="3 Data Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ALLOW_DCACHE_WR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_ADDR_TAG</spirit:name>
+      <spirit:displayName>Set number of D-cache address tag bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_ADDR_TAG" spirit:order="3230" spirit:configGroups="3 NoDisplay">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_ADDR_TAG">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_BYTE_SIZE</spirit:name>
+      <spirit:displayName>Size in Bytes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_BYTE_SIZE" spirit:choiceRef="choice_pairs_8b498448" spirit:order="3110" spirit:configGroups="3 Data Cache Feature">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_BYTE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_LINE_LEN</spirit:name>
+      <spirit:displayName>Line Length</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_LINE_LEN" spirit:choiceRef="choice_list_f86403bf" spirit:order="3120" spirit:configGroups="3 Data Cache Feature">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_LINE_LEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_ALWAYS_USED</spirit:name>
+      <spirit:displayName>Use Cache for All Memory Accesses</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_ALWAYS_USED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3160" spirit:configGroups="3 Data Cache Feature">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_ALWAYS_USED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_USE_WRITEBACK</spirit:name>
+      <spirit:displayName>Enable Write-back Storage Policy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_USE_WRITEBACK" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3180" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_USE_WRITEBACK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_VICTIMS</spirit:name>
+      <spirit:displayName>Number of Victims</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_VICTIMS" spirit:choiceRef="choice_list_b94541ab" spirit:order="3190" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_VICTIMS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_FORCE_TAG_LUTRAM</spirit:name>
+      <spirit:displayName>Use Distributed RAM for Tags</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_FORCE_TAG_LUTRAM" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3170" spirit:configGroups="3 Data Cache Feature">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_FORCE_TAG_LUTRAM">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_DCACHE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DCACHE_DATA_WIDTH" spirit:choiceRef="choice_pairs_b1fa18d9" spirit:order="3250" spirit:configGroups="3 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DCACHE_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_THREAD_ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_THREAD_ID_WIDTH" spirit:order="8280" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_THREAD_ID_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_ADDR_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_ADDR_WIDTH" spirit:order="8290" spirit:configGroups="8 NoDisplay">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_AWUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_AWUSER_WIDTH" spirit:order="8300" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_AWUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_ARUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_ARUSER_WIDTH" spirit:order="8310" spirit:configGroups="8 NoDisplay" spirit:minimum="5" spirit:maximum="5" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_ARUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_WUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_WUSER_WIDTH" spirit:order="8320" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_WUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_RUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DC_RUSER_WIDTH" spirit:order="8330" spirit:configGroups="8 NoDisplay" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_DC_RUSER_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_DC_BUSER_WIDTH</spirit:name>
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+      <spirit:name>C_USE_MMU</spirit:name>
+      <spirit:displayName>Memory Management</spirit:displayName>
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+      <spirit:name>C_MMU_DTLB_SIZE</spirit:name>
+      <spirit:displayName>Data Shadow Translation Look-Aside Buffer Size</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>C_MMU_TLB_ACCESS</spirit:name>
+      <spirit:displayName>Enable Access to Memory Management Special Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_TLB_ACCESS" spirit:choiceRef="choice_pairs_7ad6afc0" spirit:order="4300" spirit:configGroups="4 Memory Management Unit">3</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MMU_ZONES</spirit:name>
+      <spirit:displayName>Number of Memory Protection Zones</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_ZONES" spirit:order="4400" spirit:configGroups="4 Memory Management Unit" spirit:minimum="0" spirit:maximum="16" spirit:rangeType="long">16</spirit:value>
+      <spirit:vendorExtensions>
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+          <xilinx:enablement>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MMU_PRIVILEGED_INSTR</spirit:name>
+      <spirit:displayName>Privileged Instructions</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MMU_PRIVILEGED_INSTR" spirit:choiceRef="choice_pairs_443ae6cc" spirit:order="4500" spirit:configGroups="4 Memory Management Unit">0</spirit:value>
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+        </xilinx:parameterInfo>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_INTERRUPT</spirit:name>
+      <spirit:displayName>Use Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_INTERRUPT" spirit:choiceRef="choice_pairs_db57ca32" spirit:order="6300" spirit:configGroups="6 Interrupt">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>C_INTERRUPT_MON</spirit:name>
+      <spirit:displayName>Use Monitor Interface for Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERRUPT_MON" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6305" spirit:configGroups="6 Interrupt">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_EXT_BRK</spirit:name>
+      <spirit:displayName>Use Ext_Brk</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_EXT_BRK" spirit:choiceRef="choice_list_8af5a703" spirit:order="6400" spirit:configGroups="6 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_EXT_BRK">true</xilinx:isEnabled>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_EXT_NM_BRK</spirit:name>
+      <spirit:displayName>Use Ext_Nm_Brk</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_EXT_NM_BRK" spirit:choiceRef="choice_list_8af5a703" spirit:order="6500" spirit:configGroups="6 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_EXT_NM_BRK">true</xilinx:isEnabled>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_NON_SECURE</spirit:name>
+      <spirit:displayName>Use Non-Secure AXI access permission</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_NON_SECURE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6550" spirit:configGroups="6 NoDisplay">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_NON_SECURE">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_BRANCH_TARGET_CACHE</spirit:name>
+      <spirit:displayName>Enable Branch Target Cache</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_BRANCH_TARGET_CACHE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1090" spirit:configGroups="1 Optimization">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_BRANCH_TARGET_CACHE">true</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>C_BRANCH_TARGET_CACHE_SIZE</spirit:name>
+      <spirit:displayName>Branch Target Cache Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BRANCH_TARGET_CACHE_SIZE" spirit:choiceRef="choice_pairs_e7a1eb81" spirit:order="1100" spirit:configGroups="1 Optimization">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BRANCH_TARGET_CACHE_SIZE">true</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_microblaze_I_0</spirit:value>
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+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>MicroBlaze</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.DATA_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.PROTOCOL" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ILMB.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ILMB.DATA_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ILMB.PROTOCOL" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ILMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.LOW_LATENCY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ASYNC_WAKEUP" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DCACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DEBUG_ENABLED" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DEBUG_EXTERNAL_TRACE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_D_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EDGE_IS_POSITIVE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FAULT_TOLERANT" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_ALWAYS_USED" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_BASEADDR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ICACHE_HIGHADDR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_IS_EDGE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_I_LMB_PROTOCOL" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_DC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_M_AXI_IC_USER_SIGNALS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUMBER_OF_PC_BRK" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PC_WIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TRACE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_BARREL" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_DIV" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_BRK" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_EXT_NM_BRK" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_HW_MUL" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_INTERRUPT" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_NON_SECURE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_PCMP_INSTR" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_REORDER_INSTR" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
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+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="25f528f2"/>
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+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a1288105"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="50a8fdcb"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cf8c578c"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="33347ad3"/>
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+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/bd_afa8_rst_0_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/bd_afa8_rst_0_0.xci
new file mode 100644
index 0000000..41522a3
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/bd_afa8_rst_0_0.xci
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
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+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">bd_afa8_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_afa8_rst_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;slowest_sync_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ext_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;aux_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mb_debug_sys_rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dcm_locked&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mb_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;bus_struct_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;peripheral_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;interconnect_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;peripheral_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;clock&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;mb_reset:bus_struct_re
+set:interconnect_aresetn:peripheral_aresetn:peripheral_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;slowest_sync_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;ext_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:res
+et:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;ext_reset_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;aux_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;aux_reset_in&quot;,&quot;ph
+ysical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;dbg_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;mb_debug_sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;mb_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissi
+on&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;mb_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;bus_struct_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;bus_struct_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;interconnect_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_perm
+ission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;interconnect_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;peripheral_high_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;peripheral_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,
+&quot;logical_right&quot;:&quot;0&quot;}}},&quot;peripheral_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;peripheral_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/bd_afa8_rst_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/bd_afa8_rst_0_0.xml
new file mode 100644
index 0000000..cda083c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/bd_afa8_rst_0_0.xml
@@ -0,0 +1,691 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_rst_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>clock</spirit:name>
+      <spirit:displayName>Clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>slowest_sync_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
+          <spirit:description>Slowest Synchronous clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ext_reset</spirit:name>
+      <spirit:displayName>Ext_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>aux_reset</spirit:name>
+      <spirit:displayName>aux_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aux_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dbg_reset</spirit:name>
+      <spirit:displayName>DBG_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mb_debug_sys_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>mb_rst</spirit:name>
+      <spirit:displayName>MB_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mb_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>bus_struct_reset</spirit:name>
+      <spirit:displayName>bus_struct_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bus_struct_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interconnect_low_rst</spirit:name>
+      <spirit:displayName>interconnect_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interconnect_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>peripheral_high_rst</spirit:name>
+      <spirit:displayName>peripheral_high_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>peripheral_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>peripheral_low_rst</spirit:name>
+      <spirit:displayName>peripheral_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>peripheral_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>slowest_sync_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_reset_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>aux_reset_in</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mb_debug_sys_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dcm_locked</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mb_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>bus_struct_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_BUS_RST&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>peripheral_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_RST&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>interconnect_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>peripheral_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_ARESETN&apos;)) - 1)">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+        <spirit:displayName>Ext Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+        <spirit:displayName>Aux Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+        <spirit:displayName>Aux Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_BUS_RST</spirit:name>
+        <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_RST</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+        <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_caf95c77</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>resetn</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Processor Reset System</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+      <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_RST</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_BUS_RST</spirit:name>
+      <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+      <spirit:displayName>Aux Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+      <spirit:displayName>Ext Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+      <spirit:displayName>Aux Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+      <spirit:displayName>Ext Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_rst_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_caf95c77" spirit:order="3">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Processor System Reset</xilinx:displayName>
+      <xilinx:coreRevision>13</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xci
new file mode 100644
index 0000000..9bf2e77
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xci
@@ -0,0 +1,309 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>bd_afa8_iomodule_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="iomodule" spirit:version="3.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTC_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTC_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTC_IRQ.LOW_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT1_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT2_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PIT1_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PIT2_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PIT3_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.UART_INTERRUPT.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TMR_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UART_RST.RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AVOID_PRIMITIVES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BASEADDR">0x0000000080000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT1_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT2_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT3_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIT4_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FREQ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPI1_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPI2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPI2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPI3_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPI4_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPO1_INIT">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPO3_SIZE">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPO4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HIGHADDR">0x000000008000FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INSTANCE">iomodule</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_ADDR_WIDTH">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_ASYNC_INTR">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_BASE_VECTORS">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_HAS_FAST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_INTR_SIZE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_LEVEL_EDGE">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_NUM_SYNC_FF">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_POSITIVE">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTC_USE_EXT_INTR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IO_BASEADDR">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IO_HIGHADDR">0x00000000FFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IO_MASK">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MASK">0x00000000C0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT1_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT1_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT2_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT2_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT3_PRESCALER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT3_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT4_INTERRUPT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT4_READABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIT4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TMR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_ASYNC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_BAUDRATE">9600</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_FREQ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_NUM_SYNC_FF">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_ODD_PARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_PROG_BAUDRATE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_RX_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_TX_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UART_USE_PARITY">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO3_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS" xilinx:valueSource="propagated"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_IO_BUS" xilinx:valueSource="user"/>
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+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Addr_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Read_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Write_Strobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Address&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Byte_Enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Write_Data&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Read_Data&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;IO_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LM
+B_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_s
+rc&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,
+&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;Rst:TMR_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;
+:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{
+&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.TMR_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;IO_BUS&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mcsio_bus:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mcsio_bus_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Addr_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;IO_Address&quot;,&quot;phy
+sical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;IO_Byte_Enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_Read_Data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Read_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IO_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_Write_Data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_Write_Strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml
new file mode 100644
index 0000000..53d556e
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/bd_afa8_iomodule_0_0.xml
@@ -0,0 +1,8812 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_iomodule_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.CLK</spirit:name>
+      <spirit:displayName>Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF">SLMB</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET">Rst:TMR_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Clk frequency</spirit:displayName>
+          <spirit:description>Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+      <spirit:displayName>FIT2_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+          <spirit:vendorExtensions>
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+      <spirit:displayName>FIT3_Interrupt</spirit:displayName>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+      <spirit:displayName>FIT4_Interrupt</spirit:displayName>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.FIT4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
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+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT1_INTERRUPT.PortWidth">1</spirit:value>
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+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT3_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.PIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.PIT4_Interrupt</spirit:name>
+      <spirit:displayName>PIT4_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>PIT4_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PIT4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.PIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI1_Interrupt</spirit:name>
+      <spirit:displayName>GPI1_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI1_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI1_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI2_Interrupt</spirit:name>
+      <spirit:displayName>GPI2_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI2_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI2_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI3_Interrupt</spirit:name>
+      <spirit:displayName>GPI3_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI3_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI3_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.GPI4_Interrupt</spirit:name>
+      <spirit:displayName>GPI4_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI4_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.GPI4_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.GPI4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Interrupt</spirit:name>
+      <spirit:displayName>INTC_Interrupt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Interrupt" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Irq_Single</spirit:name>
+      <spirit:displayName>INTC_IRQ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_IRQ_SINGLE.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Irq_Single" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTC_Irq</spirit:name>
+      <spirit:displayName>INTC_IRQ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbinterrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Processor_Ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_Interrupt_Address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTC_IRQ.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LOW_LATENCY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTC_IRQ.LOW_LATENCY">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTC_Irq" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTC_Irq_Out</spirit:name>
+      <spirit:displayName>INTC_IRQ_OUT</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>INTC_IRQ_OUT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTC_IRQ_OUT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTC_Irq_Out" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_USE_IRQ_OUT&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART</spirit:name>
+      <spirit:displayName>UART</spirit:displayName>
+      <spirit:description>UART TX/RX</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RxD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TxD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART.BOARD.ASSOCIATED_PARAM">UART_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART_CLK.CLK</spirit:name>
+      <spirit:displayName>UART_Clk</spirit:displayName>
+      <spirit:description>Asynchronous UART Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.ASSOCIATED_BUSIF">SLMB</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.ASSOCIATED_RESET">UART_Rst:TMR_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>UART Clk frequency</spirit:displayName>
+          <spirit:description>UART Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART_CLK.CLK" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>UART_RST.Rst</spirit:name>
+      <spirit:displayName>UART_Rst</spirit:displayName>
+      <spirit:description>Asynchronous UART Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>UART_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.TYPE">PERIPHERAL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.UART_RST.RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.UART_RST.Rst" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO1</spirit:name>
+      <spirit:displayName>GPIO1</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO1</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_USE_GPO1" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_USE_GPO1" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO1_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPO1_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPO1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO1_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPO1_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPO1_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI1</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_USE_GPI1" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_USE_GPI1" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI1_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPI1_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPI1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO1.C_GPI1_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO1.C_GPI1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO1.BOARD.ASSOCIATED_PARAM">GPIO1_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO2</spirit:name>
+      <spirit:displayName>GPIO2</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO2</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_USE_GPO2" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_USE_GPO2" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO2_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPO2_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPO2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO2_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPO2_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPO2_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI2</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_USE_GPI2" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_USE_GPI2" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI2_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPI2_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPI2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO2.C_GPI2_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO2.C_GPI2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO2.BOARD.ASSOCIATED_PARAM">GPIO2_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO3</spirit:name>
+      <spirit:displayName>GPIO3</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO3</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_USE_GPO3" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_USE_GPO3" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO3_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPO3_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPO3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO3_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPO3_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPO3_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI3</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_USE_GPI3" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_USE_GPI3" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI3_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPI3_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPI3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO3.C_GPI3_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO3.C_GPI3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO3.BOARD.ASSOCIATED_PARAM">GPIO3_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>GPIO4</spirit:name>
+      <spirit:displayName>GPIO4</spirit:displayName>
+      <spirit:description>General Purpose IO</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_I</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPI4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRI_O</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>GPO4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPO4</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_USE_GPO4" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_USE_GPO4" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO4_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPO4_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPO4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPO4_INIT</spirit:name>
+          <spirit:value spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPO4_INIT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_INIT&apos;))">0x00000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPO4_INIT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_USE_GPI4</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_USE_GPI4" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_USE_GPI4" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI4_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPI4_SIZE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;))">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPI4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.GPIO4.C_GPI4_INTERRUPT" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;))">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIFPARAM_ENABLEMENT.GPIO4.C_GPI4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO4.BOARD.ASSOCIATED_PARAM">GPIO4_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>LMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="2048" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.REG.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.REG.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>UART_RX</spirit:name>
+          <spirit:displayName>UART Receive Data Register</spirit:displayName>
+          <spirit:description>UART Receive Data Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>Receive Data</spirit:displayName>
+            <spirit:description>Data received by the UART.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_RX" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_TX</spirit:name>
+          <spirit:displayName>UART Transmit Data Register</spirit:displayName>
+          <spirit:description>UART Transmit Data Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>Transmit Data</spirit:displayName>
+            <spirit:description>Data to be transmitted by the UART.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_TX" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_Status</spirit:name>
+          <spirit:displayName>UART Status Register</spirit:displayName>
+          <spirit:description>UART Status Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Rx_Valid_Data</spirit:name>
+            <spirit:displayName>Rx Valid Data</spirit:displayName>
+            <spirit:description>Indicates if the receive register has valid data:
+  0 - Receive register is empty.
+  1 - Receive register has valid data.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Tx_Used</spirit:name>
+            <spirit:displayName>Tx Used</spirit:displayName>
+            <spirit:description>Indicates if the transmit register is in use:
+  0 - Transmit register is not in use.
+  1 - Transmit register is in use.
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Overrun_Error</spirit:name>
+            <spirit:displayName>Overrun Error</spirit:displayName>
+            <spirit:description>Indicates that an overrun error has occurred:
+  0 - No overrun has occurred.
+  1 - An overrun has occurred.
+</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Frame_Error</spirit:name>
+            <spirit:displayName>Frame Error</spirit:displayName>
+            <spirit:description>Indicates that an frame error has occurred:
+  0 - No frame error has occurred.
+  1 - A frame error has occurred.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Parity_Error</spirit:name>
+            <spirit:displayName>Parity Error</spirit:displayName>
+            <spirit:description>Indicates that a parity error has occurred:
+  0 - No parity error has occurred.
+  1 - A parity error occurred.
+</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_MODE</spirit:name>
+          <spirit:displayName>Interrupt Mode Register</spirit:displayName>
+          <spirit:description>Interrupt Mode Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Mode</spirit:name>
+            <spirit:displayName>IRQ Mode</spirit:displayName>
+            <spirit:description>Interrupt Mode.
+For each bit:
+  W - When written with 1 the corresponding interrupt will use fast mode.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_MODE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_1</spirit:name>
+          <spirit:displayName>General Purpose Output 1 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 1 Register</spirit:description>
+          <spirit:addressOffset>0x10</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_2</spirit:name>
+          <spirit:displayName>General Purpose Output 2 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 2 Register</spirit:description>
+          <spirit:addressOffset>0x14</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_3</spirit:name>
+          <spirit:displayName>General Purpose Output 3 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 3 Register</spirit:description>
+          <spirit:addressOffset>0x18</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPO_4</spirit:name>
+          <spirit:displayName>General Purpose Output 4 Register</spirit:displayName>
+          <spirit:description>General Purpose Output 4 Register</spirit:description>
+          <spirit:addressOffset>0x1C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPO</spirit:name>
+            <spirit:displayName>General Purpose Output</spirit:displayName>
+            <spirit:description>General Purpose Output.
+For each bit:
+  W - Writes general purpose output value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPO_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_1</spirit:name>
+          <spirit:displayName>General Purpose Input 1 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 1 Register</spirit:description>
+          <spirit:addressOffset>0x20</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_2</spirit:name>
+          <spirit:displayName>General Purpose Input 2 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 2 Register</spirit:description>
+          <spirit:addressOffset>0x24</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_3</spirit:name>
+          <spirit:displayName>General Purpose Input 3 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 3 Register</spirit:description>
+          <spirit:addressOffset>0x28</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GPI_4</spirit:name>
+          <spirit:displayName>General Purpose Input 4 Register</spirit:displayName>
+          <spirit:description>General Purpose Input 4 Register</spirit:description>
+          <spirit:addressOffset>0x2C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INIT&apos;)))">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>GPI</spirit:name>
+            <spirit:displayName>General Purpose Input</spirit:displayName>
+            <spirit:description>General Purpose Input.
+For each bit:
+  R - Reads general purpose input value.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.GPI_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_STATUS</spirit:name>
+          <spirit:displayName>Interrupt Status Register</spirit:displayName>
+          <spirit:description>Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>0x30</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 lapsed.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 lapsed.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 lapsed.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 lapsed.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 strobe.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 strobe.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 strobe.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 strobe.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 changed.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 changed.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 changed.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 changed.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>External interrupt input signal</spirit:displayName>
+            <spirit:description>Interrupt Status Register.
+For each bit:
+  R - Reads active interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_STATUS" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_PENDING</spirit:name>
+          <spirit:displayName>Interrupt Pending Register</spirit:displayName>
+          <spirit:description>Interrupt Pending Register</spirit:description>
+          <spirit:addressOffset>0x34</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 lapsed.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 lapsed.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 lapsed.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 lapsed.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 strobe.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 strobe.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 strobe.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 strobe.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 changed.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 changed.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 changed.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 changed.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>Enabled interrupt events that have occurred</spirit:displayName>
+            <spirit:description>Interrupt Pending.
+For each bit:
+  R - Reads enabled interrupt event that has occurred.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_PENDING" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_ENABLE</spirit:name>
+          <spirit:displayName>Interrupt Enable Register</spirit:displayName>
+          <spirit:description>Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x38</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_ERR</spirit:name>
+            <spirit:displayName>UART Error</spirit:displayName>
+            <spirit:description>UART Error interrupt enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_TX</spirit:name>
+            <spirit:displayName>UART Transmitted Data</spirit:displayName>
+            <spirit:description>UART Transmitted Data interrupt enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>UART_RX</spirit:name>
+            <spirit:displayName>UART Received Data</spirit:displayName>
+            <spirit:description>UART Received Data interrupt enabled.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_1</spirit:name>
+            <spirit:displayName>PIT 1</spirit:displayName>
+            <spirit:description>PIT 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_2</spirit:name>
+            <spirit:displayName>PIT 2</spirit:displayName>
+            <spirit:description>PIT 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_3</spirit:name>
+            <spirit:displayName>PIT 3</spirit:displayName>
+            <spirit:description>PIT 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PIT_4</spirit:name>
+            <spirit:displayName>PIT 4</spirit:displayName>
+            <spirit:description>PIT 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_1</spirit:name>
+            <spirit:displayName>FIT 1</spirit:displayName>
+            <spirit:description>FIT 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_2</spirit:name>
+            <spirit:displayName>FIT 2</spirit:displayName>
+            <spirit:description>FIT 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_3</spirit:name>
+            <spirit:displayName>FIT 3</spirit:displayName>
+            <spirit:description>FIT 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>FIT_4</spirit:name>
+            <spirit:displayName>FIT 4</spirit:displayName>
+            <spirit:description>FIT 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_1</spirit:name>
+            <spirit:displayName>GPI 1</spirit:displayName>
+            <spirit:description>GPI 1 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>11</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_2</spirit:name>
+            <spirit:displayName>GPI 2</spirit:displayName>
+            <spirit:description>GPI 2 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_3</spirit:name>
+            <spirit:displayName>GPI 3</spirit:displayName>
+            <spirit:description>GPI 3 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>GPI_4</spirit:name>
+            <spirit:displayName>GPI 4</spirit:displayName>
+            <spirit:description>GPI 4 interrupt enabled.</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>INTC_Interrupt</spirit:name>
+            <spirit:displayName>Enable external interrupt input signals</spirit:displayName>
+            <spirit:description>Interrupt Enable.
+For each bit:
+  W - Enable external interrupt input signal.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_ENABLE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_ACK</spirit:name>
+          <spirit:displayName>Interrupt Acknowledge Register</spirit:displayName>
+          <spirit:description>Interrupt Acknowledge Register</spirit:description>
+          <spirit:addressOffset>0x3C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Acknowledge</spirit:name>
+            <spirit:displayName>IRQ Acknowledge</spirit:displayName>
+            <spirit:description>Interrupt Acknowledge.
+For each bit:
+  W - When written with 1 clear bit in IRQ_STATUS and IRQ_PENDING.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) + 16)">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_ACK" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 1 Preload Register</spirit:displayName>
+          <spirit:description>PIT 1 Preload Register</spirit:description>
+          <spirit:addressOffset>0x40</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT1_Preload</spirit:name>
+            <spirit:displayName>PIT1 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_COUNTER</spirit:name>
+          <spirit:displayName>PIT 1 Counter Register</spirit:displayName>
+          <spirit:description>PIT 1 Counter Register</spirit:description>
+          <spirit:addressOffset>0x44</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT1_Counter</spirit:name>
+            <spirit:displayName>PIT1 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT1_CONTROL</spirit:name>
+          <spirit:displayName>PIT 1 Control Register</spirit:displayName>
+          <spirit:description>PIT 1 Control Register</spirit:description>
+          <spirit:addressOffset>0x48</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT1_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT1_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UART_BAUD</spirit:name>
+          <spirit:displayName>UART Programmable Baud Rate</spirit:displayName>
+          <spirit:description>UART Programmable Baud Rate</spirit:description>
+          <spirit:addressOffset>0x4C</spirit:addressOffset>
+          <spirit:size spirit:format="long">8</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UART_BAUD</spirit:name>
+            <spirit:displayName>Baud Rate</spirit:displayName>
+            <spirit:description>Programmable UART Baud Rate.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">20</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.UART_BAUD" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_PROG_BAUDRATE&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 2 Preload Register</spirit:displayName>
+          <spirit:description>PIT 2 Preload Register</spirit:description>
+          <spirit:addressOffset>0x50</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT2_Preload</spirit:name>
+            <spirit:displayName>PIT2 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_COUNTER</spirit:name>
+          <spirit:displayName>PIT 2 Counter Register</spirit:displayName>
+          <spirit:description>PIT 2 Counter Register</spirit:description>
+          <spirit:addressOffset>0x54</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT2_Counter</spirit:name>
+            <spirit:displayName>PIT2 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT2_CONTROL</spirit:name>
+          <spirit:displayName>PIT 2 Control Register</spirit:displayName>
+          <spirit:description>PIT 2 Control Register</spirit:description>
+          <spirit:addressOffset>0x58</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT2_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT2_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 3 Preload Register</spirit:displayName>
+          <spirit:description>PIT 3 Preload Register</spirit:description>
+          <spirit:addressOffset>0x60</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT3_Preload</spirit:name>
+            <spirit:displayName>PIT3 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_COUNTER</spirit:name>
+          <spirit:displayName>PIT 3 Counter Register</spirit:displayName>
+          <spirit:description>PIT 3 Counter Register</spirit:description>
+          <spirit:addressOffset>0x64</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT3_Counter</spirit:name>
+            <spirit:displayName>PIT3 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT3_CONTROL</spirit:name>
+          <spirit:displayName>PIT 3 Control Register</spirit:displayName>
+          <spirit:description>PIT 3 Control Register</spirit:description>
+          <spirit:addressOffset>0x68</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT3_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT3_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_PRELOAD</spirit:name>
+          <spirit:displayName>PIT 4 Preload Register</spirit:displayName>
+          <spirit:description>PIT 4 Preload Register</spirit:description>
+          <spirit:addressOffset>0x70</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT4_Preload</spirit:name>
+            <spirit:displayName>PIT4 Preload</spirit:displayName>
+            <spirit:description>Determines the initial value of the counter and the timer period.
+The period is the value + 2.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_PRELOAD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_COUNTER</spirit:name>
+          <spirit:displayName>PIT 4 Counter Register</spirit:displayName>
+          <spirit:description>PIT 4 Counter Register</spirit:description>
+          <spirit:addressOffset>0x74</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>PIT4_Counter</spirit:name>
+            <spirit:displayName>PIT4 Counter</spirit:displayName>
+            <spirit:description>Samples the current counter value.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_SIZE&apos;)))">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_COUNTER" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>PIT4_CONTROL</spirit:name>
+          <spirit:displayName>PIT 4 Control Register</spirit:displayName>
+          <spirit:description>PIT 4 Control Register</spirit:description>
+          <spirit:addressOffset>0x78</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>EN</spirit:name>
+            <spirit:displayName>Enable</spirit:displayName>
+            <spirit:description>Count Enable:
+  0 - Counting Disabled.
+  1 - Counting Enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>PRELOAD</spirit:name>
+            <spirit:displayName>Preload</spirit:displayName>
+            <spirit:description>Counter preload:
+  0 - Counter counts past zero and then stops.
+  1 - Counter automatically reloaded with PIT4_PRELOAD.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.PIT4_CONTROL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_0</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 0</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 0</spirit:description>
+          <spirit:addressOffset>0x80</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 0 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_1</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 1</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 1</spirit:description>
+          <spirit:addressOffset>0x84</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 1 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_2</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 2</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 2</spirit:description>
+          <spirit:addressOffset>0x88</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 2 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_3</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 3</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 3</spirit:description>
+          <spirit:addressOffset>0x8C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 3 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_4</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 4</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 4</spirit:description>
+          <spirit:addressOffset>0x90</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 4 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_5</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 5</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 5</spirit:description>
+          <spirit:addressOffset>0x94</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 5 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_6</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 6</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 6</spirit:description>
+          <spirit:addressOffset>0x98</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 6 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_7</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 7</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 7</spirit:description>
+          <spirit:addressOffset>0x9C</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 7 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_8</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 8</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 8</spirit:description>
+          <spirit:addressOffset>0xA0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 8 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_9</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 9</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 9</spirit:description>
+          <spirit:addressOffset>0xA4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 9 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_10</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 10</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 10</spirit:description>
+          <spirit:addressOffset>0xA8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 10 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_11</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 11</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 11</spirit:description>
+          <spirit:addressOffset>0xAC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 11 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_12</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 12</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 12</spirit:description>
+          <spirit:addressOffset>0xB0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 12 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_13</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 13</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 13</spirit:description>
+          <spirit:addressOffset>0xB4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 13 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_14</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 14</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 14</spirit:description>
+          <spirit:addressOffset>0xB8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 14 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_14" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_16</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 16</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 16</spirit:description>
+          <spirit:addressOffset>0xC0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 16 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_16" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_17</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 17</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 17</spirit:description>
+          <spirit:addressOffset>0xC4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 17 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_17" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 2)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_18</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 18</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 18</spirit:description>
+          <spirit:addressOffset>0xC8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 18 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_18" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 3)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_19</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 19</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 19</spirit:description>
+          <spirit:addressOffset>0xCC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 19 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_19" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 4)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_20</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 20</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 20</spirit:description>
+          <spirit:addressOffset>0xD0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 20 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_20" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 5)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_21</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 21</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 21</spirit:description>
+          <spirit:addressOffset>0xD4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 21 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_21" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 6)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_22</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 22</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 22</spirit:description>
+          <spirit:addressOffset>0xD8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 22 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_22" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 7)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_23</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 23</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 23</spirit:description>
+          <spirit:addressOffset>0xDC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 23 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_23" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 8)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_24</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 24</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 24</spirit:description>
+          <spirit:addressOffset>0xE0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 24 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_24" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 9)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_25</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 25</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 25</spirit:description>
+          <spirit:addressOffset>0xE4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 25 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_25" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 10)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_26</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 26</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 26</spirit:description>
+          <spirit:addressOffset>0xE8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 26 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_26" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 11)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_27</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 27</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 27</spirit:description>
+          <spirit:addressOffset>0xEC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 27 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_27" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 12)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_28</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 28</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 28</spirit:description>
+          <spirit:addressOffset>0xF0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 28 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_28" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 13)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_29</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 29</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 29</spirit:description>
+          <spirit:addressOffset>0xF4</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 29 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_29" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 14)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_30</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 30</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 30</spirit:description>
+          <spirit:addressOffset>0xF8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 30 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_30" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 15)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_VECTOR_31</spirit:name>
+          <spirit:displayName>Interrupt Vector Register 31</spirit:displayName>
+          <spirit:description>Interrupt Vector Register 31</spirit:description>
+          <spirit:addressOffset>0xFC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="concat(&quot;0x&quot;,substring(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;)),11,16),10)">0x0000000010</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 31 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) &lt;= 32)) + 32 * number((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32)))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_VECTOR_31" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) = 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 16)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_0</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 0</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 0</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 0 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1))">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_1</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 1</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 1</spirit:description>
+          <spirit:addressOffset>0x108</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 1 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_2</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 2</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 2</spirit:description>
+          <spirit:addressOffset>0x110</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 2 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_3</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 3</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 3</spirit:description>
+          <spirit:addressOffset>0x118</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 3 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_4</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 4</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 4</spirit:description>
+          <spirit:addressOffset>0x120</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 4 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_4" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_5</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 5</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 5</spirit:description>
+          <spirit:addressOffset>0x128</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 5 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_5" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_6</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 6</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 6</spirit:description>
+          <spirit:addressOffset>0x130</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 6 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_6" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_7</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 7</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 7</spirit:description>
+          <spirit:addressOffset>0x138</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 7 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_7" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_8</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 8</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 8</spirit:description>
+          <spirit:addressOffset>0x140</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 8 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_8" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_9</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 9</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 9</spirit:description>
+          <spirit:addressOffset>0x148</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 9 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_9" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_10</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 10</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 10</spirit:description>
+          <spirit:addressOffset>0x150</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 10 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_10" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_11</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 11</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 11</spirit:description>
+          <spirit:addressOffset>0x158</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 11 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_11" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_12</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 12</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 12</spirit:description>
+          <spirit:addressOffset>0x160</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 12 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_12" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_13</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 13</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 13</spirit:description>
+          <spirit:addressOffset>0x168</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 13 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_13" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_14</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 14</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 14</spirit:description>
+          <spirit:addressOffset>0x170</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 14 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_14" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_16</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 16</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 16</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 16 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_16" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_17</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 17</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 17</spirit:description>
+          <spirit:addressOffset>0x188</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 17 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_17" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 2)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_18</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 18</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 18</spirit:description>
+          <spirit:addressOffset>0x190</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 18 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_18" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 3)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_19</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 19</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 19</spirit:description>
+          <spirit:addressOffset>0x198</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 19 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_19" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 4)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_20</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 20</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 20</spirit:description>
+          <spirit:addressOffset>0x1A0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 20 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_20" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 5)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_21</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 21</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 21</spirit:description>
+          <spirit:addressOffset>0x1A8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 21 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_21" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 6)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_22</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 22</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 22</spirit:description>
+          <spirit:addressOffset>0x1B0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 22 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_22" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 7)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_23</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 23</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 23</spirit:description>
+          <spirit:addressOffset>0x1B8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 23 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_23" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 8)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_24</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 24</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 24</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 24 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_24" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 9)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_25</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 25</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 25</spirit:description>
+          <spirit:addressOffset>0x1C8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 25 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_25" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 10)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_26</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 26</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 26</spirit:description>
+          <spirit:addressOffset>0x1D0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 26 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_26" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 11)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_27</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 27</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 27</spirit:description>
+          <spirit:addressOffset>0x1D8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 27 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_27" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 12)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_28</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 28</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 28</spirit:description>
+          <spirit:addressOffset>0x1E0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 28 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_28" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 13)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_29</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 29</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 29</spirit:description>
+          <spirit:addressOffset>0x1E8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 29 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_29" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 14)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_30</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 30</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 30</spirit:description>
+          <spirit:addressOffset>0x1F0</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 30 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_30" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 15)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IRQ_EA_VECTOR_31</spirit:name>
+          <spirit:displayName>Interrupt Vector Address Register 31</spirit:displayName>
+          <spirit:description>Interrupt Vector Address Register 31</spirit:description>
+          <spirit:addressOffset>0x1F8</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_BASE_VECTORS&apos;))">0x0000000000000000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>IRQ_Vector</spirit:name>
+            <spirit:displayName>Interrupt Vector Address</spirit:displayName>
+            <spirit:description>Interrupt vector address of active interrupt 31 with highest priority.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;))">17</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.SLMB.REG.IRQ_EA_VECTOR_31" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) > 32) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) >= 16)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+      <spirit:addressBlock>
+        <spirit:name>IO</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="4096" spirit:rangeType="long">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.IO.OFFSET_BASE_PARAM">C_IO_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.IO.OFFSET_HIGH_PARAM">C_IO_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:vendorExtensions>
+          <xilinx:addressBlockInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.SLMB.IO" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:addressBlockInfo>
+        </spirit:vendorExtensions>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Config_Reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Config_Reset" xilinx:dependency="false">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TMR_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.TMR_Rst" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_TMR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TMR_Disable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.TMR_Disable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_TMR&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_TMR_DISABLE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ToVote</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1023</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ToVote" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_TMR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FromAVote</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1023</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FromAVote" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_TMR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FromBVote</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1023</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FromBVote" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_TMR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Addr_Strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Addr_Strobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Read_Strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Read_Strobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Write_Strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Write_Strobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Address" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Byte_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Byte_Enable" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Write_Data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Write_Data" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Read_Data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Read_Data" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.IO_Ready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UART_Rx</spirit:name>
+        <spirit:displayName>Serial Data In</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UART_Rx" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UART_Tx</spirit:name>
+        <spirit:displayName>Serial Data Out</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UART_Tx" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
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+        <spirit:name>UART_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
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+        <spirit:name>UART_Clk</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:name>UART_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UART_Rst" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ASYNC&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>FIT1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT1_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT1_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>FIT2_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT2_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>FIT3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>FIT3_Toggle</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT3_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>FIT4_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>FIT4_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.FIT4_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
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+        <spirit:name>PIT1_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT1_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1)">false</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>PIT2_Enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        <spirit:name>PIT2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>PIT2_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT2_Toggle" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>PIT3_Enable</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
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+        <spirit:name>PIT3_Interrupt</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>PIT3_Toggle</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>PIT4_Enable</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.PIT4_Enable" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_PRESCALER&apos;)) = 9)">false</xilinx:isEnabled>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPO2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPO3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO3_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPO3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPO4</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPO4_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPO4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI1_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI1_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI2_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI2_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI3_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI3_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI4</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_SIZE&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>GPI4_Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.GPI4_Interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Interrupt</spirit:name>
+        <spirit:displayName>Interrupt Inputs</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_INTR_SIZE&apos;)) - 1)">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Interrupt" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_IRQ</spirit:name>
+        <spirit:displayName>Interrupt Request Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Processor_Ack</spirit:name>
+        <spirit:displayName>Interrupt Acknowledgement Input</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Processor_Ack" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_Interrupt_Address</spirit:name>
+        <spirit:displayName>Interrupt Vector Address Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(( ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) + 31) / 64) * (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_ADDR_WIDTH&apos;)) - 32) + 32) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_Interrupt_Address" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 1) and (spirit:decode(id(&apos;PARAM_VALUE.C_INTC_IRQ_CONNECTION&apos;)) = 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>INTC_IRQ_OUT</spirit:name>
+        <spirit:displayName>Interrupt Request Output</spirit:displayName>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.INTC_IRQ_OUT" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_USE_IRQ_OUT&apos;)) = 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_RX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_TX_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT1_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT2_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT3_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PIT4_INTERRUPT&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI1_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI2_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI3_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_GPI4_INTERRUPT&apos;)) > 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREQ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_INSTANCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INSTANCE">iomodule</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CONFIG_RESET">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AVOID_PRIMITIVES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TMR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TMR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_TMR_DISABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_TMR_DISABLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000008000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_HIGHADDR" spirit:bitStringLength="64">0x00000000FFFFFFFF</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_HIGHADDR" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_BASEADDR" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_BASEADDR" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_IO_MASK</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IO_MASK" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_IO_MASK" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_IO_BUS&apos;)) = 1">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_IO_BUS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_IO_BUS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_UART_RX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_UART_RX">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_UART_TX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_UART_TX">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_BAUDRATE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_BAUDRATE">9600</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_BAUDRATE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_DATA_BITS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_DATA_BITS" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_DATA_BITS" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_USE_PARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_USE_PARITY">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_USE_PARITY" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ODD_PARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ODD_PARITY">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_ODD_PARITY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_UART_USE_PARITY&apos;)) >= 1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_RX_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_RX_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_RX_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_TX_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_TX_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_TX_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ERROR_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ERROR_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_ERROR_INTERRUPT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_PROG_BAUDRATE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_PROG_BAUDRATE">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UART_PROG_BAUDRATE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_RX&apos;)) = 1) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_UART_TX&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_FREQ" spirit:minimum="0" spirit:rangeType="long">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_ASYNC</spirit:name>
+        <spirit:displayName>Asynchronous Clock</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_ASYNC" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UART_NUM_SYNC_FF</spirit:name>
+        <spirit:displayName>Synchronizing FFs to Clk region</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UART_NUM_SYNC_FF" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT1_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT1_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT1_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT1_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT2_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT2_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT2_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT2_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT3_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT3_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT3_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT3_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIT4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIT4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT4_No_CLOCKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT4_No_CLOCKS" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT4_No_CLOCKS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FIT4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FIT4_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FIT4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_FIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT1_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT2_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT3_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIT4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIT4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_READABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_READABLE">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_READABLE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_PRESCALER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_PRESCALER" spirit:minimum="0" spirit:maximum="9" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_PRESCALER" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PIT4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PIT4_INTERRUPT">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_PIT4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PIT4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO1_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO1_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO1_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO2_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO2_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO2_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO3_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO3_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO3_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPO4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPO4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPO4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
+        <spirit:name>C_GPO4_INIT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPO4_INIT" spirit:bitStringLength="32">0x00000000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPO4_INIT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPO4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI1_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI1_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI1_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI1_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI1_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI1&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI2_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI2_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI2_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI2_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI2_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI2&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI3_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI3_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI3_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI3_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI3_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI3&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_GPI4</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_GPI4">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI4_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI4_SIZE" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI4_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GPI4_INTERRUPT" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_GPI4_INTERRUPT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_GPI4&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_USE_EXT_INTR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_USE_EXT_INTR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_INTR_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_INTR_SIZE" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_INTR_SIZE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_LEVEL_EDGE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_LEVEL_EDGE" spirit:bitStringLength="16">0x0000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_LEVEL_EDGE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_POSITIVE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_POSITIVE" spirit:bitStringLength="16">0xFFFF</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTC_POSITIVE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTC_USE_EXT_INTR&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_HAS_FAST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_HAS_FAST" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_ADDR_WIDTH" spirit:minimum="5" spirit:maximum="64" spirit:rangeType="long">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_INTC_BASE_VECTORS</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_BASE_VECTORS" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector(15 downto 0)">
+        <spirit:name>C_INTC_ASYNC_INTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_ASYNC_INTR" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTC_NUM_SYNC_FF</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTC_NUM_SYNC_FF" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0739ee39</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>rs232_uart</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_38e5a9f1</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>dip_switches_4bits</spirit:enumeration>
+      <spirit:enumeration>led_3bits</spirit:enumeration>
+      <spirit:enumeration>qsfp0_lowspeed</spirit:enumeration>
+      <spirit:enumeration>qsfp1_lowspeed</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8af5a703</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f585525a</spirit:name>
+      <spirit:enumeration>110</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>1200</spirit:enumeration>
+      <spirit:enumeration>2400</spirit:enumeration>
+      <spirit:enumeration>4800</spirit:enumeration>
+      <spirit:enumeration>9600</spirit:enumeration>
+      <spirit:enumeration>19200</spirit:enumeration>
+      <spirit:enumeration>38400</spirit:enumeration>
+      <spirit:enumeration>57600</spirit:enumeration>
+      <spirit:enumeration>115200</spirit:enumeration>
+      <spirit:enumeration>128000</spirit:enumeration>
+      <spirit:enumeration>230400</spirit:enumeration>
+      <spirit:enumeration>460800</spirit:enumeration>
+      <spirit:enumeration>921600</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_007f01e9</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4847022f</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_5f1e379e</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT1">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_7ba91213</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Both Edges">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Rising Edge">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="Falling Edge">3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_d4609148</spirit:name>
+      <spirit:enumeration spirit:text="Bus">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f0f6eb36</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT3">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="FIT4">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT2">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT3">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="PIT4">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="External">9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ffa336e4</spirit:name>
+      <spirit:enumeration spirit:text="Even">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Odd">1</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>LMB module which includes plenty of I/O peripherals</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_USE_CONFIG_RESET</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_CONFIG_RESET" spirit:order="1110" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AVOID_PRIMITIVES" spirit:order="1120" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_TMR</spirit:name>
+      <spirit:displayName>Use Triple Modular Redundancy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TMR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1125" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_TMR_DISABLE</spirit:name>
+      <spirit:displayName>Activate TMR Disable Input</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_TMR_DISABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1128" spirit:configGroups="1 System">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_TMR_DISABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FREQ" spirit:order="1090" spirit:configGroups="1 System">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INSTANCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="1100" spirit:configGroups="1 System">iomodule</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_BASE_VECTORS</spirit:name>
+      <spirit:displayName>MicroBlaze Relocatable Base Vector Value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_BASE_VECTORS" spirit:order="1130" spirit:configGroups="1 NoDisplay" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>I/O Module Register Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1000" spirit:configGroups="1 System" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>I/O Module Register High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1010" spirit:configGroups="1 System" spirit:bitStringLength="64">0x000000008000FFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>I/O Module Register Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1020" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_IO_BUS</spirit:name>
+      <spirit:displayName>Enable IO Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_IO_BUS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1030" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_BASEADDR</spirit:name>
+      <spirit:displayName>I/O Module IO Bus Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_BASEADDR" spirit:order="1040" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_BASEADDR" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_HIGHADDR</spirit:name>
+      <spirit:displayName>I/O Module IO Bus High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_HIGHADDR" spirit:order="1050" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000FFFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_HIGHADDR" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_IO_MASK</spirit:name>
+      <spirit:displayName>I/O Module IO Bus Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IO_MASK" spirit:order="1060" spirit:configGroups="1 System" spirit:bitStringLength="64">0x00000000C0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_IO_MASK" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1070" spirit:configGroups="1 System" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1080" spirit:configGroups="1 System">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1085" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_UART_RX</spirit:name>
+      <spirit:displayName>Enable Receiver</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_UART_RX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 UART">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_UART_TX</spirit:name>
+      <spirit:displayName>Enable Transmitter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_UART_TX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100" spirit:configGroups="2 UART">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_BAUDRATE</spirit:name>
+      <spirit:displayName>Define Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_BAUDRATE" spirit:choiceRef="choice_list_f585525a" spirit:order="2200" spirit:configGroups="2 UART">9600</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_BAUDRATE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_PROG_BAUDRATE</spirit:name>
+      <spirit:displayName>Programmable Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_PROG_BAUDRATE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_PROG_BAUDRATE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_DATA_BITS</spirit:name>
+      <spirit:displayName>Number of Data Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_DATA_BITS" spirit:order="2400" spirit:configGroups="2 UART" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_DATA_BITS" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_USE_PARITY</spirit:name>
+      <spirit:displayName>Use Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_USE_PARITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_USE_PARITY" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_ODD_PARITY</spirit:name>
+      <spirit:displayName>Even or Odd Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_ODD_PARITY" spirit:choiceRef="choice_pairs_ffa336e4" spirit:order="2600" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_ODD_PARITY" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_RX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Receive Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_RX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2700" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_RX_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_TX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Transmit Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_TX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2800" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_TX_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UART_ERROR_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Error Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UART_ERROR_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2900" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UART_ERROR_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT1</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3010" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT1_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT1_No_CLOCKS" spirit:order="3020" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT1_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3030" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT2</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3040" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT2_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT2_No_CLOCKS" spirit:order="3050" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT2_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3060" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT3</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3070" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT3_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT3_No_CLOCKS" spirit:order="3080" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT3_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3090" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_FIT4</spirit:name>
+      <spirit:displayName>Use FIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_FIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3100" spirit:configGroups="3 FIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT4_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT4_No_CLOCKS" spirit:order="3110" spirit:configGroups="3 FIT" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT4_No_CLOCKS" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3120" spirit:configGroups="3 FIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIT4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT1</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4010" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_SIZE" spirit:order="4020" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4030" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_PRESCALER" spirit:choiceRef="choice_pairs_f0f6eb36" spirit:order="4040" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4050" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT1_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT2</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4060" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_SIZE" spirit:order="4070" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4080" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_PRESCALER" spirit:choiceRef="choice_pairs_007f01e9" spirit:order="4090" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4100" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT2_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT3</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4110" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_SIZE" spirit:order="4120" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4130" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_PRESCALER" spirit:choiceRef="choice_pairs_4847022f" spirit:order="4140" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4150" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT3_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_PIT4</spirit:name>
+      <spirit:displayName>Use PIT</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_PIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4160" spirit:configGroups="4 PIT">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_SIZE" spirit:order="4170" spirit:configGroups="4 PIT" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4180" spirit:configGroups="4 PIT">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_READABLE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_PRESCALER" spirit:choiceRef="choice_pairs_5f1e379e" spirit:order="4190" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_PRESCALER" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_PIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4200" spirit:configGroups="4 PIT">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_PIT4_INTERRUPT" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO1</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5010" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO1_SIZE" spirit:order="5020" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO1_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO1_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO1_INIT" spirit:order="5030" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO1_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO2</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5040" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO2_SIZE" spirit:order="5050" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO2_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO2_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO2_INIT" spirit:order="5060" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO2_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO3</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5070" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO3_SIZE" spirit:order="5080" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO3_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO3_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO3_INIT" spirit:order="5090" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO3_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPO4</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPO4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5100" spirit:configGroups="5 GPO">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO4_SIZE" spirit:order="5110" spirit:configGroups="5 GPO" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO4_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPO4_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPO4_INIT" spirit:order="5120" spirit:configGroups="5 GPO" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPO4_INIT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI1</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6010" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI1_SIZE" spirit:order="6020" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI1_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI1_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6030" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI1_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI2</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6040" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI2_SIZE" spirit:order="6050" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI2_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI2_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6060" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI2_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI3</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6070" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI3_SIZE" spirit:order="6080" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI3_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI3_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6090" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI3_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_USE_GPI4</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_GPI4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 GPI">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI4_SIZE" spirit:order="6110" spirit:configGroups="6 GPI" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI4_SIZE" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_GPI4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPI4_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6120" spirit:configGroups="6 GPI">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_GPI4_INTERRUPT" xilinx:dependency="true">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_HAS_FAST</spirit:name>
+      <spirit:displayName>Use Low-latency Interrupt Handling</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_HAS_FAST" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7100" spirit:configGroups="7 Interrupt">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_USE_EXT_INTR</spirit:name>
+      <spirit:displayName>Use External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_USE_EXT_INTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7200" spirit:configGroups="7 Interrupt">0</spirit:value>
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+    <spirit:parameter>
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+      <spirit:displayName>Use Separate Interrupt Output</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_USE_IRQ_OUT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7250" spirit:configGroups="7 Interrupt">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_IRQ_CONNECTION</spirit:name>
+      <spirit:displayName>Interrupt Output Connection</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_IRQ_CONNECTION" spirit:choiceRef="choice_pairs_d4609148" spirit:order="7280">0</spirit:value>
+      <spirit:vendorExtensions>
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+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_IRQ_CONNECTION" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_INTC_HAS_FAST&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_INTR_SIZE</spirit:name>
+      <spirit:displayName>Number of External Inputs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_INTR_SIZE" spirit:order="7300" spirit:configGroups="7 Interrupt" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_INTR_SIZE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_LEVEL_EDGE</spirit:name>
+      <spirit:displayName>Level or Edge of External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_LEVEL_EDGE" spirit:order="7400" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0x0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_LEVEL_EDGE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_POSITIVE</spirit:name>
+      <spirit:displayName>Positive or Negative External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_POSITIVE" spirit:order="7500" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_POSITIVE" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Interrupt Address Width</spirit:displayName>
+      <spirit:description>Interrupt address width with Fast Mode Interrupt.</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_ADDR_WIDTH" spirit:order="7600" spirit:configGroups="7 Interrupt" spirit:minimum="5" spirit:maximum="64" spirit:rangeType="long">17</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTC_ADDR_WIDTH" xilinx:dependency="true">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_ASYNC_INTR</spirit:name>
+      <spirit:displayName>Interrupts asynchronous</spirit:displayName>
+      <spirit:description>The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous.</spirit:description>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_ASYNC_INTR" spirit:order="7700" spirit:bitStringLength="16">0xFFFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTC_NUM_SYNC_FF</spirit:name>
+      <spirit:displayName>Number of synchronization flip-flops</spirit:displayName>
+      <spirit:description>Number of synchronization flip-flops used to synchronize asynchronous interupt inputs</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTC_NUM_SYNC_FF" spirit:order="7800" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_iomodule_0_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="100" spirit:configGroups="0 Board">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO1_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="110" spirit:configGroups="0 Board">Custom</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO2_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="120" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO3_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO3_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="130" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO4_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="140" spirit:configGroups="0 Board">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:choiceRef="choice_list_0739ee39" spirit:order="150" spirit:configGroups="0 Board">Custom</spirit:value>
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+  <spirit:vendorExtensions>
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+      <xilinx:configElementInfos>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INSTANCE" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_ASYNC_INTR" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_BASE_VECTORS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_HAS_FAST" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_INTR_SIZE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_LEVEL_EDGE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_POSITIVE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTC_USE_IRQ_OUT" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IO_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_IO_BUS" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
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+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="08f03615"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="8aacb230"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="4fae1825"/>
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+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xci
new file mode 100644
index 0000000..7d91c47
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xci
@@ -0,0 +1,159 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
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+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_v10" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_afa8_ilmb_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;SYS_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;63&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;1&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;1&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;}},&quot;interfaces&quot;:{&quot;LMB_Sl_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_W
+IDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_
+rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBU
+S&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;63&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_M&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb
+:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredMaster&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_ONLY&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;M_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;M_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;LMB_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;
+,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;LMB_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;LMB_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;LMB_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;M_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;M_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;SYS_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[
+{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.SYS_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;SYS_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xml
new file mode 100644
index 0000000..c9f4cdb
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/bd_afa8_ilmb_0.xml
@@ -0,0 +1,3532 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_ilmb_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_0</spirit:name>
+      <spirit:displayName>LMB_Sl_00</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">31</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_0" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_1</spirit:name>
+      <spirit:displayName>LMB_Sl_01</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">32</spirit:left>
+              <spirit:right spirit:format="long">63</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_2</spirit:name>
+      <spirit:displayName>LMB_Sl_02</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">64</spirit:left>
+              <spirit:right spirit:format="long">95</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_3</spirit:name>
+      <spirit:displayName>LMB_Sl_03</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">96</spirit:left>
+              <spirit:right spirit:format="long">127</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_4</spirit:name>
+      <spirit:displayName>LMB_Sl_04</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">128</spirit:left>
+              <spirit:right spirit:format="long">159</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_5</spirit:name>
+      <spirit:displayName>LMB_Sl_05</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">160</spirit:left>
+              <spirit:right spirit:format="long">191</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_6</spirit:name>
+      <spirit:displayName>LMB_Sl_06</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">192</spirit:left>
+              <spirit:right spirit:format="long">223</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_6" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_7</spirit:name>
+      <spirit:displayName>LMB_Sl_07</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">224</spirit:left>
+              <spirit:right spirit:format="long">255</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_7" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_8</spirit:name>
+      <spirit:displayName>LMB_Sl_08</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">256</spirit:left>
+              <spirit:right spirit:format="long">287</spirit:right>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_8" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_9</spirit:name>
+      <spirit:displayName>LMB_Sl_09</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">288</spirit:left>
+              <spirit:right spirit:format="long">319</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_10</spirit:name>
+      <spirit:displayName>LMB_Sl_10</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">320</spirit:left>
+              <spirit:right spirit:format="long">351</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_10" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_11</spirit:name>
+      <spirit:displayName>LMB_Sl_11</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">352</spirit:left>
+              <spirit:right spirit:format="long">383</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_11" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_12</spirit:name>
+      <spirit:displayName>LMB_Sl_12</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">384</spirit:left>
+              <spirit:right spirit:format="long">415</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_13</spirit:name>
+      <spirit:displayName>LMB_Sl_13</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">416</spirit:left>
+              <spirit:right spirit:format="long">447</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_14</spirit:name>
+      <spirit:displayName>LMB_Sl_14</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">448</spirit:left>
+              <spirit:right spirit:format="long">479</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_14" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_15</spirit:name>
+      <spirit:displayName>LMB_Sl_15</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">480</spirit:left>
+              <spirit:right spirit:format="long">511</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_15" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_M</spirit:name>
+      <spirit:displayName>LMB_M</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Master interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredMaster/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">SYS_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.SYS_Rst</spirit:name>
+      <spirit:displayName>SYS_Rst</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>SYS_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:channels>
+    <spirit:channel>
+      <spirit:name>LMB_Channel</spirit:name>
+      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_0</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_2</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
+    </spirit:channel>
+  </spirit:channels>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>SYS_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:wire>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:wire>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_Wait</spirit:name>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:wireTypeDef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
+        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Awidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>C Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
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+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
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+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
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+      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>C Lmb Awidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1300" spirit:configGroups="1 LMB" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
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+          <xilinx:enablement>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_ilmb_0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="751c672a"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/bd_afa8_dlmb_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/bd_afa8_dlmb_0.xci
new file mode 100644
index 0000000..1dfaf3f
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/bd_afa8_dlmb_0.xci
@@ -0,0 +1,165 @@
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_PROTOCOL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_afa8_dlmb_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.PROTOCOL" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;SYS_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;M_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;M_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;95&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;2&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phy
+sical_right&quot;:&quot;2&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;}},&quot;interfaces&quot;:{&quot;LMB_Sl_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_W
+IDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_1&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_
+rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBU
+S&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;63&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;1&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;LMB_Sl_2&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:
+lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredSlave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right
+&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;64&quot;,&quot;physical_right&quot;:&quot;95&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;2&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_r
+ight&quot;:&quot;0&quot;}}},&quot;LMB_M&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;mirroredMaster&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;M_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;M_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_
+name&quot;:&quot;LMB_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;M_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;LMB_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;LMB_UE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;LMB_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;M_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;M_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;SYS_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permiss
+ion&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.SYS_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;SYS_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/bd_afa8_dlmb_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/bd_afa8_dlmb_0.xml
new file mode 100644
index 0000000..8c32633
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/bd_afa8_dlmb_0.xml
@@ -0,0 +1,3536 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_dlmb_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_0</spirit:name>
+      <spirit:displayName>LMB_Sl_00</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 0</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">31</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">0</spirit:left>
+              <spirit:right spirit:format="long">0</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_0" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_1</spirit:name>
+      <spirit:displayName>LMB_Sl_01</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 1</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">32</spirit:left>
+              <spirit:right spirit:format="long">63</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">1</spirit:left>
+              <spirit:right spirit:format="long">1</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_2</spirit:name>
+      <spirit:displayName>LMB_Sl_02</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 2</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">64</spirit:left>
+              <spirit:right spirit:format="long">95</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">2</spirit:left>
+              <spirit:right spirit:format="long">2</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_3</spirit:name>
+      <spirit:displayName>LMB_Sl_03</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 3</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">96</spirit:left>
+              <spirit:right spirit:format="long">127</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">3</spirit:left>
+              <spirit:right spirit:format="long">3</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_4</spirit:name>
+      <spirit:displayName>LMB_Sl_04</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 4</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">128</spirit:left>
+              <spirit:right spirit:format="long">159</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">4</spirit:left>
+              <spirit:right spirit:format="long">4</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_4.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_4" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_5</spirit:name>
+      <spirit:displayName>LMB_Sl_05</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">160</spirit:left>
+              <spirit:right spirit:format="long">191</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">5</spirit:left>
+              <spirit:right spirit:format="long">5</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_6</spirit:name>
+      <spirit:displayName>LMB_Sl_06</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">192</spirit:left>
+              <spirit:right spirit:format="long">223</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">6</spirit:left>
+              <spirit:right spirit:format="long">6</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_6" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_7</spirit:name>
+      <spirit:displayName>LMB_Sl_07</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">224</spirit:left>
+              <spirit:right spirit:format="long">255</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">7</spirit:left>
+              <spirit:right spirit:format="long">7</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_7.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_7" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 7">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_8</spirit:name>
+      <spirit:displayName>LMB_Sl_08</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 8</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">256</spirit:left>
+              <spirit:right spirit:format="long">287</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">8</spirit:left>
+              <spirit:right spirit:format="long">8</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_8.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_8" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 8">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_9</spirit:name>
+      <spirit:displayName>LMB_Sl_09</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">288</spirit:left>
+              <spirit:right spirit:format="long">319</spirit:right>
+            </spirit:vector>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">9</spirit:left>
+              <spirit:right spirit:format="long">9</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_10</spirit:name>
+      <spirit:displayName>LMB_Sl_10</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">320</spirit:left>
+              <spirit:right spirit:format="long">351</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">10</spirit:left>
+              <spirit:right spirit:format="long">10</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_10" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 10">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_11</spirit:name>
+      <spirit:displayName>LMB_Sl_11</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 11</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">352</spirit:left>
+              <spirit:right spirit:format="long">383</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">11</spirit:left>
+              <spirit:right spirit:format="long">11</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_11" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 11">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_12</spirit:name>
+      <spirit:displayName>LMB_Sl_12</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">384</spirit:left>
+              <spirit:right spirit:format="long">415</spirit:right>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">12</spirit:left>
+              <spirit:right spirit:format="long">12</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_13</spirit:name>
+      <spirit:displayName>LMB_Sl_13</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">416</spirit:left>
+              <spirit:right spirit:format="long">447</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">13</spirit:left>
+              <spirit:right spirit:format="long">13</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_14</spirit:name>
+      <spirit:displayName>LMB_Sl_14</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">448</spirit:left>
+              <spirit:right spirit:format="long">479</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">14</spirit:left>
+              <spirit:right spirit:format="long">14</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_14" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 14">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_Sl_15</spirit:name>
+      <spirit:displayName>LMB_Sl_15</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredSlave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">480</spirit:left>
+              <spirit:right spirit:format="long">511</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+            <spirit:vector>
+              <spirit:left spirit:format="long">15</spirit:left>
+              <spirit:right spirit:format="long">15</spirit:right>
+            </spirit:vector>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_15" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 15">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>LMB_M</spirit:name>
+      <spirit:displayName>LMB_M</spirit:displayName>
+      <spirit:description>Local Memory Bus Mirrored Master interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:mirroredMaster/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">SYS_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.SYS_Rst</spirit:name>
+      <spirit:displayName>SYS_Rst</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>SYS_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:channels>
+    <spirit:channel>
+      <spirit:name>LMB_Channel</spirit:name>
+      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_0</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_2</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
+      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
+    </spirit:channel>
+  </spirit:channels>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>SYS_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>M_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;))) - 1)">95</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">2</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
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+      <spirit:port>
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+      <spirit:port>
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+          <spirit:direction>out</spirit:direction>
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+      <spirit:port>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
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+      <spirit:port>
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+        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">3</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>C Lmb Awidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>C Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
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+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
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+      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1400" spirit:configGroups="1 Parameters">0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="751c672a"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci
new file mode 100644
index 0000000..8c879e1
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xci
@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml
new file mode 100644
index 0000000..08c2b4d
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/bd_afa8_dlmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_dlmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">65536</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteDBus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_AddrStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ReadStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>BRAM_Din_A</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4100" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_PROTOCOL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Protocol</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL" spirit:order="4300" spirit:configGroups="4 S AXI CTRL">AXI4LITE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_PROTOCOL" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_dlmb_cntlr_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>LMB BRAM Controller</xilinx:displayName>
+      <xilinx:coreRevision>19</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xci
new file mode 100644
index 0000000..d2c1ed5
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xml
new file mode 100644
index 0000000..9ff9637
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/bd_afa8_ilmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_ilmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">65536</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
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+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
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+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x000000000000FFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_ilmb_cntlr_0</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f6139c3b"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci
new file mode 100644
index 0000000..de3259a
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xci
@@ -0,0 +1,298 @@
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_afa8_lmb_bram_I_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">bd_afa8_lmb_bram_I_0.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">BRAM_Controller</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;web&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dinb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta_busy&quot;:{&quot;direction&quot;:&quot;ou
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_V
+IP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;
+},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rsta&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;65536&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_lef
+t&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dinb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rstb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;web&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml
new file mode 100644
index 0000000..be458ff
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/bd_afa8_lmb_bram_I_0.xml
@@ -0,0 +1,4151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_lmb_bram_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">65536</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
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+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
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+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
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+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
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+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
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+        <spirit:name>dina</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>douta</spirit:name>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>clkb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>eccpipece</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>rdaddrecc</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rdaddrecc" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) != 0) and id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;) != &apos;virtex5&apos;)) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)))">false</xilinx:isEnabled>
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+        <spirit:name>sleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sleep" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;artixu&apos;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplushbm&apos;  or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus58g&apos;or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;zynquplus&apos;))and spirit:decode(id(&apos;MODELPARAM_VALUE.C_EN_SLEEP_PIN&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>deepsleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">bd_afa8_lmb_bram_I_0.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">16384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     19.660986 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0132492a</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_302d3091</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f9a6a28b</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1f270a52</spirit:name>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_246d8066</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a6697bba</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_lmb_bram_I_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_f9a6a28b" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_a6697bba" spirit:order="8">True_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_302d3091" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="32" spirit:maximum="1024" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">16384</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_6fc15197" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0132492a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_6fc15197" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xci
new file mode 100644
index 0000000..1ab688b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.PROTOCOL" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_PROTOCOL" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK2" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
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+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xml
new file mode 100644
index 0000000..c4cf828
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/bd_afa8_second_dlmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_second_dlmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">32768</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteDBus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_AddrStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ReadStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_WriteStrobe" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>BRAM_Din_A</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000C0010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4100" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_PROTOCOL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Protocol</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL" spirit:order="4300" spirit:configGroups="4 S AXI CTRL">AXI4LITE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_PROTOCOL" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_second_dlmb_cntlr_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>LMB BRAM Controller</xilinx:displayName>
+      <xilinx:coreRevision>19</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci
new file mode 100644
index 0000000..4ba85ff
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xci
@@ -0,0 +1,189 @@
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;LMB_Clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_Rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ABus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_WriteDBus&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;LMB_AddrStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_ReadStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_WriteStrobe&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;LMB_BE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;Sl_DBus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;Sl_Ready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_Wait&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_UE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;Sl_CE&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Rst_A&quot;:{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Clk_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_Addr_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_EN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;BRAM_WEN_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;},&quot;BRAM_Dout_A&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;},&quot;BRAM_Din_A&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;}},&quot;interfaces&quot;:{&quot;SLMB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:lmb:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:lmb_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PROTOCOL&quot;:[{
+&quot;value&quot;:&quot;STANDARD&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ABUS&quot;:{&quot;physical_name&quot;:&quot;LMB_ABus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;ADDRSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_AddrStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BE&quot;:{&quot;physical_name&quot;:&quot;LMB_BE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;CE&quot;:{&quot;physical_name&quot;:&quot;Sl_CE&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READDBUS&quot;:{&quot;physical_name&quot;:&quot;Sl_DBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;READSTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_ReadStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;Sl_Ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;UE&quot;:{&quot;physical_name&quot;:&quot;Sl_UE&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WAIT&quot;:{&quot;physical_name&quot;:&quot;Sl_Wait&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITEDBUS&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteDBus&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;WRITESTROBE&quot;:{&quot;physical_name&quot;:&quot;LMB_WriteStrobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORT&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;r
+esolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;BRAM_Addr_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;BRAM_Clk_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;BRAM_Dout_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;BRAM_Din_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;BRAM_EN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;BRAM_Rst_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;BRA
+M_WEN_A&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;}}},&quot;CLK.LMB_Clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;SLMB:SLMB1:SLMB2:SLMB3&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;LMB_Rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;bd_afa8_Clk&quot;},{&quot;value_src&quot;:&quot;constant_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;LMB_Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.LMB_Rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;LMB_Rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.S_AXI_CTRL_ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permis
+sion&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;S_AXI_CTRL_ARESETN&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.S_AXI_CTRL_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:
+&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xml
new file mode 100644
index 0000000..ffdda68
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/bd_afa8_second_ilmb_cntlr_0.xml
@@ -0,0 +1,4011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_second_ilmb_cntlr_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.INTERRUPT</spirit:name>
+      <spirit:displayName>Interrupt</spirit:displayName>
+      <spirit:description>Interrupt output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUGGESTED_PRIORITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.SUGGESTED_PRIORITY">HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.INTERRUPT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:displayName>SLMB</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:displayName>SLMB1</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB1"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl1_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB1_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB1.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:displayName>SLMB2</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB2"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl2_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB2_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB2.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:displayName>SLMB3</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="SLMB3"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ABUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ABus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_AddrStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_BE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_CE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_DBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READSTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_ReadStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>UE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_UE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WAIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Sl3_Wait</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITEDBUS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteDBus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITESTROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB3_WriteStrobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLMB3.PROTOCOL">STANDARD</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SLMB3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORT</spirit:name>
+      <spirit:displayName>BRAM_PORT</spirit:displayName>
+      <spirit:description>Data Processor Local Bus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Addr_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Clk_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Dout_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Din_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_EN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_Rst_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>BRAM_WEN_A</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">32768</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE">BRAM_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:displayName>S_AXI_CTRL</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_CTRL"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_CTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.LMB_Clk</spirit:name>
+      <spirit:displayName>LMB_Clk</spirit:displayName>
+      <spirit:description>Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_BUSIF">SLMB:SLMB1:SLMB2:SLMB3</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.ASSOCIATED_RESET">LMB_Rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>LMB_Clk frequency</spirit:displayName>
+          <spirit:description>LMB_Clk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.LMB_Rst</spirit:name>
+      <spirit:displayName>Reset</spirit:displayName>
+      <spirit:description>Reset</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>LMB_Rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.TYPE">INTERCONNECT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.LMB_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.S_AXI_CTRL_ACLK</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ACLK</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ACLK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_BUSIF">S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.ASSOCIATED_RESET">S_AXI_CTRL_ARESETN</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_AXI_CTRL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.S_AXI_CTRL_ARESETN</spirit:name>
+      <spirit:displayName>S_AXI_CTRL_ARESETN</spirit:displayName>
+      <spirit:description>Slave AXI4Lite Control Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_AXI_CTRL_ARESETN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_AXI_CTRL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>SLMB</spirit:name>
+      <spirit:description>SLMB memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB1</spirit:name>
+      <spirit:description>SLMB1 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB1.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB2</spirit:name>
+      <spirit:description>SLMB2 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB2.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>SLMB3</spirit:name>
+      <spirit:description>SLMB3 memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Mem</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">8192</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.SLMB3.MEM.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_CTRL</spirit:name>
+      <spirit:description>S_AXI_CTRL memory map</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>ECC_Status</spirit:name>
+          <spirit:displayName>ECC Status Register</spirit:displayName>
+          <spirit:description>ECC Status Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_Status</spirit:name>
+            <spirit:displayName>UE Status</spirit:displayName>
+            <spirit:description>Indicates if an uncorrectable error has occurred:
+  0 - No uncorrectable error occurred.
+  1 - Uncorrectable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_Status</spirit:name>
+            <spirit:displayName>CE Status</spirit:displayName>
+            <spirit:description>Indicates if a correctable error has occurred:
+  0 - No correctable error occurred.
+  1 - Correctable error occurred, cleared when 1 is written.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_Status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_EN_IRQ</spirit:name>
+          <spirit:displayName>ECC Interrupt Enable Register</spirit:displayName>
+          <spirit:description>ECC Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>0x4</spirit:addressOffset>
+          <spirit:size spirit:format="long">2</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_EN_IRQ</spirit:name>
+            <spirit:displayName>UE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register UE bit:
+  0 - UE bit is not propagated to interrupt signal.
+  1 - UE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CE_EN_IRQ</spirit:name>
+            <spirit:displayName>CE Enable Interrupt</spirit:displayName>
+            <spirit:description>Determines effect of ECC Status Register CE bit:
+  0 - CE bit is not propagated to interrupt signal.
+  1 - CE bit is propagated to interrupt signal.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_EN_IRQ" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>ECC_ONOFF</spirit:name>
+          <spirit:displayName>ECC On/Off Register</spirit:displayName>
+          <spirit:description>ECC On/Off Register</spirit:description>
+          <spirit:addressOffset>0x8</spirit:addressOffset>
+          <spirit:size spirit:format="long">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE&apos;))">1</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>ON_OFF</spirit:name>
+            <spirit:displayName>On/Off</spirit:displayName>
+            <spirit:description>Determines if ECC checking is enabled:
+  0 - ECC checking is disabled.
+  1 - ECC checking is enabled.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.ECC_ONOFF" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_CNT</spirit:name>
+          <spirit:displayName>Correctable Error Counter Register</spirit:displayName>
+          <spirit:description>Correctable Error Counter Register</spirit:description>
+          <spirit:addressOffset>0xC</spirit:addressOffset>
+          <spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_CNT</spirit:name>
+            <spirit:displayName>Correctable Error Count</spirit:displayName>
+            <spirit:description>Holds number of correctable errors encountered.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) + number(spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) = 0))">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_CNT" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_COUNTER_WIDTH&apos;)) > 0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFD</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x100</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFD</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFE</spirit:name>
+          <spirit:displayName>Correctable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x180</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFE</spirit:name>
+            <spirit:displayName>Correctable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>CE_FFA</spirit:name>
+          <spirit:displayName>Correctable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Correctable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x1C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CE_FFA</spirit:name>
+            <spirit:displayName>Correctable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of a correctable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.CE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFD</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Data Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Data Register</spirit:description>
+          <spirit:addressOffset>0x200</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFD</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Data</spirit:displayName>
+            <spirit:description>Data of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFD" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFE</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing ECC Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing ECC Register</spirit:description>
+          <spirit:addressOffset>0x280</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFE</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing ECC</spirit:displayName>
+            <spirit:description>ECC of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>UE_FFA</spirit:name>
+          <spirit:displayName>Uncorrectable Error First Failing Address Register</spirit:displayName>
+          <spirit:description>Uncorrectable Error First Failing Address Register</spirit:description>
+          <spirit:addressOffset>0x2C0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>UE_FFA</spirit:name>
+            <spirit:displayName>Uncorrectable Error First Failing Address</spirit:displayName>
+            <spirit:description>Address of the first occurrence of an uncorrectable error.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.UE_FFA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_UE_FAILING_REGISTERS&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_D</spirit:name>
+          <spirit:displayName>Fault Inject Data Register</spirit:displayName>
+          <spirit:description>Fault Inject Data Register</spirit:description>
+          <spirit:addressOffset>0x300</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_D</spirit:name>
+            <spirit:displayName>Fault Inject Data</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next data word written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_D" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>FI_ECC</spirit:name>
+          <spirit:displayName>Fault Inject ECC Register</spirit:displayName>
+          <spirit:description>Fault Inject ECC Register</spirit:description>
+          <spirit:addressOffset>0x380</spirit:addressOffset>
+          <spirit:size spirit:format="long">7</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>FI_ECC</spirit:name>
+            <spirit:displayName>Fault Inject ECC</spirit:displayName>
+            <spirit:description>Bits set to 1 toggle the bits of next ECC written.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">7</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>write-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_CTRL.REG.FI_ECC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAULT_INJECT&apos;)) = 1)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>LMB_Clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_Rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_AddrStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_ReadStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_WriteStrobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB_BE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) / 8) - 1)">3</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_DBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_Wait</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Sl_CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_ABus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.LMB1_ABus" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>LMB1_WriteDBus</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_WREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_BREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_BREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARADDR</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARADDR" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_ARREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_ARREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RDATA</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RDATA" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RRESP</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RRESP" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RVALID</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RVALID" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>S_AXI_CTRL_RREADY</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXI_CTRL_RREADY" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>UE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.UE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>CE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.CE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>Interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.Interrupt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) > 0) and  (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_LMB</spirit:name>
+        <spirit:displayName>Number of LMB Ports</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_LMB" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK</spirit:name>
+        <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK1</spirit:name>
+        <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK1" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK1" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK2</spirit:name>
+        <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK2" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK2" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_MASK3</spirit:name>
+        <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK3" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_MASK3" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_LMB&apos;)) > 3">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_AWIDTH</spirit:name>
+        <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_DWIDTH</spirit:name>
+        <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LMB_PROTOCOL</spirit:name>
+        <spirit:displayName>LMB Protocol</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC</spirit:name>
+        <spirit:displayName>Error Correction Code</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERCONNECT</spirit:name>
+        <spirit:displayName>Select Interconnect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_INTERCONNECT" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FAULT_INJECT</spirit:name>
+        <spirit:displayName>Fault Inject Registers</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_FAULT_INJECT" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_ACCESS&apos;)) != 0))">false</xilinx:isEnabled>
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+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+        <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_UE_FAILING_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
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+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+        <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+        <spirit:displayName>ECC On/Off Register</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+        <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+        <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_CE_COUNTER_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) != 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRITE_ACCESS</spirit:name>
+        <spirit:displayName>Write Access setting</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2">2</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_WRITE_ACCESS" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ECC&apos;)) = 1">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_BRAM_AWIDTH</spirit:name>
+        <spirit:displayName>BRAM Address Bus Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BRAM_AWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_CTRL_DATA_WIDTH</spirit:name>
+        <spirit:displayName>S_AXI_CTRL Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXI_CTRL_DATA_WIDTH" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0873e75e</spirit:name>
+      <spirit:enumeration spirit:text="STANDARD">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="FREQUENCY">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_449ac0d2</spirit:name>
+      <spirit:enumeration spirit:text="NONE">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="WORD_ONLY">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="FULL">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4873554b</spirit:name>
+      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8d6e70ff</spirit:name>
+      <spirit:enumeration spirit:text="None">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_BASEADDR</spirit:name>
+      <spirit:displayName>LMB BRAM Base Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1100" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_HIGHADDR</spirit:name>
+      <spirit:displayName>LMB BRAM High Address</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1200" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000017FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK</spirit:name>
+      <spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="1300" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000080010000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK1</spirit:name>
+      <spirit:displayName>SLMB1 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK1" spirit:order="1400" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK2</spirit:name>
+      <spirit:displayName>SLMB2 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK2" spirit:order="1500" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_MASK3</spirit:name>
+      <spirit:displayName>SLMB3 Address Decode Mask</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK3" spirit:order="1600" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000000800000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_MASK3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_LMB</spirit:name>
+      <spirit:displayName>Number of LMB Ports</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_LMB" spirit:order="1000" spirit:configGroups="1 Addresses" spirit:minimum="1" spirit:maximum="4" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_LMB">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_AWIDTH</spirit:name>
+      <spirit:displayName>LMB Address Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1700" spirit:configGroups="1 Addresses" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_DWIDTH</spirit:name>
+      <spirit:displayName>LMB Data Bus Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1800" spirit:configGroups="1 Addresses">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_LMB_PROTOCOL</spirit:name>
+      <spirit:displayName>LMB Protocol</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_PROTOCOL" spirit:choiceRef="choice_pairs_0873e75e" spirit:order="1900" spirit:configGroups="1 Parameters">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_INTERCONNECT</spirit:name>
+      <spirit:displayName>Select Interconnect</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERCONNECT" spirit:choiceRef="choice_pairs_8d6e70ff" spirit:order="2100" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INTERCONNECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_FAULT_INJECT</spirit:name>
+      <spirit:displayName>Fault Inject Registers</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAULT_INJECT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAULT_INJECT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Correctable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_UE_FAILING_REGISTERS</spirit:name>
+      <spirit:displayName>Uncorrectable Error First Failing Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_UE_FAILING_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2400" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_UE_FAILING_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_STATUS_REGISTERS</spirit:name>
+      <spirit:displayName>ECC Status and Control Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_STATUS_REGISTERS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_STATUS_REGISTERS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_REGISTER</spirit:name>
+      <spirit:displayName>ECC On/Off Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_REGISTER" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2600" spirit:configGroups="2 ECC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_REGISTER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_ECC_ONOFF_RESET_VALUE</spirit:name>
+      <spirit:displayName>ECC On/Off Reset Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE" spirit:order="2700" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_ECC_ONOFF_RESET_VALUE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_CE_COUNTER_WIDTH</spirit:name>
+      <spirit:displayName>Correctable Error Counter Register Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_CE_COUNTER_WIDTH" spirit:order="2800" spirit:configGroups="2 ECC" spirit:minimum="0" spirit:maximum="30" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_CE_COUNTER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_WRITE_ACCESS</spirit:name>
+      <spirit:displayName>Write Access setting</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_WRITE_ACCESS" spirit:choiceRef="choice_pairs_449ac0d2" spirit:order="2900" spirit:configGroups="2 ECC">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_WRITE_ACCESS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ACLK_FREQ_HZ</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Clock Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ACLK_FREQ_HZ" spirit:order="4200" spirit:configGroups="4 S AXI CTRL">100000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ACLK_FREQ_HZ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERCONNECT&apos;)) = 2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S_AXI_CTRL_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>S_AXI_CTRL Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="4000" spirit:configGroups="4 S AXI CTRL">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI_CTRL_ADDR_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK1" xilinx:valuePermission="bd_and_user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK3" xilinx:valuePermission="bd_and_user"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f6139c3b"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci
new file mode 100644
index 0000000..e441f33
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xci
@@ -0,0 +1,298 @@
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_afa8_second_lmb_bram_I_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">bd_afa8_second_lmb_bram_I_0.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;web&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dinb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rsta_busy&quot;:{&quot;direction&quot;:&quot;ou
+t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rstb_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_V
+IP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;
+},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rsta&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0
+&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;32768&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;ip_propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;user_prop&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;BRAM_CTRL&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;},{&quot;value_src&quot;:&quot;propagated&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;bd&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_lef
+t&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dinb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RST&quot;:{&quot;physical_name&quot;:&quot;rstb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;web&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml
new file mode 100644
index 0000000..2960628
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/bd_afa8_second_lmb_bram_I_0.xml
@@ -0,0 +1,4151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>bd_afa8_second_lmb_bram_I_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">32768</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
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+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
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+      </spirit:portMaps>
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+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">32768</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
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+      </spirit:vendorExtensions>
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+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
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+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_READ_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rstb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rstb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>enb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.enb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and(spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>regceb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regceb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        <spirit:name>web</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>eccpipece</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>rdaddrecc</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rdaddrecc" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) != 0) and id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;) != &apos;virtex5&apos;)) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)))">false</xilinx:isEnabled>
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+        <spirit:name>sleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sleep" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;artixu&apos;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplushbm&apos;  or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus58g&apos;or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;zynquplus&apos;))and spirit:decode(id(&apos;MODELPARAM_VALUE.C_EN_SLEEP_PIN&apos;)) = 1)">false</xilinx:isEnabled>
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+        <spirit:name>deepsleep</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">bd_afa8_second_lmb_bram_I_0.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     17.246228 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0132492a</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_302d3091</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f9a6a28b</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1f270a52</spirit:name>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_246d8066</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a6697bba</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_afa8_second_lmb_bram_I_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_f9a6a28b" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_a6697bba" spirit:order="8">True_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_302d3091" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="32" spirit:maximum="1024" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">8192</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_6fc15197" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0132492a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_6fc15197" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_1f270a52" spirit:order="3">BRAM_Controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">bd_afa8_second_lmb_bram_I_0.mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9c3516e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/phy_rdimm_x8_dual_microblaze_mcs.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/phy_rdimm_x8_dual_microblaze_mcs.xci
new file mode 100644
index 0000000..cda91b1
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/phy_rdimm_x8_dual_microblaze_mcs.xci
@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>phy_rdimm_x8_dual_microblaze_mcs</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze_mcs" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET">Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM">CLK_BOARD_INTERFACE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVOID_PRIMITIVES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BSCANID">76547328</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_rdimm_x8_dual_microblaze_mcs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEBUG_ENABLED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_No_CLOCKS">6216</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI1_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_INTERRUPT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO3_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO2_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO2_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO3_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO3_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO4_INIT">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO4_SIZE">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_ASYNC_INTR">0xFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_INTR_SIZE">1</spirit:configurableElementValue>
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+solve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;ASSOCIATED_ASYNC_RESET&quot;:[{&quot;value&quot;:&quot;Reset&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;CLK_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;Clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.Reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;user&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;gene
+rated&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;Reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;IO&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mcsio_bus:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mcsio_bus_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_addr_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ADDRESS&quot;:{&quot;physical_name&quot;:&quot;IO_address&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;IO_byte_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_read_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_read_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READY&quot;:{&quot;physical_name&quot;:&quot;IO_ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_righ
+t&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;IO_write_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_STROBE&quot;:{&quot;physical_name&quot;:&quot;IO_write_strobe&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;TRACE&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:mbtrace:2.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:mbtrace_rtl:2.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;DATA_ACCESS&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_ADDRESS&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_address&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DATA_BYTE_ENABLE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_byte_enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;3&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;3&quot;},&quot;DATA_READ&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;
+},&quot;DATA_WRITE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DATA_WRITE_VALUE&quot;:{&quot;physical_name&quot;:&quot;TRACE_data_write_value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;DCACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_READ&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DCACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;TRACE_dcache_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DELAY_SLOT&quot;:{&quot;physical_name&quot;:&quot;TRACE_delay_slot&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EX_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_ex_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;p
+hysical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EXCEPTION_KIND&quot;:{&quot;physical_name&quot;:&quot;TRACE_exception_kind&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;EXCEPTION_TAKEN&quot;:{&quot;physical_name&quot;:&quot;TRACE_exception_taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_RDY&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_rdy&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ICACHE_REQ&quot;:{&quot;physical_name&quot;:&quot;TRACE_icache_req&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;INSTRUCTION&quot;:{&quot;physical_name&quot;:&quot;TRACE_instruction&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;JUMP_HIT&quot;:{&quot;physical_name&quot;:&quot;TRACE_jump_hit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;JUMP_TAKEN&quot;
+:{&quot;physical_name&quot;:&quot;TRACE_jump_taken&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MB_HALTED&quot;:{&quot;physical_name&quot;:&quot;TRACE_mb_halted&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MEM_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_mem_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;MSR_REG&quot;:{&quot;physical_name&quot;:&quot;TRACE_msr_reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;14&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;14&quot;},&quot;NEW_REG_VALUE&quot;:{&quot;physical_name&quot;:&quot;TRACE_new_reg_value&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;OF_PIPERUN&quot;:{&quot;physical_name&quot;:&quot;TRACE_of_piperun&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PC&quot;:{&quot;physical_name&quot;:&quot;TRACE_pc&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;31&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;31&quot;},&quot;PID_REG&quot;:{&quot;physical_name&quot;:&quot;TRACE_pid_reg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;7&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical
+_right&quot;:&quot;7&quot;},&quot;REG_ADDR&quot;:{&quot;physical_name&quot;:&quot;TRACE_reg_addr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;4&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;4&quot;},&quot;REG_WRITE&quot;:{&quot;physical_name&quot;:&quot;TRACE_reg_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;VALID_INSTR&quot;:{&quot;physical_name&quot;:&quot;TRACE_valid_instr&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/phy_rdimm_x8_dual_microblaze_mcs.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/phy_rdimm_x8_dual_microblaze_mcs.xml
new file mode 100644
index 0000000..697f8a3
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/phy_rdimm_x8_dual_microblaze_mcs.xml
@@ -0,0 +1,2227 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_rdimm_x8_dual_microblaze_mcs</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.Clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">bd_afa8_Clk</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET">Reset</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM">CLK_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.Reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>Reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>IO</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mcsio_bus" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mcsio_bus_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR_STROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_addr_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDRESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_ENABLE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_STROBE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>IO_read_strobe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READY</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_ready</spirit:name>
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+            <spirit:name>WRITE_DATA</spirit:name>
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+          <spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>WRITE_STROBE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>IO_write_strobe</spirit:name>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mbtrace_rtl" spirit:version="2.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>DATA_ACCESS</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_access</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_ADDRESS</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_address</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_BYTE_ENABLE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_byte_enable</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_READ</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_read</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_write</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_WRITE_VALUE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_data_write_value</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_HIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_hit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_RDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_rdy</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DCACHE_READ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_read</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DCACHE_REQ</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_dcache_req</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DELAY_SLOT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_delay_slot</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>EX_PIPERUN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_ex_piperun</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_KIND</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_exception_kind</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EXCEPTION_TAKEN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_exception_taken</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_HIT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_hit</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_RDY</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_rdy</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ICACHE_REQ</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_icache_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INSTRUCTION</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_instruction</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>JUMP_HIT</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_jump_hit</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>JUMP_TAKEN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_jump_taken</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>MB_HALTED</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_mb_halted</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>MEM_PIPERUN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_mem_piperun</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>MSR_REG</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_msr_reg</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NEW_REG_VALUE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_new_reg_value</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>OF_PIPERUN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_of_piperun</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>PC</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_pc</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PID_REG</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_pid_reg</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>REG_ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_reg_addr</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REG_WRITE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>TRACE_reg_write</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>VALID_INSTR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>TRACE_valid_instr</spirit:name>
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+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
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+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_elaborateports</spirit:name>
+        <spirit:displayName>Elaborate Ports</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaborateports_view_fileset</spirit:localName>
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+      <spirit:view>
+        <spirit:name>xilinx_elaboratebd</spirit:name>
+        <spirit:displayName>Elaborate BD</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.bd</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaboratebd_view_fileset</spirit:localName>
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+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:9a8bf86c</spirit:value>
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+      <spirit:port>
+        <spirit:name>Clk</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>Reset</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_access</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_address</spirit:name>
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+            <spirit:left spirit:format="long">0</spirit:left>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_byte_enable</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_read</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_write</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_data_write_value</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_rdy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_read</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_dcache_req</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_delay_slot</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_ex_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_exception_kind</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">4</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_exception_taken</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_rdy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_icache_req</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_instruction</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_jump_hit</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      <spirit:port>
+        <spirit:name>TRACE_jump_taken</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      <spirit:port>
+        <spirit:name>TRACE_mb_halted</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>TRACE_mem_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:name>TRACE_msr_reg</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_new_reg_value</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_of_piperun</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_pc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_pid_reg</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">7</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_reg_addr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">4</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_reg_write</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>TRACE_valid_instr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+      <spirit:port>
+        <spirit:name>IO_addr_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
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+      <spirit:port>
+        <spirit:name>IO_address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_byte_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_read_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_read_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_ready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_write_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>IO_write_strobe</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_elaborateports_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../bd_0/bd_afa8.bd</spirit:name>
+        <spirit:userFileType>block_diagram</spirit:userFileType>
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+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratebd_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../bd_0/bd_afa8.bd</spirit:name>
+        <spirit:userFileType>block_diagram</spirit:userFileType>
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+  <spirit:description>MicroBlaze Micro Controller System (MCS) is a light-weight general purpose micro controller system, based on the MicroBlaze processor. It is primarily intended for simple control applications, where a hardware solution would be less flexible and more difficult to implement. Software development with the Xilinx Software Development Kit (SDK) is supported, including a software driver for the peripherals. Debugging including UART is available either via SDK or directly with the Xilinx Microprocessor Debugger.
+The MCS consists of the processor itself, local memory with sizes ranging from 4KB to 128KB, up to 4 Fixed Interval Timers, up to 4 Programmable Interval Timers, up to 4 32-bit General Purpose Output ports, up to 4 32-bit General Purpose Input ports, and an Interrupt Controller with up to 16 external interrupt inputs.
+</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>JTAG_CHAIN</spirit:name>
+      <spirit:displayName>Debug JTAG User-defined Register</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.JTAG_CHAIN" spirit:choiceRef="choice_pairs_5502e96b" spirit:order="1065" spirit:configGroups="1 NoDisplay">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.JTAG_CHAIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MICROBLAZE_INSTANCE</spirit:name>
+      <spirit:displayName>MicroBlaze Instance Name</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MICROBLAZE_INSTANCE" spirit:order="1010" spirit:configGroups="1 NoDisplay">microblaze_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AVOID_PRIMITIVES</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AVOID_PRIMITIVES" spirit:order="1015" spirit:configGroups="1 NoDisplay">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PATH</spirit:name>
+      <spirit:displayName>Instance Hierarchical Design Name</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PATH" spirit:order="1020" spirit:configGroups="1 NoDisplay">mcs_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FREQ</spirit:name>
+      <spirit:displayName>Input Clock Frequency (MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ" spirit:order="1030" spirit:configGroups="1 System">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OPTIMIZATION</spirit:name>
+      <spirit:displayName>Select MicroBlaze Optimization</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZATION" spirit:choiceRef="choice_pairs_563648c8" spirit:order="1025" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DEBUG_ENABLED</spirit:name>
+      <spirit:displayName>Enable Debug Support</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEBUG_ENABLED" spirit:choiceRef="choice_pairs_0d2d32a8" spirit:order="1060" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BSCAN</spirit:name>
+      <spirit:displayName>Select BSCAN location</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BSCAN" spirit:choiceRef="choice_pairs_366c5f3d" spirit:order="1062" spirit:configGroups="1 System">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_BSCAN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BSCANID</spirit:name>
+      <spirit:displayName>Define BSCAN id</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BSCANID" spirit:order="1064" spirit:configGroups="1 System">76547328</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.BSCANID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TRACE</spirit:name>
+      <spirit:displayName>Enable MicroBlaze Trace Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TRACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1070" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:displayName>Error Correction Code</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1035" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEMSIZE</spirit:name>
+      <spirit:displayName>Memory Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEMSIZE" spirit:choiceRef="choice_pairs_f7e0b771" spirit:order="1040" spirit:configGroups="1 System">98304</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEMTYPE</spirit:name>
+      <spirit:displayName>Memory Type</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MEMTYPE" spirit:choiceRef="choice_pairs_9de6ed99" spirit:order="1045" spirit:configGroups="1 System">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_IO_BUS</spirit:name>
+      <spirit:displayName>Enable IO Bus</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_IO_BUS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1050" spirit:configGroups="1 System">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_UART_RX</spirit:name>
+      <spirit:displayName>Enable Receiver</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_UART_RX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_UART_RX">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_UART_TX</spirit:name>
+      <spirit:displayName>Enable Transmitter</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_UART_TX" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_UART_TX">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BAUDRATE</spirit:name>
+      <spirit:displayName>Define Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BAUDRATE" spirit:choiceRef="choice_list_f585525a" spirit:order="2200" spirit:configGroups="2 UART">9600</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_BAUDRATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_PROG_BAUDRATE</spirit:name>
+      <spirit:displayName>Programmable Baud Rate</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_PROG_BAUDRATE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2300" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_PROG_BAUDRATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_DATA_BITS</spirit:name>
+      <spirit:displayName>Number of Data Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_DATA_BITS" spirit:order="2400" spirit:configGroups="2 UART" spirit:minimum="5" spirit:maximum="8" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_DATA_BITS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_USE_PARITY</spirit:name>
+      <spirit:displayName>Use Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_USE_PARITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2500" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_USE_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_ODD_PARITY</spirit:name>
+      <spirit:displayName>Even or Odd Parity</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_ODD_PARITY" spirit:choiceRef="choice_pairs_ffa336e4" spirit:order="2600" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_ODD_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_RX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Receive Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_RX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2700" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_RX_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_TX_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Transmit Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_TX_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2800" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_TX_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_ERROR_INTERRUPT</spirit:name>
+      <spirit:displayName>Implement Error Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_ERROR_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2900" spirit:configGroups="2 UART">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_ERROR_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT1</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3001" spirit:configGroups="3 FIT1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT1_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT1_No_CLOCKS" spirit:order="3002" spirit:configGroups="3 FIT1" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT1_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3005" spirit:configGroups="3 FIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT2</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3101" spirit:configGroups="3 FIT2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT2_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT2_No_CLOCKS" spirit:order="3102" spirit:configGroups="3 FIT2" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT2_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3105" spirit:configGroups="3 FIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT3</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3201" spirit:configGroups="3 FIT3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT3_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT3_No_CLOCKS" spirit:order="3202" spirit:configGroups="3 FIT3" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT3_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3205" spirit:configGroups="3 FIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FIT4</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3301" spirit:configGroups="3 FIT4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT4_No_CLOCKS</spirit:name>
+      <spirit:displayName>Number of Clocks Between Strobes</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT4_No_CLOCKS" spirit:order="3302" spirit:configGroups="3 FIT4" spirit:minimum="3" spirit:maximum="2147483647" spirit:rangeType="long">6216</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT4_No_CLOCKS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="3305" spirit:configGroups="3 FIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIT4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT1</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4001" spirit:configGroups="4 PIT1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_SIZE" spirit:order="4002" spirit:configGroups="4 PIT1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4003" spirit:configGroups="4 PIT1">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_PRESCALER" spirit:choiceRef="choice_pairs_f0f6eb36" spirit:order="4004" spirit:configGroups="4 PIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT1_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4008" spirit:configGroups="4 PIT1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT2</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4101" spirit:configGroups="4 PIT2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_SIZE" spirit:order="4102" spirit:configGroups="4 PIT2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4103" spirit:configGroups="4 PIT2">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_PRESCALER" spirit:choiceRef="choice_pairs_007f01e9" spirit:order="4104" spirit:configGroups="4 PIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT2_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4108" spirit:configGroups="4 PIT2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT3</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4201" spirit:configGroups="4 PIT3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_SIZE" spirit:order="4202" spirit:configGroups="4 PIT3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4203" spirit:configGroups="4 PIT3">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_PRESCALER" spirit:choiceRef="choice_pairs_4847022f" spirit:order="4204" spirit:configGroups="4 PIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT3_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4208" spirit:configGroups="4 PIT3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PIT4</spirit:name>
+      <spirit:displayName>Use Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PIT4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4301" spirit:configGroups="4 PIT4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits for Timer</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_SIZE" spirit:order="4302" spirit:configGroups="4 PIT4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_READABLE</spirit:name>
+      <spirit:displayName>Shall Counter Value Be Readable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_READABLE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4303" spirit:configGroups="4 PIT4">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_READABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_PRESCALER</spirit:name>
+      <spirit:displayName>Define Prescaler</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_PRESCALER" spirit:choiceRef="choice_pairs_5f1e379e" spirit:order="4304" spirit:configGroups="4 PIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_PRESCALER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PIT4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIT4_INTERRUPT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="4308" spirit:configGroups="4 PIT4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PIT4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO1</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5000" spirit:configGroups="5 GPO1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO1_SIZE" spirit:order="5001" spirit:configGroups="5 GPO1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO1_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO1_INIT" spirit:order="5002" spirit:configGroups="5 GPO1" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO1_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO2</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5100" spirit:configGroups="5 GPO2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO2_SIZE" spirit:order="5101" spirit:configGroups="5 GPO2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO2_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO2_INIT" spirit:order="5102" spirit:configGroups="5 GPO2" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO2_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO3</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5200" spirit:configGroups="5 GPO3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO3">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO3_SIZE" spirit:order="5201" spirit:configGroups="5 GPO3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO3_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO3_INIT" spirit:order="5202" spirit:configGroups="5 GPO3" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO3_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPO4</spirit:name>
+      <spirit:displayName>Use GPO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPO4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="5300" spirit:configGroups="5 GPO4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPO4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO4_SIZE" spirit:order="5301" spirit:configGroups="5 GPO4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPO4_INIT</spirit:name>
+      <spirit:displayName>Initial Value of GPO</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.GPO4_INIT" spirit:order="5302" spirit:configGroups="5 GPO4" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPO4_INIT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI1</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI1" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6000" spirit:configGroups="6 GPI1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI1_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI1_SIZE" spirit:order="6001" spirit:configGroups="6 GPI1" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI1_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI1_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI1_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6002" spirit:configGroups="6 GPI1">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI1_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI2</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6100" spirit:configGroups="6 GPI2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI2_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI2_SIZE" spirit:order="6101" spirit:configGroups="6 GPI2" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI2_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI2_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI2_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6102" spirit:configGroups="6 GPI2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI2_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI3</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI3" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6200" spirit:configGroups="6 GPI3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI3">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI3_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI3_SIZE" spirit:order="6201" spirit:configGroups="6 GPI3" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI3_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI3_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI3_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6202" spirit:configGroups="6 GPI3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI3_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_GPI4</spirit:name>
+      <spirit:displayName>Use GPI</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_GPI4" spirit:choiceRef="choice_pairs_4873554b" spirit:order="6300" spirit:configGroups="6 GPI4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_GPI4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI4_SIZE</spirit:name>
+      <spirit:displayName>Number of Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI4_SIZE" spirit:order="6301" spirit:configGroups="6 GPI4" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI4_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPI4_INTERRUPT</spirit:name>
+      <spirit:displayName>Generate Interrupt</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.GPI4_INTERRUPT" spirit:choiceRef="choice_pairs_7ba91213" spirit:order="6302" spirit:configGroups="6 GPI4">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPI4_INTERRUPT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_USE_EXT_INTR</spirit:name>
+      <spirit:displayName>Use External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_USE_EXT_INTR" spirit:choiceRef="choice_pairs_4873554b" spirit:order="7000" spirit:configGroups="7 Interrupt">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_INTR_SIZE</spirit:name>
+      <spirit:displayName>Number of External Inputs</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_INTR_SIZE" spirit:order="7100" spirit:configGroups="7 Interrupt" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_INTR_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_LEVEL_EDGE</spirit:name>
+      <spirit:displayName>Level or Edge of External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_LEVEL_EDGE" spirit:order="7200" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0x0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_LEVEL_EDGE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_POSITIVE</spirit:name>
+      <spirit:displayName>Positive or Negative External Interrupts</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_POSITIVE" spirit:order="7300" spirit:configGroups="7 Interrupt" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_POSITIVE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_ASYNC_INTR</spirit:name>
+      <spirit:displayName>Interrupts asynchronous</spirit:displayName>
+      <spirit:description>The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous.</spirit:description>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_ASYNC_INTR" spirit:order="7400" spirit:bitStringLength="16">0xFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTC_ASYNC_INTR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTC_NUM_SYNC_FF</spirit:name>
+      <spirit:displayName>Number of synchronization flip-flops</spirit:displayName>
+      <spirit:description>Number of synchronization flip-flops used to synchronize asynchronous interupt inputs</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INTC_NUM_SYNC_FF" spirit:order="7500" spirit:minimum="0" spirit:maximum="7" spirit:rangeType="long">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_rdimm_x8_dual_microblaze_mcs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="100" spirit:configGroups="0 Board">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="103" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CLK_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_30de7c39" spirit:order="106" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RESET_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO1_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="110" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO1_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO2_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="120" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO2_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO3_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO3_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="130" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO3_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GPIO4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO4_BOARD_INTERFACE" spirit:choiceRef="choice_list_38e5a9f1" spirit:order="140" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.GPIO4_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>UART_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:choiceRef="choice_list_0739ee39" spirit:order="150" spirit:configGroups="0 Board">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UART_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>MicroBlaze MCS</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>14</xilinx:coreRevision>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="bd_viewable">true</xilinx:tag>
+        <xilinx:tag xilinx:name="driver_mode">subcore</xilinx:tag>
+      </xilinx:tags>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_ASYNC_RESET" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.BOARD.ASSOCIATED_PARAM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.BOARD.ASSOCIATED_PARAM" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESET.POLARITY" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEMSIZE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OPTIMIZATION" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TRACE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_IO_BUS" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6ddedfe4"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="08e90b19"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="3d2f3b86"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/phy_rdimm_x8_dual_phy.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/phy_rdimm_x8_dual_phy.xci
new file mode 100644
index 0000000..a54f76d
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/phy_rdimm_x8_dual_phy.xci
@@ -0,0 +1,665 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>phy_rdimm_x8_dual_phy</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4_phy" spirit:version="2.2"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_ADDR_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_DATA_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI_ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_GROUP_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_TYPE">HP_IO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BANK_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_DIV_LOC_1">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_DIV_LOC_2">X0Y10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_LOC_1">X0Y70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BUFG_LOC_2">X0Y11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BYTES">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CA_MIRROR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CENTER_BANK_CLOCK_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CKE_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKIN_PERIOD">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COLUMN_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CS_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATABITS_PER_STROBE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_BUF_ADDR_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DBYTES">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DM_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQS_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DQ_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_OTHER_PN_CLOCK_PARAM">{{9{2&apos;b01}}, {3{2&apos;b00}}} </spirit:configurableElementValue>
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+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111                                                                                }</spirit:configurableElementValue>
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+1_001_001_001_001,                                                                                  39&apos;b000_001_001_001_001_101_101_001_001_001_001_001_001  </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_CUSTOM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_COMP_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_DEVICE_WIDTH">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MEM_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MMCM_IDX_BANK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MR0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MR2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_CH1_BYTES_MAP">12&apos;b000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RANK_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELF_CALIBRATE">{12{2&apos;b11}} </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_CENTER_INFO">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Slot">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_OUTPUT_PHASE_90">{ 13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_CS_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_DM_PORT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.nCK_PER_CLK">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tCK">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tMRD">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tRTP">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tWR">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tXPR">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tZQINIT">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasLatency">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MTA9ASF1G72PZ-2G3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">RDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_customPartAbsPath">no_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_rdimm_x8_dual_phy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Phy_Only_Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_act_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_addr_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_adr_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ba_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_bg_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cas_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_c_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_p_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ck_t_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cke_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_cs_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_data_compare_error">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dm_dbi_n_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_100">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_101">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_102">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_103">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_104">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_105">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_106">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_107">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_108">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_109">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_110">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_111">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_112">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_113">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_114">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_115">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_116">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_117">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_118">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_119">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_120">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_131">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_140">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_36">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_37">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_38">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_39">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_40">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_41">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_42">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_43">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_44">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_45">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_46">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_47">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_48">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_49">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_50">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_51">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_52">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_53">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_54">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_55">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_56">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_57">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_58">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_59">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_60">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_61">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_62">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_63">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_64">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_65">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_66">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_67">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_68">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_69">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_70">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_71">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_72">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_73">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_74">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_75">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_76">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_77">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_78">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_79">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_80">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_81">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_82">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_83">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_84">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_85">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_86">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_87">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_88">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_89">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_90">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_91">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_92">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_93">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_94">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_95">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_96">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_97">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_98">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dq_99">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_c_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_n_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_p_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_10">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_11">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_12">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_13">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_14">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_15">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_16">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_17">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_18">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_19">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_20">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_21">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_22">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_23">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_24">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_25">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_26">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_27">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_28">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_29">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_30">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_31">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_32">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_33">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_34">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_35">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_4">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_5">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_6">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_7">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_8">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_dqs_t_9">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_init_calib_complete">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_0">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_1">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_2">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_odt_3">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_parity">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_ras_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_reset_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_sys_clk_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_sys_clk_p">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c0_we_n">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_rst">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ControllerType" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Clamshell" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataMask" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Ecc" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MIN_PERIOD" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Slot" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_StackHeight" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_VrefVoltage" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DIVIDE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Debug_Signal" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_FROM_PHY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Simulation_Mode" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.System_Clock" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/phy_rdimm_x8_dual_phy.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/phy_rdimm_x8_dual_phy.xml
new file mode 100644
index 0000000..007cf12
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/phy_rdimm_x8_dual_phy.xml
@@ -0,0 +1,4897 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_rdimm_x8_dual_phy</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>sys_clk_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_p" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_n" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk_i</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_i" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;No_Buffer&quot; )">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mmcm_lock</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mmcm_lock" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>pllGate</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pllGate" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>div_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.div_clk" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>div_clk_rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.div_clk_rst" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>riu_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.riu_clk" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>riu_clk_rst</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>ddr4_odt</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>ddr4_ck_c</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>inout</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>mcal_CK_c</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcal_CK_c" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mcal_CK_t</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcal_CK_t" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+            </xilinx:enablement>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dq</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr4_dq" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>ddr4_dqs_c</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr4_dqs_c" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+        <spirit:name>ddr4_dqs_t</spirit:name>
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+          <spirit:direction>inout</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ddr4_dqs_t" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+        <spirit:name>mcal_BG</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcal_BG" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+        <spirit:name>C0.ControllerType</spirit:name>
+        <spirit:displayName>ControllerType</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>BANK_TYPE</spirit:name>
+        <spirit:displayName>Bank Type</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_TYPE">HP_IO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>ADDR_WIDTH</spirit:name>
+        <spirit:displayName>ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADDR_WIDTH">17</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>BANK_WIDTH</spirit:name>
+        <spirit:displayName>BANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_WIDTH">2</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>BANK_GROUP_WIDTH</spirit:name>
+        <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BANK_GROUP_WIDTH">2</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>LR_WIDTH</spirit:name>
+        <spirit:displayName>LR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LR_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CKE_WIDTH</spirit:name>
+        <spirit:displayName>CKE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CKE_WIDTH">1</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>COLUMN_WIDTH</spirit:name>
+        <spirit:displayName>COLUMN WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COLUMN_WIDTH">10</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>CS_WIDTH</spirit:name>
+        <spirit:displayName>CS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CS_WIDTH">1</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>ODT_WIDTH</spirit:name>
+        <spirit:displayName>ODT WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ODT_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DQ_WIDTH</spirit:name>
+        <spirit:displayName>DQ WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQ_WIDTH">72</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>DQS_WIDTH</spirit:name>
+        <spirit:displayName>DQS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DQS_WIDTH">9</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>DM_WIDTH</spirit:name>
+        <spirit:displayName>DM WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DM_WIDTH">9</spirit:value>
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+      <spirit:modelParameter>
+        <spirit:name>MR0</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
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+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MR2</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MR2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tCK</spirit:name>
+        <spirit:displayName>tCK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tCK">1500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tXPR</spirit:name>
+        <spirit:displayName>tXPR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tXPR">60</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>nCK_PER_CLK</spirit:name>
+        <spirit:displayName>nCK PER CLK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.nCK_PER_CLK">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tMRD</spirit:name>
+        <spirit:displayName>tMRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tMRD">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tZQINIT</spirit:name>
+        <spirit:displayName>tZQINIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tZQINIT">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_COMP_WIDTH</spirit:name>
+        <spirit:displayName>MEM COMP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_COMP_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_DEVICE_WIDTH</spirit:name>
+        <spirit:displayName>MEMORY DEVICE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_DEVICE_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PLL_WIDTH</spirit:name>
+        <spirit:displayName>PLL WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PLL_WIDTH">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>IOBTYPE</spirit:name>
+        <spirit:displayName>IOBTYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IOBTYPE">                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b
+000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                  
+                                                39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_011_011_011_011_111_111_011_011_011_011_000_011,                                                                                  39&apos;b000_000_000_000_000_000_000_001_000_001_001_001_001,                                                                                  39&apos;b001_001_001_000_000_001_001_001_00
+1_001_001_001_001,                                                                                  39&apos;b000_001_001_001_001_101_101_001_001_001_001_001_001  </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BYTES</spirit:name>
+        <spirit:displayName>BYTES</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BYTES">12</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DBYTES</spirit:name>
+        <spirit:displayName>DBYTES</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DBYTES">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_CH1_BYTES_MAP</spirit:name>
+        <spirit:displayName>PING_PONG_CH1_BYTES_MAP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_CH1_BYTES_MAP">12&apos;b000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_PHY</spirit:name>
+        <spirit:displayName>PING PONG PHY</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RX_DATA_TYPE</spirit:name>
+        <spirit:displayName>RX DATA TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_DATA_TYPE">{ 15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                               
+                 15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b011110_11_11110_01,                                                                                15&apos;b000000_00_10111_11,                                                
+                                15&apos;b111001_11_11111_11,                                                                                15&apos;b011111_11_11111_11                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>INIT</spirit:name>
+        <spirit:displayName>INIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INIT">{                            15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111111,                                                                                15&apos;b111111111111101,                                                   
+                             15&apos;b111111111111111,                                                                                15&apos;b111111111111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>SELF_CALIBRATE</spirit:name>
+        <spirit:displayName>SELF CALIBRATE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELF_CALIBRATE">{12{2&apos;b11}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>TX_OUTPUT_PHASE_90</spirit:name>
+        <spirit:displayName>TX OUTPUT PHASE 90</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_OUTPUT_PHASE_90">{ 13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000
+011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000011000000,                                                                                13&apos;b0000000101111,                                                                                13&apos;b1110011111111,
+                                                                                13&apos;b0111111111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RXTX_BITSLICE_EN</spirit:name>
+        <spirit:displayName>RXTX BITSLICE EN</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RXTX_BITSLICE_EN">{13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b01111
+01111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0111101111101,                                                                                13&apos;b0000000101111,                                                                                13&apos;b1110011111111, 
+                                                                               13&apos;b0111101111111                                                                                }</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>EN_OTHER_PN_CLOCK_PARAM</spirit:name>
+        <spirit:displayName>EN OTHER PN CLOCK PARAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_OTHER_PN_CLOCK_PARAM">{{9{2&apos;b01}}, {3{2&apos;b00}}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PHY_BYTE_ALLOC_PARAM</spirit:name>
+        <spirit:displayName>PHY BYTE ALLOC PARAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PHY_BYTE_ALLOC_PARAM">{{9{2&apos;b11}}, {3{2&apos;b00}}} </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DATA_BUF_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>DATA BUF ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_BUF_ADDR_WIDTH">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKIN_PERIOD</spirit:name>
+        <spirit:displayName>CLKIN PERIOD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MEM_TYPE</spirit:name>
+        <spirit:displayName>MEM TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_ID_WIDTH</spirit:name>
+        <spirit:displayName>AXI ID WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ID_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI DATA WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_DATA_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ADDR_WIDTH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>USE_DM_PORT</spirit:name>
+        <spirit:displayName>USE DM PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_DM_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_LOC_1</spirit:name>
+        <spirit:displayName>BUFG LOC 1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_LOC_1">X0Y70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_LOC_2</spirit:name>
+        <spirit:displayName>BUFG LOC 2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_LOC_2">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_DIV_LOC_1</spirit:name>
+        <spirit:displayName>BUFG DIV LOC 1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_DIV_LOC_1">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>BUFG_DIV_LOC_2</spirit:name>
+        <spirit:displayName>BUFG DIV LOC 2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFG_DIV_LOC_2">X0Y10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_SLICE_LOC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_SLICE_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB36_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB18_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_SLICE_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_SLICE_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB36_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB36_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PBLOCK_RAMB18_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PBLOCK_RAMB18_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>MMCM_IDX_BANK</spirit:name>
+        <spirit:displayName>MMCM IDX BANK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MMCM_IDX_BANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CENTER_BANK_CLOCK_REGION</spirit:name>
+        <spirit:displayName>CENTER BANK CLOCK REGION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CENTER_BANK_CLOCK_REGION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CENTER_BANK_MMCME3_ADV_SITE</spirit:name>
+        <spirit:displayName>CENTER BANK MMCME3 ADV SITE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>SYSCLK_CENTER_INFO</spirit:name>
+        <spirit:displayName>SYSCLK_CENTER_INFO</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYSCLK_CENTER_INFO">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tWR</spirit:name>
+        <spirit:displayName>tWR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tWR">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>tRTP</spirit:name>
+        <spirit:displayName>tRTP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.tRTP">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>RANK_WIDTH</spirit:name>
+        <spirit:displayName>RANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RANK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CK_WIDTH</spirit:name>
+        <spirit:displayName>CK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>DATABITS_PER_STROBE</spirit:name>
+        <spirit:displayName>DATABITS PER STROBE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATABITS_PER_STROBE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>USE_CS_PORT</spirit:name>
+        <spirit:displayName>USE CS PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_CS_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CA_MIRROR</spirit:name>
+        <spirit:displayName>CA MIRROR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CA_MIRROR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>IS_CUSTOM</spirit:name>
+        <spirit:displayName>IS CUSTOM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_CUSTOM">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Slot</spirit:name>
+        <spirit:displayName>Slot</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Slot">1</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>phy_rdimm_x8_dual_phy</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="dummy"/>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>PHY for DDR4 interfaces for Ultrascale Architecture</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C0.ControllerType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ControllerType" spirit:order="2">DDR4_SDRAM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_FROM_PHY</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IS_FROM_PHY" spirit:order="3">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Phy_Only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Phy_Only" spirit:order="4">Phy_Only_Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>No_Controller</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.No_Controller" spirit:order="5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Default_Bank_Selections</spirit:name>
+      <spirit:displayName>Default Bank Selections</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Default_Bank_Selections" spirit:order="6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Debug_Signal</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Debug_Signal" spirit:order="7">Disable</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Simulation_Mode</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Simulation_Mode" spirit:order="8">BFM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PARTIAL_RECONFIG_FLOW_MIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" spirit:order="9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DIVIDE" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DIVIDE" spirit:order="11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DIVIDE" spirit:order="12">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DIVIDE" spirit:order="13">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>System_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.System_Clock" spirit:order="14">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RECONFIG_XSDB_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" spirit:order="15">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_TERM_SYSCLK</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_TERM_SYSCLK" spirit:order="16">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TimePeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TimePeriod" spirit:order="17">1500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_InputClockPeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_InputClockPeriod" spirit:order="18">3333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" spirit:order="19">5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" spirit:order="20">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" spirit:order="21">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PhyClockRatio</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PhyClockRatio" spirit:order="22">4:1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryType" spirit:order="23">RDIMMs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryPart</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryPart" spirit:order="24">MTA9ASF1G72PZ-2G3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Slot</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Slot" spirit:order="25">Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryVoltage</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryVoltage" spirit:order="26">1.2V</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataWidth" spirit:order="27">72</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataMask</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataMask" spirit:order="28">DM_NO_DBI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ecc" spirit:order="29">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasLatency" spirit:order="30">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasWriteLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasWriteLatency" spirit:order="31">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ChipSelect</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ChipSelect" spirit:order="32">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCKEShared</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCKEShared" spirit:order="33">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name>
+      <spirit:displayName>CLKOUTPHY MODE</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" spirit:order="34">VCO</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name>
+      <spirit:displayName>High Range Supported frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_HR_MIN_FREQ" spirit:order="35">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name>
+      <spirit:displayName>Memory Min Period</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MIN_PERIOD" spirit:order="36">833</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name>
+      <spirit:displayName>Indicates Faster Speed RAM Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM" spirit:order="37">No</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_VrefVoltage</spirit:name>
+      <spirit:displayName>Vref Voltage</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_VrefVoltage" spirit:order="38">0.84</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_customPartAbsPath</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_customPartAbsPath" spirit:order="39">no_file_loaded</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_StackHeight</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_StackHeight" spirit:order="40">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CUSTOM_PART_ATTRIBUTES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CUSTOM_PART_ATTRIBUTES" spirit:order="41">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SELF_REFRESH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SELF_REFRESH" spirit:order="42">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" spirit:order="43">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Clamshell</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Clamshell" spirit:order="44">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Enable_LVAUX</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Enable_LVAUX" spirit:order="45">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_EN_PARITY</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_EN_PARITY" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_EN_PARITY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_0" spirit:order="47">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_1" spirit:order="48">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_2" spirit:order="49">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_3" spirit:order="50">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_4" spirit:order="51">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_5" spirit:order="52">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_6" spirit:order="53">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_7" spirit:order="54">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_8" spirit:order="55">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_9" spirit:order="56">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_10" spirit:order="57">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_11" spirit:order="58">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_12" spirit:order="59">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_13" spirit:order="60">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_14" spirit:order="61">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_15" spirit:order="62">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_16" spirit:order="63">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_17" spirit:order="64">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_18" spirit:order="65">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_19" spirit:order="66">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_20" spirit:order="67">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_21" spirit:order="68">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_22" spirit:order="69">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_23" spirit:order="70">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_24" spirit:order="71">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_25" spirit:order="72">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_26" spirit:order="73">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_27" spirit:order="74">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_28" spirit:order="75">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_29" spirit:order="76">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_30" spirit:order="77">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_31" spirit:order="78">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_32" spirit:order="79">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_33" spirit:order="80">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_34" spirit:order="81">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_35" spirit:order="82">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_36</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_36" spirit:order="83">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_37</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_37" spirit:order="84">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_38</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_38" spirit:order="85">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_39</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_39" spirit:order="86">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_40</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_40" spirit:order="87">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_41</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_41" spirit:order="88">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_42</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_42" spirit:order="89">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_43</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_43" spirit:order="90">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_44</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_44" spirit:order="91">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_45</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_45" spirit:order="92">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_46</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_46" spirit:order="93">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_47</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_47" spirit:order="94">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_48</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_48" spirit:order="95">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_49</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_49" spirit:order="96">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_50</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_50" spirit:order="97">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_51</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_51" spirit:order="98">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_52</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_52" spirit:order="99">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_53</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_53" spirit:order="100">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_54</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_54" spirit:order="101">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_55</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_55" spirit:order="102">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_56</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_56" spirit:order="103">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_57</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_57" spirit:order="104">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_58</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_58" spirit:order="105">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_59</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_59" spirit:order="106">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_60</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_60" spirit:order="107">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_61</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_61" spirit:order="108">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_62</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_62" spirit:order="109">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_63</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_63" spirit:order="110">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_64</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_64" spirit:order="111">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_65</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_65" spirit:order="112">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_66</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_66" spirit:order="113">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_67</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_67" spirit:order="114">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_68</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_68" spirit:order="115">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_69</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_69" spirit:order="116">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_70</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_70" spirit:order="117">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_71</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_71" spirit:order="118">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_72</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_72" spirit:order="119">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_73</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_73" spirit:order="120">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_74</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_74" spirit:order="121">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_75</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_75" spirit:order="122">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_76</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_76" spirit:order="123">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_77</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_77" spirit:order="124">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_78</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_78" spirit:order="125">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_79</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_79" spirit:order="126">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_80</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_80" spirit:order="127">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_81</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_81" spirit:order="128">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_82</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_82" spirit:order="129">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_83</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_83" spirit:order="130">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_84</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_84" spirit:order="131">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_85</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_85" spirit:order="132">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_86</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_86" spirit:order="133">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_87</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_87" spirit:order="134">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_88</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_88" spirit:order="135">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_89</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_89" spirit:order="136">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_90</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_90" spirit:order="137">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_91</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_91" spirit:order="138">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_92</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_92" spirit:order="139">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_93</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_93" spirit:order="140">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_94</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_94" spirit:order="141">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_95</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_95" spirit:order="142">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_96</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_96" spirit:order="143">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_97</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_97" spirit:order="144">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_98</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_98" spirit:order="145">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_99</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_99" spirit:order="146">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_100</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_100" spirit:order="147">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_101</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_101" spirit:order="148">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_102</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_102" spirit:order="149">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_103</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_103" spirit:order="150">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_104</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_104" spirit:order="151">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_105</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_105" spirit:order="152">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_106</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_106" spirit:order="153">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_107</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_107" spirit:order="154">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_108</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_108" spirit:order="155">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_109</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_109" spirit:order="156">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_110</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_110" spirit:order="157">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_111</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_111" spirit:order="158">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_112</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_112" spirit:order="159">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_113</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_113" spirit:order="160">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_114</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_114" spirit:order="161">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_115</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_115" spirit:order="162">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_116</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_116" spirit:order="163">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_117</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_117" spirit:order="164">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_118</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_118" spirit:order="165">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_119</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_119" spirit:order="166">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_120</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_120" spirit:order="167">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_121</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_121" spirit:order="168">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_122</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_122" spirit:order="169">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_123</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_123" spirit:order="170">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_124</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_124" spirit:order="171">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_125</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_125" spirit:order="172">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_126</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_126" spirit:order="173">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_127</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_127" spirit:order="174">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_128</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_128" spirit:order="175">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_129</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_129" spirit:order="176">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_130</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_130" spirit:order="177">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_131</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_131" spirit:order="178">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_132</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_132" spirit:order="179">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_133</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_133" spirit:order="180">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_134</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_134" spirit:order="181">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_135</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_135" spirit:order="182">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_136</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_136" spirit:order="183">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_137</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_137" spirit:order="184">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_138</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_138" spirit:order="185">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_139</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_139" spirit:order="186">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_140</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_140" spirit:order="187">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_141</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_141" spirit:order="188">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_142</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_142" spirit:order="189">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dq_143</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dq_143" spirit:order="190">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_0" spirit:order="191">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_1" spirit:order="192">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_2" spirit:order="193">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_3" spirit:order="194">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_4" spirit:order="195">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_5" spirit:order="196">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_6" spirit:order="197">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_7" spirit:order="198">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_8" spirit:order="199">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_9" spirit:order="200">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_10" spirit:order="201">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_11" spirit:order="202">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_12" spirit:order="203">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_13" spirit:order="204">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_14" spirit:order="205">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_15" spirit:order="206">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_16" spirit:order="207">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_17" spirit:order="208">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_18" spirit:order="209">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_19" spirit:order="210">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_20" spirit:order="211">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_adr_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_adr_21" spirit:order="212">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_0" spirit:order="213">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_1" spirit:order="214">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_2" spirit:order="215">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_3" spirit:order="216">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_4" spirit:order="217">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_5" spirit:order="218">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_6" spirit:order="219">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_7" spirit:order="220">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_8" spirit:order="221">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_9" spirit:order="222">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_10" spirit:order="223">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_11" spirit:order="224">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_12" spirit:order="225">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_13" spirit:order="226">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_14" spirit:order="227">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_15" spirit:order="228">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_16" spirit:order="229">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_17" spirit:order="230">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_18" spirit:order="231">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_19" spirit:order="232">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_20" spirit:order="233">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_addr_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_addr_21" spirit:order="234">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_0" spirit:order="235">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_1" spirit:order="236">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_2" spirit:order="237">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_3" spirit:order="238">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_4" spirit:order="239">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_5" spirit:order="240">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_6" spirit:order="241">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_7" spirit:order="242">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_8" spirit:order="243">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_9" spirit:order="244">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_10" spirit:order="245">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_11" spirit:order="246">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_12" spirit:order="247">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_13" spirit:order="248">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_14" spirit:order="249">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_15" spirit:order="250">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_16" spirit:order="251">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_17" spirit:order="252">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_18" spirit:order="253">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_19" spirit:order="254">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_20" spirit:order="255">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_21" spirit:order="256">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_22" spirit:order="257">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_23" spirit:order="258">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_24" spirit:order="259">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_25" spirit:order="260">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_26" spirit:order="261">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_27" spirit:order="262">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_28" spirit:order="263">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_29" spirit:order="264">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_30" spirit:order="265">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_31" spirit:order="266">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_32" spirit:order="267">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_33" spirit:order="268">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_34" spirit:order="269">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_35" spirit:order="270">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_0" spirit:order="271">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_1" spirit:order="272">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_2" spirit:order="273">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_3" spirit:order="274">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_4" spirit:order="275">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_5" spirit:order="276">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_6" spirit:order="277">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_7" spirit:order="278">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_8" spirit:order="279">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_9" spirit:order="280">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_10" spirit:order="281">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_11" spirit:order="282">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_12" spirit:order="283">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_13" spirit:order="284">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_14" spirit:order="285">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_15" spirit:order="286">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_16" spirit:order="287">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_17" spirit:order="288">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_18" spirit:order="289">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_19" spirit:order="290">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_20" spirit:order="291">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_21" spirit:order="292">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_22" spirit:order="293">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_23" spirit:order="294">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_24" spirit:order="295">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_25" spirit:order="296">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_26" spirit:order="297">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_27" spirit:order="298">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_28" spirit:order="299">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_29" spirit:order="300">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_30" spirit:order="301">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_31" spirit:order="302">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_32" spirit:order="303">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_33" spirit:order="304">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_34" spirit:order="305">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dm_dbi_n_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dm_dbi_n_35" spirit:order="306">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_0" spirit:order="307">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_1" spirit:order="308">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_2" spirit:order="309">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_3" spirit:order="310">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_4" spirit:order="311">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_5" spirit:order="312">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_6" spirit:order="313">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_7" spirit:order="314">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_8" spirit:order="315">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_9" spirit:order="316">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_10" spirit:order="317">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_11" spirit:order="318">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_12" spirit:order="319">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_13" spirit:order="320">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_14" spirit:order="321">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_15" spirit:order="322">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_16" spirit:order="323">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_17" spirit:order="324">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_18" spirit:order="325">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_19" spirit:order="326">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_20" spirit:order="327">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_21" spirit:order="328">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_22" spirit:order="329">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_23" spirit:order="330">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_24" spirit:order="331">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_25" spirit:order="332">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_26" spirit:order="333">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_27" spirit:order="334">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_28" spirit:order="335">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_29" spirit:order="336">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_30" spirit:order="337">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_31" spirit:order="338">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_32" spirit:order="339">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_33" spirit:order="340">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_34" spirit:order="341">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_t_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_t_35" spirit:order="342">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_0" spirit:order="343">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_1" spirit:order="344">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_2" spirit:order="345">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_3" spirit:order="346">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_4" spirit:order="347">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_5" spirit:order="348">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_6" spirit:order="349">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_7" spirit:order="350">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_8" spirit:order="351">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_9" spirit:order="352">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_10" spirit:order="353">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_11" spirit:order="354">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_12" spirit:order="355">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_13" spirit:order="356">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_14" spirit:order="357">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_15" spirit:order="358">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_16" spirit:order="359">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_17" spirit:order="360">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_18" spirit:order="361">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_19" spirit:order="362">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_20" spirit:order="363">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_21" spirit:order="364">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_22" spirit:order="365">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_23" spirit:order="366">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_24" spirit:order="367">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_25" spirit:order="368">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_26" spirit:order="369">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_27" spirit:order="370">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_28" spirit:order="371">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_29" spirit:order="372">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_30" spirit:order="373">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_31" spirit:order="374">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_32" spirit:order="375">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_33" spirit:order="376">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_34" spirit:order="377">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_c_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_c_35" spirit:order="378">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_0" spirit:order="379">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_1" spirit:order="380">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_2" spirit:order="381">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_3" spirit:order="382">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_4" spirit:order="383">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_5" spirit:order="384">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_6" spirit:order="385">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_7" spirit:order="386">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_8" spirit:order="387">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_9" spirit:order="388">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_10" spirit:order="389">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_11" spirit:order="390">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_12" spirit:order="391">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_13" spirit:order="392">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_14" spirit:order="393">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_15" spirit:order="394">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_16" spirit:order="395">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_17" spirit:order="396">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_18" spirit:order="397">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_19" spirit:order="398">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_20" spirit:order="399">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_21" spirit:order="400">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_22" spirit:order="401">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_23" spirit:order="402">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_24" spirit:order="403">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_25" spirit:order="404">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_26" spirit:order="405">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_27" spirit:order="406">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_28" spirit:order="407">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_29" spirit:order="408">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_30" spirit:order="409">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_31" spirit:order="410">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_32" spirit:order="411">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_33" spirit:order="412">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_34" spirit:order="413">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_n_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_n_35" spirit:order="414">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_0" spirit:order="415">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_1" spirit:order="416">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_2" spirit:order="417">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_3" spirit:order="418">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_4" spirit:order="419">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_5" spirit:order="420">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_6" spirit:order="421">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_7" spirit:order="422">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_8</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_8" spirit:order="423">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_9</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_9" spirit:order="424">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_10</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_10" spirit:order="425">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_11</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_11" spirit:order="426">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_12</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_12" spirit:order="427">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_13</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_13" spirit:order="428">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_14</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_14" spirit:order="429">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_15</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_15" spirit:order="430">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_16</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_16" spirit:order="431">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_17</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_17" spirit:order="432">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_18</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_18" spirit:order="433">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_19</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_19" spirit:order="434">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_20</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_20" spirit:order="435">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_21</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_21" spirit:order="436">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_22</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_22" spirit:order="437">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_23</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_23" spirit:order="438">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_24</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_24" spirit:order="439">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_25</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_25" spirit:order="440">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_26</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_26" spirit:order="441">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_27</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_27" spirit:order="442">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_28</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_28" spirit:order="443">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_29</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_29" spirit:order="444">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_30</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_30" spirit:order="445">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_31</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_31" spirit:order="446">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_32</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_32" spirit:order="447">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_33</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_33" spirit:order="448">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_34</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_34" spirit:order="449">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_dqs_p_35</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_dqs_p_35" spirit:order="450">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_0" spirit:order="451">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_1" spirit:order="452">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_2" spirit:order="453">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ba_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ba_3" spirit:order="454">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_0" spirit:order="455">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_1" spirit:order="456">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_bg_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_bg_2" spirit:order="457">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_0" spirit:order="458">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_1" spirit:order="459">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_c_2" spirit:order="460">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_0" spirit:order="461">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_1" spirit:order="462">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_2" spirit:order="463">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cke_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cke_3" spirit:order="464">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_0" spirit:order="465">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_1" spirit:order="466">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_2" spirit:order="467">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p_3" spirit:order="468">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_0" spirit:order="469">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_1" spirit:order="470">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_2" spirit:order="471">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n_3" spirit:order="472">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_0" spirit:order="473">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_1" spirit:order="474">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_2" spirit:order="475">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_3" spirit:order="476">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_4" spirit:order="477">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_5" spirit:order="478">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_6" spirit:order="479">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n_7</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n_7" spirit:order="480">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_0" spirit:order="481">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_1" spirit:order="482">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_2" spirit:order="483">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_odt_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_odt_3" spirit:order="484">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_0" spirit:order="485">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_1" spirit:order="486">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_2" spirit:order="487">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_t_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_t_3" spirit:order="488">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_0" spirit:order="489">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_1" spirit:order="490">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_2" spirit:order="491">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_c_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_c_3" spirit:order="492">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_reset_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_reset_n" spirit:order="493">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_act_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_act_n" spirit:order="494">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ras_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ras_n" spirit:order="495">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cas_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cas_n" spirit:order="496">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_we_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_we_n" spirit:order="497">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_parity</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_parity" spirit:order="498">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_p</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_p" spirit:order="499">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_ck_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_ck_n" spirit:order="500">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_cs_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_cs_n" spirit:order="501">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>sys_rst</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sys_rst" spirit:order="502">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_sys_clk_n</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_sys_clk_n" spirit:order="503">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_sys_clk_p</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_sys_clk_p" spirit:order="504">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_data_compare_error</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_data_compare_error" spirit:order="505">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c0_init_calib_complete</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c0_init_calib_complete" spirit:order="506">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_rdimm_x8_dual_phy</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>DDR4 SDRAM PHY IP</xilinx:displayName>
+      <xilinx:coreRevision>0</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ControllerType" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="propagated"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xci b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xci
new file mode 100644
index 0000000..493afe4
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xci
@@ -0,0 +1,478 @@
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">3333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MCS_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MTA9ASF1G72PZ-2G3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">RDIMMs</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC_DLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TXPR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">1500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TREFI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TXPR">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.LR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.MIGRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ODT_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.StackHeight">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phy_rdimm_x8_dual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCI_Cascade">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_PP_4R_MIR">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Power_Reduction">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Phy_Only_Single</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reference_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SET_DW_TO_40">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_3DS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CKE_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.CS_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryType" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.ODT_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Phy_Only" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;c0_init_calib_complete&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dbg_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_sys_clk_p&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_sys_clk_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dbg_bus&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_parity&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_ui_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;c0_ddr4_ui_clk_sync_rst&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_rst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataEn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataEnd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;per_rd_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rmw_rd_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physica
+l_right&quot;:&quot;0&quot;},&quot;wrDataEn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_ACT_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcCasSlot&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcCasSlot2&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcRdCAS&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mcWrCAS&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winInjTxn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winRmw&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;gt_data_ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winRank&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;tCWL&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrData&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;575&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataMask&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdData&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;575&quot;,&quot;physic
+al_right&quot;:&quot;0&quot;},&quot;mc_ADR&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;135&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_BA&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_CKE&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_CS_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_ODT&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dBufAdr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rdDataAddr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wrDataAddr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;winBuf&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_act_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_adr&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;16&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ba&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_bg&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_par&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_
+right&quot;:&quot;0&quot;},&quot;ddr4_cke&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_odt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_cs_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ck_t&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_ck_c&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_reset_n&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_parity&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dm_dbi_n&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dq&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dqs_c&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ddr4_dqs_t&quot;:{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;mc_BG&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;C0_SYS_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:diff_clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilin
+x.com:interface:diff_clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;C0_CLOCK_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;CLK_N&quot;:{&quot;physical_name&quot;:&quot;c0_sys_clk_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK_P&quot;:{&quot;physical_name&quot;:&quot;c0_sys_clk_p&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;C0_DDR4_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;defa
+ult&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk_sync_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;C0_DDR4_CLOCK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;1.665e+08&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;dependent&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.00&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:
+[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;SYSTEM_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xml b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xml
new file mode 100644
index 0000000..b01a907
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/phy_rdimm_x8_dual.xml
@@ -0,0 +1,8686 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>phy_rdimm_x8_dual</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>C0_SYS_CLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.BOARD.ASSOCIATED_PARAM">C0_CLOCK_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; (spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;Differential&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_SYS_CLK_I</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_sys_clk_i</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_SYS_CLK_I" xilinx:dependency="( C0.ControllerType == &quot;DDR4_SDRAM&quot; ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.System_Clock&apos;)) = &quot;No_Buffer&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACT_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_act_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_adr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ba</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BG</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_bg</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>C_ID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CK_C</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ck_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CK_T</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ck_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CKE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_cke</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CS_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_cs_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DM_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dm_dbi_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dq</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQS_C</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dqs_c</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DQS_T</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_dqs_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ODT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_odt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PAR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_parity</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RESET_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4.BOARD.ASSOCIATED_PARAM">C0_DDR4_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TIMEPERIOD_PS</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEMORY_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEMORY_PART</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CS_ENABLED</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_MASK_ENABLED</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SLOT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CUSTOM_PARTS</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ADDR_MAP</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAS_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAS_WRITE_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4" xilinx:dependency="( ( spirit:decode(id(&apos;PARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_CTRL</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="C0_DDR4_MEMORY_MAP_CTRL"/>
+      </spirit:slave>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_ctrl_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_S_AXI_CTRL" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_ECC&apos;)) = true()() ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="C0_DDR4_MEMORY_MAP"/>
+      </spirit:slave>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_S_AXI" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_ARESETN</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_ARESETN" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_RESET</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ui_clk_sync_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_RESET" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_CLOCK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c0_ddr4_ui_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_HZ" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_UI_CLOCK&apos;))">1.665e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.PHASE">0.00</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.ASSOCIATED_BUSIF">C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.ASSOCIATED_RESET">c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.C0_DDR4_CLOCK" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT1</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT1" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT2</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT2" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT3</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT3" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ADDN_UI_CLKOUT4</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addn_ui_clkout4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_HZ" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ&apos;))*1000000)">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.PHASE" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE&apos;))">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_ASYNC_RESET">c0_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ADDN_UI_CLKOUT4" xilinx:dependency="( spirit:decode(id(&apos;PARAM_VALUE.No_Controller&apos;)) > 0 ) &amp;&amp; ( spirit:decode(id(&apos;PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ&apos;)) != &quot;NONE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SYSTEM_RESET</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:connectionRequired>true</spirit:connectionRequired>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>C0_DDR4_S_AXI_CTRL_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_CTRL_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>C0_DDR_SAXI_CTRL_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>C0_DDR4_MEMORY_MAP</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>C0_DDR4_ADDRESS_BLOCK</spirit:name>
+        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C0.DDR4_MEM_SIZE&apos;))">8589934592</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:vendorExtensions>
+          <xilinx:addressBlockInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C0_DDR4_MEMORY_MAP.C0_DDR4_ADDRESS_BLOCK" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.Phy_Only&apos;)) = &quot;Complete_Memory_Controller&quot; ) )">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:addressBlockInfo>
+        </spirit:vendorExtensions>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+    <spirit:memoryMap>
+      <spirit:name>C0_DDR4_MEMORY_MAP_CTRL</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>C0_REG</spirit:name>
+        <spirit:baseAddress spirit:format="long" spirit:resolve="dependent">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:vendorExtensions>
+          <xilinx:addressBlockInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.C0_DDR4_MEMORY_MAP_CTRL.C0_REG" xilinx:dependency="( ( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_AxiSelection&apos;)) = true ) and ( spirit:decode(id(&apos;PARAM_VALUE.C0.DDR4_ECC&apos;)) = true()() ))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:addressBlockInfo>
+        </spirit:vendorExtensions>
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+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_elaborateports</spirit:name>
+        <spirit:displayName>Elaborate Ports</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e90b6257</spirit:value>
+          </spirit:parameter>
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+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_elaboratesubcores</spirit:name>
+        <spirit:displayName>Elaborate Sub-Cores</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.subcores</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_elaboratesubcores_view_fileset</spirit:localName>
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+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:b07e40ac</spirit:value>
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+        <spirit:name>c0_init_calib_complete</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_init_calib_complete" xilinx:dependency="( spirit:decode(id(&apos;MODELPARAM_VALUE.C0.ControllerType&apos;)) = &quot;DDR4_SDRAM&quot; )">true</xilinx:isEnabled>
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+        <spirit:name>dbg_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_CKE</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_CS_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_ODT</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dBufAdr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rdDataAddr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wrDataAddr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>winBuf</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">4</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_act_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_adr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">16</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_ba</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_bg</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_par</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_cke</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_odt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_cs_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_ck_t</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_ck_c</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_reset_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_parity</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dm_dbi_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">8</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dq</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">71</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dqs_c</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">8</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ddr4_dqs_t</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">8</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mc_BG</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_wr_socket</spirit:name>
+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>wr_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_rd_socket</spirit:name>
+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>rd_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_CTRL_wr_socket</spirit:name>
+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>wr_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>C0_DDR_SAXI_CTRL_rd_socket</spirit:name>
+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
+            <spirit:initiative>provides</spirit:initiative>
+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
+                  <spirit:parameter>
+                    <spirit:name>name</spirit:name>
+                    <spirit:value>rd_socket</spirit:value>
+                  </spirit:parameter>
+                  <spirit:parameter>
+                    <spirit:name>width</spirit:name>
+                    <spirit:value spirit:format="long">32</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType">
+        <spirit:name>C0.DDR4_Mem_Add_Map</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>System_Clock</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.System_Clock" spirit:choiceRef="choice_list_2b96b8de">Differential</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.ControllerType</spirit:name>
+        <spirit:displayName>ControllerType</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>App Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">30</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.MEM_TYPE</spirit:name>
+        <spirit:displayName>MEM TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_LOC_1</spirit:name>
+        <spirit:displayName>BUFG LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_LOC_1">X0Y70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_LOC_2</spirit:name>
+        <spirit:displayName>BUFG LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_DIV_LOC_1</spirit:name>
+        <spirit:displayName>BUFG DIV LOC1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_1">X0Y11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.BUFG_DIV_LOC_2</spirit:name>
+        <spirit:displayName>BUFG DIV LOC2</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_2">X0Y10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_SLICE_LOC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB36_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB18_LOC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_SLICE_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK SLICE LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB36_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB36 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.PBLOCK_RAMB18_LOC_SC</spirit:name>
+        <spirit:displayName>PBLOCK RAMB18 LOC SC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.MMCM_IDX_BANK</spirit:name>
+        <spirit:displayName>MMCM IDX BANK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.CENTER_BANK_CLOCK_REGION</spirit:name>
+        <spirit:displayName>CENTER BANK CLOCK REGION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.CENTER_BANK_CLOCK_REGION">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.CENTER_BANK_MMCME3_ADV_SITE</spirit:name>
+        <spirit:displayName>CENTER BANK MMCME3 ADV SITE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.SYSCLK_CENTER_INFO</spirit:name>
+        <spirit:displayName>SYSCLK CENTER INFO</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>PING_PONG_PHY</spirit:name>
+        <spirit:displayName>Ping Pong Phy</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CS_ADDR</spirit:name>
+        <spirit:displayName>CS Width Check</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CS_ADDR">30</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_VrefVoltage</spirit:name>
+        <spirit:displayName>Vref Voltage</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AL</spirit:name>
+        <spirit:displayName>Additive Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DQ_WIDTH</spirit:name>
+        <spirit:displayName>DQ WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nCK_PER_CLK</spirit:name>
+        <spirit:displayName>nCK PER CLK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DM_WIDTH</spirit:name>
+        <spirit:displayName>DM WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DQS_WIDTH</spirit:name>
+        <spirit:displayName>DQS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nCS_PER_RANK</spirit:name>
+        <spirit:displayName>nCS PER RANK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DEVICE_WIDTH</spirit:name>
+        <spirit:displayName>MEM DEVICE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_USE_DM_PORT</spirit:name>
+        <spirit:displayName>USE DM PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_USE_CS_PORT</spirit:name>
+        <spirit:displayName>USE CS PORT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ROW_WIDTH</spirit:name>
+        <spirit:displayName>ROW WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>ADDR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ADDR_WIDTH">17</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BANK_WIDTH</spirit:name>
+        <spirit:displayName>BANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BANK_WIDTH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BANK_GROUP_WIDTH</spirit:name>
+        <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BANK_GROUP_WIDTH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>LR_WIDTH</spirit:name>
+        <spirit:displayName>LR WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LR_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CK_WIDTH</spirit:name>
+        <spirit:displayName>CK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CKE_WIDTH</spirit:name>
+        <spirit:displayName>CKE WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CKE_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CS_WIDTH</spirit:name>
+        <spirit:displayName>CS WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_ODT_WIDTH</spirit:name>
+        <spirit:displayName>ODT WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEMORY_TYPE</spirit:name>
+        <spirit:displayName>MEMORY TYPE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">RDIMMs</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEMORY_PART</spirit:name>
+        <spirit:displayName>MEMORY PART</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">MTA9ASF1G72PZ-2G3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DATA_MASK</spirit:name>
+        <spirit:displayName>DATA MASK</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_COLUMN_WIDTH</spirit:name>
+        <spirit:displayName>COLUMN WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_SPEED_GRADE</spirit:name>
+        <spirit:displayName>SPEED GRADE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">083</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY</spirit:name>
+        <spirit:displayName>MEM DENSITY</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">8GB</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY_MB</spirit:name>
+        <spirit:displayName>MEM DENSITY MB</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">8192</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_DENSITY_GB</spirit:name>
+        <spirit:displayName>MEM DENSITY GB</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_COMP_DENSITY</spirit:name>
+        <spirit:displayName>COMP DENSITY</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">8Gb</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_COMP_WIDTH</spirit:name>
+        <spirit:displayName>MEM COMP WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DATABITS_PER_STROBE</spirit:name>
+        <spirit:displayName>DATABITS PER STROBE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MODEL_SPEED_GRADE</spirit:name>
+        <spirit:displayName>MODEL SPEED GRADE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_833_Timing</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RANK_WIDTH</spirit:name>
+        <spirit:displayName>RANK WIDTH</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IO_VOLTAGE</spirit:name>
+        <spirit:displayName>IO VOLTAGE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name>
+        <spirit:displayName>MIN PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">833</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MAX_PERIOD</spirit:name>
+        <spirit:displayName>MAX PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MR0</spirit:name>
+        <spirit:displayName>Mode register_0 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MR2</spirit:name>
+        <spirit:displayName>Mode register_2 value</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_nAL</spirit:name>
+        <spirit:displayName>Additive Latency in number of clock</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BURST_MODE</spirit:name>
+        <spirit:displayName>Burst Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_BURST_TYPE</spirit:name>
+        <spirit:displayName>Burst Type</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CL</spirit:name>
+        <spirit:displayName>Cas Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CWL</spirit:name>
+        <spirit:displayName>Cas Write Latency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_OUTPUT_DRV</spirit:name>
+        <spirit:displayName>Output drive Strength</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RTT_NOM</spirit:name>
+        <spirit:displayName>RTT Nominal</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_RTT_WR</spirit:name>
+        <spirit:displayName>RTT WR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM</spirit:name>
+        <spirit:displayName>Memory Name</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DBAW</spirit:name>
+        <spirit:displayName>DBAW</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCK</spirit:name>
+        <spirit:displayName>tCK</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCK">1500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Configuration</spirit:name>
+        <spirit:displayName>Configuration</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCKE</spirit:name>
+        <spirit:displayName>tCKE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tFAW</spirit:name>
+        <spirit:displayName>tFAW</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW">14</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tFAW_dlr</spirit:name>
+        <spirit:displayName>tFAW_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tMRD</spirit:name>
+        <spirit:displayName>tMRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRAS</spirit:name>
+        <spirit:displayName>tRAS</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRAS">22</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRCD</spirit:name>
+        <spirit:displayName>tRCD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRCD">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tREFI</spirit:name>
+        <spirit:displayName>tREFI</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tREFI">5200</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRFC</spirit:name>
+        <spirit:displayName>tRFC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC">234</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRFC_dlr</spirit:name>
+        <spirit:displayName>tRFC_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">80</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRP</spirit:name>
+        <spirit:displayName>tRP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRP">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWR</spirit:name>
+        <spirit:displayName>tWR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWR">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD</spirit:name>
+        <spirit:displayName>tRRD</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRTP</spirit:name>
+        <spirit:displayName>tRTP</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRTP">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_S</spirit:name>
+        <spirit:displayName>tRRD_S</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_S">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_L</spirit:name>
+        <spirit:displayName>tRRD_L</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_L">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tRRD_dlr</spirit:name>
+        <spirit:displayName>tRRD_dlr</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR</spirit:name>
+        <spirit:displayName>tWTR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR_S</spirit:name>
+        <spirit:displayName>tWTR_S</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_S">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tWTR_L</spirit:name>
+        <spirit:displayName>tWTR_L</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_L">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tXPR</spirit:name>
+        <spirit:displayName>tXPR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tXPR">60</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQI</spirit:name>
+        <spirit:displayName>tZQI</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQCS</spirit:name>
+        <spirit:displayName>tZQCS</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tZQINIT</spirit:name>
+        <spirit:displayName>tZQINIT</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_tCCD_3ds</spirit:name>
+        <spirit:displayName>tCCD_3ds</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name>
+        <spirit:displayName>CLKOUTPHY_MODE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT0_DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKOUT1_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT1_DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+        <spirit:displayName>CLKFBOUT_MULT</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+        <spirit:displayName>DIVCLK DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CAL_INPUT_CLK_PERIOD</spirit:name>
+        <spirit:displayName>Calculated Input Clock Period</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CLKIN_PERIOD</spirit:name>
+        <spirit:displayName>CLKIN_PERIOD</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">3333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name>
+        <spirit:displayName>High Range Supported frequency</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_DCI_CASCADE_CUTOFF</spirit:name>
+        <spirit:displayName>DCI Cascade Cutoff</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name>
+        <spirit:displayName>Is Faster Speed RAM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_ID_WIDTH</spirit:name>
+        <spirit:displayName>AXI ID Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI Address Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MEM_SIZE</spirit:name>
+        <spirit:displayName>Memory Size</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">8589934592</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_UI_CLOCK</spirit:name>
+        <spirit:displayName>DDR4 UI CLOCK</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">166500000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_CA_MIRROR</spirit:name>
+        <spirit:displayName>CA MIRROR</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_IS_CUSTOM</spirit:name>
+        <spirit:displayName>IS CUSTOM</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name>
+        <spirit:displayName>AUTO AP COL A3</spirit:displayName>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_MCS_ECC</spirit:name>
+        <spirit:displayName>MCS ECC</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Slot</spirit:name>
+        <spirit:displayName>Slot Type</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_DATA_WIDTH</spirit:name>
+        <spirit:displayName>APP Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">576</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.APP_MASK_WIDTH</spirit:name>
+        <spirit:displayName>APP Mask Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.APP_MASK_WIDTH">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_StackHeight</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CUSTOM_PART_ATTRIBUTES</spirit:name>
+        <spirit:displayName>custom_part_attributes</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT1_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT1 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT2_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT2 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT3_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT3 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT4_FREQ_HZ</spirit:name>
+        <spirit:displayName>CLKOUT4 FREQ HZ</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT1_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT1 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT2_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT2 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT3_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT3 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>M_ADDN_UI_CLKOUT4_PHASE</spirit:name>
+        <spirit:displayName>CLKOUT4 PHASE</spirit:displayName>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT0_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT0 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT1_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT1 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT1_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT2_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT2 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT3_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT3 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT4_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT4 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>CLKOUT6_DIVIDE</spirit:name>
+        <spirit:displayName>CLKOUT6 DIVIDE</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Debug_Signal</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>Simulation_Mode</spirit:name>
+        <spirit:displayName>Simulation Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter>
+        <spirit:name>C0.DDR4_Ecc</spirit:name>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_09ec3310</spirit:name>
+      <spirit:enumeration>Single</spirit:enumeration>
+      <spirit:enumeration>Dual</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_157065e4</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+      <spirit:enumeration>10</spirit:enumeration>
+      <spirit:enumeration>11</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_266493f0</spirit:name>
+      <spirit:enumeration>DDR4_SDRAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_28391b73</spirit:name>
+      <spirit:enumeration>1.2V</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_29a21725</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk0</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk1</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk2</spirit:enumeration>
+      <spirit:enumeration>default_300mhz_clk3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_2b96b8de</spirit:name>
+      <spirit:enumeration>Differential</spirit:enumeration>
+      <spirit:enumeration>No_Buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_301b19dd</spirit:name>
+      <spirit:enumeration>ON</spirit:enumeration>
+      <spirit:enumeration>OFF</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_30636008</spirit:name>
+      <spirit:enumeration>4:1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_30de7c39</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pcie_perstn</spirit:enumeration>
+      <spirit:enumeration>resetn</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_34c5244e</spirit:name>
+      <spirit:enumeration>Components</spirit:enumeration>
+      <spirit:enumeration>UDIMMs</spirit:enumeration>
+      <spirit:enumeration>SODIMMs</spirit:enumeration>
+      <spirit:enumeration>RDIMMs</spirit:enumeration>
+      <spirit:enumeration>LRDIMMs</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4665eb01</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4e3dbc0a</spirit:name>
+      <spirit:enumeration>SIMPLE_TG</spirit:enumeration>
+      <spirit:enumeration>ADVANCED_TG</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6330c9d2</spirit:name>
+      <spirit:enumeration>10</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_66456a11</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c0</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c1</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c2</spirit:enumeration>
+      <spirit:enumeration>ddr4_sdram_c3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_67b045e5</spirit:name>
+      <spirit:enumeration>BFM</spirit:enumeration>
+      <spirit:enumeration>Unisim</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_687ca1a5</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>500</spirit:enumeration>
+      <spirit:enumeration>375</spirit:enumeration>
+      <spirit:enumeration>300</spirit:enumeration>
+      <spirit:enumeration>250</spirit:enumeration>
+      <spirit:enumeration>214</spirit:enumeration>
+      <spirit:enumeration>188</spirit:enumeration>
+      <spirit:enumeration>167</spirit:enumeration>
+      <spirit:enumeration>150</spirit:enumeration>
+      <spirit:enumeration>136</spirit:enumeration>
+      <spirit:enumeration>125</spirit:enumeration>
+      <spirit:enumeration>115</spirit:enumeration>
+      <spirit:enumeration>107</spirit:enumeration>
+      <spirit:enumeration>100</spirit:enumeration>
+      <spirit:enumeration>94</spirit:enumeration>
+      <spirit:enumeration>88</spirit:enumeration>
+      <spirit:enumeration>83</spirit:enumeration>
+      <spirit:enumeration>79</spirit:enumeration>
+      <spirit:enumeration>75</spirit:enumeration>
+      <spirit:enumeration>71</spirit:enumeration>
+      <spirit:enumeration>68</spirit:enumeration>
+      <spirit:enumeration>65</spirit:enumeration>
+      <spirit:enumeration>63</spirit:enumeration>
+      <spirit:enumeration>60</spirit:enumeration>
+      <spirit:enumeration>58</spirit:enumeration>
+      <spirit:enumeration>56</spirit:enumeration>
+      <spirit:enumeration>54</spirit:enumeration>
+      <spirit:enumeration>52</spirit:enumeration>
+      <spirit:enumeration>50</spirit:enumeration>
+      <spirit:enumeration>48</spirit:enumeration>
+      <spirit:enumeration>47</spirit:enumeration>
+      <spirit:enumeration>45</spirit:enumeration>
+      <spirit:enumeration>44</spirit:enumeration>
+      <spirit:enumeration>43</spirit:enumeration>
+      <spirit:enumeration>42</spirit:enumeration>
+      <spirit:enumeration>41</spirit:enumeration>
+      <spirit:enumeration>39</spirit:enumeration>
+      <spirit:enumeration>38</spirit:enumeration>
+      <spirit:enumeration>37</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
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+      <spirit:enumeration>33</spirit:enumeration>
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+      <spirit:enumeration>27</spirit:enumeration>
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+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
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+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_7240037c</spirit:name>
+      <spirit:enumeration>MTA18ASF1G72PDZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA9ASF51272PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF2G72PDZ-2G3</spirit:enumeration>
+      <spirit:enumeration>MTA9ASF1G72PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>M393A1G43DB1-CRC</spirit:enumeration>
+      <spirit:enumeration>MTA9ASF51272PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>MTA18ADF1G72PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF1G72PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA36ASF2G72PZ-2G1</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF2G72PZ-2G9</spirit:enumeration>
+      <spirit:enumeration>MTA18ASF2G72PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>MTA36ASF4G72PZ-2G3</spirit:enumeration>
+      <spirit:enumeration>M393A2G40DB1-CRC</spirit:enumeration>
+      <spirit:enumeration>M393A8K40B21-CTC</spirit:enumeration>
+      <spirit:enumeration>M393AAK40B41-CTC</spirit:enumeration>
+      <spirit:enumeration>M393A2K40BB1-CRC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8b4f223f</spirit:name>
+      <spirit:enumeration>Strict</spirit:enumeration>
+      <spirit:enumeration>Normal</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8d3f5284</spirit:name>
+      <spirit:enumeration>DM_NO_DBI</spirit:enumeration>
+      <spirit:enumeration>DM_DBI_RD</spirit:enumeration>
+      <spirit:enumeration>NO_DM_DBI_RD</spirit:enumeration>
+      <spirit:enumeration>NO_DM_DBI_WR</spirit:enumeration>
+      <spirit:enumeration>NO_DM_DBI_WR_RD</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_98f5c8fa</spirit:name>
+      <spirit:enumeration>RZQ/6</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a187d5e4</spirit:name>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ad101c66</spirit:name>
+      <spirit:enumeration>RZQ/7</spirit:enumeration>
+      <spirit:enumeration>RZQ/6</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ae57517c</spirit:name>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c89503c8</spirit:name>
+      <spirit:enumeration>ROW_BANK_COLUMN</spirit:enumeration>
+      <spirit:enumeration>BANK_ROW_COLUMN</spirit:enumeration>
+      <spirit:enumeration>ROW_COLUMN_BANK</spirit:enumeration>
+      <spirit:enumeration>ROW_COLUMN_BANK_INTLV</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d6556846</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d8920bdd</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_df7e3f8b</spirit:name>
+      <spirit:enumeration>Sequential</spirit:enumeration>
+      <spirit:enumeration>Interleaved</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e7093afb</spirit:name>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>33</spirit:enumeration>
+      <spirit:enumeration>34</spirit:enumeration>
+      <spirit:enumeration>35</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ed30197c</spirit:name>
+      <spirit:enumeration>TDM</spirit:enumeration>
+      <spirit:enumeration>ROUND_ROBIN</spirit:enumeration>
+      <spirit:enumeration>RD_PRI_REG</spirit:enumeration>
+      <spirit:enumeration>RD_PRI_REG_STARVE_LIMIT</spirit:enumeration>
+      <spirit:enumeration>WRITE_PRIORITY_REG</spirit:enumeration>
+      <spirit:enumeration>WRITE_PRIORITY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ef319ec8</spirit:name>
+      <spirit:enumeration>Differential</spirit:enumeration>
+      <spirit:enumeration>Single_Ended</spirit:enumeration>
+      <spirit:enumeration>No_Buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f3cd92fb</spirit:name>
+      <spirit:enumeration>Disable</spirit:enumeration>
+      <spirit:enumeration>Enable</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fe2d3253</spirit:name>
+      <spirit:enumeration>72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ff0950bb</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>CL-1</spirit:enumeration>
+      <spirit:enumeration>CL-2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_01257c99</spirit:name>
+      <spirit:enumeration spirit:text="Controller_and_physical_layer">Complete_Memory_Controller</spirit:enumeration>
+      <spirit:enumeration spirit:text="Physical_Layer_Only">Phy_Only_Single</spirit:enumeration>
+      <spirit:enumeration spirit:text="Physical_Layer_PingPong">Phy_Only_PingPong</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_05415bea</spirit:name>
+      <spirit:enumeration spirit:text="14000 (71.4286Mhz)">14000</spirit:enumeration>
+      <spirit:enumeration spirit:text="13999 (71.4286Mhz)">13999</spirit:enumeration>
+      <spirit:enumeration spirit:text="13200 (75.7576Mhz)">13200</spirit:enumeration>
+      <spirit:enumeration spirit:text="13199 (75.7576Mhz)">13199</spirit:enumeration>
+      <spirit:enumeration spirit:text="12000 (83.3333Mhz)">12000</spirit:enumeration>
+      <spirit:enumeration spirit:text="11999 (83.3333Mhz)">11999</spirit:enumeration>
+      <spirit:enumeration spirit:text="10801 (92.5926Mhz)">10801</spirit:enumeration>
+      <spirit:enumeration spirit:text="10800 (92.5926Mhz)">10800</spirit:enumeration>
+      <spirit:enumeration spirit:text="10500 (95.2381Mhz)">10500</spirit:enumeration>
+      <spirit:enumeration spirit:text="10499 (95.2381Mhz)">10499</spirit:enumeration>
+      <spirit:enumeration spirit:text="10000 (100Mhz)">10000</spirit:enumeration>
+      <spirit:enumeration spirit:text="9601 (104.167Mhz)">9601</spirit:enumeration>
+      <spirit:enumeration spirit:text="9600 (104.167Mhz)">9600</spirit:enumeration>
+      <spirit:enumeration spirit:text="9599 (104.167Mhz)">9599</spirit:enumeration>
+      <spirit:enumeration spirit:text="9000 (111.111Mhz)">9000</spirit:enumeration>
+      <spirit:enumeration spirit:text="8999 (111.111Mhz)">8999</spirit:enumeration>
+      <spirit:enumeration spirit:text="8572 (116.667Mhz)">8572</spirit:enumeration>
+      <spirit:enumeration spirit:text="8571 (116.667Mhz)">8571</spirit:enumeration>
+      <spirit:enumeration spirit:text="8400 (119.048Mhz)">8400</spirit:enumeration>
+      <spirit:enumeration spirit:text="8399 (119.048Mhz)">8399</spirit:enumeration>
+      <spirit:enumeration spirit:text="8000 (125Mhz)">8000</spirit:enumeration>
+      <spirit:enumeration spirit:text="7715 (129.618Mhz)">7715</spirit:enumeration>
+      <spirit:enumeration spirit:text="7714 (129.618Mhz)">7714</spirit:enumeration>
+      <spirit:enumeration spirit:text="7501 (133.333Mhz)">7501</spirit:enumeration>
+      <spirit:enumeration spirit:text="7500 (133.333Mhz)">7500</spirit:enumeration>
+      <spirit:enumeration spirit:text="7499 (133.333Mhz)">7499</spirit:enumeration>
+      <spirit:enumeration spirit:text="7201 (138.889Mhz)">7201</spirit:enumeration>
+      <spirit:enumeration spirit:text="7200 (138.889Mhz)">7200</spirit:enumeration>
+      <spirit:enumeration spirit:text="7000 (142.857Mhz)">7000</spirit:enumeration>
+      <spirit:enumeration spirit:text="6999 (142.857Mhz)">6999</spirit:enumeration>
+      <spirit:enumeration spirit:text="6858 (145.815Mhz)">6858</spirit:enumeration>
+      <spirit:enumeration spirit:text="6857 (145.815Mhz)">6857</spirit:enumeration>
+      <spirit:enumeration spirit:text="6500 (153.846Mhz)">6500</spirit:enumeration>
+      <spirit:enumeration spirit:text="6499 (153.846Mhz)">6499</spirit:enumeration>
+      <spirit:enumeration spirit:text="6000 (166.667Mhz)">6000</spirit:enumeration>
+      <spirit:enumeration spirit:text="5999 (166.667Mhz)">5999</spirit:enumeration>
+      <spirit:enumeration spirit:text="5573 (179.469Mhz)">5573</spirit:enumeration>
+      <spirit:enumeration spirit:text="5572 (179.469Mhz)">5572</spirit:enumeration>
+      <spirit:enumeration spirit:text="5571 (179.487Mhz)">5571</spirit:enumeration>
+      <spirit:enumeration spirit:text="5401 (185.185Mhz)">5401</spirit:enumeration>
+      <spirit:enumeration spirit:text="5400 (185.185Mhz)">5400</spirit:enumeration>
+      <spirit:enumeration spirit:text="5335 (187.477Mhz)">5335</spirit:enumeration>
+      <spirit:enumeration spirit:text="5334 (187.5Mhz)">5334</spirit:enumeration>
+      <spirit:enumeration spirit:text="5333 (187.5Mhz)">5333</spirit:enumeration>
+      <spirit:enumeration spirit:text="5000 (200Mhz)">5000</spirit:enumeration>
+      <spirit:enumeration spirit:text="4876 (205.128Mhz)">4876</spirit:enumeration>
+      <spirit:enumeration spirit:text="4875 (205.128Mhz)">4875</spirit:enumeration>
+      <spirit:enumeration spirit:text="4801 (208.333Mhz)">4801</spirit:enumeration>
+      <spirit:enumeration spirit:text="4800 (208.333Mhz)">4800</spirit:enumeration>
+      <spirit:enumeration spirit:text="4715 (212.089Mhz)">4715</spirit:enumeration>
+      <spirit:enumeration spirit:text="4714 (212.089Mhz)">4714</spirit:enumeration>
+      <spirit:enumeration spirit:text="4667 (214.286Mhz)">4667</spirit:enumeration>
+      <spirit:enumeration spirit:text="4666 (214.286Mhz)">4666</spirit:enumeration>
+      <spirit:enumeration spirit:text="4573 (218.723Mhz)">4573</spirit:enumeration>
+      <spirit:enumeration spirit:text="4572 (218.723Mhz)">4572</spirit:enumeration>
+      <spirit:enumeration spirit:text="4571 (218.75Mhz)">4571</spirit:enumeration>
+      <spirit:enumeration spirit:text="4500 (222.222Mhz)">4500</spirit:enumeration>
+      <spirit:enumeration spirit:text="4499 (222.222Mhz)">4499</spirit:enumeration>
+      <spirit:enumeration spirit:text="4446 (224.972Mhz)">4446</spirit:enumeration>
+      <spirit:enumeration spirit:text="4445 (224.972Mhz)">4445</spirit:enumeration>
+      <spirit:enumeration spirit:text="4444 (225Mhz)">4444</spirit:enumeration>
+      <spirit:enumeration spirit:text="4401 (227.273Mhz)">4401</spirit:enumeration>
+      <spirit:enumeration spirit:text="4400 (227.273Mhz)">4400</spirit:enumeration>
+      <spirit:enumeration spirit:text="4286 (233.333Mhz)">4286</spirit:enumeration>
+      <spirit:enumeration spirit:text="4285 (233.333Mhz)">4285</spirit:enumeration>
+      <spirit:enumeration spirit:text="4223 (236.842Mhz)">4223</spirit:enumeration>
+      <spirit:enumeration spirit:text="4222 (236.842Mhz)">4222</spirit:enumeration>
+      <spirit:enumeration spirit:text="4126 (242.424Mhz)">4126</spirit:enumeration>
+      <spirit:enumeration spirit:text="4125 (242.424Mhz)">4125</spirit:enumeration>
+      <spirit:enumeration spirit:text="4124 (242.424Mhz)">4124</spirit:enumeration>
+      <spirit:enumeration spirit:text="4000 (250Mhz)">4000</spirit:enumeration>
+      <spirit:enumeration spirit:text="3858 (259.202Mhz)">3858</spirit:enumeration>
+      <spirit:enumeration spirit:text="3857 (259.202Mhz)">3857</spirit:enumeration>
+      <spirit:enumeration spirit:text="3779 (264.69Mhz)">3779</spirit:enumeration>
+      <spirit:enumeration spirit:text="3778 (264.706Mhz)">3778</spirit:enumeration>
+      <spirit:enumeration spirit:text="3777 (264.706Mhz)">3777</spirit:enumeration>
+      <spirit:enumeration spirit:text="3715 (269.231Mhz)">3715</spirit:enumeration>
+      <spirit:enumeration spirit:text="3714 (269.231Mhz)">3714</spirit:enumeration>
+      <spirit:enumeration spirit:text="3601 (277.778Mhz)">3601</spirit:enumeration>
+      <spirit:enumeration spirit:text="3600 (277.778Mhz)">3600</spirit:enumeration>
+      <spirit:enumeration spirit:text="3563 (280.702Mhz)">3563</spirit:enumeration>
+      <spirit:enumeration spirit:text="3562 (280.702Mhz)">3562</spirit:enumeration>
+      <spirit:enumeration spirit:text="3557 (281.215Mhz)">3557</spirit:enumeration>
+      <spirit:enumeration spirit:text="3556 (281.215Mhz)">3556</spirit:enumeration>
+      <spirit:enumeration spirit:text="3555 (281.25Mhz)">3555</spirit:enumeration>
+      <spirit:enumeration spirit:text="3500 (285.714Mhz)">3500</spirit:enumeration>
+      <spirit:enumeration spirit:text="3499 (285.714Mhz)">3499</spirit:enumeration>
+      <spirit:enumeration spirit:text="3429 (291.63Mhz)">3429</spirit:enumeration>
+      <spirit:enumeration spirit:text="3428 (291.63Mhz)">3428</spirit:enumeration>
+      <spirit:enumeration spirit:text="3335 (299.94Mhz)">3335</spirit:enumeration>
+      <spirit:enumeration spirit:text="3334 (300Mhz)">3334</spirit:enumeration>
+      <spirit:enumeration spirit:text="3333 (300Mhz)">3333</spirit:enumeration>
+      <spirit:enumeration spirit:text="3250 (307.692Mhz)">3250</spirit:enumeration>
+      <spirit:enumeration spirit:text="3249 (307.692Mhz)">3249</spirit:enumeration>
+      <spirit:enumeration spirit:text="3188 (313.725Mhz)">3188</spirit:enumeration>
+      <spirit:enumeration spirit:text="3187 (313.725Mhz)">3187</spirit:enumeration>
+      <spirit:enumeration spirit:text="3112 (321.429Mhz)">3112</spirit:enumeration>
+      <spirit:enumeration spirit:text="3111 (321.429Mhz)">3111</spirit:enumeration>
+      <spirit:enumeration spirit:text="3000 (333.333Mhz)">3000</spirit:enumeration>
+      <spirit:enumeration spirit:text="2999 (333.333Mhz)">2999</spirit:enumeration>
+      <spirit:enumeration spirit:text="2889 (346.154Mhz)">2889</spirit:enumeration>
+      <spirit:enumeration spirit:text="2888 (346.154Mhz)">2888</spirit:enumeration>
+      <spirit:enumeration spirit:text="2801 (357.143Mhz)">2801</spirit:enumeration>
+      <spirit:enumeration spirit:text="2800 (357.143Mhz)">2800</spirit:enumeration>
+      <spirit:enumeration spirit:text="2787 (358.938Mhz)">2787</spirit:enumeration>
+      <spirit:enumeration spirit:text="2786 (358.938Mhz)">2786</spirit:enumeration>
+      <spirit:enumeration spirit:text="2785 (358.974Mhz)">2785</spirit:enumeration>
+      <spirit:enumeration spirit:text="2751 (363.636Mhz)">2751</spirit:enumeration>
+      <spirit:enumeration spirit:text="2750 (363.636Mhz)">2750</spirit:enumeration>
+      <spirit:enumeration spirit:text="2701 (370.37Mhz)">2701</spirit:enumeration>
+      <spirit:enumeration spirit:text="2700 (370.37Mhz)">2700</spirit:enumeration>
+      <spirit:enumeration spirit:text="2668 (374.953Mhz)">2668</spirit:enumeration>
+      <spirit:enumeration spirit:text="2667 (375Mhz)">2667</spirit:enumeration>
+      <spirit:enumeration spirit:text="2666 (375Mhz)">2666</spirit:enumeration>
+      <spirit:enumeration spirit:text="2641 (378.788Mhz)">2641</spirit:enumeration>
+      <spirit:enumeration spirit:text="2640 (378.788Mhz)">2640</spirit:enumeration>
+      <spirit:enumeration spirit:text="2639 (378.788Mhz)">2639</spirit:enumeration>
+      <spirit:enumeration spirit:text="2625 (380.952Mhz)">2625</spirit:enumeration>
+      <spirit:enumeration spirit:text="2624 (380.952Mhz)">2624</spirit:enumeration>
+      <spirit:enumeration spirit:text="2572 (388.802Mhz)">2572</spirit:enumeration>
+      <spirit:enumeration spirit:text="2571 (388.802Mhz)">2571</spirit:enumeration>
+      <spirit:enumeration spirit:text="2500 (400Mhz)">2500</spirit:enumeration>
+      <spirit:enumeration spirit:text="2445 (409.091Mhz)">2445</spirit:enumeration>
+      <spirit:enumeration spirit:text="2444 (409.091Mhz)">2444</spirit:enumeration>
+      <spirit:enumeration spirit:text="2438 (410.256Mhz)">2438</spirit:enumeration>
+      <spirit:enumeration spirit:text="2437 (410.256Mhz)">2437</spirit:enumeration>
+      <spirit:enumeration spirit:text="2401 (416.667Mhz)">2401</spirit:enumeration>
+      <spirit:enumeration spirit:text="2400 (416.667Mhz)">2400</spirit:enumeration>
+      <spirit:enumeration spirit:text="2399 (416.667Mhz)">2399</spirit:enumeration>
+      <spirit:enumeration spirit:text="2334 (428.571Mhz)">2334</spirit:enumeration>
+      <spirit:enumeration spirit:text="2333 (428.571Mhz)">2333</spirit:enumeration>
+      <spirit:enumeration spirit:text="2287 (437.445Mhz)">2287</spirit:enumeration>
+      <spirit:enumeration spirit:text="2286 (437.445Mhz)">2286</spirit:enumeration>
+      <spirit:enumeration spirit:text="2250 (444.444Mhz)">2250</spirit:enumeration>
+      <spirit:enumeration spirit:text="2249 (444.444Mhz)">2249</spirit:enumeration>
+      <spirit:enumeration spirit:text="2223 (450Mhz)">2223</spirit:enumeration>
+      <spirit:enumeration spirit:text="2222 (450Mhz)">2222</spirit:enumeration>
+      <spirit:enumeration spirit:text="2201 (454.545Mhz)">2201</spirit:enumeration>
+      <spirit:enumeration spirit:text="2200 (454.545Mhz)">2200</spirit:enumeration>
+      <spirit:enumeration spirit:text="2161 (462.963Mhz)">2161</spirit:enumeration>
+      <spirit:enumeration spirit:text="2160 (462.963Mhz)">2160</spirit:enumeration>
+      <spirit:enumeration spirit:text="2143 (466.667Mhz)">2143</spirit:enumeration>
+      <spirit:enumeration spirit:text="2142 (466.667Mhz)">2142</spirit:enumeration>
+      <spirit:enumeration spirit:text="2112 (473.684Mhz)">2112</spirit:enumeration>
+      <spirit:enumeration spirit:text="2111 (473.684Mhz)">2111</spirit:enumeration>
+      <spirit:enumeration spirit:text="2100 (476.19Mhz)">2100</spirit:enumeration>
+      <spirit:enumeration spirit:text="2099 (476.19Mhz)">2099</spirit:enumeration>
+      <spirit:enumeration spirit:text="2063 (484.849Mhz)">2063</spirit:enumeration>
+      <spirit:enumeration spirit:text="2062 (484.849Mhz)">2062</spirit:enumeration>
+      <spirit:enumeration spirit:text="2000 (500Mhz)">2000</spirit:enumeration>
+      <spirit:enumeration spirit:text="1960 (510.417Mhz)">1960</spirit:enumeration>
+      <spirit:enumeration spirit:text="1959 (510.417Mhz)">1959</spirit:enumeration>
+      <spirit:enumeration spirit:text="1921 (520.833Mhz)">1921</spirit:enumeration>
+      <spirit:enumeration spirit:text="1920 (520.833Mhz)">1920</spirit:enumeration>
+      <spirit:enumeration spirit:text="1919 (520.833Mhz)">1919</spirit:enumeration>
+      <spirit:enumeration spirit:text="1890 (529.381Mhz)">1890</spirit:enumeration>
+      <spirit:enumeration spirit:text="1889 (529.412Mhz)">1889</spirit:enumeration>
+      <spirit:enumeration spirit:text="1888 (529.412Mhz)">1888</spirit:enumeration>
+      <spirit:enumeration spirit:text="1886 (530.303Mhz)">1886</spirit:enumeration>
+      <spirit:enumeration spirit:text="1885 (530.303Mhz)">1885</spirit:enumeration>
+      <spirit:enumeration spirit:text="1858 (538.462Mhz)">1858</spirit:enumeration>
+      <spirit:enumeration spirit:text="1857 (538.462Mhz)">1857</spirit:enumeration>
+      <spirit:enumeration spirit:text="1801 (555.556Mhz)">1801</spirit:enumeration>
+      <spirit:enumeration spirit:text="1800 (555.556Mhz)">1800</spirit:enumeration>
+      <spirit:enumeration spirit:text="1799 (555.556Mhz)">1799</spirit:enumeration>
+      <spirit:enumeration spirit:text="1782 (561.404Mhz)">1782</spirit:enumeration>
+      <spirit:enumeration spirit:text="1781 (561.404Mhz)">1781</spirit:enumeration>
+      <spirit:enumeration spirit:text="1779 (562.43Mhz)">1779</spirit:enumeration>
+      <spirit:enumeration spirit:text="1778 (562.43Mhz)">1778</spirit:enumeration>
+      <spirit:enumeration spirit:text="1777 (562.5Mhz)">1777</spirit:enumeration>
+      <spirit:enumeration spirit:text="1750 (571.429Mhz)">1750</spirit:enumeration>
+      <spirit:enumeration spirit:text="1749 (571.429Mhz)">1749</spirit:enumeration>
+      <spirit:enumeration spirit:text="1715 (583.333Mhz)">1715</spirit:enumeration>
+      <spirit:enumeration spirit:text="1714 (583.333Mhz)">1714</spirit:enumeration>
+      <spirit:enumeration spirit:text="1680 (595.238Mhz)">1680</spirit:enumeration>
+      <spirit:enumeration spirit:text="1679 (595.238Mhz)">1679</spirit:enumeration>
+      <spirit:enumeration spirit:text="1668 (599.88Mhz)">1668</spirit:enumeration>
+      <spirit:enumeration spirit:text="1667 (600Mhz)">1667</spirit:enumeration>
+      <spirit:enumeration spirit:text="1666 (600Mhz)">1666</spirit:enumeration>
+      <spirit:enumeration spirit:text="1625 (615.385Mhz)">1625</spirit:enumeration>
+      <spirit:enumeration spirit:text="1624 (615.385Mhz)">1624</spirit:enumeration>
+      <spirit:enumeration spirit:text="1600 (625Mhz)">1600</spirit:enumeration>
+      <spirit:enumeration spirit:text="1594 (627.451Mhz)">1594</spirit:enumeration>
+      <spirit:enumeration spirit:text="1593 (627.451Mhz)">1593</spirit:enumeration>
+      <spirit:enumeration spirit:text="1592 (628.205Mhz)">1592</spirit:enumeration>
+      <spirit:enumeration spirit:text="1591 (628.205Mhz)">1591</spirit:enumeration>
+      <spirit:enumeration spirit:text="1556 (642.857Mhz)">1556</spirit:enumeration>
+      <spirit:enumeration spirit:text="1555 (642.857Mhz)">1555</spirit:enumeration>
+      <spirit:enumeration spirit:text="1544 (648.088Mhz)">1544</spirit:enumeration>
+      <spirit:enumeration spirit:text="1543 (648.088Mhz)">1543</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratesubcores_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>ip_0/phy_rdimm_x8_dual_microblaze_mcs.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_0/phy_rdimm_x8_dual_microblaze_mcs.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/phy_rdimm_x8_dual_phy.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/phy_rdimm_x8_dual_phy.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:cpus>
+    <spirit:cpu>
+      <spirit:name>phy_rdimm_x8_dual</spirit:name>
+      <spirit:addressSpaceRef spirit:addressSpaceRef="dummy"/>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>instance_path</spirit:name>
+          <spirit:value>inst/u_ddr_cal_riu/mcs0/inst/microblaze_I</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bootloop_file</spirit:name>
+          <spirit:value>sw/calibration_0/Debug/calibration_ddr.elf</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>endian</spirit:name>
+          <spirit:value>little</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>processor_type</spirit:name>
+          <spirit:value>MICROBLAZE-LE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>is_visible</spirit:name>
+          <spirit:value>false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:cpu>
+  </spirit:cpus>
+  <spirit:description>DDR4 Interface Generator for Ultrascale Architecture</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C0.ControllerType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ControllerType" spirit:choiceRef="choice_list_266493f0" spirit:order="2">DDR4_SDRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.ControllerType">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IOPowerReduction</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IOPowerReduction" spirit:choiceRef="choice_list_301b19dd" spirit:order="3">OFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_SysPorts</spirit:name>
+      <spirit:displayName>Auto assign static ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_SysPorts" spirit:order="4">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Phy_Only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Phy_Only" spirit:choiceRef="choice_pairs_01257c99" spirit:order="5">Phy_Only_Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_30de7c39" spirit:order="6">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RESET_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0_CLOCK_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE" spirit:choiceRef="choice_list_29a21725" spirit:order="7">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C0_CLOCK_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IS_FROM_PHY</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IS_FROM_PHY" spirit:order="8">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RECONFIG_XSDB_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE" spirit:order="9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AL_SEL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AL_SEL" spirit:choiceRef="choice_list_ff0950bb" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Example_TG</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Example_TG" spirit:choiceRef="choice_list_4e3dbc0a" spirit:order="11">SIMPLE_TG</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.Example_TG">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Clamshell</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Clamshell" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_Clamshell">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.MIGRATION</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.MIGRATION" spirit:order="13">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_OP1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_OP1" spirit:order="14">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_OP2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_OP2" spirit:order="15">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TIMING_3DS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TIMING_3DS" spirit:order="16">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SET_DW_TO_40</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SET_DW_TO_40" spirit:order="17">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_TERM_SYSCLK</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_TERM_SYSCLK" spirit:order="18">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0_DDR4_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE" spirit:choiceRef="choice_list_66456a11" spirit:order="19">Custom</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C0_DDR4_BOARD_INTERFACE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TimePeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TimePeriod" spirit:order="20" spirit:minimum="750" spirit:maximum="1600" spirit:rangeType="long">1500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_InputClockPeriod</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_InputClockPeriod" spirit:choiceRef="choice_pairs_05415bea" spirit:order="21">3333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Specify_MandD</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Specify_MandD" spirit:order="22">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" spirit:order="23" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CLKFBOUT_MULT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE" spirit:order="24" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_DIVCLK_DIVIDE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" spirit:order="25" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CLKOUT0_DIVIDE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PhyClockRatio</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PhyClockRatio" spirit:choiceRef="choice_list_30636008" spirit:order="26">4:1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryType" spirit:choiceRef="choice_list_34c5244e" spirit:order="27">RDIMMs</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryPart</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryPart" spirit:choiceRef="choice_list_7240037c" spirit:order="28">MTA9ASF1G72PZ-2G3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Slot</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Slot" spirit:choiceRef="choice_list_09ec3310" spirit:order="29">Single</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryVoltage</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryVoltage" spirit:choiceRef="choice_list_28391b73" spirit:order="30">1.2V</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataWidth" spirit:choiceRef="choice_list_fe2d3253" spirit:order="31">72</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_DataMask</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_DataMask" spirit:choiceRef="choice_list_8d3f5284" spirit:order="32">DM_NO_DBI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ecc" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_Ecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MCS_ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MCS_ECC" spirit:order="34">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiSelection</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiSelection" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_AxiSelection">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3" spirit:order="36">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Ordering</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Ordering" spirit:choiceRef="choice_list_8b4f223f" spirit:order="37">Normal</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BurstLength</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BurstLength" spirit:choiceRef="choice_list_d8920bdd" spirit:order="38">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_BurstLength">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BurstType</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BurstType" spirit:choiceRef="choice_list_df7e3f8b" spirit:order="39">Sequential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_OutputDriverImpedenceControl</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl" spirit:choiceRef="choice_list_ad101c66" spirit:order="40">RZQ/7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_OnDieTermination</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_OnDieTermination" spirit:choiceRef="choice_list_98f5c8fa" spirit:order="41">RZQ/6</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasLatency" spirit:choiceRef="choice_list_6330c9d2" spirit:order="42">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CasWriteLatency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CasWriteLatency" spirit:choiceRef="choice_list_ae57517c" spirit:order="43">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ChipSelect</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ChipSelect" spirit:order="44">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_ChipSelect">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCKEShared</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCKEShared" spirit:order="45">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiDataWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiDataWidth" spirit:choiceRef="choice_list_d6556846" spirit:order="46">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiArbitrationScheme</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme" spirit:choiceRef="choice_list_ed30197c" spirit:order="47">RD_PRI_REG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiNarrowBurst</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiNarrowBurst" spirit:order="48">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiAddressWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiAddressWidth" spirit:choiceRef="choice_list_e7093afb" spirit:order="49">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AxiIDWidth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AxiIDWidth" spirit:choiceRef="choice_list_157065e4" spirit:order="50">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Capacity</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Capacity" spirit:choiceRef="choice_list_a187d5e4" spirit:order="51">512</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_Mem_Add_Map</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_Mem_Add_Map" spirit:choiceRef="choice_list_c89503c8" spirit:order="52">ROW_COLUMN_BANK</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_MemoryName</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_MemoryName" spirit:order="53">MainMemory</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_AutoPrecharge</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_AutoPrecharge" spirit:order="54">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_AutoPrecharge">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_UserRefresh_ZQCS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS" spirit:order="55">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_UserRefresh_ZQCS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CustomParts</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CustomParts" spirit:order="56">no_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:parameterType>file_csv</xilinx:parameterType>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_CustomParts">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_isCustom</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_isCustom" spirit:order="57">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SELF_REFRESH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SELF_REFRESH" spirit:order="58">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_SELF_REFRESH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_SAVE_RESTORE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_SAVE_RESTORE" spirit:order="59">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_RESTORE_CRC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_RESTORE_CRC" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C0.DDR4_RESTORE_CRC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT1_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="61">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT2_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="62">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT3_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="63">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDN_UI_CLKOUT4_FREQ_HZ</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ" spirit:choiceRef="choice_list_687ca1a5" spirit:order="64">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6" spirit:order="65">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">phy_rdimm_x8_dual</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>No_Controller</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.No_Controller" spirit:choiceRef="choice_list_4665eb01" spirit:order="100">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>System_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.System_Clock" spirit:choiceRef="choice_list_2b96b8de" spirit:order="200">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reference_Clock</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reference_Clock" spirit:choiceRef="choice_list_ef319ec8" spirit:order="300">Differential</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Debug_Signal</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Debug_Signal" spirit:choiceRef="choice_list_f3cd92fb" spirit:order="400">Disable</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IO_Power_Reduction</spirit:name>
+      <spirit:displayName>IO_Power_Reduction</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.IO_Power_Reduction" spirit:order="500">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DCI_Cascade</spirit:name>
+      <spirit:displayName>DCI Cascade</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.DCI_Cascade" spirit:order="600">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Default_Bank_Selections</spirit:name>
+      <spirit:displayName>Default Bank Selections</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Default_Bank_Selections" spirit:order="700">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Simulation_Mode</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Simulation_Mode" spirit:choiceRef="choice_list_67b045e5" spirit:order="800">BFM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PARTIAL_RECONFIG_FLOW_MIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG" spirit:order="801">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PARTIAL_RECONFIG_FLOW_MIG">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MCS_DBG_EN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MCS_DBG_EN" spirit:order="802">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_0" spirit:order="803" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_1" spirit:order="804" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_2" spirit:order="805" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CK_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CK_SKEW_3" spirit:order="806" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0" spirit:order="807" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1" spirit:order="808" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2" spirit:order="809" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3" spirit:order="810" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_4</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4" spirit:order="811" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_5</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5" spirit:order="812" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_6</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6" spirit:order="813" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_7</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7" spirit:order="814" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_8</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8" spirit:order="815" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_9</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9" spirit:order="816" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_10</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10" spirit:order="817" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_11</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_11" spirit:order="818" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_12</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_12" spirit:order="819" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_13</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13" spirit:order="820" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_14</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14" spirit:order="821" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_15</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15" spirit:order="822" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_16</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16" spirit:order="823" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ADDR_SKEW_17</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17" spirit:order="824" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BA_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BA_SKEW_0" spirit:order="825" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BA_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BA_SKEW_1" spirit:order="826" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BG_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BG_SKEW_0" spirit:order="827" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_BG_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_BG_SKEW_1" spirit:order="828" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_0" spirit:order="829" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_1" spirit:order="830" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_2" spirit:order="831" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CS_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CS_SKEW_3" spirit:order="832" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_0" spirit:order="833" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_1" spirit:order="834" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_2" spirit:order="835" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_CKE_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_CKE_SKEW_3" spirit:order="836" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ACT_SKEW</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ACT_SKEW" spirit:order="837" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_PAR_SKEW</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_PAR_SKEW" spirit:order="838" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_0" spirit:order="839" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_1" spirit:order="840" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_2</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_2" spirit:order="841" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_ODT_SKEW_3</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_ODT_SKEW_3" spirit:order="842" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_LR_SKEW_0</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_LR_SKEW_0" spirit:order="843" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_LR_SKEW_1</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_LR_SKEW_1" spirit:order="844" spirit:minimum="0" spirit:maximum="75" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TREFI</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TREFI" spirit:order="845">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TRFC</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TRFC" spirit:order="846">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TRFC_DLR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TRFC_DLR" spirit:order="847">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_TXPR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_TXPR" spirit:order="848">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TREFI</spirit:name>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TRFC</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TRFC" spirit:order="850">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.DDR4_nCK_TRFC_DLR</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR" spirit:order="851">0</spirit:value>
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+    </spirit:parameter>
+    <spirit:parameter>
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+      <spirit:displayName>BANK GROUP WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.BANK_GROUP_WIDTH" spirit:order="854">2</spirit:value>
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+    <spirit:parameter>
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+      <spirit:displayName>LR WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.LR_WIDTH" spirit:order="855">1</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>C0.CK_WIDTH</spirit:name>
+      <spirit:displayName>CK WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CK_WIDTH" spirit:order="856">1</spirit:value>
+    </spirit:parameter>
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+      <spirit:name>C0.CKE_WIDTH</spirit:name>
+      <spirit:displayName>CKE WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CKE_WIDTH" spirit:order="857">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.CS_WIDTH</spirit:name>
+      <spirit:displayName>CS WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.CS_WIDTH" spirit:order="858">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C0.ODT_WIDTH</spirit:name>
+      <spirit:displayName>ODT WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.ODT_WIDTH" spirit:order="859">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
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+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C0.StackHeight" spirit:order="860">1</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>PING_PONG_PHY</spirit:name>
+      <spirit:displayName>Ping Pong Phy</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PING_PONG_PHY" spirit:order="861">1</spirit:value>
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+    </spirit:parameter>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig
new file mode 100644
index 0000000..698f7e5
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.orig
@@ -0,0 +1,313 @@
+/******************************************************************************
+// (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+******************************************************************************/
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor             : Xilinx
+// \   \   \/     Version            : 1.1
+//  \   \         Application        : MIG
+//  /   /         Filename           : ddr4_v2_2_10_cal_rd_en.sv
+// /___/   /\     Date Last Modified : $Date: 2015/04/23 $
+// \   \  /  \    Date Created       : Thu Apr 18 2013
+//  \___\/\___\
+//
+// Device           : UltraScale
+// Design Name      : DDR4 SDRAM & DDR3 SDRAM
+// Purpose          :
+//                   ddr4_v2_2_10_cal_rd_en module
+// Reference        :
+// Revision History :
+//*****************************************************************************
+
+`timescale 1ns/100ps
+
+module ddr4_v2_2_10_cal_rd_en #(parameter
+    RANKS = 1
+   ,RL  = 11
+   ,EXTRA_CMD_DELAY  = 0
+   ,TCQ = 0.1
+)(
+    input clk
+   ,input rst
+
+   ,output [3:0] mc_clb2phy_rden
+   ,output [3:0] mc_clb2phy_rdcs0
+   ,output [3:0] mc_clb2phy_rdcs1
+
+   ,input [1:0] casSlot       // spyglass disable W498
+   ,input       mccasSlot2
+   ,input       rdCAS
+   ,input       calrdCAS
+   ,input       mcrdCAS
+   ,input [5:0] mCL0
+   ,input [5:0] mCL1
+   ,input [5:0] mCL2
+   ,input [5:0] mCL3
+   ,input [1:0] winRank
+   ,input [1:0] calRank
+   ,input [1:0] mcwinRank
+   ,input       calDone
+);
+
+wire [5:0] mCL[0:3];
+assign mCL[0] = mCL0;
+assign mCL[1] = mCL1;
+assign mCL[2] = mCL2;
+assign mCL[3] = mCL3;
+
+// This section generates the Gate enable mc_clb2phy_rden.
+// This logic is used in calibration and during normal operation.
+// Case 4'b0110 defines nominal timing where the trained mCL value equals RL.
+// This logic supports mCL = RL - 3, to enable the Gate 3tCK earlier than nominal RL.
+// Early gate enable is needed in Gate training, during normal operation
+// if command delays are very low, and to compensate for extra Gate delay
+// in the XiPhy that is allocated for VT tracking.  The logic also supports Gate
+// enable 4tCK later than nominal to allow for command fly-by routing.
+// The Gate enable can be further delayed to allow for extra command pipeline delays.
+// The Gate enable supports RL as low as 7 with no extra command delays, but other
+// blocks have higher low limits, so the minimum RL without extra command delays
+// is expected to be RL=8.
+
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+(* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+reg                      [18:0]                        rsMask[0:7];
+
+function [18:0] rs2mask;
+   input [3:0] diff;
+   input       slot2;
+case ({diff, slot2})
+   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
+     default: rs2mask = 19'b000_0000_1000_0000_1111;
+endcase
+endfunction
+
+always @(posedge clk) begin: blk1
+   reg [3:0] rsNdx;
+   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
+end
+
+always @(*) if (rst) begin
+   rdEn_nxt = 'b0;
+end else begin
+   rdEn_nxt =   (rdEn >> 4)
+                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                : 'b0);
+end
+
+always @(posedge clk)
+   rdEn <= #TCQ rdEn_nxt;
+
+assign mc_clb2phy_rden = rdEn[3:0];
+
+///////////////////////////////////////////////////////////////////
+// This logic is used during normal, multi-rank operation only. Durring cal or single
+// rank operation this logic is bypassed and the output of this section is static.
+// This section generates the read rank signals used by the XiPhy to select per rank
+// cal values during read operations.
+
+integer tck_index;
+localparam rdcs_msb = RL + 8 + 4*EXTRA_CMD_DELAY;
+
+reg  [rdcs_msb :0] rdcs0;
+reg  [rdcs_msb :0] rdcs0_mc;
+reg  [rdcs_msb :0] rdcs1;
+reg  [rdcs_msb :0] rdcs1_mc;
+reg  [6:0]           rdcs_rdcas_lsb_slot0;
+reg                  calDone_dly;
+
+// Extend newest cs (MSB) and shift out the oldest (low 4 LSBs)
+wire [rdcs_msb :0] rdcs0_shift  = { { 4 { rdcs0[rdcs_msb] } }, rdcs0[ rdcs_msb : 4] };
+wire [rdcs_msb :0] rdcs1_shift  = { { 4 { rdcs1[rdcs_msb] } }, rdcs1[ rdcs_msb : 4] };
+
+// Create rdcs mask for the current rdcas
+wire [6:0]         rdcs_rdcas_lsb_slot0_nxt  = { 1'b0, mCL0 } + 4*EXTRA_CMD_DELAY - 7'd7;
+wire [rdcs_msb :0] rdcs_rdcas_mask_slot0     = { ( rdcs_msb + 1 ) { 1'b1 } } << rdcs_rdcas_lsb_slot0;
+wire [rdcs_msb :0] rdcs_rdcas_mask           = rdcs_rdcas_mask_slot0 << 2*mccasSlot2;
+
+// Merge the shifted rdcs and winRank based on the rdcs mask for the current rdcas
+always @(*) begin
+   for (tck_index = 0; tck_index <= rdcs_msb; tck_index = tck_index + 1) begin
+     rdcs0_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[0] : rdcs0_shift[tck_index];
+     rdcs1_mc[tck_index] = ( mcrdCAS & rdcs_rdcas_mask[tck_index] ) ? mcwinRank[1] : rdcs1_shift[tck_index];
+   end
+end
+
+// Select mc or cal rdcs
+wire [rdcs_msb :0] rdcs0_nxt = calDone_dly ? rdcs0_mc : { rdcs_msb+1 { calRank[0] } };
+wire [rdcs_msb :0] rdcs1_nxt = calDone_dly ? rdcs1_mc : { rdcs_msb+1 { calRank[1] } };
+
+// Final 4 bit rdcs output
+assign mc_clb2phy_rdcs0 = rdcs0[3:0] & ~{ 4 { RANKS == 1 } };
+assign mc_clb2phy_rdcs1 = rdcs1[3:0] & ~{ 4 { RANKS == 1 } };
+
+// Flops
+always @(posedge clk) begin
+  rdcs_rdcas_lsb_slot0 <= #TCQ rdcs_rdcas_lsb_slot0_nxt;
+  calDone_dly          <= #TCQ calDone;
+end
+
+// Reset flops
+always @(posedge clk) if (rst) begin
+  rdcs0 <= #TCQ '0;
+  rdcs1 <= #TCQ '0;
+end else begin
+  rdcs0 <= #TCQ rdcs0_nxt;
+  rdcs1 <= #TCQ rdcs1_nxt;
+end
+
+
+//synopsys translate_off
+
+`ifdef MEM_INTERNAL
+// Events - When asserted high in a test that passes all verification checks, these coverage
+//          properties indicate that a functional coverage event has been hit.
+// ---------------------------------------------------------------------------------------------
+
+// Minimum mCL in normal operation
+//wire   e_mc_rd_en_000 = ( ( mCL0 + 4*EXTRA_CMD_DELAY ) == 13 ) & calDone & ~( RANKS == 1 ) & rdCAS;
+//always @(posedge clk) mc_rd_en_000: if (~rst) cover property (e_mc_rd_en_000);
+
+
+// Asserts - When asserted high, an illegal condition has been detected and the test has failed.
+// ---------------------------------------------------------------------------------------------
+
+// Check for illegal rank switch in rdEn and rdcs.  rdEn gap must be at least 2tCK wide.  rdcs must be stable for 2tCK after rdEn de-assertion.
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdEn;
+reg                      [rdcs_msb :0]                 a_rdcs0_dly;
+reg                      [rdcs_msb :0]                 a_rdcs1_dly;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0;
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs0_nxt = { rdcs0, a_rdcs0_dly[3:0] };
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1;
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY :0] a_rdcs1_nxt = { rdcs1, a_rdcs1_dly[3:0] };
+wire                     [RL+12 + 4*EXTRA_CMD_DELAY -1 :0] a_rdEn_falling_edge = ~a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY :1] & a_rdEn[RL+12 + 4*EXTRA_CMD_DELAY -1 :0];
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold0_fail;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_hold1_fail;
+reg                      [RL+12 + 4*EXTRA_CMD_DELAY -3 :0] a_rdEn_gap_fail;
+always @(*) begin
+   for (tck_index = 0; tck_index < RL+12 + 4*EXTRA_CMD_DELAY -2; tck_index = tck_index + 1) begin
+     a_rdEn_hold0_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+1] ) | ( a_rdcs0[tck_index] ^ a_rdcs0[tck_index+2] ) );
+     a_rdEn_hold1_fail[tck_index] = calDone & a_rdEn_falling_edge[tck_index] & ( ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+1] ) | ( a_rdcs1[tck_index] ^ a_rdcs1[tck_index+2] ) );
+     a_rdEn_gap_fail[tck_index]   = calDone & a_rdEn_falling_edge[tck_index] & a_rdEn[tck_index+2];
+   end
+end
+always @(posedge clk) if (rst) begin
+         a_rdEn      <= #TCQ '0;
+         a_rdcs0_dly <= #TCQ '0;
+         a_rdcs1_dly <= #TCQ '0;
+         a_rdcs0     <= #TCQ '0;
+         a_rdcs1     <= #TCQ '0;
+end else begin
+         a_rdEn      <= #TCQ rdEn;
+         a_rdcs0_dly <= #TCQ rdcs0;
+         a_rdcs1_dly <= #TCQ rdcs1;
+         a_rdcs0     <= #TCQ a_rdcs0_nxt;
+         a_rdcs1     <= #TCQ a_rdcs1_nxt;
+end
+
+// rdcs0 not held for 2tCK after end of burst
+wire a_mc_rd_en_000_hld = calDone & ( | a_rdEn_hold0_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_000_hld);
+
+// rdcs1 not held for 2tCK after end of burst
+wire a_mc_rd_en_001_hld = calDone & ( | a_rdEn_hold1_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_001_hld);
+
+// rdEn not held low for 2tCK after end of burst
+wire a_mc_rd_en_002_hld = calDone & ( | a_rdEn_gap_fail ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_002_hld);
+
+// mCL0 is less than RL-3
+wire a_mc_rd_en_003_ovf = ( mCL0 < (RL - 3) ) & ( mCL0 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_003_ovf);
+
+// mCL1 is less than RL-3
+wire a_mc_rd_en_004_ovf = ( mCL1 < (RL - 3) ) & ( mCL1 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_004_ovf);
+
+// mCL2 is less than RL-3
+wire a_mc_rd_en_005_ovf = ( mCL2 < (RL - 3) ) & ( mCL2 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_005_ovf);
+
+// mCL3 is less than RL-3
+wire a_mc_rd_en_006_ovf = ( mCL3 < (RL - 3) ) & ( mCL3 > 6'b0 );
+always @(posedge clk) if (~rst) assert property (~a_mc_rd_en_006_ovf);
+
+
+`endif
+//synopsys translate_on
+
+endmodule
+
+
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej
new file mode 100644
index 0000000..dd5a9cf
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv.rej
@@ -0,0 +1,124 @@
+--- U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv
++++ /dev/null
+@@ -114,55 +114,86 @@
+ 
+ reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg                      [18:0]                        rsMask[0:7];
++reg                      [19:0]                        rsMask[0:15];
+ 
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+    input [3:0] diff;
+    input       slot2;
+-case ({diff, slot2})
+-   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+-   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+-   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+-   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++   input       slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++    6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++   6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++    6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++   6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++    6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++   6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++    6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+      default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+ 
+ always @(posedge clk) begin: blk1
+-   reg [3:0] rsNdx;
+-   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+-      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++   reg [4:0] rsNdx;
++   for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+ 
+ always @(*) if (rst) begin
+    rdEn_nxt = 'b0;
+ end else begin
+    rdEn_nxt =   (rdEn >> 4)
+-                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++                | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                 : 'b0);
+ end
+ 
diff --git a/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv.rej b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv.rej
new file mode 100644
index 0000000..1d2fee7
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv.rej
@@ -0,0 +1,31 @@
+--- U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv
++++ /dev/null
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register.  These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = (   ALL_WR_LATENCY       / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 =   ( ALL_WR_LATENCY     ) % 4;
++localparam OFFSET_CASSLOT1 =   ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 =   ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 =   ( ALL_WR_LATENCY + 3 ) % 4;
+ 
+ integer i;
+ 
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc.  mccasSlot2 is timing critical.
+ reg  [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone    ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric        = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric        = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++                         (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+ 
+ // tCK offset for mc.  mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++                         (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+ 
+ // Output enable shift register load value for cal and mc.  mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf,   calRank, OFFSET_CASSLOT2[1:0], 1'b1};
diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci
new file mode 100644
index 0000000..73efc2c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci
@@ -0,0 +1,329 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>pr_read_mem</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     5.931282 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">pr_read_mem.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">pr_read_mem.mif</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../../../../coe/pr_read.coe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pr_read_mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">64</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;val
+ue_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissio
+n&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_lef
+t&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
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+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml
new file mode 100644
index 0000000..b374295
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xml
@@ -0,0 +1,4182 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pr_read_mem</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_READ_WIDTH_A&apos;))-1">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rstb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arsize" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) =1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_SLAVE_TYPE&apos;)) = 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arburst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arburst" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) =1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_SLAVE_TYPE&apos;)) = 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">pr_read_mem.mif</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">pr_read_mem.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     5.931282 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f5f941aa</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pr_read_mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Single_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">16</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_f5f941aa" spirit:order="22">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_f5f941aa" spirit:order="25">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_f5f941aa" spirit:order="26">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Always_Enabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">../../../../coe/pr_read.coe</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_27c66b0d" spirit:order="3">Stand_Alone</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">no_mem_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9c3516e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci
new file mode 100644
index 0000000..ec19729
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci
@@ -0,0 +1,330 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
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+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>pr_ref_mem</spirit:instanceName>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pr_ref_mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
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+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;val
+ue_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissio
+n&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_lef
+t&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml
new file mode 100644
index 0000000..45667dd
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xml
@@ -0,0 +1,4185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pr_ref_mem</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">pr_ref_mem.mif</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">pr_ref_mem.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     5.931282 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0e6ad450</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+      <spirit:enumeration>2048</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pr_ref_mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Single_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_0e6ad450" spirit:order="22">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="25">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="26">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Always_Enabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">../../../../coe/pr_ref.coe</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
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+        <xilinx:parameterInfo>
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+  <spirit:vendorExtensions>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci b/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci
new file mode 100644
index 0000000..3710aa1
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci
@@ -0,0 +1,580 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">rdback_fifo</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Builtin_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">895</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">894</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Valid_Flag" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.asymmetric_port_width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;srst&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;din&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wr_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rd_en&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dout&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;full&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;empty&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;valid&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;prog_full&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;prog_empty&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wr_rst_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;rd_rst_busy&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;core_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,
+&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;FIFO_WRITE
+&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:fifo_write:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:fifo_write_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;FULL&quot;:{&quot;physical_name&quot;:&quot;full&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WR_DATA&quot;:{&quot;physical_name&quot;:&quot;din&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;511&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WR_EN&quot;:{&quot;physical_name&quot;:&quot;wr_en&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;FIFO_READ&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:fifo_read:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:fifo_read_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;EMPTY&quot;:{&quot;physical_name&quot;:&quot;empty&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RD_DATA&quot;:{&quot;physical_name&quot;:&quot;dout&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;RD_EN&quot;:{&quot;physical_name&quot;:&quot;rd_en&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_righ
+t&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xml b/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xml
new file mode 100644
index 0000000..397f9dc
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xml
@@ -0,0 +1,10791 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>rdback_fifo</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:bridge spirit:masterRef="M_AXI" spirit:opaque="false"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BD_ATTRIBUTE.TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI.BD_ATTRIBUTE.TYPE">INTERIOR</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=2))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>core_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>clock frequency</spirit:displayName>
+          <spirit:description>specify frequency of the clock connected to port clk</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.core_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_COMMON_CLOCK&apos;)) != 0)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>master_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_BUSIF">M_AXIS:M_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_aclk frequency</spirit:displayName>
+          <spirit:description>specify frequency of the clock connected to port m_aclk</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.master_aclk" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))>0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_COMMON_CLOCK&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>slave_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.ASSOCIATED_BUSIF">S_AXIS:S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_aclk frequency</spirit:displayName>
+          <spirit:description>specify frequency of the clock connected to port m_aclk</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.slave_aclk" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))>0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>write_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wr_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>write clock frequency</spirit:displayName>
+          <spirit:description>specify frequency of the clock connected to port wr_clk</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.write_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_COMMON_CLOCK&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>read_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rd_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>read clock frequency</spirit:displayName>
+          <spirit:description>specify frequency of the clock connected to port rd_clk</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.READ_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.read_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_COMMON_CLOCK&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>slave_aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SLAVE_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.slave_aresetn" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))>0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>FIFO_WRITE</spirit:name>
+      <spirit:displayName>FIFO_WRITE</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ALMOST_FULL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>almost_full</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FULL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>full</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>din</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wr_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.FIFO_WRITE" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>FIFO_READ</spirit:name>
+      <spirit:displayName>FIFO_READ</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ALMOST_EMPTY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>almost_empty</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EMPTY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>empty</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dout</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rd_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.FIFO_READ" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>backup</spirit:name>
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+        <spirit:name>injectsbiterr</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.injectsbiterr" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE&apos;)) = 3 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
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+        <spirit:name>sleep</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sleep" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;artixu&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;zynquplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;kintexuplus&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;zynquplusrfsoc&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplushbm&apos; or spirit:decode(id(&apos;MODELPARAM_VALUE.C_FAMILY&apos;)) = &apos;virtexuplus58g&apos;) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEMORY_TYPE&apos;)) = 4 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_POWER_SAVING_MODE&apos;))) = 1)">false</xilinx:isEnabled>
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+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dout" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0)">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>full</spirit:name>
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+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.full" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0)">true</xilinx:isEnabled>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>almost_full</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.almost_full" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ALMOST_FULL&apos;)) != 0)">false</xilinx:isEnabled>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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+        <spirit:name>overflow</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.overflow" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_OVERFLOW&apos;)) != 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) > 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW&apos;)) = 1)">false</xilinx:isEnabled>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        <spirit:name>almost_empty</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+      <spirit:port>
+        <spirit:name>valid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+      <spirit:port>
+        <spirit:name>underflow</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.underflow" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_UNDERFLOW&apos;)) != 0) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) > 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW&apos;)) = 1)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>data_count</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_DATA_COUNT_WIDTH&apos;)) - 1)">9</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.data_count" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_DATA_COUNT&apos;)) != 0)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>rd_data_count</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH&apos;))-1">10</spirit:left>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rd_data_count" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT&apos;)) != 0)">false</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>wr_data_count</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wr_data_count" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT&apos;)) != 0)">false</xilinx:isEnabled>
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+        <spirit:name>prog_full</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.prog_full" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_PROG_FULL_TYPE&apos;)) != 0)">true</xilinx:isEnabled>
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+        <spirit:name>prog_empty</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
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+        <spirit:name>sbiterr</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>dbiterr</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>STD_LOGIC</spirit:typeName>
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+              <spirit:typeName>STD_LOGIC</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.axis_underflow" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_UNDERFLOW&apos;)) != 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>axis_prog_full</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.axis_prog_full" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS&apos;)) != 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>axis_prog_empty</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.axis_prog_empty" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS&apos;)) != 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_COMMON_CLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SELECT_XPM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_COUNT_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DATA_COUNT_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_DEFAULT_VALUE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_DOUT_RST_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DOUT_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_WIDTH">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ENABLE_RLOCS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FULL_FLAGS_RST_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_ALMOST_EMPTY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_ALMOST_FULL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_BACKUP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_INT_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_MEMINIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_OVERFLOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_RD_DATA_COUNT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_RD_RST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_RST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RST">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_SRST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_UNDERFLOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_VALID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_VALID">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_WR_ACK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_WR_DATA_COUNT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_WR_RST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INIT_WR_PNTR_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MEMORY_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEMORY_TYPE">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_MIF_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OPTIMIZATION_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OVERFLOW_LOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PRELOAD_LATENCY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PRELOAD_REGS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx36</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_NEGATE_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">895</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_NEGATE_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">894</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RD_DATA_COUNT_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RD_DEPTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RD_DEPTH">2048</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RD_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RD_PNTR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_UNDERFLOW_LOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DOUT_RST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_EMBEDDED_REG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_PIPELINE_REG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_POWER_SAVING_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FIFO16_FLAGS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_FWFT_DATA_COUNT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_VALID_LOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_ACK_LOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DATA_COUNT_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_RESPONSE_LATENCY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MSGON_VAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ENABLE_RST_SYNC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SYNCHRONIZER_STAGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_WR_CHANNEL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_RD_CHANNEL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_SLAVE_CE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_MASTER_CE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ADD_NGC_CONSTRAINT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_COMMON_OVERFLOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_COMMON_UNDERFLOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_DEFAULT_SETTINGS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_LEN_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_LOCK_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_AWUSER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_WUSER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_BUSER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_ARUSER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXI_RUSER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_ARUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_AWUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_WUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_BUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_RUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TDATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TDEST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TUSER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TREADY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TLAST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TSTRB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_AXIS_TKEEP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TDATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TDEST_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TSTRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TKEEP_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WACH_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WDCH_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WRCH_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RACH_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RDCH_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIS_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_IMPLEMENTATION_TYPE_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_APPLICATION_TYPE_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_APPLICATION_TYPE_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_APPLICATION_TYPE_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_APPLICATION_TYPE_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_APPLICATION_TYPE_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_APPLICATION_TYPE_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE_WACH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE_WDCH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">512x72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE_WRCH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE_RACH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE_RDCH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">512x72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRIM_FIFO_TYPE_AXIS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USE_ECC_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ERROR_INJECTION_TYPE_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_DIN_WIDTH_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_DEPTH_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_WR_PNTR_WIDTH_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNTS_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNTS_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNTS_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNTS_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNTS_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_DATA_COUNTS_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_PROG_FLAGS_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_PROG_FLAGS_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_PROG_FLAGS_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_PROG_FLAGS_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_PROG_FLAGS_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_HAS_PROG_FLAGS_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_TYPE_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_FULL_THRESH_ASSERT_VAL_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_TYPE_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_REG_SLICE_MODE_WACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_REG_SLICE_MODE_WDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_REG_SLICE_MODE_WRCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_REG_SLICE_MODE_RACH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_REG_SLICE_MODE_RDCH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_REG_SLICE_MODE_AXIS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_087d29fa</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_165ed04b</spirit:name>
+      <spirit:enumeration>64</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_22f447d7</spirit:name>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_62eb4a48</spirit:name>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+      <spirit:enumeration>2048</spirit:enumeration>
+      <spirit:enumeration>4096</spirit:enumeration>
+      <spirit:enumeration>8192</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6727dfa6</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8af5a703</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_bf1143fa</spirit:name>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+      <spirit:enumeration>2048</spirit:enumeration>
+      <spirit:enumeration>4096</spirit:enumeration>
+      <spirit:enumeration>8192</spirit:enumeration>
+      <spirit:enumeration>16384</spirit:enumeration>
+      <spirit:enumeration>32768</spirit:enumeration>
+      <spirit:enumeration>65536</spirit:enumeration>
+      <spirit:enumeration>131072</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_08e28d5f</spirit:name>
+      <spirit:enumeration spirit:text="Active High">Active_High</spirit:enumeration>
+      <spirit:enumeration spirit:text="Active Low">Active_Low</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0d7cd34d</spirit:name>
+      <spirit:enumeration spirit:text="Common Clock Builtin FIFO">Common_Clock_Builtin_FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Common Clock Block RAM">Common_Clock_Block_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Common Clock Distributed RAM">Common_Clock_Distributed_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Common Clock Shift Register">Common_Clock_Shift_Register</spirit:enumeration>
+      <spirit:enumeration spirit:text="Independent Clocks Builtin FIFO">Independent_Clocks_Builtin_FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Independent Clocks Block RAM">Independent_Clocks_Block_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Independent Clocks Distributed RAM">Independent_Clocks_Distributed_RAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_19452de4</spirit:name>
+      <spirit:enumeration spirit:text="No Programmable Empty Threshold">No_Programmable_Empty_Threshold</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Programmable Empty Threshold Constant">Single_Programmable_Empty_Threshold_Constant</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3c123ec0</spirit:name>
+      <spirit:enumeration spirit:text="Common Clock Block RAM">Common_Clock_Block_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Common Clock Distributed RAM">Common_Clock_Distributed_RAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_40558afa</spirit:name>
+      <spirit:enumeration spirit:text="No Programmable Full Threshold">No_Programmable_Full_Threshold</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Programmable Full Threshold Constant">Single_Programmable_Full_Threshold_Constant</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_53eba4dc</spirit:name>
+      <spirit:enumeration spirit:text="Native">Native</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI Memory Mapped">AXI_MEMORY_MAPPED</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI Stream">AXI_STREAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_5548b404</spirit:name>
+      <spirit:enumeration spirit:text="Common Clock">Common_Clock</spirit:enumeration>
+      <spirit:enumeration spirit:text="Independent Clock">Independent_Clock</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_5f1451ad</spirit:name>
+      <spirit:enumeration spirit:text="Standard FIFO">Standard_FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="First Word Fall Through">First_Word_Fall_Through</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_619f3529</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI3">AXI3</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8334cf20</spirit:name>
+      <spirit:enumeration spirit:text="Data FIFO">Data_FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Packet FIFO">Packet_FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Latency Data FIFO">Low_Latency_Data_FIFO</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_9b232fe1</spirit:name>
+      <spirit:enumeration spirit:text="Slave Interface Clock Enable">Slave_Interface_Clock_Enable</spirit:enumeration>
+      <spirit:enumeration spirit:text="Master Interface Clock Enable">Master_Interface_Clock_Enable</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a8c5818a</spirit:name>
+      <spirit:enumeration spirit:text="Fully Registered">Fully_Registered</spirit:enumeration>
+      <spirit:enumeration spirit:text="Light Weight">Light_Weight</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b3e9d19b</spirit:name>
+      <spirit:enumeration spirit:text="FIFO">FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Register Slice">Register_Slice</spirit:enumeration>
+      <spirit:enumeration spirit:text="Pass Through Wire">Pass_Through_Wire</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_bec132cf</spirit:name>
+      <spirit:enumeration spirit:text="FIFO">FIFO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Register Slice">Register_Slice</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c94a1851</spirit:name>
+      <spirit:enumeration spirit:text="Hard ECC">Hard_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ccb14e2b</spirit:name>
+      <spirit:enumeration spirit:text="Read Write">READ_WRITE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read Only">READ_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Write Only">WRITE_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_eb98f74b</spirit:name>
+      <spirit:enumeration spirit:text="No Programmable Empty Threshold">No_Programmable_Empty_Threshold</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Programmable Empty Threshold Constant">Single_Programmable_Empty_Threshold_Constant</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Programmable Empty Threshold Input Port">Single_Programmable_Empty_Threshold_Input_Port</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ec2b452f</spirit:name>
+      <spirit:enumeration spirit:text="No Programmable Full Threshold">No_Programmable_Full_Threshold</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Programmable Full Threshold Constant">Single_Programmable_Full_Threshold_Constant</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Programmable Full Threshold Input Port">Single_Programmable_Full_Threshold_Input_Port</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ef3e87e1</spirit:name>
+      <spirit:enumeration spirit:text="Embedded Registers">Embedded_Reg</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f78383bc</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous Reset">Synchronous_Reset</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">rdback_fifo</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fifo_Implementation</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Fifo_Implementation" spirit:choiceRef="choice_pairs_0d7cd34d" spirit:order="2">Common_Clock_Builtin_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fifo_Implementation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>synchronization_stages</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.synchronization_stages" spirit:order="4" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.synchronization_stages">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>synchronization_stages_axi</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.synchronization_stages_axi" spirit:order="50" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.synchronization_stages_axi">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERFACE_TYPE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_TYPE" spirit:choiceRef="choice_pairs_53eba4dc" spirit:order="3">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.INTERFACE_TYPE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Performance_Options</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Performance_Options" spirit:choiceRef="choice_pairs_5f1451ad" spirit:order="5">First_Word_Fall_Through</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Performance_Options">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>asymmetric_port_width</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.asymmetric_port_width" spirit:order="10">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.asymmetric_port_width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Data_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Data_Width" spirit:order="6" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">512</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Data_Width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth" spirit:choiceRef="choice_list_62eb4a48" spirit:order="7">1024</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Data_Width</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Data_Width" spirit:choiceRef="choice_list_22f447d7" spirit:order="8">256</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Data_Width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Depth</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Depth" spirit:order="9" spirit:minimum="16" spirit:maximum="33554432" spirit:rangeType="long">2048</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Depth">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC" spirit:order="10">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Embedded_Registers</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Embedded_Registers" spirit:order="11">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Embedded_Registers">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Pin" spirit:order="12">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Reset_Synchronization</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Reset_Synchronization" spirit:order="13">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Reset_Synchronization">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_f78383bc" spirit:order="14">Synchronous_Reset</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Flags_Reset_Value</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Flags_Reset_Value" spirit:choiceRef="choice_list_8af5a703" spirit:order="15">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Flags_Reset_Value">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Dout_Reset</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Dout_Reset" spirit:order="16">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Dout_Reset">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Dout_Reset_Value</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Dout_Reset_Value" spirit:order="17">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Dout_Reset_Value">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dynamic_power_saving</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.dynamic_power_saving" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.dynamic_power_saving">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Almost_Full_Flag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Almost_Full_Flag" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Almost_Full_Flag">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Almost_Empty_Flag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Almost_Empty_Flag" spirit:order="19">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Almost_Empty_Flag">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Valid_Flag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Valid_Flag" spirit:order="20">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Valid_Flag">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Valid_Sense</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Valid_Sense" spirit:choiceRef="choice_pairs_08e28d5f" spirit:order="21">Active_High</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Valid_Sense">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Underflow_Flag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Underflow_Flag" spirit:order="22">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Underflow_Flag">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Underflow_Sense</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Underflow_Sense" spirit:choiceRef="choice_pairs_08e28d5f" spirit:order="23">Active_High</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Underflow_Sense">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Acknowledge_Flag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Acknowledge_Flag" spirit:order="24">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Acknowledge_Flag">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Acknowledge_Sense</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Acknowledge_Sense" spirit:choiceRef="choice_pairs_08e28d5f" spirit:order="25">Active_High</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Acknowledge_Sense">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Overflow_Flag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Overflow_Flag" spirit:order="26">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Overflow_Flag">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Overflow_Sense</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Overflow_Sense" spirit:choiceRef="choice_pairs_08e28d5f" spirit:order="27">Active_High</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Overflow_Sense">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error" spirit:order="28">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecc_pipeline_reg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ecc_pipeline_reg" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecc_pipeline_reg">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Extra_Logic</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Extra_Logic" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Extra_Logic">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Data_Count</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Data_Count" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Data_Count">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Data_Count_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Data_Count_Width" spirit:order="32" spirit:minimum="1" spirit:maximum="10" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Data_Count_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Data_Count</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Data_Count" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Data_Count">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Data_Count_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Data_Count_Width" spirit:order="34" spirit:minimum="1" spirit:maximum="10" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Data_Count_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Data_Count</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Data_Count" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Data_Count">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Data_Count_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Data_Count_Width" spirit:order="36" spirit:minimum="1" spirit:maximum="11" spirit:rangeType="long">11</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Data_Count_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Timing_Violations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Timing_Violations" spirit:order="37">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Timing_Violations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Clock_Frequency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Clock_Frequency" spirit:order="38" spirit:minimum="1" spirit:maximum="1000" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Clock_Frequency">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Clock_Frequency</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Clock_Frequency" spirit:order="39" spirit:minimum="1" spirit:maximum="1000" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Clock_Frequency">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type" spirit:choiceRef="choice_pairs_40558afa" spirit:order="40">Single_Programmable_Full_Threshold_Constant</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value" spirit:order="41" spirit:minimum="11" spirit:maximum="1021" spirit:rangeType="long">895</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Negate_Value</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Negate_Value" spirit:order="42" spirit:minimum="10" spirit:maximum="894" spirit:rangeType="long">894</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Negate_Value">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type" spirit:choiceRef="choice_pairs_19452de4" spirit:order="43">Single_Programmable_Empty_Threshold_Constant</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value" spirit:order="44" spirit:minimum="4" spirit:maximum="2046" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Negate_Value</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Negate_Value" spirit:order="45" spirit:minimum="5" spirit:maximum="2048" spirit:rangeType="long">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Negate_Value">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PROTOCOL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROTOCOL" spirit:choiceRef="choice_pairs_619f3529" spirit:order="46">AXI4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PROTOCOL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Clock_Type_AXI</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Clock_Type_AXI" spirit:choiceRef="choice_pairs_5548b404" spirit:order="47">Common_Clock</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Clock_Type_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>HAS_ACLKEN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_ACLKEN" spirit:order="48">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.HAS_ACLKEN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Clock_Enable_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Clock_Enable_Type" spirit:choiceRef="choice_pairs_9b232fe1" spirit:order="49">Slave_Interface_Clock_Enable</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Clock_Enable_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_ccb14e2b" spirit:order="51">READ_WRITE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_WRITE_MODE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="53" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ID_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDRESS_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDRESS_WIDTH" spirit:order="54" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ADDRESS_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DATA_WIDTH</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:choiceRef="choice_list_165ed04b" spirit:order="55">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AWUSER_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AWUSER_Width" spirit:order="57" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AWUSER_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>WUSER_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WUSER_Width" spirit:order="59" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.WUSER_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BUSER_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUSER_Width" spirit:order="61" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.BUSER_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ARUSER_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ARUSER_Width" spirit:order="63" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ARUSER_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RUSER_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RUSER_Width" spirit:order="65" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RUSER_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TDATA_NUM_BYTES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TDATA_NUM_BYTES" spirit:choiceRef="choice_list_087d29fa" spirit:order="67">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TDATA_NUM_BYTES">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TID_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TID_WIDTH" spirit:order="69" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TID_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TDEST_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TDEST_WIDTH" spirit:order="71" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TDEST_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TUSER_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TUSER_WIDTH" spirit:order="73" spirit:minimum="0" spirit:maximum="4096" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TUSER_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_TREADY</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_TREADY" spirit:order="74">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_TREADY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_TLAST</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_TLAST" spirit:order="75">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_TLAST">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>HAS_TSTRB</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_TSTRB" spirit:order="76">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.HAS_TSTRB">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TSTRB_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TSTRB_WIDTH" spirit:order="77" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TSTRB_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>HAS_TKEEP</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_TKEEP" spirit:order="78">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.HAS_TKEEP">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TKEEP_WIDTH</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TKEEP_WIDTH" spirit:order="79" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.TKEEP_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>wach_type</spirit:name>
+      <spirit:displayName>Configuration Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.wach_type" spirit:choiceRef="choice_pairs_b3e9d19b" spirit:order="80">FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.wach_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Implementation_wach</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Implementation_wach" spirit:choiceRef="choice_pairs_3c123ec0" spirit:order="81">Common_Clock_Block_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Implementation_wach">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Application_Type_wach</spirit:name>
+      <spirit:displayName>FIFO Application Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Application_Type_wach" spirit:choiceRef="choice_pairs_8334cf20" spirit:order="82">Data_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Application_Type_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC_wach</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_wach" spirit:order="83">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error_wach</spirit:name>
+      <spirit:displayName>Single Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error_wach" spirit:order="84">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error_wach</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error_wach" spirit:order="85">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth_wach</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth_wach" spirit:choiceRef="choice_list_bf1143fa" spirit:order="86">16</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth_wach">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Data_Counts_wach</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Data_Counts_wach" spirit:order="88">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Data_Counts_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type_wach</spirit:name>
+      <spirit:displayName>Deassert READY When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type_wach" spirit:choiceRef="choice_pairs_ec2b452f" spirit:order="89">No_Programmable_Full_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value_wach</spirit:name>
+      <spirit:displayName>Full Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value_wach" spirit:order="90" spirit:minimum="6" spirit:maximum="1023" spirit:rangeType="long">1023</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type_wach</spirit:name>
+      <spirit:displayName>Deassert VALID When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type_wach" spirit:choiceRef="choice_pairs_eb98f74b" spirit:order="91">No_Programmable_Empty_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value_wach</spirit:name>
+      <spirit:displayName>Empty Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" spirit:order="92" spirit:minimum="4" spirit:maximum="1022" spirit:rangeType="long">1022</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value_wach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>wdch_type</spirit:name>
+      <spirit:displayName>Configuration Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.wdch_type" spirit:choiceRef="choice_pairs_b3e9d19b" spirit:order="93">FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.wdch_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Implementation_wdch</spirit:name>
+      <spirit:displayName>FIFO Implementation Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Implementation_wdch" spirit:choiceRef="choice_pairs_3c123ec0" spirit:order="94">Common_Clock_Block_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Implementation_wdch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Application_Type_wdch</spirit:name>
+      <spirit:displayName>FIFO Application Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Application_Type_wdch" spirit:choiceRef="choice_pairs_8334cf20" spirit:order="95">Data_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Application_Type_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC_wdch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_wdch" spirit:order="96">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error_wdch</spirit:name>
+      <spirit:displayName>Single Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error_wdch" spirit:order="97">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error_wdch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error_wdch" spirit:order="98">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth_wdch</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth_wdch" spirit:choiceRef="choice_list_bf1143fa" spirit:order="99">1024</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth_wdch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Data_Counts_wdch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Data_Counts_wdch" spirit:order="101">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Data_Counts_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type_wdch</spirit:name>
+      <spirit:displayName>Deassert READY When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type_wdch" spirit:choiceRef="choice_pairs_ec2b452f" spirit:order="102">No_Programmable_Full_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value_wdch</spirit:name>
+      <spirit:displayName>Full Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value_wdch" spirit:order="103" spirit:minimum="6" spirit:maximum="1023" spirit:rangeType="long">1023</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type_wdch</spirit:name>
+      <spirit:displayName>Deassert VALID When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type_wdch" spirit:choiceRef="choice_pairs_eb98f74b" spirit:order="104">No_Programmable_Empty_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value_wdch</spirit:name>
+      <spirit:displayName>Empty Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" spirit:order="105" spirit:minimum="4" spirit:maximum="1022" spirit:rangeType="long">1022</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value_wdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>wrch_type</spirit:name>
+      <spirit:displayName>Configuration Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.wrch_type" spirit:choiceRef="choice_pairs_b3e9d19b" spirit:order="106">FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.wrch_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Implementation_wrch</spirit:name>
+      <spirit:displayName>FIFO Implementation Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Implementation_wrch" spirit:choiceRef="choice_pairs_3c123ec0" spirit:order="107">Common_Clock_Block_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Implementation_wrch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Application_Type_wrch</spirit:name>
+      <spirit:displayName>FIFO Application Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Application_Type_wrch" spirit:choiceRef="choice_pairs_8334cf20" spirit:order="108">Data_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Application_Type_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC_wrch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_wrch" spirit:order="109">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error_wrch</spirit:name>
+      <spirit:displayName>Single Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error_wrch" spirit:order="110">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error_wrch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error_wrch" spirit:order="111">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth_wrch</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth_wrch" spirit:choiceRef="choice_list_bf1143fa" spirit:order="112">16</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth_wrch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Data_Counts_wrch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Data_Counts_wrch" spirit:order="114">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Data_Counts_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type_wrch</spirit:name>
+      <spirit:displayName>Deassert READY When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type_wrch" spirit:choiceRef="choice_pairs_ec2b452f" spirit:order="115">No_Programmable_Full_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value_wrch</spirit:name>
+      <spirit:displayName>Full Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" spirit:order="116" spirit:minimum="6" spirit:maximum="1023" spirit:rangeType="long">1023</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type_wrch</spirit:name>
+      <spirit:displayName>Deassert VALID When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type_wrch" spirit:choiceRef="choice_pairs_eb98f74b" spirit:order="117">No_Programmable_Empty_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value_wrch</spirit:name>
+      <spirit:displayName>Empty Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" spirit:order="118" spirit:minimum="4" spirit:maximum="1022" spirit:rangeType="long">1022</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value_wrch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rach_type</spirit:name>
+      <spirit:displayName>Configuration Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.rach_type" spirit:choiceRef="choice_pairs_b3e9d19b" spirit:order="119">FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.rach_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Implementation_rach</spirit:name>
+      <spirit:displayName>FIFO Implementation Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Implementation_rach" spirit:choiceRef="choice_pairs_3c123ec0" spirit:order="120">Common_Clock_Block_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Implementation_rach">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Application_Type_rach</spirit:name>
+      <spirit:displayName>FIFO Application Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Application_Type_rach" spirit:choiceRef="choice_pairs_8334cf20" spirit:order="121">Data_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Application_Type_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC_rach</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_rach" spirit:order="122">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error_rach</spirit:name>
+      <spirit:displayName>Single Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error_rach" spirit:order="123">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error_rach</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error_rach" spirit:order="124">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth_rach</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth_rach" spirit:choiceRef="choice_list_bf1143fa" spirit:order="125">16</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth_rach">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Data_Counts_rach</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Data_Counts_rach" spirit:order="127">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Data_Counts_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type_rach</spirit:name>
+      <spirit:displayName>Deassert READY When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type_rach" spirit:choiceRef="choice_pairs_ec2b452f" spirit:order="128">No_Programmable_Full_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value_rach</spirit:name>
+      <spirit:displayName>Full Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value_rach" spirit:order="129" spirit:minimum="6" spirit:maximum="1023" spirit:rangeType="long">1023</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type_rach</spirit:name>
+      <spirit:displayName>Deassert VALID When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type_rach" spirit:choiceRef="choice_pairs_eb98f74b" spirit:order="130">No_Programmable_Empty_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value_rach</spirit:name>
+      <spirit:displayName>Empty Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" spirit:order="131" spirit:minimum="4" spirit:maximum="1022" spirit:rangeType="long">1022</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value_rach">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rdch_type</spirit:name>
+      <spirit:displayName>Configuration Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.rdch_type" spirit:choiceRef="choice_pairs_b3e9d19b" spirit:order="132">FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.rdch_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Implementation_rdch</spirit:name>
+      <spirit:displayName>FIFO Implementation Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Implementation_rdch" spirit:choiceRef="choice_pairs_3c123ec0" spirit:order="133">Common_Clock_Block_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Implementation_rdch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Application_Type_rdch</spirit:name>
+      <spirit:displayName>FIFO Application Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Application_Type_rdch" spirit:choiceRef="choice_pairs_8334cf20" spirit:order="134">Data_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Application_Type_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC_rdch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_rdch" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error_rdch</spirit:name>
+      <spirit:displayName>Single Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error_rdch" spirit:order="136">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error_rdch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error_rdch" spirit:order="137">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth_rdch</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth_rdch" spirit:choiceRef="choice_list_bf1143fa" spirit:order="138">1024</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth_rdch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Data_Counts_rdch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Data_Counts_rdch" spirit:order="140">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Data_Counts_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type_rdch</spirit:name>
+      <spirit:displayName>Deassert READY When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type_rdch" spirit:choiceRef="choice_pairs_ec2b452f" spirit:order="141">No_Programmable_Full_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value_rdch</spirit:name>
+      <spirit:displayName>Full Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value_rdch" spirit:order="142" spirit:minimum="6" spirit:maximum="1023" spirit:rangeType="long">1023</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type_rdch</spirit:name>
+      <spirit:displayName>Deassert VALID When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type_rdch" spirit:choiceRef="choice_pairs_eb98f74b" spirit:order="143">No_Programmable_Empty_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value_rdch</spirit:name>
+      <spirit:displayName>Empty Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" spirit:order="144" spirit:minimum="4" spirit:maximum="1022" spirit:rangeType="long">1022</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value_rdch">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axis_type</spirit:name>
+      <spirit:displayName>Configuration Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axis_type" spirit:choiceRef="choice_pairs_bec132cf" spirit:order="145">FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.axis_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Implementation_axis</spirit:name>
+      <spirit:displayName>FIFO Implementation Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Implementation_axis" spirit:choiceRef="choice_pairs_3c123ec0" spirit:order="146">Common_Clock_Block_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Implementation_axis">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_Application_Type_axis</spirit:name>
+      <spirit:displayName>FIFO Application Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_Application_Type_axis" spirit:choiceRef="choice_pairs_8334cf20" spirit:order="147">Data_FIFO</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_Application_Type_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_ECC_axis</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_axis" spirit:order="148">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_ECC_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Sbit_Error_axis</spirit:name>
+      <spirit:displayName>Single Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Sbit_Error_axis" spirit:order="149">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Sbit_Error_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Inject_Dbit_Error_axis</spirit:name>
+      <spirit:displayName>Double Bit Error Injection</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Inject_Dbit_Error_axis" spirit:order="150">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Inject_Dbit_Error_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Input_Depth_axis</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Input_Depth_axis" spirit:choiceRef="choice_list_bf1143fa" spirit:order="151">1024</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Input_Depth_axis">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_Data_Counts_axis</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Data_Counts_axis" spirit:order="153">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Data_Counts_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Full_Type_axis</spirit:name>
+      <spirit:displayName>Deassert READY When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Full_Type_axis" spirit:choiceRef="choice_pairs_ec2b452f" spirit:order="154">No_Programmable_Full_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Full_Type_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Full_Threshold_Assert_Value_axis</spirit:name>
+      <spirit:displayName>Full Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Full_Threshold_Assert_Value_axis" spirit:order="155" spirit:minimum="6" spirit:maximum="1023" spirit:rangeType="long">1023</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Full_Threshold_Assert_Value_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Programmable_Empty_Type_axis</spirit:name>
+      <spirit:displayName>Deassert VALID When</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Programmable_Empty_Type_axis" spirit:choiceRef="choice_pairs_eb98f74b" spirit:order="156">No_Programmable_Empty_Threshold</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Programmable_Empty_Type_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Empty_Threshold_Assert_Value_axis</spirit:name>
+      <spirit:displayName>Empty Threshold Assert Value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" spirit:order="157" spirit:minimum="4" spirit:maximum="1022" spirit:rangeType="long">1022</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Empty_Threshold_Assert_Value_axis">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_Slice_Mode_wach</spirit:name>
+      <spirit:displayName>Register Slice Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Register_Slice_Mode_wach" spirit:choiceRef="choice_pairs_a8c5818a" spirit:order="158">Fully_Registered</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_Slice_Mode_wach">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_Slice_Mode_wdch</spirit:name>
+      <spirit:displayName>Register Slice Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Register_Slice_Mode_wdch" spirit:choiceRef="choice_pairs_a8c5818a" spirit:order="159">Fully_Registered</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_Slice_Mode_wdch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_Slice_Mode_wrch</spirit:name>
+      <spirit:displayName>Register Slice Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Register_Slice_Mode_wrch" spirit:choiceRef="choice_pairs_a8c5818a" spirit:order="160">Fully_Registered</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_Slice_Mode_wrch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_Slice_Mode_rach</spirit:name>
+      <spirit:displayName>Register Slice Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Register_Slice_Mode_rach" spirit:choiceRef="choice_pairs_a8c5818a" spirit:order="161">Fully_Registered</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_Slice_Mode_rach">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_Slice_Mode_rdch</spirit:name>
+      <spirit:displayName>Register Slice Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Register_Slice_Mode_rdch" spirit:choiceRef="choice_pairs_a8c5818a" spirit:order="162">Fully_Registered</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_Slice_Mode_rdch">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_Slice_Mode_axis</spirit:name>
+      <spirit:displayName>Register Slice Options</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Register_Slice_Mode_axis" spirit:choiceRef="choice_pairs_a8c5818a" spirit:order="163">Fully_Registered</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_Slice_Mode_axis">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Underflow_Flag_AXI</spirit:name>
+      <spirit:displayName>Underflow Flag</spirit:displayName>
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+      <spirit:vendorExtensions>
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+      <spirit:name>Underflow_Sense_AXI</spirit:name>
+      <spirit:displayName>Underflow (Read Error)</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Underflow_Sense_AXI" spirit:choiceRef="choice_pairs_08e28d5f" spirit:order="165">Active_High</spirit:value>
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+      <spirit:name>Overflow_Flag_AXI</spirit:name>
+      <spirit:displayName>Overflow Flag</spirit:displayName>
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+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Overflow_Sense_AXI</spirit:name>
+      <spirit:displayName>Overflow (Write Error)</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Overflow_Sense_AXI" spirit:choiceRef="choice_pairs_08e28d5f" spirit:order="167">Active_High</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Timing_Violations_AXI">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+          <xilinx:enablement>
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+      <spirit:name>Enable_Common_Underflow</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Common_Underflow" spirit:order="170">false</spirit:value>
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+      <spirit:name>enable_read_pointer_increment_by2</spirit:name>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.enable_low_latency">false</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>use_dout_register</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.use_dout_register" spirit:order="176">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_dout_register">false</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>Master_interface_Clock_enable_memory_mapped</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped" spirit:order="177">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+      <spirit:name>Slave_interface_Clock_enable_memory_mapped</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped" spirit:order="178">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
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+          </xilinx:enablement>
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+      <spirit:name>Output_Register_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Register_Type" spirit:choiceRef="choice_pairs_ef3e87e1" spirit:order="179">Embedded_Reg</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Register_Type">true</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>Enable_Safety_Circuit</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_Safety_Circuit" spirit:order="180">false</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_Safety_Circuit">false</xilinx:isEnabled>
+          </xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Enable_ECC_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_ECC_Type" spirit:choiceRef="choice_pairs_c94a1851" spirit:order="181">Hard_ECC</spirit:value>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Valid_Flag" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.asymmetric_port_width" xilinx:valueSource="user"/>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xci b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xci
new file mode 100644
index 0000000..44575ea
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xci
@@ -0,0 +1,327 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:library>xci</spirit:library>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;9&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;val
+ue_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissio
+n&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;9&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;9&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_lef
+t&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xml b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xml
new file mode 100644
index 0000000..b489504
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/scratchpad/scratchpad.xml
@@ -0,0 +1,4182 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>scratchpad</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>MEM_WIDTH</spirit:name>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <xilinx:enablement>
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+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
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+          <spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
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+            <spirit:name>EN</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
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+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
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+        <spirit:portMap>
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+            <spirit:name>WE</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
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+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
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+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">false</xilinx:isEnabled>
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+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
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+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
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+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">9</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
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+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
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+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_READ_WIDTH_A&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+        <spirit:name>clkb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        <spirit:name>rstb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rstb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+        <spirit:name>enb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.enb" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and(spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENB&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arburst" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) =1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_SLAVE_TYPE&apos;)) = 0))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_ID_WIDTH&apos;))-1">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_AXI_ID&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_B&apos;))-1">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">9</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">scratchpad.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">1024</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     2.119075 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_784e1e2a</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">scratchpad</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Single_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">1024</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_784e1e2a" spirit:order="22">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_784e1e2a" spirit:order="25">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_784e1e2a" spirit:order="26">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Always_Enabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_27c66b0d" spirit:order="3">Stand_Alone</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">no_mem_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9c3516e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci
new file mode 100644
index 0000000..083af2b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xci
@@ -0,0 +1,1433 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xdma_pcie4_ip_gt</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard_ultrascale" spirit:version="1.7"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CPLL_VCO_FREQUENCY">2500.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_COMMON_USRCLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FORCE_COMMONS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FREERUN_FREQUENCY">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_REV">67</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_TYPE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_CPLL_CAL">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCATE_IN_SYSTEM_IBERT_CORE">2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_USRCLK_FREQUENCY">400.0000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_QPLL_REFCLK_FREQUENCY">257.8125</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TOTAL_NUM_COMMONS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TOTAL_NUM_COMMONS_EXAMPLE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_ENABLE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_SOURCE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_VAL">400</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_BUFFER_BYPASS_INSTANCE_CTRL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_BUFFER_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_DATA_ENCODING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_ENABLE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_INT_DATA_WIDTH">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_LINE_RATE">8</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_OUTCLK_BUFG_GT_DIV">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_OUTCLK_FREQUENCY">400.0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_OUTCLK_SOURCE">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_PLL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_REFCLK_FREQUENCY">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_CONTENTS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_INSTANCE_CTRL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_SOURCE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_DATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USRCLK2_FREQUENCY">400.0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USRCLK_FREQUENCY">400.0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_GTPOWERGOOD_DELAY_EN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE">X1Y35 X1Y34 X1Y33 X1Y32 X1Y31 X1Y30 X1Y29 X1Y28</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xdma_pcie4_ip_gt</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_LOC_XDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_USRCLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_OPTIONAL_PORTS">txpdelecidlemode_in txprgdivresetdone_out rcalenb_in txpisopd_in rxratemode_in dmonfiforeset_in dmonitorclk_in dmonitorout_out txdlysresetdone_out rxdlysresetdone_out rxphaligndone_out rxsyncdone_out eyescanreset_in txdiffctrl_in rxtermination_in cpllpd_in drpaddr_common_in drpclk_common_in drpdi_common_in drpen_common_in drpwe_common_in loopback_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in qpll0pd_in qpll1pd_in rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpc
+sreset_in rxpd_in rxpmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcie
+usergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe
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+ rxcdrfreqreset_in resetovrd_in txoutclksel_in cplllock_out gtrefclk0_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREERUN_FREQUENCY">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DIRECTION">BOTH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_REV">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_TYPE">GTY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_CPLL_CAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_CHANNEL_COLUMN_LOC_MAX">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_CHANNEL_SITES_UPDATED">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_GT_PRIM_TYPE">gtye4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_NUM_COMMONS_CORE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_NUM_COMMONS_EXAMPLE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGBYPASSB_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGMONITORENB_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGPDB_IN">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTDIV_OUT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CDRSTEPSX_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CFGRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CLKRSVD0_IN">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCK_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLPD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONFIFORESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONITORCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONITOROUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPADDR_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDI_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDO_OUT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPWE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANMODE_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_FREQOS_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTGREFCLK0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTGREFCLK1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTGREFCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHRXN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHRXP_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHTXN_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHTXP_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK00_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK01_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK10_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK11_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRESETSEL_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRSVD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRXRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTTXRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYRXN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYRXP_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYTXN_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYTXP_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_INCPCTRL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_LOOPBACK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_LOOPRSVD_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCSRSVDIN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PHYSTATUS_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVD0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVD1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVDIN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_POWERPRESENT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0CLK_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0PD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0RESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1CLK_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1PD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1RESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD1_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD2_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD3_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD4_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RCALENB_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RESETOVRD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RSTCLKENTX_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RX8B10BEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBUFRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDI_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDO_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCKCALRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCKCALSTART_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMMADET_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL0_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL1_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL2_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL3_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDATAVALID_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDATA_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVSEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXELECIDLE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXEQTRAINING_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXHEADER_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLATCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXMONITORSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOOBRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSCALRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTCFG_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLK_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPCSRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYPD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPMARESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPOLARITY_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSERR_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXQPIEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXQPISENN_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXQPISENP_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRATEDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRATEMODE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRATE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRESETDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIDE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPPMA_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSTATUS_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCIN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCMODE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXTERMINATION_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXUSERRDY_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXUSRCLK2_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXUSRCLK_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXVALID_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0DATA_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0RESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0WIDTH_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1DATA_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1RESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1WIDTH_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONGPI_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONGPO_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONPOWERUP_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONRESET_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TSTIN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TX8B10BEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMINIT_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMSAS_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMWAKE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCTRL0_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCTRL1_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCTRL2_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDATA_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDCCDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDCCRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDEEMPH_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDETECTRX_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDIFFPD_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYHOLD_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYSRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXELECIDLE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXELFORCESTART_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXHEADER_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXINHIBIT_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLATCLK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMARGIN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXONESZEROS_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLK_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPCSRESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHALIGN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHDLYPD_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHINIT_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMPD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPISOPD_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPMARESET_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPOLARITY_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRBSSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRECURSOR_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPISENN_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPISENP_OUT">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRATEDONE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRATEMODE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRATE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRESETDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSEQUENCE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSWING_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCIN_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCMODE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXUSERRDY_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXUSRCLK2_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXUSRCLK_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDADDR_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDEN_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDI_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDO_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDRDY_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDWE_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBENABLE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBGPI_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBINTR_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBIOLMBRST_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMBRST_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMREGEN_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTCK_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDI_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDO_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBTXUART_OUT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">23</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_USAGE_UPDATED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PRESET">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_COMMA_PRESET_UPDATE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_USRCLK_FREQUENCY">400.0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TOTAL_NUM_CHANNELS">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TOTAL_NUM_COMMONS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TX_USRCLK_FREQUENCY">400.0000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_UPDATE_IP_SYMBOL_drpclk_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_COMMON">CORE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_IN_SYSTEM_IBERT_CORE">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_RESET_CONTROLLER">EXAMPLE_DESIGN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_RX_BUFFER_BYPASS_CONTROLLER">CORE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_RX_USER_CLOCKING">EXAMPLE_DESIGN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_TX_BUFFER_BYPASS_CONTROLLER">EXAMPLE_DESIGN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_TX_USER_CLOCKING">EXAMPLE_DESIGN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_USER_DATA_WIDTH_SIZING">EXAMPLE_DESIGN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OOB_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ORGANIZE_PORTS_BY">NAME</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_64BIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_CORECLK_FREQ">500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_ENABLE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_GEN4_EIOS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_USERCLK_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRESET">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_SEQUENCE_INTERVAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_BYPASS_MODE">MULTI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_MODE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_REFCLK_SOURCE"/>
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+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.cpllpd_in">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.cpllreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.dmonfiforeset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.dmonitorclk_in">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.drpaddr_common_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.drpaddr_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.drpclk_common_in">true</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtpowergood_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk00_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk01_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk0_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk10_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk11_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclkmonitor_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtresetsel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrsvd_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrxreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrxresetsel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk00_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk01_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk0_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk10_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk11_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gttxreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gttxresetsel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_done_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_error_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_reset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_start_user_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_done_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_error_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_reset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_start_user_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gthe3_cpll_cal_bufg_ce_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gthe3_cpll_cal_cnt_tol_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gthe3_cpll_cal_txoutclk_period_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gthe4_cpll_cal_bufg_ce_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gthe4_cpll_cal_cnt_tol_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gthe4_cpll_cal_txoutclk_period_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gtye4_cpll_cal_bufg_ce_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gtye4_cpll_cal_cnt_tol_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_gtye4_cpll_cal_txoutclk_period_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_all_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_clk_freerun_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_qpll0lock_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_qpll0reset_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_qpll1lock_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_qpll1reset_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_rx_cdr_stable_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_rx_datapath_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_rx_done_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_rx_done_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_rx_pll_and_datapath_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_tx_datapath_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_tx_done_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_tx_done_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_reset_tx_pll_and_datapath_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_rx_active_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_rx_active_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_rx_reset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_rx_srcclk_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_rx_usrclk2_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_rx_usrclk_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_tx_active_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_tx_active_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_tx_reset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_tx_srcclk_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_tx_usrclk2_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userclk_tx_usrclk_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userdata_rx_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_userdata_tx_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtyrxn_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtyrxp_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtytxn_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtytxp_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.incpctrl_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.loopback_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.looprsvd_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.lpbkrxtxseren_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.lpbktxrxseren_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcieeqrxeqadaptdone_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierategen3_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierateidle_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierateqpll0_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierateqpll1_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierateqpllpd_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierateqpllreset_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcierstidle_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pciersttxsyncstart_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pciesynctxsyncdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcieusergen3rdy_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcieuserphystatusrst_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcieuserratedone_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcieuserratestart_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcsrsvdin2_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcsrsvdin_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pcsrsvdout_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.phystatus_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pinrsrvdas_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pmarsvd0_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pmarsvd1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pmarsvdin_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pmarsvdout0_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.pmarsvdout1_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.powerpresent_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0clk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0clkrsvd0_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0clkrsvd1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0fbclklost_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0fbdiv_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0freqlock_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0lock_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0lockdetclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0locken_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0outclk_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0outrefclk_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0pd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0refclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0refclklost_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0refclksel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll0reset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1clk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1clkrsvd0_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1clkrsvd1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1fbclklost_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1fbdiv_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1freqlock_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1lock_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1lockdetclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1locken_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1outclk_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1outrefclk_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1pd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1refclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1refclklost_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1refclksel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpll1reset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qplldmonitor0_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qplldmonitor1_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpllrsvd1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpllrsvd2_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpllrsvd3_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.qpllrsvd4_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rcalenb_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.refclkoutmonitor0_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.refclkoutmonitor1_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.resetexception_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.resetovrd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rstclkentx_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rx8b10ben_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxafecfoken_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxbufreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxbufstatus_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxbyteisaligned_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxbyterealign_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrfreqreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrlock_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrphdone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrresetrsv_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchanbondseq_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchanisaligned_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchanrealign_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchbonden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchbondi_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchbondlevel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchbondmaster_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchbondo_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxchbondslave_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxckcaldone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxckcalreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxckcalstart_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxclkcorcnt_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcominitdet_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcommadet_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcommadeten_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcomsasdet_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcomwakedet_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxctrl0_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxctrl1_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxctrl2_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxctrl3_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdata_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdataextendrsvd_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdatavalid_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdccforcestart_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfeagcctrl_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfeagchold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfeagcovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfecfokfcnum_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfecfokfen_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfecfokfpulse_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfecfokhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfecfokovren_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfekhhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfekhovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfelfhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfelfovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfelpmreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap10hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap10ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap11hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap11ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap12hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap12ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap13hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap13ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap14hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap14ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap15hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap15ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap2hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap2ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap3hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap3ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap4hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap4ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap5hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap5ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap6hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap6ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap7hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap7ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap8hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap8ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap9hold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfetap9ovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfeuthold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfeutovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfevphold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfevpovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfevsen_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdfexyden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdlybypass_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdlyen_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdlyovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdlysreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxdlysresetdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxelecidle_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxelecidlemode_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxeqtraining_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxgearboxslip_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxheader_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxheadervalid_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlatclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlfpstresetdet_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlfpsu2lpexitdet_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlfpsu3wakedet_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmen_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmgchold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmgcovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmhfhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmhfovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmlfhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmlfklovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmoshold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxlpmosovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxmcommaalignen_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxmonitorout_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxmonitorsel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoobreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoscalreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoshold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintcfg_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintdone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosinten_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosinthold_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintstarted_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintstrobe_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintstrobedone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosintstrobestarted_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosinttestovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxosovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoutclk_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoutclkfabric_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoutclkpcs_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxoutclksel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpcommaalignen_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpcsreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphalign_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphaligndone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphalignen_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphalignerr_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphdlypd_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphdlyreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxphovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpllclksel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpmareset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpmaresetdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxpolarity_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxprbscntreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxprbserr_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxprbslocked_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxprbssel_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxprgdivresetdone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxprogdivreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxqpien_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxqpisenn_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxqpisenp_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxrate_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxratedone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxratemode_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxrecclk0_sel_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxrecclk0sel_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxrecclk1_sel_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxrecclk1sel_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxrecclkout_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxresetdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxslide_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsliderdy_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxslipdone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxslipoutclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxslipoutclkrdy_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxslippma_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxslippmardy_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxstartofseq_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxstatus_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsyncallin_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsyncdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsyncin_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsyncmode_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsyncout_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxsysclksel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxtermination_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxuserrdy_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxusrclk2_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxusrclk_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxvalid_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm0data_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm0finalout_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm0reset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm0testdata_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm0toggle_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm0width_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm1data_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm1finalout_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm1reset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm1testdata_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm1toggle_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sdm1width_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.sigvalidclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tcongpi_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tcongpo_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tconpowerup_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tconreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tconrsvdin1_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tconrsvdout0_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tstin_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tx8b10bbypass_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.tx8b10ben_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txbufdiffctrl_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txbufstatus_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txcomfinish_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txcominit_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txcomsas_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txcomwake_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txctrl0_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txctrl1_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txctrl2_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdata_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdataextendrsvd_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdccdone_out">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdccforcestart_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdccreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdeemph_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdetectrx_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdiffctrl_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdiffpd_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlybypass_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlyen_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlyhold_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlyovrden_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlysreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlysresetdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txdlyupdown_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txelecidle_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txelforcestart_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txheader_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txinhibit_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txlatclk_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txlfpstreset_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txlfpsu2lpexit_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txlfpsu3wake_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txmaincursor_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txmargin_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txmuxdcdexhold_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txmuxdcdorwren_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txoneszeros_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txoutclk_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txoutclkfabric_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txoutclkpcs_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txoutclksel_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpcsreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpdelecidlemode_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphalign_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphaligndone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphalignen_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphdlypd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphdlyreset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphdlytstclk_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphinit_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphinitdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txphovrden_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpippmen_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpippmovrden_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpippmpd_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpippmsel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpippmstepsize_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpisopd_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpllclksel_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpmareset_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpmaresetdone_out">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpolarity_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpostcursor_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txpostcursorinv_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txprbsforceerr_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txprbssel_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txprecursor_in">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txprecursorinv_in">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.txprgdivresetdone_out">true</spirit:configurableElementValue>
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diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xml b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xml
new file mode 100644
index 0000000..6d46f55
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/ip_0/xdma_pcie4_ip_gt.xml
@@ -0,0 +1,22837 @@
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+        <spirit:name>sdm0data_in</spirit:name>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+        <spirit:name>sdm1data_in</spirit:name>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+        <spirit:name>sdm1toggle_in</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+      <spirit:port>
+        <spirit:name>rxrecclk0sel_out</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.rxrecclk0sel_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rxrecclk1sel_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.rxrecclk1sel_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
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+        <spirit:name>sdm0finalout_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.sdm0finalout_out">false</xilinx:isEnabled>
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+          </xilinx:portInfo>
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+        <spirit:name>sdm0testdata_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+      </spirit:port>
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+        <spirit:name>sdm1finalout_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.sdm1finalout_out">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sdm1testdata_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.sdm1testdata_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tcongpo_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.tcongpo_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
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+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tconrsvdout0_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>illegal</xilinx:presence>
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+            </xilinx:enablement>
+          </xilinx:portInfo>
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+        <spirit:name>ubdaddr_out</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.ubdaddr_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+        <spirit:name>ubden_out</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.ubden_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
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+      <spirit:port>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+            <xilinx:enablement>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+              <spirit:typeName>wire</spirit:typeName>
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+          <spirit:direction>out</spirit:direction>
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+          <spirit:direction>out</spirit:direction>
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+        <spirit:name>drprdy_out</spirit:name>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txdlysresetdone_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
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+        </spirit:vendorExtensions>
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+        <spirit:name>txoutclk_out</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txoutclk_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txoutclkfabric_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txoutclkfabric_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txoutclkpcs_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txoutclkpcs_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txphaligndone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_TOTAL_NUM_CHANNELS&apos;)) * 1) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txphaligndone_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txphinitdone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_TOTAL_NUM_CHANNELS&apos;)) * 1) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txphinitdone_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txpmaresetdone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_TOTAL_NUM_CHANNELS&apos;)) * 1) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txpmaresetdone_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txprgdivresetdone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
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+          </spirit:driver>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txprgdivresetdone_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txqpisenn_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txqpisenn_out">false</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
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+        <spirit:name>txqpisenp_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>illegal</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txqpisenp_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txratedone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txratedone_out">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txresetdone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_TOTAL_NUM_CHANNELS&apos;)) * 1) - 1)">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txresetdone_out">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>txsyncdone_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txsyncdone_out">true</xilinx:isEnabled>
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+        </spirit:vendorExtensions>
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+      <spirit:port>
+        <spirit:name>txsyncout_out</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>required</xilinx:presence>
+              <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PORT_ENABLEMENT.txsyncout_out">true</xilinx:isEnabled>
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+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
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+        <spirit:name>C_CHANNEL_ENABLE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CHANNEL_ENABLE" spirit:bitStringLength="192">&quot;000000000000000000000000000000000000000000000000000000000000111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000&quot;</spirit:value>
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+        <spirit:name>C_PCIE_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIE_ENABLE">1</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PCIE_CORECLK_FREQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIE_CORECLK_FREQ">500</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_COMMON_SCALING_FACTOR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_SCALING_FACTOR">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_CPLL_VCO_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CPLL_VCO_FREQUENCY">2500.0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_FORCE_COMMONS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FORCE_COMMONS">0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_FREERUN_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FREERUN_FREQUENCY">100</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_GT_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GT_TYPE">3</spirit:value>
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+        <spirit:name>C_GT_REV</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_GT_REV">67</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLUDE_CPLL_CAL">1</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ENABLE_COMMON_USRCLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_COMMON_USRCLK">0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_USER_GTPOWERGOOD_DELAY_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_GTPOWERGOOD_DELAY_EN">1</spirit:value>
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+        <spirit:name>C_SIM_CPLL_CAL_BYPASS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_CPLL_CAL_BYPASS">1</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_COMMON</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_COMMON">0</spirit:value>
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+        <spirit:name>C_LOCATE_RESET_CONTROLLER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_RESET_CONTROLLER">1</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_USER_DATA_WIDTH_SIZING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_USER_DATA_WIDTH_SIZING">1</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER">0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_IN_SYSTEM_IBERT_CORE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_IN_SYSTEM_IBERT_CORE">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_RX_USER_CLOCKING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_RX_USER_CLOCKING">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_LOCATE_TX_USER_CLOCKING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCATE_TX_USER_CLOCKING">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RESET_CONTROLLER_INSTANCE_CTRL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_CONTROLLER_INSTANCE_CTRL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_BUFFBYPASS_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_BUFFBYPASS_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_BUFFER_BYPASS_INSTANCE_CTRL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_BUFFER_BYPASS_INSTANCE_CTRL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_BUFFER_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_BUFFER_MODE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CB_DISP</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CB_DISP" spirit:bitStringLength="8">&quot;00000000&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CB_K</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CB_K" spirit:bitStringLength="8">&quot;00000000&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CB_MAX_LEVEL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CB_MAX_LEVEL">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CB_LEN_SEQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CB_LEN_SEQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CB_NUM_SEQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CB_NUM_SEQ">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_RX_CB_VAL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CB_VAL" spirit:bitStringLength="80">&quot;00000000000000000000000000000000000000000000000000000000000000000000000000000000&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CC_DISP</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_DISP" spirit:bitStringLength="8">&quot;00000000&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CC_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_ENABLE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RESET_SEQUENCE_INTERVAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_SEQUENCE_INTERVAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CC_K</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_K" spirit:bitStringLength="8">&quot;00000001&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CC_LEN_SEQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_LEN_SEQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CC_NUM_SEQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_NUM_SEQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_CC_PERIODICITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_PERIODICITY">5000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_RX_CC_VAL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_CC_VAL" spirit:bitStringLength="80">&quot;00000000000000000000000000000000000000000000000000000000000000000000000000011100&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_COMMA_M_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_COMMA_M_ENABLE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_COMMA_M_VAL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_COMMA_M_VAL" spirit:bitStringLength="10">&quot;1010000011&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_COMMA_P_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_COMMA_P_ENABLE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_COMMA_P_VAL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_COMMA_P_VAL" spirit:bitStringLength="10">&quot;0101111100&quot;</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_DATA_DECODING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_DATA_DECODING">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_ENABLE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_INT_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_INT_DATA_WIDTH">20</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_RX_LINE_RATE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_LINE_RATE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_MASTER_CHANNEL_IDX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_MASTER_CHANNEL_IDX">131</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_OUTCLK_BUFG_GT_DIV</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_OUTCLK_BUFG_GT_DIV">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_RX_OUTCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_OUTCLK_FREQUENCY">400.0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_OUTCLK_SOURCE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_OUTCLK_SOURCE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_PLL_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_PLL_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_RX_RECCLK_OUTPUT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_RECCLK_OUTPUT" spirit:bitStringLength="192">0x000000000000000000000000000000000000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_RX_REFCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_REFCLK_FREQUENCY">100</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_SLIDE_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_SLIDE_MODE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_USER_CLOCKING_CONTENTS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USER_CLOCKING_CONTENTS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_USER_CLOCKING_INSTANCE_CTRL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USER_CLOCKING_INSTANCE_CTRL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_USER_CLOCKING_SOURCE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USER_CLOCKING_SOURCE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_RX_USER_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USER_DATA_WIDTH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_RX_USRCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USRCLK_FREQUENCY">400.0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_RX_USRCLK2_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RX_USRCLK2_FREQUENCY">400.0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SECONDARY_QPLL_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_QPLL_ENABLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_SECONDARY_QPLL_REFCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_QPLL_REFCLK_FREQUENCY">257.8125</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TOTAL_NUM_CHANNELS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TOTAL_NUM_CHANNELS">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TOTAL_NUM_COMMONS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TOTAL_NUM_COMMONS">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TOTAL_NUM_COMMONS_EXAMPLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TOTAL_NUM_COMMONS_EXAMPLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TXPROGDIV_FREQ_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_ENABLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TXPROGDIV_FREQ_SOURCE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_SOURCE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_TXPROGDIV_FREQ_VAL</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_VAL">400</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_BUFFBYPASS_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_BUFFBYPASS_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_BUFFER_BYPASS_INSTANCE_CTRL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_BUFFER_BYPASS_INSTANCE_CTRL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_BUFFER_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_BUFFER_MODE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_DATA_ENCODING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_DATA_ENCODING">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_ENABLE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_INT_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_INT_DATA_WIDTH">20</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_TX_LINE_RATE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_LINE_RATE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_MASTER_CHANNEL_IDX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_MASTER_CHANNEL_IDX">131</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_OUTCLK_BUFG_GT_DIV</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_OUTCLK_BUFG_GT_DIV">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_TX_OUTCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_OUTCLK_FREQUENCY">400.0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_OUTCLK_SOURCE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_OUTCLK_SOURCE">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_PLL_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_PLL_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_TX_REFCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_REFCLK_FREQUENCY">100</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_USER_CLOCKING_CONTENTS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USER_CLOCKING_CONTENTS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_USER_CLOCKING_INSTANCE_CTRL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USER_CLOCKING_INSTANCE_CTRL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_USER_CLOCKING_SOURCE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USER_CLOCKING_SOURCE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_TX_USER_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USER_DATA_WIDTH">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_TX_USRCLK_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USRCLK_FREQUENCY">400.0000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="signed">
+        <spirit:name>C_TX_USRCLK2_FREQUENCY</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TX_USRCLK2_FREQUENCY">400.0000000</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
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+    <spirit:choice>
+      <spirit:name>choice_list_00d9575a</spirit:name>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_list_0fbde0c1</spirit:name>
+      <spirit:enumeration>20</spirit:enumeration>
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+      <spirit:name>choice_list_13717074</spirit:name>
+      <spirit:enumeration>-20</spirit:enumeration>
+      <spirit:enumeration>-40</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_1fad77c0</spirit:name>
+      <spirit:enumeration>RXOUTCLKPMA</spirit:enumeration>
+      <spirit:enumeration>RXOUTCLKPCS</spirit:enumeration>
+      <spirit:enumeration>RXPROGDIVCLK</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_2170b2c2</spirit:name>
+      <spirit:enumeration>400</spirit:enumeration>
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+      <spirit:name>choice_list_24871ac1</spirit:name>
+      <spirit:enumeration>AC</spirit:enumeration>
+      <spirit:enumeration>DC</spirit:enumeration>
+    </spirit:choice>
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+      <spirit:name>choice_list_2e5a39e9</spirit:name>
+      <spirit:enumeration>500</spirit:enumeration>
+      <spirit:enumeration>250</spirit:enumeration>
+      <spirit:enumeration>125</spirit:enumeration>
+      <spirit:enumeration>62.5</spirit:enumeration>
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+      <spirit:name>choice_list_3145f35e</spirit:name>
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+      <spirit:enumeration>200</spirit:enumeration>
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+      <spirit:enumeration>400</spirit:enumeration>
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+      <spirit:enumeration spirit:text="1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="2">2</spirit:enumeration>
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+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0c77e1fe</spirit:name>
+      <spirit:enumeration spirit:text="8B/10B commas">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Valid IEEE 802.3 commas only">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1040277f</spirit:name>
+      <spirit:enumeration spirit:text="AVTT">AVTT</spirit:enumeration>
+      <spirit:enumeration spirit:text="FLOAT">FLOAT</spirit:enumeration>
+      <spirit:enumeration spirit:text="GND">GND</spirit:enumeration>
+      <spirit:enumeration spirit:text="Programmable">PROGRAMMABLE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_1436b008</spirit:name>
+      <spirit:enumeration spirit:text="Multi-lane mode">MULTI</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single-lane mode">SINGLE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_40d02874</spirit:name>
+      <spirit:enumeration spirit:text="10GBASE-KR">10GBASE_KR</spirit:enumeration>
+      <spirit:enumeration spirit:text="Custom">CUSTOM</spirit:enumeration>
+      <spirit:enumeration spirit:text="PCIe Gen1/Gen2">PCIE_GEN1_GEN2</spirit:enumeration>
+      <spirit:enumeration spirit:text="PCIe Gen3">PCIE_GEN3</spirit:enumeration>
+      <spirit:enumeration spirit:text="QPI">QPI</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_4e550952</spirit:name>
+      <spirit:enumeration spirit:text="No (do not include)">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Yes (include in Example Design)">EXAMPLE_DESIGN</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_5d4d976c</spirit:name>
+      <spirit:enumeration spirit:text="Start from scratch">None</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 100GAUI_4 (Beta)">GTY-100GAUI_4</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 100GBASE-KR4 (Beta)">GTY-100GBASE-KR4</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 10GBASE-KR (Production)">GTY-10GBASE-KR</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 10GBASE-R (Production)">GTY-10GBASE-R</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 12G-SDI (Production)">GTY-12G_SDI</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 1G_10G_25G_switchable (Beta)">GTY-1G_10G_25G_switchable</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 3G-SDI (Production)">GTY-3G_SDI</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: 50GAUI_2 (Beta)">GTY-50GAUI_2</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Aurora 64B/66B (Production)">GTY-Aurora_64B66B</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Aurora 8B/10B (Beta)">GTY-Aurora_8B10B</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: MoSys Bandwidth Engine (Beta)">GTY-Bandwidth_Engine</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CAUI-10 (Production)">GTY-CAUI_10</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CAUI-10 (Raw mode) (Production)">GTY-CAUI_10_raw</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CAUI-4 (Raw mode) (Production)">GTY-CAUI_4</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CEI-11G-SR (Pre-Production)">GTY-CEI_11G_SR</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CPRI 9.8 Gb/s, 8B10B, high loss (Production)">GTY-CPRI_10G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CPRI 10.1 Gb/s and above, 64B66B, high loss (Production)">GTY-CPRI_10_1G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CPRI 10.1 Gb/s and above, 64B66B, low loss (Production)">GTY-CPRI_10_1G_lowloss</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: CPRI 6 Gb/s and below, 8B10B, low loss (Production)">GTY-CPRI_6G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: DisplayPort 1.62 Gb/s (Production)">GTY-DisplayPort_1_62G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: DisplayPort 2.7 Gb/s (Production)">GTY-DisplayPort_2_7G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: DisplayPort 5.4 Gb/s (Production)">GTY-DisplayPort_5_4G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: DisplayPort 8.1 Gb/s (Production)">GTY-DisplayPort_8_1G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Gigabit Ethernet (Production)">GTY-Gigabit_Ethernet</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: HDMI (Beta)">GTY-HDMI</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: HD-SDI (Production)">GTY-HD_SDI</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Hybrid Memory Cube 16x12.5G (Beta)">GTY-HMC_12_5G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Interlaken 10x10.3125G (Raw mode) (Production)">GTY-Interlaken_10G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Interlaken 12x12.5G (Raw mode) (Production)">GTY-Interlaken_12_5G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Interlaken 6x25.78125G (Raw mode) (Production)">GTY-Interlaken_25G</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: JESD204 (Production)">GTY-JESD204</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: JESD204B high loss (Production)">GTY-JESD204B_highloss</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: JESD204B low loss (Production)">GTY-JESD204B_lowloss</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: OTL4.10 (Beta)">GTY-OTL4_10</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: OTU2 (Beta)">GTY-OTU2</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: OTU2e (Beta)">GTY-OTU2e</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: OTL4.4 (Beta)">GTY-OTU4</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: QSGMII (Pre-Production)">GTY-QSGMII</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: RXAUI (Pre-Production)">GTY-RXAUI</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: SATA (Beta)">GTY-SATA</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: Serial RapidIO Gen2 3.125 Gb/s default (Pre-Production)">GTY-SRIO_Gen2</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: VbyOne (Beta)">GTY-VbyOne</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: XAUI (Pre-Production)">GTY-XAUI</spirit:enumeration>
+      <spirit:enumeration spirit:text="GTY: XLAUI (Beta)">GTY-XLAUI</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_pairs_7b0c3758</spirit:name>
+      <spirit:enumeration spirit:text="Receive Only (RX)">RX</spirit:enumeration>
+      <spirit:enumeration spirit:text="Transmit and Receive (BOTH)">BOTH</spirit:enumeration>
+      <spirit:enumeration spirit:text="Transmit Only (TX)">TX</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_85f99b7f</spirit:name>
+      <spirit:enumeration spirit:text="K28.1">K28.1</spirit:enumeration>
+      <spirit:enumeration spirit:text="K28.5">K28.5</spirit:enumeration>
+      <spirit:enumeration spirit:text="Select a preset">NONE</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_pairs_8846c8f0</spirit:name>
+      <spirit:enumeration spirit:text="Raw (no encoding)">RAW</spirit:enumeration>
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+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/66B">64B66B</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/66B (CAUI mode)">64B66B_CAUI</spirit:enumeration>
+      <spirit:enumeration spirit:text="Async. gearbox for 64B/66B">64B66B_ASYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Async. gearbox for 64B/66B (CAUI mode)">64B66B_ASYNC_CAUI</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/67B">64B67B</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/67B (CAUI mode)">64B67B_CAUI</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_pairs_88c85933</spirit:name>
+      <spirit:enumeration spirit:text="8B/10B">8B10B</spirit:enumeration>
+      <spirit:enumeration spirit:text="Async. gearbox for 64B/66B">64B66B_ASYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Async. gearbox for 64B/66B (CAUI mode)">64B66B_ASYNC_CAUI</spirit:enumeration>
+      <spirit:enumeration spirit:text="Raw (no encoding)">RAW</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/66B">64B66B</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/66B (CAUI mode)">64B66B_CAUI</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/67B">64B67B</spirit:enumeration>
+      <spirit:enumeration spirit:text="Sync. gearbox for 64B/67B (CAUI mode)">64B67B_CAUI</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_93c2d4ee</spirit:name>
+      <spirit:enumeration spirit:text="Core">CORE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Example Design">EXAMPLE_DESIGN</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_9c19f015</spirit:name>
+      <spirit:enumeration spirit:text="Any byte boundary (1)">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Two byte boundary">2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a537ddda</spirit:name>
+      <spirit:enumeration spirit:text="Bypass (0)">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Enable (1)">1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_aa541099</spirit:name>
+      <spirit:enumeration spirit:text="Auto">AUTO</spirit:enumeration>
+      <spirit:enumeration spirit:text="DFE">DFE</spirit:enumeration>
+      <spirit:enumeration spirit:text="LPM">LPM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_ae574462</spirit:name>
+      <spirit:enumeration spirit:text="Off">OFF</spirit:enumeration>
+      <spirit:enumeration spirit:text="PCS">PCS</spirit:enumeration>
+      <spirit:enumeration spirit:text="PMA">PMA</spirit:enumeration>
+      <spirit:enumeration spirit:text="Automated PMA">AUTO</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b0974ef0</spirit:name>
+      <spirit:enumeration spirit:text="1">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="2">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="No clock correction (0)">0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_d4feb97d</spirit:name>
+      <spirit:enumeration spirit:text="Disable">DISABLE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Enable">ENABLE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f05b8192</spirit:name>
+      <spirit:enumeration spirit:text="Channel">CHANNEL</spirit:enumeration>
+      <spirit:enumeration spirit:text="Name">NAME</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you&apos;ve selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>GT_TYPE</spirit:name>
+      <spirit:displayName>Transceiver type</spirit:displayName>
+      <spirit:description>For devices which contain more than one serial transceiver type, select the type of transceiver to configure</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GT_TYPE" spirit:choiceRef="choice_list_98ff8152" spirit:order="2">GTY</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_GT_PRIM_TYPE</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_GT_PRIM_TYPE" spirit:order="3">gtye4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_GT_PRIM_TYPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GT_REV</spirit:name>
+      <spirit:displayName>Transceiver revision</spirit:displayName>
+      <spirit:description>Select the serial transceiver silicon revision</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GT_REV" spirit:order="4">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>GT_DIRECTION</spirit:name>
+      <spirit:displayName>Transmit and/or Receive direction</spirit:displayName>
+      <spirit:description>Enable transmit and/or receive</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GT_DIRECTION" spirit:choiceRef="choice_pairs_7b0c3758" spirit:order="5">BOTH</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_ENABLE</spirit:name>
+      <spirit:displayName>Enabled</spirit:displayName>
+      <spirit:description>Enable the receiver for use</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_ENABLE" spirit:order="6">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_ENABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_ENABLE</spirit:name>
+      <spirit:displayName>Enabled</spirit:displayName>
+      <spirit:description>Enable the transmitter for use</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="PARAM_VALUE.TX_ENABLE" spirit:order="7">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.TX_ENABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CHANNEL_ENABLE</spirit:name>
+      <spirit:displayName>Enable channel</spirit:displayName>
+      <spirit:description>Indicate whether this transceiver channel is instantiated and enabled for use</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CHANNEL_ENABLE" spirit:order="8">X1Y35 X1Y34 X1Y33 X1Y32 X1Y31 X1Y30 X1Y29 X1Y28</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_MASTER_CHANNEL</spirit:name>
+      <spirit:displayName>Master TX channel</spirit:displayName>
+      <spirit:description>Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected)</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_MASTER_CHANNEL" spirit:choiceRef="choice_list_c043f539" spirit:order="9">X1Y35</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_MASTER_CHANNEL</spirit:name>
+      <spirit:displayName>Master RX channel</spirit:displayName>
+      <spirit:description>Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected)</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_MASTER_CHANNEL" spirit:choiceRef="choice_list_c043f539" spirit:order="10">X1Y35</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_TOTAL_NUM_CHANNELS</spirit:name>
+      <spirit:displayName>Total number of channels</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_TOTAL_NUM_CHANNELS" spirit:order="11" spirit:minimum="0" spirit:rangeType="long">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_TOTAL_NUM_CHANNELS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_TOTAL_NUM_COMMONS</spirit:name>
+      <spirit:displayName>Total number of commons required</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_TOTAL_NUM_COMMONS" spirit:order="12" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_TOTAL_NUM_COMMONS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_COMMON</spirit:name>
+      <spirit:displayName>Include transceiver COMMON in the</spirit:displayName>
+      <spirit:description>If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_COMMON" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="13">CORE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_NUM_COMMONS_CORE</spirit:name>
+      <spirit:displayName>Number of commons in core</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_NUM_COMMONS_CORE" spirit:order="14" spirit:minimum="0" spirit:rangeType="long">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_NUM_COMMONS_CORE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_NUM_COMMONS_EXAMPLE</spirit:name>
+      <spirit:displayName>Number of commons in example</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_NUM_COMMONS_EXAMPLE" spirit:order="15" spirit:minimum="0" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_NUM_COMMONS_EXAMPLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_TX_USRCLK_FREQUENCY</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_TX_USRCLK_FREQUENCY" spirit:order="16">400.0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_TX_USRCLK_FREQUENCY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_RX_USRCLK_FREQUENCY</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_RX_USRCLK_FREQUENCY" spirit:order="17">400.0000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_RX_USRCLK_FREQUENCY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_PPM_OFFSET</spirit:name>
+      <spirit:displayName>PPM offset between receiver and transmitter</spirit:displayName>
+      <spirit:description>Specify the PPM offset between received data and transmitted data</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PPM_OFFSET" spirit:order="18" spirit:minimum="0" spirit:maximum="1250" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OOB_ENABLE</spirit:name>
+      <spirit:displayName>Enable Out of Band signaling (OOB)/Electrical Idle</spirit:displayName>
+      <spirit:description>Enable or disable Out of Band signaling (OOB)/Electrical Idle</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OOB_ENABLE" spirit:order="19">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.OOB_ENABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_SSC_PPM</spirit:name>
+      <spirit:displayName>Spread spectrum clocking</spirit:displayName>
+      <spirit:description>Specify the spread spectrum clocking modulation in PPM</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_SSC_PPM" spirit:order="20" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INS_LOSS_NYQ</spirit:name>
+      <spirit:displayName>Insertion loss at Nyquist (dB)</spirit:displayName>
+      <spirit:description>Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.INS_LOSS_NYQ" spirit:order="21" spirit:minimum="0">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_CORECLK_FREQ</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_CORECLK_FREQ" spirit:choiceRef="choice_list_3d9ff82c" spirit:order="22">500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_USERCLK_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_USERCLK_FREQ" spirit:choiceRef="choice_list_2e5a39e9" spirit:order="23">250</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_LINE_RATE</spirit:name>
+      <spirit:displayName>Line rate (Gb/s)</spirit:displayName>
+      <spirit:description>Enter the transmitter line rate in Gb/s</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_LINE_RATE" spirit:order="24" spirit:minimum="0.5" spirit:maximum="28.21">8</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_PLL_TYPE</spirit:name>
+      <spirit:displayName>PLL type</spirit:displayName>
+      <spirit:description>Select the transmitter PLL type</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_PLL_TYPE" spirit:choiceRef="choice_list_3179277f" spirit:order="25">QPLL1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_REFCLK_FREQUENCY</spirit:name>
+      <spirit:displayName>Actual Reference clock (MHz)</spirit:displayName>
+      <spirit:description>Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type </spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_REFCLK_FREQUENCY" spirit:choiceRef="choice_list_f01dcfac" spirit:order="26">100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_DATA_ENCODING</spirit:name>
+      <spirit:displayName>Encoding</spirit:displayName>
+      <spirit:description>Select the encoding format for data transmission, or choose &apos;Raw&apos; for no data encoding</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_DATA_ENCODING" spirit:choiceRef="choice_pairs_88c85933" spirit:order="27">8B10B</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_USER_DATA_WIDTH</spirit:name>
+      <spirit:displayName>User data width</spirit:displayName>
+      <spirit:description>Select the width at which the user logic will provide parallel data to the serial transceiver for transmission</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_USER_DATA_WIDTH" spirit:choiceRef="choice_list_00d9575a" spirit:order="28">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_INT_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Internal data width</spirit:displayName>
+      <spirit:description>Select the width of the serial transceiver internal transmitter data path</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_INT_DATA_WIDTH" spirit:choiceRef="choice_list_0fbde0c1" spirit:order="29">20</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_BUFFER_MODE</spirit:name>
+      <spirit:displayName>Buffer</spirit:displayName>
+      <spirit:description>Select whether to enable or to bypass the transmitter buffer</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_BUFFER_MODE" spirit:choiceRef="choice_pairs_a537ddda" spirit:order="30">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_QPLL_FRACN_NUMERATOR</spirit:name>
+      <spirit:displayName>Fractional part of QPLL feedback divider</spirit:displayName>
+      <spirit:description>For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_QPLL_FRACN_NUMERATOR" spirit:order="31" spirit:minimum="0" spirit:maximum="16777215" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_OUTCLK_SOURCE</spirit:name>
+      <spirit:displayName>TXOUTCLK source</spirit:displayName>
+      <spirit:description>Select the source of TXOUTCLK</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_OUTCLK_SOURCE" spirit:choiceRef="choice_list_66ca0f1f" spirit:order="32">TXPROGDIVCLK</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_DIFF_SWING_EMPH_MODE</spirit:name>
+      <spirit:displayName>Differential swing and emphasis mode</spirit:displayName>
+      <spirit:description>Select the transmitter differential swing and emphasis mode for your application</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_DIFF_SWING_EMPH_MODE" spirit:choiceRef="choice_pairs_40d02874" spirit:order="33">PCIE_GEN1_GEN2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_LINE_RATE</spirit:name>
+      <spirit:displayName>Line rate (Gb/s)</spirit:displayName>
+      <spirit:description>Enter the receiver line rate in Gb/s</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_LINE_RATE" spirit:order="34" spirit:minimum="0.5" spirit:maximum="28.21">8</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_PLL_TYPE</spirit:name>
+      <spirit:displayName>PLL type</spirit:displayName>
+      <spirit:description>Select the receiver PLL type</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PLL_TYPE" spirit:choiceRef="choice_list_3179277f" spirit:order="35">QPLL1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_REFCLK_FREQUENCY</spirit:name>
+      <spirit:displayName>Actual Reference clock (MHz)</spirit:displayName>
+      <spirit:description>Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_REFCLK_FREQUENCY" spirit:choiceRef="choice_list_f01dcfac" spirit:order="36">100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_DATA_DECODING</spirit:name>
+      <spirit:displayName>Decoding</spirit:displayName>
+      <spirit:description>Select the decoding format for data reception, or choose &apos;Raw&apos; for no data decoding</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_DATA_DECODING" spirit:choiceRef="choice_pairs_8846c8f0" spirit:order="37">8B10B</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_USER_DATA_WIDTH</spirit:name>
+      <spirit:displayName>User data width</spirit:displayName>
+      <spirit:description>Select the width at which the serial transceiver will provide received parallel data to the user logic</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_USER_DATA_WIDTH" spirit:choiceRef="choice_list_00d9575a" spirit:order="38">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_INT_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Internal data width</spirit:displayName>
+      <spirit:description>Select the width of the serial transceiver internal receiver data path</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_INT_DATA_WIDTH" spirit:choiceRef="choice_list_0fbde0c1" spirit:order="39">20</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_BUFFER_MODE</spirit:name>
+      <spirit:displayName>Buffer</spirit:displayName>
+      <spirit:description>Select whether to enable or to bypass the receiver elastic buffer</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_BUFFER_MODE" spirit:choiceRef="choice_pairs_a537ddda" spirit:order="40">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_QPLL_FRACN_NUMERATOR</spirit:name>
+      <spirit:displayName>Fractional part of QPLL feedback divider</spirit:displayName>
+      <spirit:description>For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_QPLL_FRACN_NUMERATOR" spirit:order="41" spirit:minimum="0" spirit:maximum="16777215" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_EQ_MODE</spirit:name>
+      <spirit:displayName>Equalization mode</spirit:displayName>
+      <spirit:description>Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_EQ_MODE" spirit:choiceRef="choice_pairs_aa541099" spirit:order="42">DFE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_JTOL_FC</spirit:name>
+      <spirit:displayName>Mask corner frequency (MHz)</spirit:displayName>
+      <spirit:description>Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency.</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_JTOL_FC" spirit:order="43" spirit:minimum="0" spirit:maximum="10">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_JTOL_LF_SLOPE</spirit:name>
+      <spirit:displayName>Mask low frequency slope (dB/decade)</spirit:displayName>
+      <spirit:description>Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope.</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_JTOL_LF_SLOPE" spirit:choiceRef="choice_list_13717074" spirit:order="44">-20</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_OUTCLK_SOURCE</spirit:name>
+      <spirit:displayName>RXOUTCLK source</spirit:displayName>
+      <spirit:description>Select the source of RXOUTCLK</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_OUTCLK_SOURCE" spirit:choiceRef="choice_list_1fad77c0" spirit:order="45">RXOUTCLKPMA</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SIM_CPLL_CAL_BYPASS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIM_CPLL_CAL_BYPASS" spirit:order="46" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_ENABLE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_ENABLE" spirit:order="47">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_TERMINATION</spirit:name>
+      <spirit:displayName>Termination</spirit:displayName>
+      <spirit:description>Select the receiver termination</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_TERMINATION" spirit:choiceRef="choice_pairs_1040277f" spirit:order="48">PROGRAMMABLE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_TERMINATION_PROG_VALUE</spirit:name>
+      <spirit:displayName>Programmable termination voltage (mV)</spirit:displayName>
+      <spirit:description>Select the termination voltage (in mV) when in programmable mode</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_TERMINATION_PROG_VALUE" spirit:choiceRef="choice_list_3145f35e" spirit:order="49">800</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COUPLING</spirit:name>
+      <spirit:displayName>Link coupling</spirit:displayName>
+      <spirit:description>Select the link coupling</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COUPLING" spirit:choiceRef="choice_list_24871ac1" spirit:order="50">AC</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_BUFFER_BYPASS_MODE</spirit:name>
+      <spirit:displayName>Receiver elastic buffer bypass mode</spirit:displayName>
+      <spirit:description>Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_BUFFER_BYPASS_MODE" spirit:choiceRef="choice_pairs_1436b008" spirit:order="51">MULTI</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_BUFFER_BYPASS_MODE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_BUFFER_RESET_ON_CB_CHANGE</spirit:name>
+      <spirit:displayName>Reset receiver elastic buffer on channel bonding change</spirit:displayName>
+      <spirit:description>Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_BUFFER_RESET_ON_CB_CHANGE" spirit:choiceRef="choice_pairs_d4feb97d" spirit:order="52">ENABLE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_BUFFER_RESET_ON_CB_CHANGE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_BUFFER_RESET_ON_COMMAALIGN</spirit:name>
+      <spirit:displayName>Reset receiver elastic buffer on comma alignment</spirit:displayName>
+      <spirit:description>Control whether the receiver elastic buffer is reset on comma alignment</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_BUFFER_RESET_ON_COMMAALIGN" spirit:choiceRef="choice_pairs_d4feb97d" spirit:order="53">DISABLE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_BUFFER_RESET_ON_RATE_CHANGE</spirit:name>
+      <spirit:displayName>Reset receiver elastic buffer on rate change</spirit:displayName>
+      <spirit:description>Control whether the receiver elastic buffer is reset on rate change</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_BUFFER_RESET_ON_RATE_CHANGE" spirit:choiceRef="choice_pairs_d4feb97d" spirit:order="54">ENABLE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_BUFFER_RESET_ON_RATE_CHANGE</spirit:name>
+      <spirit:displayName>Reset transmitter buffer on rate change</spirit:displayName>
+      <spirit:description>Control whether the transmitter buffer is reset on rate change</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_BUFFER_RESET_ON_RATE_CHANGE" spirit:choiceRef="choice_pairs_d4feb97d" spirit:order="55">ENABLE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.TX_BUFFER_RESET_ON_RATE_CHANGE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_SEQUENCE_INTERVAL</spirit:name>
+      <spirit:displayName>Reset sequence time interval (ns)</spirit:displayName>
+      <spirit:description>Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_SEQUENCE_INTERVAL" spirit:choiceRef="choice_list_556e59ba" spirit:order="56">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_PRESET</spirit:name>
+      <spirit:displayName>Comma value preset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_PRESET" spirit:choiceRef="choice_pairs_85f99b7f" spirit:order="57">K28.5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_VALID_ONLY</spirit:name>
+      <spirit:displayName>Valid comma values for 8B/10B decoding</spirit:displayName>
+      <spirit:description>Select the range of comma characters decoded by the 8B/10B decoder</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_VALID_ONLY" spirit:choiceRef="choice_pairs_0c77e1fe" spirit:order="58">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_P_ENABLE</spirit:name>
+      <spirit:displayName>Detect plus comma</spirit:displayName>
+      <spirit:description>Indicate whether or not the specified bit pattern is detected as a plus comma</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_P_ENABLE" spirit:order="59">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_M_ENABLE</spirit:name>
+      <spirit:displayName>Detect minus comma</spirit:displayName>
+      <spirit:description>Indicate whether or not the specified bit pattern is detected as a minus comma</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_M_ENABLE" spirit:order="60">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_DOUBLE_ENABLE</spirit:name>
+      <spirit:displayName>Detect combined plus/minus (double-length) comma</spirit:displayName>
+      <spirit:description>Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_DOUBLE_ENABLE" spirit:order="61">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_P_VAL</spirit:name>
+      <spirit:displayName>Plus comma value</spirit:displayName>
+      <spirit:description>Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_P_VAL" spirit:order="62" spirit:bitStringLength="10">0101111100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_M_VAL</spirit:name>
+      <spirit:displayName>Minus comma value</spirit:displayName>
+      <spirit:description>Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_M_VAL" spirit:order="63" spirit:bitStringLength="10">1010000011</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_MASK</spirit:name>
+      <spirit:displayName>Mask</spirit:displayName>
+      <spirit:description>Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a &quot;don&apos;t care&quot;</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_MASK" spirit:order="64" spirit:bitStringLength="10">1111111111</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_ALIGN_WORD</spirit:name>
+      <spirit:displayName>Alignment boundary</spirit:displayName>
+      <spirit:description>Select which data byte boundaries are allowed for comma alignment</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_ALIGN_WORD" spirit:choiceRef="choice_pairs_9c19f015" spirit:order="65">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_COMMA_SHOW_REALIGN_ENABLE</spirit:name>
+      <spirit:displayName>Show realign comma</spirit:displayName>
+      <spirit:description>Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_COMMA_SHOW_REALIGN_ENABLE" spirit:order="66">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_SLIDE_MODE</spirit:name>
+      <spirit:displayName>Manual alignment (RXSLIDE) mode</spirit:displayName>
+      <spirit:description>Select whether to enable manual alignment, and in what mode if enabled</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_SLIDE_MODE" spirit:choiceRef="choice_pairs_ae574462" spirit:order="67">PMA</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_NUM_SEQ</spirit:name>
+      <spirit:displayName>Enable and select number of sequences to use</spirit:displayName>
+      <spirit:description>Select whether to enable channel bonding, and how many sequences to use if enabled</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_NUM_SEQ" spirit:choiceRef="choice_pairs_03018cc1" spirit:order="68">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_LEN_SEQ</spirit:name>
+      <spirit:displayName>Length of each sequence</spirit:displayName>
+      <spirit:description>Select the number of characters in each channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_LEN_SEQ" spirit:choiceRef="choice_list_e6469819" spirit:order="69">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_LEN_SEQ">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MAX_SKEW</spirit:name>
+      <spirit:displayName>Sequence maximum skew</spirit:displayName>
+      <spirit:description>Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MAX_SKEW" spirit:order="70" spirit:minimum="1" spirit:maximum="14" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MAX_SKEW">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MAX_LEVEL</spirit:name>
+      <spirit:displayName>Maximum channel bonding level to be used</spirit:displayName>
+      <spirit:description>Select the maximum channel bonding level that will be used in the system channel bonding topology</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MAX_LEVEL" spirit:order="71" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MAX_LEVEL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CB_MASK" spirit:order="72">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CB_VAL" spirit:order="73">00000000000000000000000000000000000000000000000000000000000000000000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CB_K" spirit:order="74">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CB_DISP" spirit:order="75">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_0_0</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_0_0" spirit:order="76">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_0_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_0_0</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_0_0" spirit:order="77">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_0_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_0_0</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_0_0" spirit:order="78">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_0_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_0_0</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_0_0" spirit:order="79">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_0_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_0_1</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_0_1" spirit:order="80">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_0_1</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_0_1" spirit:order="81">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_0_1</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_0_1" spirit:order="82">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_0_1</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_0_1" spirit:order="83">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_0_2</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_0_2" spirit:order="84">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_0_2</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_0_2" spirit:order="85">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_0_2</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_0_2" spirit:order="86">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_0_2</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_0_2" spirit:order="87">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_0_3</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_0_3" spirit:order="88">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_0_3</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_0_3" spirit:order="89">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_0_3</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_0_3" spirit:order="90">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_0_3</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_0_3" spirit:order="91">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_1_0</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_1_0" spirit:order="92">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_1_0</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_1_0" spirit:order="93">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_1_0</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_1_0" spirit:order="94">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_1_0</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_1_0" spirit:order="95">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_1_1</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_1_1" spirit:order="96">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_1_1</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_1_1" spirit:order="97">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_1_1</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_1_1" spirit:order="98">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_1_1</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_1_1" spirit:order="99">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_1_2</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_1_2" spirit:order="100">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_1_2</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_1_2" spirit:order="101">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_1_2</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_1_2" spirit:order="102">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_1_2</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_1_2" spirit:order="103">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_MASK_1_3</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a channel bonding sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_MASK_1_3" spirit:order="104">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_MASK_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_VAL_1_3</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this channel bonding sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_VAL_1_3" spirit:order="105">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_VAL_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_K_1_3</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_K_1_3" spirit:order="106">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_K_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CB_DISP_1_3</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CB_DISP_1_3" spirit:order="107">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CB_DISP_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_NUM_SEQ</spirit:name>
+      <spirit:displayName>Enable and select number of sequences to use</spirit:displayName>
+      <spirit:description>Select whether to enable clock correction, and how many sequences to use if enabled</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_NUM_SEQ" spirit:choiceRef="choice_pairs_b0974ef0" spirit:order="108">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_LEN_SEQ</spirit:name>
+      <spirit:displayName>Length of each sequence</spirit:displayName>
+      <spirit:description>Select the number of characters in each channel clock correction sequence</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_LEN_SEQ" spirit:choiceRef="choice_list_e6469819" spirit:order="109">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_PERIODICITY</spirit:name>
+      <spirit:displayName>Periodicity of the sequence (in bytes)</spirit:displayName>
+      <spirit:description>Specify the separation between clock correction sequences, in bytes</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_PERIODICITY" spirit:order="110" spirit:minimum="1" spirit:rangeType="long">5000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_KEEP_IDLE</spirit:name>
+      <spirit:displayName>Keep idle</spirit:displayName>
+      <spirit:description>Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_KEEP_IDLE" spirit:choiceRef="choice_pairs_d4feb97d" spirit:order="111">ENABLE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_PRECEDENCE</spirit:name>
+      <spirit:displayName>Precedence</spirit:displayName>
+      <spirit:description>Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_PRECEDENCE" spirit:choiceRef="choice_pairs_d4feb97d" spirit:order="112">ENABLE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_PRECEDENCE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_REPEAT_WAIT</spirit:name>
+      <spirit:displayName>Minimum repetition</spirit:displayName>
+      <spirit:description>Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_REPEAT_WAIT" spirit:order="113" spirit:minimum="0" spirit:maximum="31" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CC_MASK" spirit:order="114">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL" spirit:order="115">00000000000000000000000000000000000000000000000000000000000000000000000000011100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CC_K" spirit:order="116">00000001</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP</spirit:name>
+      <spirit:value spirit:resolve="generated" spirit:id="PARAM_VALUE.RX_CC_DISP" spirit:order="117">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_0_0</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_0_0" spirit:order="118">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_0_0</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_0_0" spirit:order="119">00011100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_0_0</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_0_0" spirit:order="120">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_0_0</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_0_0" spirit:order="121">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_0_1</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_0_1" spirit:order="122">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_0_1</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_0_1" spirit:order="123">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_0_1</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_0_1" spirit:order="124">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_0_1</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_0_1" spirit:order="125">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_0_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_0_2</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_0_2" spirit:order="126">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_0_2</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_0_2" spirit:order="127">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_0_2</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_0_2" spirit:order="128">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_0_2</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_0_2" spirit:order="129">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_0_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_0_3</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_0_3" spirit:order="130">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_0_3</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_0_3" spirit:order="131">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_0_3</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_0_3" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_0_3</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_0_3" spirit:order="133">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_0_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_1_0</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_1_0" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_1_0</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_1_0" spirit:order="135">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_1_0</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_1_0" spirit:order="136">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_1_0</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_1_0" spirit:order="137">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_1_0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_1_1</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_1_1" spirit:order="138">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_1_1</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_1_1" spirit:order="139">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_1_1</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_1_1" spirit:order="140">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_1_1</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_1_1" spirit:order="141">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_1_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_1_2</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_1_2" spirit:order="142">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_1_2</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_1_2" spirit:order="143">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_1_2</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_1_2" spirit:order="144">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_1_2</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_1_2" spirit:order="145">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_1_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_MASK_1_3</spirit:name>
+      <spirit:displayName>Don&apos;t care</spirit:displayName>
+      <spirit:description>Mark this pattern &quot;don&apos;t care&quot; to always consider it as a match within a clock correction sequence</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_MASK_1_3" spirit:order="146">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_MASK_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_VAL_1_3</spirit:name>
+      <spirit:displayName>Value</spirit:displayName>
+      <spirit:description>Specify the value for this clock correction sequence and pattern</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_VAL_1_3" spirit:order="147">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_VAL_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_K_1_3</spirit:name>
+      <spirit:displayName>K character</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value is a K character</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_K_1_3" spirit:order="148">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_K_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_CC_DISP_1_3</spirit:name>
+      <spirit:displayName>Inverted disparity</spirit:displayName>
+      <spirit:description>Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_CC_DISP_1_3" spirit:order="149">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.RX_CC_DISP_1_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_OPTIONAL_PORTS</spirit:name>
+      <spirit:displayName>Enable optional ports</spirit:displayName>
+      <spirit:description>Indicate whether a port should be included</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_OPTIONAL_PORTS" spirit:order="150">txpdelecidlemode_in txprgdivresetdone_out rcalenb_in txpisopd_in rxratemode_in dmonfiforeset_in dmonitorclk_in dmonitorout_out txdlysresetdone_out rxdlysresetdone_out rxphaligndone_out rxsyncdone_out eyescanreset_in txdiffctrl_in rxtermination_in cpllpd_in drpaddr_common_in drpclk_common_in drpdi_common_in drpen_common_in drpwe_common_in loopback_in pcieeqrxeqadaptdone_in pcierstidle_in pciersttxsyncstart_in pcieuserratedone_in qpll0pd_in qpll1pd_in rxcdrreset_in rxdfelpmreset_in rxlpmen_in rxpc
+sreset_in rxpd_in rxpmareset_in rxpolarity_in rxprbscntreset_in rxprbssel_in rxrate_in txdeemph_in txdetectrx_in txelecidle_in txmaincursor_in txmargin_in txpcsreset_in txpd_in txpmareset_in txpostcursor_in txprbsforceerr_in txprbssel_in txprecursor_in txrate_in txswing_in bufgtce_out bufgtcemask_out bufgtdiv_out bufgtreset_out bufgtrstmask_out drpdo_common_out drprdy_common_out gtpowergood_out pcierategen3_out pcierateidle_out pcierateqpllpd_out pcierateqpllreset_out pciesynctxsyncdone_out pcie
+usergen3rdy_out pcieuserphystatusrst_out pcieuserratestart_out phystatus_out rxelecidle_out rxoutclkfabric_out rxoutclkpcs_out rxprbserr_out rxprbslocked_out rxrecclkout_out rxstatus_out rxvalid_out txoutclkfabric_out txoutclkpcs_out qpll1freqlock_in qpll0freqlock_in cpllfreqlock_in qpll0lock_out qpll1lock_out drpclk_in cpllreset_in qpll1outclk_out qpll1outrefclk_out qpll0outclk_out qpll0outrefclk_out pcierateqpll0_in pcierateqpll1_in gtrefclk00_in gtrefclk01_in qpll0reset_in qpll1reset_in drpwe
+_in drpaddr_in drpen_in drprst_in drprdy_out drpdi_in drpdo_out rxcdrhold_in rxdfeagchold_in rxdfecfokhold_in rxdfelfhold_in rxdfekhhold_in rxdfetap2hold_in rxdfetap3hold_in rxdfetap4hold_in rxdfetap5hold_in rxdfetap6hold_in rxdfetap7hold_in rxdfetap8hold_in rxdfetap9hold_in rxdfetap10hold_in rxdfetap11hold_in rxdfetap12hold_in rxdfetap13hold_in rxdfetap14hold_in rxdfetap15hold_in rxdfeuthold_in rxdfevphold_in rxoshold_in rxlpmgchold_in rxlpmhfhold_in rxlpmlfhold_in rxlpmoshold_in rxratedone_out
+ rxcdrfreqreset_in resetovrd_in txoutclksel_in cplllock_out gtrefclk0_in</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_REFCLK_SOURCE</spirit:name>
+      <spirit:displayName>Receiver reference clock source</spirit:displayName>
+      <spirit:description>Select a reference clock input to drive the PLL chosen for receiver operation</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_REFCLK_SOURCE" spirit:order="151"/>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TX_REFCLK_SOURCE</spirit:name>
+      <spirit:displayName>Transmitter reference clock source</spirit:displayName>
+      <spirit:description>Select a reference clock input to drive the PLL chosen for transmitter operation</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TX_REFCLK_SOURCE" spirit:order="152"/>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_RECCLK_OUTPUT</spirit:name>
+      <spirit:displayName>Drive recovered clock out of device</spirit:displayName>
+      <spirit:description>Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RX_RECCLK_OUTPUT" spirit:order="153"/>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_RESET_CONTROLLER</spirit:name>
+      <spirit:displayName>Include reset controller in the</spirit:displayName>
+      <spirit:description>Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_RESET_CONTROLLER" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="154">EXAMPLE_DESIGN</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_TX_BUFFER_BYPASS_CONTROLLER</spirit:name>
+      <spirit:displayName>Include transmitter buffer bypass controller in the</spirit:displayName>
+      <spirit:description>If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_TX_BUFFER_BYPASS_CONTROLLER" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="155">EXAMPLE_DESIGN</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_RX_BUFFER_BYPASS_CONTROLLER</spirit:name>
+      <spirit:displayName>Include receiver elastic buffer bypass controller in the</spirit:displayName>
+      <spirit:description>If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_RX_BUFFER_BYPASS_CONTROLLER" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="156">CORE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.LOCATE_RX_BUFFER_BYPASS_CONTROLLER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_IN_SYSTEM_IBERT_CORE</spirit:name>
+      <spirit:displayName>Include In-System IBERT core</spirit:displayName>
+      <spirit:description>Indicate whether or not the In-System IBERT core should be instantiated in the example design.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_IN_SYSTEM_IBERT_CORE" spirit:choiceRef="choice_pairs_4e550952" spirit:order="157">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_TX_USER_CLOCKING</spirit:name>
+      <spirit:displayName>Include simple transmitter user clocking network in the</spirit:displayName>
+      <spirit:description>Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_TX_USER_CLOCKING" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="158">EXAMPLE_DESIGN</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_RX_USER_CLOCKING</spirit:name>
+      <spirit:displayName>Include simple receiver user clocking network in the</spirit:displayName>
+      <spirit:description>Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_RX_USER_CLOCKING" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="159">EXAMPLE_DESIGN</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCATE_USER_DATA_WIDTH_SIZING</spirit:name>
+      <spirit:displayName>Include user data width sizing in the</spirit:displayName>
+      <spirit:description>Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCATE_USER_DATA_WIDTH_SIZING" spirit:choiceRef="choice_pairs_93c2d4ee" spirit:order="160">EXAMPLE_DESIGN</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ORGANIZE_PORTS_BY</spirit:name>
+      <spirit:displayName>In the example design, organize ports across multiple channels by</spirit:displayName>
+      <spirit:description>If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel)</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ORGANIZE_PORTS_BY" spirit:choiceRef="choice_pairs_f05b8192" spirit:order="161">NAME</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRESET</spirit:name>
+      <spirit:displayName>Transceiver configuration preset</spirit:displayName>
+      <spirit:description>You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRESET" spirit:choiceRef="choice_pairs_5d4d976c" spirit:order="162">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PRESET</spirit:name>
+      <spirit:displayName>Transceiver configuration preset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERNAL_PRESET" spirit:order="163">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_USAGE_UPDATED</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_USAGE_UPDATED" spirit:order="164">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_USAGE_UPDATED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLEMENT_UPDATED</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED" spirit:order="165">23</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLEMENT_UPDATED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_CHANNEL_SITES_UPDATED</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_CHANNEL_SITES_UPDATED" spirit:order="166">5</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_CHANNEL_SITES_UPDATED">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_CHANNEL_COLUMN_LOC_MAX</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_CHANNEL_COLUMN_LOC_MAX" spirit:order="167">96</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_CHANNEL_COLUMN_LOC_MAX">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_RX_COMMA_PRESET_UPDATE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_RX_COMMA_PRESET_UPDATE" spirit:order="168">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_RX_COMMA_PRESET_UPDATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_UPDATE_IP_SYMBOL_drpclk_in</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_UPDATE_IP_SYMBOL_drpclk_in" spirit:order="169">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_UPDATE_IP_SYMBOL_drpclk_in">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_QPLL_ENABLE</spirit:name>
+      <spirit:displayName>Enable secondary QPLL</spirit:displayName>
+      <spirit:description>Enable and configure the QPLL which is not used in this core configuration</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_QPLL_ENABLE" spirit:order="170">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_QPLL_LINE_RATE</spirit:name>
+      <spirit:displayName>Line rate of second core (Gb/s)</spirit:displayName>
+      <spirit:description>Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_QPLL_LINE_RATE" spirit:order="171" spirit:minimum="0.5" spirit:maximum="28.21">10.3125</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.SECONDARY_QPLL_LINE_RATE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_QPLL_FRACN_NUMERATOR</spirit:name>
+      <spirit:displayName>Fractional part of QPLL feedback divider</spirit:displayName>
+      <spirit:description>For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_QPLL_FRACN_NUMERATOR" spirit:order="172" spirit:minimum="0" spirit:maximum="16777215" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.SECONDARY_QPLL_FRACN_NUMERATOR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_QPLL_REFCLK_FREQUENCY</spirit:name>
+      <spirit:displayName>Actual Reference clock frequency (MHz)</spirit:displayName>
+      <spirit:description>Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_QPLL_REFCLK_FREQUENCY" spirit:choiceRef="choice_list_98c4d361" spirit:order="173">257.8125</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.SECONDARY_QPLL_REFCLK_FREQUENCY">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TXPROGDIV_FREQ_ENABLE</spirit:name>
+      <spirit:displayName>Enable selectable TXOUTCLK frequency</spirit:displayName>
+      <spirit:description>Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency</spirit:description>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.TXPROGDIV_FREQ_ENABLE" spirit:order="174">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TXPROGDIV_FREQ_SOURCE</spirit:name>
+      <spirit:displayName>Programmable divider clock source</spirit:displayName>
+      <spirit:description>Select which PLL source is used to generate the selectable TXOUTCLK frequency</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TXPROGDIV_FREQ_SOURCE" spirit:choiceRef="choice_list_3c2e0592" spirit:order="175">QPLL1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.TXPROGDIV_FREQ_SOURCE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TXPROGDIV_FREQ_VAL</spirit:name>
+      <spirit:displayName>TXOUTCLK frequency (MHz)</spirit:displayName>
+      <spirit:description>Select the TXOUTCLK frequency to be generated by the TX programmable divider</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.TXPROGDIV_FREQ_VAL" spirit:choiceRef="choice_list_2170b2c2" spirit:order="176">400</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.TXPROGDIV_FREQ_VAL">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SATA_TX_BURST_LEN</spirit:name>
+      <spirit:displayName>TX COM sequence burst length</spirit:displayName>
+      <spirit:description>Select the number of bursts that make up a SATA COM sequence</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SATA_TX_BURST_LEN" spirit:choiceRef="choice_list_be18be20" spirit:order="177">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FREERUN_FREQUENCY</spirit:name>
+      <spirit:displayName>Free-running and DRP clock frequency (MHz)</spirit:displayName>
+      <spirit:description>Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREERUN_FREQUENCY" spirit:order="178" spirit:minimum="3.125" spirit:maximum="250">100</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INCLUDE_CPLL_CAL</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.INCLUDE_CPLL_CAL" spirit:order="179" spirit:minimum="0" spirit:maximum="3" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USER_GTPOWERGOOD_DELAY_EN</spirit:name>
+      <spirit:description>Select 1 to enable powergood delay circuit</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_GTPOWERGOOD_DELAY_EN" spirit:order="180" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DISABLE_LOC_XDC</spirit:name>
+      <spirit:description>Select to disable generation of LOC constraints in xdc</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DISABLE_LOC_XDC" spirit:order="181" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_COMMON_USRCLK</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_COMMON_USRCLK" spirit:order="182" spirit:minimum="0" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USB_ENABLE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USB_ENABLE" spirit:order="183">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_64BIT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_64BIT" spirit:order="184">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_GEN4_EIOS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_GEN4_EIOS" spirit:order="185">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BGBYPASSB_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGBYPASSB_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BGBYPASSB_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BGMONITORENB_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGMONITORENB_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BGMONITORENB_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BGPDB_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGPDB_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BGPDB_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BGRCALOVRD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGRCALOVRD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BGRCALOVRD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTGREFCLK0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTGREFCLK0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTGREFCLK0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTGREFCLK1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTGREFCLK1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTGREFCLK1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLK00_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK00_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLK00_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLK01_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK01_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLK01_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLK10_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK10_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLK10_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLK11_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK11_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLK11_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PMARSVD0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVD0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PMARSVD0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PMARSVD1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVD1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PMARSVD1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0PD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0PD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0PD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1PD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1PD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1PD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLLRSVD1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLLRSVD1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLLRSVD2_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD2_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLLRSVD2_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLLRSVD3_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD3_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLLRSVD3_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLLRSVD4_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLRSVD4_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLLRSVD4_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RCALENB_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RCALENB_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RCALENB_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM0DATA_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0DATA_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM0DATA_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM0RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM0RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM0WIDTH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0WIDTH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM0WIDTH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM1DATA_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1DATA_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM1DATA_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM1RESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1RESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM1RESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM1WIDTH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1WIDTH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM1WIDTH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TCONGPI_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONGPI_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TCONGPI_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TCONPOWERUP_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONPOWERUP_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TCONPOWERUP_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TCONRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TCONRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBDO_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDO_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBDO_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBDRDY_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDRDY_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBDRDY_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBENABLE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBENABLE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBENABLE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBGPI_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBGPI_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBGPI_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBINTR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBINTR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBINTR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBIOLMBRST_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBIOLMBRST_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBIOLMBRST_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMBRST_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMBRST_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMBRST_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMREGEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMREGEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMREGEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMTCK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTCK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMTCK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMTDI_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDI_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMTDI_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TCONGPO_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONGPO_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TCONGPO_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBDADDR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDADDR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBDADDR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBDEN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDEN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBDEN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBDI_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDI_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBDI_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBDWE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBDWE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBDWE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBMDMTDO_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDO_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBMDMTDO_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_UBTXUART_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBTXUART_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_UBTXUART_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CDRSTEPSX_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CDRSTEPSX_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CDRSTEPSX_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CFGRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CFGRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CFGRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CLKRSVD0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CLKRSVD0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CLKRSVD0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CLKRSVD1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CLKRSVD1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CLKRSVD1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DMONFIFORESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONFIFORESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DMONFIFORESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DMONITORCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONITORCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DMONITORCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPADDR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPADDR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPADDR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPDI_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDI_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPDI_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPRST_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPRST_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPRST_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPWE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPWE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPWE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EYESCANMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EYESCANMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EYESCANRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EYESCANRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_FREQOS_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_FREQOS_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_FREQOS_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTGREFCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTGREFCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTGREFCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTHRXN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHRXN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTHRXN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTHRXP_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHRXP_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTHRXP_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLK0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLK0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLK1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLK1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTRESETSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRESETSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTRESETSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTRSVD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRSVD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTRSVD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTRXRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRXRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTRXRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTTXRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTTXRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTTXRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_INCPCTRL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_INCPCTRL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_INCPCTRL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTYRXN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYRXN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTYRXN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTYRXP_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYRXP_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTYRXP_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_LOOPBACK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_LOOPBACK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_LOOPBACK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_LOOPRSVD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_LOOPRSVD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_LOOPRSVD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCSRSVDIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCSRSVDIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCSRSVDIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PMARSVDIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PMARSVDIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PMARSVDIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0CLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0CLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0CLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1CLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1CLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1CLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RESETOVRD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RESETOVRD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RESETOVRD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RSTCLKENTX_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RSTCLKENTX_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RSTCLKENTX_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RX8B10BEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RX8B10BEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RX8B10BEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXBUFRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBUFRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXBUFRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDRHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDRHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDRRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDRRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHBONDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHBONDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHBONDI_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDI_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHBONDI_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCKCALRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCKCALRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCKCALRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCKCALSTART_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCKCALSTART_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCKCALSTART_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEVSEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVSEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEVSEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDLYEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDLYEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDLYSRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDLYSRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXEQTRAINING_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXEQTRAINING_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXEQTRAINING_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLATCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLATCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLATCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXMONITORSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXMONITORSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXMONITORSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOOBRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOOBRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOOBRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSCALRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSCALRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSCALRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTCFG_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTCFG_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTCFG_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPCSRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPCSRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPCSRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHALIGN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHALIGN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHDLYPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHDLYPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPMARESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPMARESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPMARESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPOLARITY_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPOLARITY_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPOLARITY_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPRBSSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPRBSSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXQPIEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXQPIEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXQPIEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRATE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRATE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRATE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRATEMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRATEMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRATEMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIDE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIDE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIDE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIPPMA_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPPMA_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIPPMA_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSYNCIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSYNCIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSYNCMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSYNCMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXTERMINATION_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXTERMINATION_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXTERMINATION_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXUSERRDY_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXUSERRDY_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXUSERRDY_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXUSRCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXUSRCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXUSRCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXUSRCLK2_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXUSRCLK2_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXUSRCLK2_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TSTIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TSTIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TSTIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TX8B10BEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TX8B10BEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TX8B10BEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCOMINIT_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMINIT_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCOMINIT_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCOMSAS_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMSAS_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCOMSAS_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCOMWAKE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMWAKE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCOMWAKE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCTRL0_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCTRL0_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCTRL0_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCTRL1_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCTRL1_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCTRL1_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCTRL2_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCTRL2_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCTRL2_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDATA_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDATA_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDATA_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDCCRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDCCRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDCCRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDEEMPH_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDEEMPH_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDEEMPH_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDETECTRX_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDETECTRX_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDETECTRX_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDIFFPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDIFFPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDIFFPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYSRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYSRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYSRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXELECIDLE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXELECIDLE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXELECIDLE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXELFORCESTART_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXELFORCESTART_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXELFORCESTART_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXHEADER_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXHEADER_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXHEADER_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXINHIBIT_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXINHIBIT_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXINHIBIT_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXLATCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLATCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXLATCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXMARGIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMARGIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXMARGIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXONESZEROS_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXONESZEROS_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXONESZEROS_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPCSRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPCSRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPCSRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHALIGN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHALIGN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHALIGN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHDLYPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHDLYPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHDLYPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHINIT_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHINIT_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHINIT_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPIPPMEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPIPPMEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPIPPMPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPIPPMPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPISOPD_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPISOPD_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPISOPD_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPMARESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPMARESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPMARESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPOLARITY_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPOLARITY_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPOLARITY_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPRBSSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRBSSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPRBSSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPRECURSOR_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRECURSOR_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPRECURSOR_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXRATE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRATE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXRATE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXRATEMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRATEMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXRATEMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSEQUENCE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSEQUENCE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSEQUENCE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSWING_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSWING_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSWING_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSYNCIN_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCIN_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSYNCIN_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSYNCMODE_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCMODE_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSYNCMODE_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXUSERRDY_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXUSERRDY_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXUSERRDY_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXUSRCLK_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXUSRCLK_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXUSRCLK_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXUSRCLK2_IN</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXUSRCLK2_IN" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXUSRCLK2_IN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BUFGTCE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTCE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BUFGTCE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BUFGTDIV_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTDIV_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BUFGTDIV_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BUFGTRESET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTRESET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BUFGTRESET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLLOCK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLLOCK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DMONITOROUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONITOROUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DMONITOROUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPDO_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPDO_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPDO_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_DRPRDY_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_DRPRDY_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_DRPRDY_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTHTXN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHTXN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTHTXN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTHTXP_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTHTXP_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTHTXP_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTYTXN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYTXN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTYTXN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_GTYTXP_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTYTXP_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_GTYTXP_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PHYSTATUS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PHYSTATUS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PHYSTATUS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_POWERPRESENT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_POWERPRESENT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_POWERPRESENT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCHBONDO_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCHBONDO_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCHBONDO_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCOMMADET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMMADET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCOMMADET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCTRL0_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL0_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCTRL0_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCTRL1_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL1_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCTRL1_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCTRL2_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL2_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCTRL2_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXCTRL3_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXCTRL3_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXCTRL3_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDATA_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDATA_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDATA_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDATAVALID_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDATAVALID_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDATAVALID_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXELECIDLE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXELECIDLE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXELECIDLE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXHEADER_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXHEADER_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXHEADER_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOUTCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOUTCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPRBSERR_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSERR_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPRBSERR_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXQPISENN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXQPISENN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXQPISENN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXQPISENP_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXQPISENP_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXQPISENP_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRATEDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRATEDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRATEDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXRESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXRESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXRESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSTATUS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSTATUS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSTATUS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_RXVALID_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXVALID_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_RXVALID_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDCCDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDCCDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDCCDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXOUTCLK_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLK_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXOUTCLK_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXQPISENN_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPISENN_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXQPISENN_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXQPISENP_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXQPISENP_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">-1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXQPISENP_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXRATEDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRATEDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXRATEDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXRESETDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXRESETDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXRESETDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="PARAM_VALUE.INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT" spirit:minimum="-1" spirit:maximum="2" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xdma_pcie4_ip_gt</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>UltraScale FPGAs Transceivers Wizard</xilinx:displayName>
+      <xilinx:coreRevision>9</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CHANNEL_ENABLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DISABLE_LOC_XDC" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_OPTIONAL_PORTS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FREERUN_FREQUENCY" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_TYPE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_CPLL_CAL" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INS_LOSS_NYQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCATE_COMMON" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCATE_RESET_CONTROLLER" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCATE_TX_BUFFER_BYPASS_CONTROLLER" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCATE_USER_DATA_WIDTH_SIZING" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCIE_CORECLK_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCIE_ENABLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCIE_GEN4_EIOS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCIE_USERCLK_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_CC_KEEP_IDLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_CC_K_0_0" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_CC_LEN_SEQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_CC_NUM_SEQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_CC_VAL_0_0" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_COMMA_M_ENABLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_COMMA_PRESET" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_COMMA_P_ENABLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_DATA_DECODING" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_EQ_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_JTOL_FC" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_LINE_RATE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_MASTER_CHANNEL" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_PLL_TYPE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_PPM_OFFSET" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_REFCLK_FREQUENCY" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_SLIDE_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_USER_DATA_WIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SIM_CPLL_CAL_BYPASS" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TXPROGDIV_FREQ_ENABLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_BUFFER_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_DATA_ENCODING" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_DIFF_SWING_EMPH_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_LINE_RATE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_MASTER_CHANNEL" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_PLL_TYPE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_REFCLK_FREQUENCY" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_USER_DATA_WIDTH" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="86239c52"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="240e62dd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="81cdd016"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="22678636"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xci b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xci
new file mode 100644
index 0000000..f632fb1
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xci
@@ -0,0 +1,1508 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH">62</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ACS_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ACS_EXT_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AWS_MODE_VALUE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI4_CC_TUSER_WIDTH">33</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI4_CQ_TUSER_WIDTH">88</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI4_DATA_WIDTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI4_RC_TUSER_WIDTH">75</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXI4_RQ_TUSER_WIDTH">62</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE">0x1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.AXISTEN_IF_MSIX_RX_PARITY_EN">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.BROADCOM_SBR_WA">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_CTL_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_EXT_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_MGMT_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_PM_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_STATUS_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CFG_TX_MSG_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMPLETER_MODEL">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CRM_CORE_CLK_FREQ_500">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CRM_USER_CLK_FREQ">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CTRL_SKIP_MASK">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEDICATE_PERST">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DSN_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_AUTO_RXEQ">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_SYS_CLK_BUFG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FREE_RUN_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GEN4_EIEOS_0S7">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GTCOM_IN_CORE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GTWIZ_IN_CORE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.GT_DRP_CLK_SRC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.INS_LOSS_PROFILE">ADD-IN_CARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_BOARD_PROJECT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LEGACY_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LL_RX_TLP_PARITY_GEN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LL_TX_TLP_PARITY_CHK">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MASTER_GT_CONTAINER">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MASTER_GT_QUAD_INX">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_ENABLEMENT">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MCAP_FPGA_BITSTREAM_VERSION">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_INT">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MSI_X_OPTIONS">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MULT_PF_DES">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE4_DRP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_CONFIGURATION">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_FAST_CONFIG">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PCIE_ID_IF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PER_FUNC_STATUS_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR">0x1C0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR">0x1C0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE">0x009</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR0_CONTROL">0x4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR1_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR2_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR3_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR4_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_BAR5_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER">0x40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_CLASS_CODE">0x070001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEVICE_ID">0x9038</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE">0x3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR">0x1C0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_INTERRUPT_PIN">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR">0x70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR">0x70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_MSI_CAP_PERVECMASKCAP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PCIE_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR">0x48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_0">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_1">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_2">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_3">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_4">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_5">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR0_LOWER">0x0000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR0_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR1_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR1_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR2_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR2_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR3_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR3_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR4_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR4_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR5_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR5_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_RBAR_NUM_BAR">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SECONDARY_PCIE_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_APERTURE_SIZE">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR1_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR3_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_APERTURE_SIZE">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_BAR5_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_TOTAL_VF">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">0x00000553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_TPHR_CAP_VER">0x1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF0_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ARI_CAP_NEXT_FUNC">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE">0x009</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR0_CONTROL">0x4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR1_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR2_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER">0x40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CLASS_CODE">0x058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEVICE_ID">0x9011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEV_CAP_MAX_PAYLOAD_SIZE">0x3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_INTERRUPT_PIN">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR">0x70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_NEXTPTR">0x70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSI_CAP_PERVECMASKCAP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIE_CAP_NEXTPTR">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR">0x70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_0">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_1">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_2">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_3">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_4">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_5">0x7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR0_LOWER">0x0000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR0_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR1_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR1_UPPER">0x0000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR2_UPPER">0x0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR3_LOWER">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR3_UPPER">0x0000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF3_PM_CAP_NEXTPTR">0x70</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF3_TPHR_CAP_ST_MODE_SEL">0x0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_DISABLE_LANE_REVERSAL">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PM_ENABLE_L23_ENTRY">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.QDMA_TPH_MSIX_BRAMS_DIS">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RBAR_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RCV_MSG_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELECT_QUAD">GTY_Quad_227</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPARE_WORD1">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_CAP_ENABLE">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_EXD_MODE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYS_RESET_POLARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.THREE_PORT_SWITCH">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL2CFG_IF_PARITY_CHK">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_CD">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PD">0x3E0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_CREDITS_PH">0x20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TRANSCEIVER_CTRL_STATUS_PORTS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TWO_PORT_CONFIG">X8G3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TWO_PORT_SWITCH">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TX_FC_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_STANDARD_INTERFACES">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER">0x70</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF0_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF3_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG0_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG1_MSIX_CAP_PBA_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG1_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG1_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG1_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG2_MSIX_CAP_PBA_BIR">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG2_MSIX_CAP_TABLE_BIR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG2_MSIX_CAP_TABLE_OFFSET">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VFG2_MSIX_CAP_TABLE_SIZE">0x000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VU9P_BOARD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y0_xdc">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y1_xdc">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y4_xdc">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x0y5_xdc">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x1y0_xdc">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gen_x1y5_xdc">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_blk_locn">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_revision">Beta</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axisten_if_enable_msg_route">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.coreclk_freq">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_transceiver_status_ports">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.enable_jtag_dbg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.enable_ltssm_dbg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.ins_loss_profile">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE">Address_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_EXT_512_CC_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_EXT_512_CQ_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_EXT_512_RQ_STRADDLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xdma_pcie4_ip</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MASTER_GT">GTHE4_CHANNEL_X49Y99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_X_OPTIONS">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_CLASS_CODE">070001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID">9038</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN">INTA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID">9011</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">BAR_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">BAR_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_PPM_OFFSET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_SSC_PPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_FIRST_VF_OFFSET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYS_RST_N_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TL_PF_ENABLE_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG0_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG0_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG0_MSIX_CAP_TABLE_SIZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG1_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG1_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG1_MSIX_CAP_TABLE_SIZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG2_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG2_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG2_MSIX_CAP_TABLE_SIZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG3_MSIX_CAP_PBA_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG3_MSIX_CAP_TABLE_OFFSET">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VFG3_MSIX_CAP_TABLE_SIZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.acs_ext_cap_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.alignment_mode_256b">DWORD_Aligned</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aws_mode_value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_client_tag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">20000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route_override">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_rx_msg_intfc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_width">256_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bmd_pio_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.broadcom_sbr_wa">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ctl_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_pm_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_tx_msg_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.completer_model">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_ctrl_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_fc_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_mgmt_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_pwr_mgmt_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_status_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.config_tx_mesg_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.copy_pf0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.copy_sriov_pf0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.coreclk_freq">500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ctrl_skip_mask">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dbg_checker">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dedicate_perst">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.descrambler_pipe_debug_signals">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.descrambler_user_interface_signals">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dis_gt_wizard">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_bram_pipeline">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_eq_synchronizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_gt_loc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_user_clock_root">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disconnect_hot_reset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dma_2rp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.double_quad">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dbg_descramble">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_gt_selection">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_l23_entry">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_msi_per_vec_masking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_parity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_conf">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pl_ifc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_usp_ct1h">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_auto_rxeq">False</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_clkmux">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_code">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_epyc_chipset_fix">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_gen4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ibert">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_jtag_dbg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ltssm_dbg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_mark_debug">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_more_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_msix_32vec">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_multi_pcie">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_multipf_aer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.exdes_simulation_tab">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_startup_primitive">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_sys_clk_bufg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_xvc_vsec_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.extended_tag_field">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.free_run_freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen4_eieos_0s7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x0y5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x1y0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x1y1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x1y2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x1y3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x1y4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_x1y5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_drp_clk_src">Internal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtcom_in_core">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ins_loss_profile">Add-in_Card</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.interrupt_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ku15p_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ku15p_gt_long_route">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.legacy_ext_pcie_cfg_space_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.link_training_signals">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.local_test">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.master_cal_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_enablement">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Advanced</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_type">HARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mult_pf_des">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X1Y2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_id_if">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.per_func_status_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.perf_level">Extreme</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">07</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dev_cap_max_payload">1024_bytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_dsn_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">16450_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_tphr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vc_cap_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_size">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_base_class_menu">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_msi_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_size">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_base_class_menu">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_msi_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.plltype">QPLL1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.qdma_tph_msix_brams_dis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rbar_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcv_msg_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rx_mesg_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.select_quad">GTY_Quad_227</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.set_finite_credit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sriov_exd_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_reset_polarity">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.testname">sample_smoke_test0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.three_port_switch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_credits_cd">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_credits_ch">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_tx_mux_strict_priority">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.transmit_fc_interface">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.two_port_config">X8G3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.two_port_switch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tx_fc_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.type1_membase_memlimit_enable">Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.type1_prefetchable_membase_memlimit">64bit_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_msix_pfs_for_vfs">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_standard_interfaces">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.user_interface_signals">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu9p_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">AU200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INS_LOSS_NYQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_CLASS_CODE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_REVISION_ID" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PHY_LP_TXPRESET" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.REF_CLK_FREQ" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_SSC_PPM" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.acs_ext_cap_enable" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.aspm_support" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_enable_client_tag" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_enable_msg_route" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_enable_msg_route_override" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_width" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.broadcom_sbr_wa" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cfg_ext_if" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.coreclk_freq" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ctrl_skip_mask" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dedicate_perst" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.device_port_type" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_bram_pipeline" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_eq_synchronizer" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_gt_loc" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_user_clock_root" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_dbg_descramble" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_ext_ch_gt_drp" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_ext_clk" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_gt_selection" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_l23_entry" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_parity" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_pcie_drp" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_transceiver_status_ports" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_auto_rxeq" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_code" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_epyc_chipset_fix" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_gen4" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_ibert" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_jtag_dbg" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_ltssm_dbg" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_mark_debug" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_more_clk" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_msix_32vec" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_multi_pcie" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_startup_primitive" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_sys_clk_bufg" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_xvc_vsec_enable" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.extended_tag_field" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.free_run_freq" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gen4_eieos_0s7" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_drp_clk_src" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gtcom_in_core" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gtwiz_in_core" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ins_loss_profile" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.local_test" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.master_cal_only" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mcap_enablement" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mode_selection" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.msix_type" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_blk_locn" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_id_if" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_64bit" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_scale" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_size" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar2_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar3_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar4_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar5_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_base_class_menu" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_base" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_interface" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_sub" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msi_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_num" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar1_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar2_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar3_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar4_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar5_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_num" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar0_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar1_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar2_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar3_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar4_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar5_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_num" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar0_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar1_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar2_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar3_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar4_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar5_index" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_num" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pipe_sim" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.rbar_enable" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.set_finite_credit" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.sys_reset_polarity" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.tl_credits_cd" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.tl_credits_ch" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.tl_tx_mux_strict_priority" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.vendor_id" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.vu9p_board" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xlnx_ref_board" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;pci_exp_txn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_txp&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_rxn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_rxp&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;user_clk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;user_reset&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;user_lnk_up&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_rq_tdata&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_rq_tkeep&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_rq_tlast&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_rq_tready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_rq_tuser&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;61&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_rq_tvalid&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;0&quot;},&quot;m_axis_rc_tdata&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_rc_tkeep&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_rc_tlast&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_rc_tready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_rc_tuser&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;74&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_rc_tvalid&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_cq_tdata&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_cq_tkeep&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_cq_tlast&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_cq_tready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_cq_tuser&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;87&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_cq_tvalid&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_cc_tdata&quot;:{&quot;dire
+ction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_cc_tkeep&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_cc_tlast&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_cc_tready&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_cc_tuser&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_cc_tvalid&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_seq_num0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_seq_num_vld0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_seq_num1&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_seq_num_vld1&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_tag0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_tag1&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_tag_av&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_rig
+ht&quot;:&quot;0&quot;},&quot;pcie_rq_tag_vld0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_rq_tag_vld1&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_tfc_nph_av&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_tfc_npd_av&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_cq_np_req&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pcie_cq_np_req_count&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_phy_link_down&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_phy_link_status&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_negotiated_width&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_current_speed&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_max_payload&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_max_read_req&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_function_status&quot;:{
+&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_function_power_state&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_status&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;503&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_power_state&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;755&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_link_power_state&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_addr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;9&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_function_number&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_write&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_write_data&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_byte_enable&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_read&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_read_data&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_read_write_done&quot;:{&quot;directio
+n&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_debug_access&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_err_cor_out&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_err_nonfatal_out&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_err_fatal_out&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_local_error_valid&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_local_error_out&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_ltssm_state&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_rx_pm_state&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_tx_pm_state&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_rcb_status&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_obff_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_pl_status_change&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:
+&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_tph_requester_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_tph_st_mode&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_tph_requester_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;251&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_tph_st_mode&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;755&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_received&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_received_data&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_received_type&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_transmit&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_transmit_type&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_transmit_data&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_msg_transmit_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_ph&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left
+&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_pd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_nph&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_npd&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_cplh&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_cpld&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_fc_sel&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_dsn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_bus_number&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_power_state_change_ack&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_power_state_change_interrupt&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_err_cor_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_err_uncor_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_flr_in_process&quot;:{&quot;direction&quot;:
+&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_flr_done&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_flr_in_process&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;251&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_flr_func_num&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_vf_flr_done&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_link_training_enable&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_int&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_pending&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_sent&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_mmenable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_mask_update&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_data&quot;
+:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_select&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_int&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_pending_status&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_pending_status_data_enable&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_pending_status_function_num&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_sent&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_fail&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_attr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_tph_present&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_tph_type&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_
+msi_tph_st_tag&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_interrupt_msi_function_number&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_pm_aspm_l1_entry_reject&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_pm_aspm_tx_l0s_entry_disable&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_hot_reset_out&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_config_space_enable&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_req_pm_transition_l23_ready&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_hot_reset_in&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_ds_port_number&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_ds_bus_number&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_ds_device_number&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_
+right&quot;:&quot;0&quot;},&quot;sys_clk_gt&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_reset&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;phy_rdy_out&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;m_axis_cq&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;88&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_
+permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;m_axis_cq_tdata&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;m_axis_
+cq_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;m_axis_cq_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;m_axis_cq_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TUSER&quot;:{&quot;physical_name&quot;:&quot;m_axis_cq_tuser&quot;,&quot;physical_left&quot;:&quot;87&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;87&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;m_axis_cq_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;s_axis_cc&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;co
+nstant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;33&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;d
+efault&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;s_axis_cc_tdata&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;s_axis_cc_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;s_axis_cc_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;s_axis_cc_tready&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TUSER&quot;:{&quot;physical_name&quot;:&quot;s_axis_cc_tuser&quot;,&quot;physical_left&quot;:&quot;32&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;32&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;s_axis_cc_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;s_axis_rq&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abst
+raction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;62&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;valu
+e_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;s_axis_rq_tdata&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;s_axis_rq_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;s_axis_rq_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;s_axis_rq_tready&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;log
+ical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TUSER&quot;:{&quot;physical_name&quot;:&quot;s_axis_rq_tuser&quot;,&quot;physical_left&quot;:&quot;61&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;61&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;s_axis_rq_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;m_axis_rc&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;75&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;va
+lue&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;m_axis_rc_tdata&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_ri
+ght&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;m_axis_rc_tkeep&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;m_axis_rc_tlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;m_axis_rc_tready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TUSER&quot;:{&quot;physical_name&quot;:&quot;m_axis_rc_tuser&quot;,&quot;physical_left&quot;:&quot;74&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;74&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;m_axis_rc_tvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.sys_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;SYS_RST_N_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PCIE_PERST&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;use
+r&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;sys_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_mgt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie_7x_mgt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie_7x_mgt_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;PCIE_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;rxn&quot;:{&quot;physical_name&quot;:&quot;pci_exp_rxn&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rxp&quot;:{&quot;physical_name&quot;:&quot;pci_exp_rxp&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;txn&quot;:{&quot;physical_name&quot;:&quot;pci_exp_txn&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_r
+ight&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;txp&quot;:{&quot;physical_name&quot;:&quot;pci_exp_txp&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_fc&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie_cfg_fc:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie_cfg_fc_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;CPLD&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_cpld&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CPLH&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_cplh&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;NPD&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_npd&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;NPH&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_nph&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PD&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_pd&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PH&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_ph&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_rig
+ht&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;SEL&quot;:{&quot;physical_name&quot;:&quot;cfg_fc_sel&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_mgmt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_mgmt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_mgmt_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_addr&quot;,&quot;physical_left&quot;:&quot;9&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;9&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_EN&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_byte_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DEBUG_ACCESS&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_debug_access&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;FUNCTION_NUMBER&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_function_number&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_read_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;log
+ical_right&quot;:&quot;0&quot;},&quot;READ_EN&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_WRITE_DONE&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_read_write_done&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_write_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_EN&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_pm&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_pm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_pm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;pm_aspm_l1entry_reject&quot;:{&quot;physical_name&quot;:&quot;cfg_pm_aspm_l1_entry_reject&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;pm_aspm_tx_l0s_entry_disable&quot;:{&quot;physical_name&quot;:&quot;cfg_pm_aspm_tx_l0s_entry_disable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;
+0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_msi&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie3_cfg_msi:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie3_cfg_msi_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;attr&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_attr&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;data&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;enable&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;fail&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_fail&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;function_number&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_function_number&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;int_vector&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_int&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logica
+l_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;mask_update&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_mask_update&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;mmenable&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_mmenable&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;pending_status&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_pending_status&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;pending_status_data_enable&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_pending_status_data_enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;pending_status_function_num&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_pending_status_function_num&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;select&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_select&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;sent&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_se
+nt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;tph_present&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_tph_present&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;tph_st_tag&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_tph_st_tag&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;tph_type&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_msi_tph_type&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_interrupt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie3_cfg_interrupt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie3_cfg_interrupt_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;INTx_VECTOR&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_int&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;PENDING&quot;:{&quot;physical_name&quot;:&quot;cfg_interrupt_pending&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;SENT&quot;:{&quot;physical_name&quot;:&quot;cfg_inte
+rrupt_sent&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_mesg_tx&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie3_cfg_mesg_tx:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie3_cfg_mesg_tx_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;TRANSMIT&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_transmit&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TRANSMIT_DATA&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_transmit_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TRANSMIT_DONE&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_transmit_done&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TRANSMIT_TYPE&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_transmit_type&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_mesg_rcvd&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie3_cfg_msg_received:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie3_cfg_msg_received_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;pa
+rameters&quot;:{},&quot;port_maps&quot;:{&quot;recd&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_received&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;recd_data&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_received_data&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;recd_type&quot;:{&quot;physical_name&quot;:&quot;cfg_msg_received_type&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;4&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_control&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_control:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_control_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;bus_number&quot;:{&quot;physical_name&quot;:&quot;cfg_bus_number&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;config_space_enable&quot;:{&quot;physical_name&quot;:&quot;cfg_config_space_enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ds_bus_number&quot;:{&quot;physical_name&quot;:&quot;cfg_ds_bus_number&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;
+,&quot;logical_right&quot;:&quot;0&quot;},&quot;ds_device_number&quot;:{&quot;physical_name&quot;:&quot;cfg_ds_device_number&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;4&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ds_port_number&quot;:{&quot;physical_name&quot;:&quot;cfg_ds_port_number&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;dsn&quot;:{&quot;physical_name&quot;:&quot;cfg_dsn&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;err_cor_in&quot;:{&quot;physical_name&quot;:&quot;cfg_err_cor_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;err_uncor_in&quot;:{&quot;physical_name&quot;:&quot;cfg_err_uncor_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;flr_done&quot;:{&quot;physical_name&quot;:&quot;cfg_flr_done&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;flr_in_process&quot;:{&quot;physical_name&quot;:&quot;cfg_flr_in_process&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;hot_reset_in&quot;:{&quot;physical_name&quot;:&quot;cfg_hot_reset_in&quot;,&quot;physical_left
+&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;hot_reset_out&quot;:{&quot;physical_name&quot;:&quot;cfg_hot_reset_out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;link_training_enable&quot;:{&quot;physical_name&quot;:&quot;cfg_link_training_enable&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;power_state_change_ack&quot;:{&quot;physical_name&quot;:&quot;cfg_power_state_change_ack&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;power_state_change_interrupt&quot;:{&quot;physical_name&quot;:&quot;cfg_power_state_change_interrupt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;req_pm_transition_l23_ready&quot;:{&quot;physical_name&quot;:&quot;cfg_req_pm_transition_l23_ready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;vf_flr_done&quot;:{&quot;physical_name&quot;:&quot;cfg_vf_flr_done&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;vf_flr_func_num&quot;:{&quot;physical_name&quot;:&quot;cfg_vf
+_flr_func_num&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;vf_flr_in_process&quot;:{&quot;physical_name&quot;:&quot;cfg_vf_flr_in_process&quot;,&quot;physical_left&quot;:&quot;251&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;251&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_cfg_status&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_status:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:display_pcie4:pcie4_cfg_status_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;cq_np_req&quot;:{&quot;physical_name&quot;:&quot;pcie_cq_np_req&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;cq_np_req_count&quot;:{&quot;physical_name&quot;:&quot;pcie_cq_np_req_count&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;current_speed&quot;:{&quot;physical_name&quot;:&quot;cfg_current_speed&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;err_cor_out&quot;:{&quot;physical_name&quot;:&quot;cfg_err_cor_out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;err_fatal_out&quot;:{&quot;physical_name&quot;:&quot;
+cfg_err_fatal_out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;err_nonfatal_out&quot;:{&quot;physical_name&quot;:&quot;cfg_err_nonfatal_out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;function_power_state&quot;:{&quot;physical_name&quot;:&quot;cfg_function_power_state&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;function_status&quot;:{&quot;physical_name&quot;:&quot;cfg_function_status&quot;,&quot;physical_left&quot;:&quot;15&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;15&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;link_power_state&quot;:{&quot;physical_name&quot;:&quot;cfg_link_power_state&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;local_error_out&quot;:{&quot;physical_name&quot;:&quot;cfg_local_error_out&quot;,&quot;physical_left&quot;:&quot;4&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;4&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;local_error_valid&quot;:{&quot;physical_name&quot;:&quot;cfg_local_error_valid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;ltssm_state&quot;:{&quot;physical_name&quot;:&quot;cfg_ltssm_state&quot;,
+&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;max_payload&quot;:{&quot;physical_name&quot;:&quot;cfg_max_payload&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;max_read_req&quot;:{&quot;physical_name&quot;:&quot;cfg_max_read_req&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;negotiated_width&quot;:{&quot;physical_name&quot;:&quot;cfg_negotiated_width&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;obff_enable&quot;:{&quot;physical_name&quot;:&quot;cfg_obff_enable&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;phy_link_down&quot;:{&quot;physical_name&quot;:&quot;cfg_phy_link_down&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;phy_link_status&quot;:{&quot;physical_name&quot;:&quot;cfg_phy_link_status&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;pl_status_change&quot;:{&quot;physical_name&quot;:&quot;cfg_pl_status_change&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;
+:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rcb_status&quot;:{&quot;physical_name&quot;:&quot;cfg_rcb_status&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_seq_num0&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_seq_num0&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_seq_num1&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_seq_num1&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_seq_num_vld0&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_seq_num_vld0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_seq_num_vld1&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_seq_num_vld1&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_tag0&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_tag0&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_tag1&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_tag1&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_tag_av&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_tag_av&quot;,&quot;physical_lef
+t&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_tag_vld0&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_tag_vld0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rq_tag_vld1&quot;:{&quot;physical_name&quot;:&quot;pcie_rq_tag_vld1&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rx_pm_state&quot;:{&quot;physical_name&quot;:&quot;cfg_rx_pm_state&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;tph_requester_enable&quot;:{&quot;physical_name&quot;:&quot;cfg_tph_requester_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;tph_st_mode&quot;:{&quot;physical_name&quot;:&quot;cfg_tph_st_mode&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;tx_pm_state&quot;:{&quot;physical_name&quot;:&quot;cfg_tx_pm_state&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;vf_power_state&quot;:{&quot;physical_name&quot;:&quot;cfg_vf_power_state&quot;,&quot;physical_left&quot;:&quot;755&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;755&quot;,&quot;logical_r
+ight&quot;:&quot;0&quot;},&quot;vf_status&quot;:{&quot;physical_name&quot;:&quot;cfg_vf_status&quot;,&quot;physical_left&quot;:&quot;503&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;503&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;vf_tph_requester_enable&quot;:{&quot;physical_name&quot;:&quot;cfg_vf_tph_requester_enable&quot;,&quot;physical_left&quot;:&quot;251&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;251&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;vf_tph_st_mode&quot;:{&quot;physical_name&quot;:&quot;cfg_vf_tph_st_mode&quot;,&quot;physical_left&quot;:&quot;755&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;755&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie4_transmit_fc&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie3_transmit_fc:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie3_transmit_fc_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;npd_av&quot;:{&quot;physical_name&quot;:&quot;pcie_tfc_npd_av&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;nph_av&quot;:{&quot;physical_name&quot;:&quot;pcie_tfc_nph_av&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.sys_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,
+&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;sys_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.sys_clk_gt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_ty
+pe&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;sys_clk_gt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.user_clk&quot;
+:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;125000000&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;user_reset&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;us
+er_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.user_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;user_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml
new file mode 100644
index 0000000..26fa7a1
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_0/xdma_pcie4_ip.xml
@@ -0,0 +1,28293 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>xdma_pcie4_ip</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>m_axis_cq</spirit:name>
+      <spirit:displayName>m_axis_cq</spirit:displayName>
+      <spirit:description>The Completer Request interface is used to transmit Completion TLP&apos;s to the Client Application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH">88</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_cc</spirit:name>
+      <spirit:displayName>s_axis_cc</spirit:displayName>
+      <spirit:description>The Completer Completion Interface is used to transmit Completion TLP&apos;s</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH">33</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_rq</spirit:name>
+      <spirit:displayName>s_axis_rq</spirit:displayName>
+      <spirit:description>The Requestor Request interface received requests TLP&apos;s from the Client Application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH">62</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axis_rc</spirit:name>
+      <spirit:displayName>m_axis_rc</spirit:displayName>
+      <spirit:description>The Requestor Completer interface transmits completions to the client application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH">75</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.sys_rst</spirit:name>
+      <spirit:displayName>RST.sys_rst</spirit:displayName>
+      <spirit:description>sys_rst interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.BOARD.ASSOCIATED_PARAM">SYS_RST_N_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">PCIE_PERST</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_mgt</spirit:name>
+      <spirit:displayName>pcie_7x_mgt</spirit:displayName>
+      <spirit:description>PCIExpress Serial Link Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_7x_mgt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_7x_mgt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_rxn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxp</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_rxp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_txn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txp</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_txp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PCIE4_MGT.BOARD.ASSOCIATED_PARAM">PCIE_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_mgt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 1)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_fc</spirit:name>
+      <spirit:displayName>pcie_cfg_fc</spirit:displayName>
+      <spirit:description>Configuration Flow Control INTERFACE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CPLD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_cpld</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CPLH</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_cplh</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NPD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_npd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NPH</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_nph</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PD</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_pd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PH</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_ph</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SEL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_sel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_fc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_FC_IF&apos;)) = &quot;TRUE&quot; )">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_mgmt</spirit:name>
+      <spirit:displayName>pcie4_cfg_mgmt</spirit:displayName>
+      <spirit:description>PCIE Configuration Management Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_mgmt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_mgmt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEBUG_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_debug_access</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FUNCTION_NUMBER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_WRITE_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_write_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mgmt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_MGMT_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_mgmt_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_mgmt</spirit:displayName>
+      <spirit:description>PCIE Configuration Management Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_mgmt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_mgmt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEBUG_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_debug_access</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FUNCTION_NUMBER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_WRITE_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_write_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mgmt_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_MGMT_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_pm</spirit:name>
+      <spirit:displayName>pcie4_cfg_pm</spirit:displayName>
+      <spirit:description>PCIE4 Power Management Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_pm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_pm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pm_aspm_l1entry_reject</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pm_aspm_l1_entry_reject</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pm_aspm_tx_l0s_entry_disable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pm_aspm_tx_l0s_entry_disable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_pm" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_PM_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msi</spirit:name>
+      <spirit:displayName>pcie4_cfg_msi</spirit:displayName>
+      <spirit:description>PCIE MSI interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msi" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msi_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>attr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_attr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask_update</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_mask_update</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mmenable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_mmenable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pending_status_data_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_pending_status_data_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pending_status_function_num</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_pending_status_function_num</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>select</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_select</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_present</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_present</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_tag</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_st_tag</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_type</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msi" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) != &quot;MSI-X_Internal&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msix_internal</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_internal</spirit:displayName>
+      <spirit:description>PCIE MSIx Int Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_internal" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_internal_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>attr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_attr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mint_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_present</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_present</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_tag</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_st_tag</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_type</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_internal" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) = &quot;MSI-X_Internal&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msix_internal_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_internal</spirit:displayName>
+      <spirit:description>PCIE MSIx Int Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>attr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_attr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mint_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_present</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_present</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_tag</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_st_tag</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_type</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_internal_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) = &quot;MSI-X_Internal&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_external_msix</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix_without_msi</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_external_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_external_msix_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_EN&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) = &quot;MSI-X_External&quot;  and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_external_msix_without_msi_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix_without_msi</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix_without_msi_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_EN&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) = &quot;MSI-X_External&quot;  and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msix_external</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix_with_msi</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_external" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_external_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_external" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) = &quot;MSI-X_External&quot;  and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_external_msix_with_msi_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix_with_msi</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix_with_msi_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_EN&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_X_OPTIONS&apos;)) = &quot;MSI-X_External&quot;  and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_interrupt</spirit:name>
+      <spirit:displayName>pcie4_cfg_interrupt</spirit:displayName>
+      <spirit:description>PCIE Legacy Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_interrupt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTx_VECTOR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PENDING</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_pending</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SENT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_ext</spirit:name>
+      <spirit:displayName>pcie4_cfg_ext</spirit:displayName>
+      <spirit:description>Configuration Extend Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_ext" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_ext_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read_data_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_read_data_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read_received</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_read_received</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>register_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_register_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_byte_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_write_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_write_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_received</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_write_received</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_ext" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EXTENDED_CFG_EXTEND_INTERFACE_ENABLE&apos;)) = &quot;TRUE&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.LEGACY_CFG_EXTEND_INTERFACE_ENABLE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_rbar</spirit:name>
+      <spirit:displayName>pcie4_rbar</spirit:displayName>
+      <spirit:description>Resizable bar Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_rbar" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_rbar_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bar_size</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_bar_size</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar5</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_rbar" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RBAR_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_mesg_tx</spirit:name>
+      <spirit:displayName>pcie4_cfg_mesg_tx</spirit:displayName>
+      <spirit:description>Configuration Transmit Message Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_mesg_tx" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_mesg_tx_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT_TYPE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_type</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mesg_tx" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_TX_MSG_IF&apos;)) = &quot;TRUE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_mesg_rcvd</spirit:name>
+      <spirit:displayName>pcie4_cfg_mesg_rcvd</spirit:displayName>
+      <spirit:description>Configuration Received Message Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msg_received" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msg_received_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>recd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_received</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>recd_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_received_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>recd_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_received_type</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mesg_rcvd" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RCV_MSG_IF&apos;)) = &quot;TRUE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_control</spirit:name>
+      <spirit:displayName>pcie4_cfg_control</spirit:displayName>
+      <spirit:description>It allows a broad range of information exchange between user application and the core</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_control" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_control_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bus_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_bus_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>config_space_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_config_space_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_bus_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_bus_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_device_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_device_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_port_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_port_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dsn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_uncor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_uncor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_in_process</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>hot_reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_hot_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>hot_reset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_hot_reset_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>link_training_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_link_training_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>power_state_change_ack</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_power_state_change_ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>power_state_change_interrupt</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_power_state_change_interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>req_pm_transition_l23_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_req_pm_transition_l23_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_func_num</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_func_num</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_in_process</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_control" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_CTL_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_control_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_control</spirit:displayName>
+      <spirit:description>It allows a broad range of information exchange between user application and the core</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_control" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_control_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bus_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_bus_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>config_space_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_config_space_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_bus_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_bus_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_device_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_device_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_port_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_port_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dsn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_uncor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_uncor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_in_process</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>hot_reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_hot_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>hot_reset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_hot_reset_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>link_training_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_link_training_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pm_aspm_l1entry_reject</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pm_aspm_l1_entry_reject</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pm_aspm_tx_l0s_entry_disable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pm_aspm_tx_l0s_entry_disable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>power_state_change_ack</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_power_state_change_ack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>power_state_change_interrupt</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_power_state_change_interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rbar_function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rbar_size</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_bar_size</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>req_pm_transition_l23_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_req_pm_transition_l23_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_func_num</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_func_num</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_in_process</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar5</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_control_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_CTL_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id</spirit:name>
+      <spirit:displayName>pcie4_pcie_id</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_vend_id</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_vend_id</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vend_id</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vend_id</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf0</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf0</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 0 or  spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf1</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf1</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf2</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf2</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf3</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf3</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_status</spirit:name>
+      <spirit:displayName>pcie4_cfg_status</spirit:displayName>
+      <spirit:description>Configuration Status Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_status" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_status_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req_count</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req_count</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>current_speed</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_current_speed</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_fatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_fatal_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_nonfatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_nonfatal_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_power_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_function_power_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_function_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>link_power_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_link_power_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>local_error_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>local_error_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ltssm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ltssm_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_payload</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_payload</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_read_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_read_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>negotiated_width</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_negotiated_width</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>obff_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_obff_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_down</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_down</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pl_status_change</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pl_status_change</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rcb_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rcb_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag_av</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag_vld0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag_vld0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag_vld1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag_vld1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rx_pm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rx_pm_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_requester_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_tph_requester_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_mode</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_tph_st_mode</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tx_pm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_tx_pm_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_power_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_power_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_tph_requester_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_tph_requester_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_tph_st_mode</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_tph_st_mode</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_STATUS_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_status_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_status</spirit:displayName>
+      <spirit:description>Configuration Status Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_status" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_status_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req_count</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req_count</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>current_speed</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_current_speed</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_fatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_fatal_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_nonfatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_nonfatal_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_power_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_function_power_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_function_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>link_power_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_link_power_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>local_error_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>local_error_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ltssm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ltssm_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_payload</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_payload</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_read_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_read_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>negotiated_width</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_negotiated_width</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>obff_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_obff_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_down</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_down</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pl_status_change</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pl_status_change</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rcb_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rcb_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag_av</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag_vld0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag_vld0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tag_vld1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_tag_vld1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rx_pm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rx_pm_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_requester_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_tph_requester_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_mode</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_tph_st_mode</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tx_pm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_tx_pm_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_power_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_power_state</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_status</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_tph_requester_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_tph_requester_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_tph_st_mode</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_tph_st_mode</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_status_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_STATUS_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_transmit_fc</spirit:name>
+      <spirit:displayName>pcie4_transmit_fc</spirit:displayName>
+      <spirit:description>Transmit Flow Control Interfce</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>npd_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
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+      <spirit:displayName>pcie4_drp</spirit:displayName>
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+            <spirit:name>DWE</spirit:name>
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+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_drp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE4_DRP&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
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+      <spirit:displayName>pcie4_drp</spirit:displayName>
+      <spirit:description>PCIE DRP Interface</spirit:description>
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+          <spirit:physicalPort>
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+            <spirit:name>DEN</spirit:name>
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+            <spirit:name>drp_en</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>drp_di</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>drp_do</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>DRDY</spirit:name>
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+            <spirit:name>DWE</spirit:name>
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+            <spirit:name>drp_we</spirit:name>
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+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_drp_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE4_DRP&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
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+      <spirit:name>CLK.sys_clk</spirit:name>
+      <spirit:displayName>CLK.sys_clk</spirit:displayName>
+      <spirit:description>sys_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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+            <spirit:name>CLK</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>sys_clk</spirit:name>
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+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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+      <spirit:name>CLK.sys_clk_gt</spirit:name>
+      <spirit:displayName>CLK.sys_clk_gt</spirit:displayName>
+      <spirit:description>sys_clk_gt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>sys_clk_gt</spirit:name>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
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+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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+          </spirit:vendorExtensions>
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+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.user_clk</spirit:name>
+      <spirit:displayName>CLK.user_clk</spirit:displayName>
+      <spirit:description>user_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>user_clk</spirit:name>
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+        </spirit:portMap>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_BUSIF">m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.FREQ_HZ">125000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_RESET">user_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.mcap_clk</spirit:name>
+      <spirit:displayName>CLK.mcap_clk</spirit:displayName>
+      <spirit:description>mcap_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mcap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.FREQ_HZ">125000000</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.MCAP_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.mcap_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
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+    <spirit:busInterface>
+      <spirit:name>CLK.core_clk</spirit:name>
+      <spirit:displayName>CLK.core_clk</spirit:displayName>
+      <spirit:description>core_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>core_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.FREQ_HZ">500000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.core_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_MORE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
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+    <spirit:busInterface>
+      <spirit:name>CLK.gt_drp_clk</spirit:name>
+      <spirit:displayName>CLK.gt_drp_clk</spirit:displayName>
+      <spirit:description>gt_drp_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
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+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_drp_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.FREQ_HZ">125000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.gt_drp_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_MORE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
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+      <spirit:name>RST.user_reset</spirit:name>
+      <spirit:displayName>RST.user_reset</spirit:displayName>
+      <spirit:description>user_reset interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
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+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>user_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.USER_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.USER_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+      <spirit:name>pcie4_pl</spirit:name>
+      <spirit:displayName>pcie4_pl</spirit:displayName>
+      <spirit:description>Physical Layer Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pl" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pl_rtl" spirit:version="1.0"/>
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+      <spirit:portMaps>
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+          <spirit:logicalPort>
+            <spirit:name>eq_in_progress</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_eq_in_progress</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eq_mismatch</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_eq_mismatch</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eq_phase</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_eq_phase</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gen2_upstream_prefer_deemph</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_gen2_upstream_prefer_deemph</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>redo_eq</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_redo_eq</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>redo_eq_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_redo_eq_pending</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>redo_eq_speed</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pl_redo_eq_speed</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pl" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PL_INTERFACE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>configure</spirit:name>
+      <spirit:displayName>configure</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_ultrascale" spirit:name="configure" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_ultrascale" spirit:name="configure_rtl" spirit:version="1.0"/>
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+      <spirit:portMaps>
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+          <spirit:logicalPort>
+            <spirit:name>req_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_req_data</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>req_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_req_ready</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>req_reg_num</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_req_reg_num</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>req_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_req_type</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>req_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_req_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>resp_rdata</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_resp_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>resp_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>conf_resp_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.configure" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cap</spirit:name>
+      <spirit:displayName>cap</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cap" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cap_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>GNT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cap_gnt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cap_rel</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cap_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cap" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_ext_pipe_rp</spirit:name>
+      <spirit:displayName>pcie4_ext_pipe_rp</spirit:displayName>
+      <spirit:description>PCIE4 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
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+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_8_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_9_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_10_sigs</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_11_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_12_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_13_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_14_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_15_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_ext_pipe_rp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 2)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_ext_pipe_ep</spirit:name>
+      <spirit:displayName>pcie4_ext_pipe_ep</spirit:displayName>
+      <spirit:description>PCIE4 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_ext_pipe_ep" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_ext_pipe_ep_legacy</spirit:name>
+      <spirit:displayName>pcie4_ext_pipe_ep_legacy</spirit:displayName>
+      <spirit:description>PCIE4 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_ext_pipe_ep_legacy" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_usp_ext_gtcom</spirit:name>
+      <spirit:displayName>pcie4_usp_ext_gtcommon</spirit:displayName>
+      <spirit:description>PCIE4 Ultrascale+ External GT COMMON Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="ext_gtcom" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="ext_gtcom_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll0lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll0outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll0outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0pd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll0pd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll0reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1pd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1pd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpllxrate</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpllxrate</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpllxrcalenb</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpllxrcalenb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpllxrefclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpllxrefclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_usp_ext_gtcom" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTCOM_IN_CORE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) != 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_usp_int_gtcom</spirit:name>
+      <spirit:displayName>pcie4_usp_int_gtcommon</spirit:displayName>
+      <spirit:description>PCIE4 Ultrascale+ Internal GT COMMON Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="int_gtcom" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="int_gtcom_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll0lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll0lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll0outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll0outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll0outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll0outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_usp_int_gtcom" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTCOM_IN_CORE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) != 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_ext_ch_gt</spirit:name>
+      <spirit:displayName>pcie_ext_ch_gt</spirit:displayName>
+      <spirit:description>channel DRP signals</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DI</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpdi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DO</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpdo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DRDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drprdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DWE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpwe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_ch_gt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EXT_CH_GT_DRP&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>transceiver_debug</spirit:name>
+      <spirit:displayName>transceiver_debug</spirit:displayName>
+      <spirit:description>Transceiver Debug Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="transceiver_debug" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="transceiver_debug_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtdiv</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_bufgtdiv</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpll_lock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_cplllock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonfiforeset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_dmonfiforeset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_dmonitorclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorout</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_dmonitorout</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eyescandataerror</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_eyescandataerror</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gen34_eios_det</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_gen34_eios_det</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtpowergood</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_gtpowergood</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>loopback</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_loopback</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratedone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_pcieuserratedone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratestart</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_pcieuserratestart</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phystatus</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_phystatus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>prst_n</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_prst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0_lock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_qpll0lock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1_lock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_qpll1lock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rate_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_pcierateidle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rrst_n</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_rrst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rst_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_rst_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rst_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_rst_idle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxbufreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufstatus</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxbufstatus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrlock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxcdrlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxcdrreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadet</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxcommadet</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelpmreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxdfelpmreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxdlysresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxeq_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_rxeq_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkfabric</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclkfabric</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkpcs</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclkpcs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcsreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxpcsreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxphaligndone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmareset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxpmareset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxpmaresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbscntreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbscntreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbserr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbserr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbslocked</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbslocked</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbssel</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbssel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrecclkout</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxrecclkout</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxstatus</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxstatus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxsyncdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxsyncdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxvalid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txdlysresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txelecidle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txelecidle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txeq_ctrl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_ctrl</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txeq_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txeq_preset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_preset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txinhibit</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txinhibit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txoutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkfabric</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txoutclkfabric</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkpcs</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txoutclkpcs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpcsreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txpcsreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphaligndone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txphaligndone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinitdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txphinitdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmareset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txpmareset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmaresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txpmaresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbsforceerr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txprbsforceerr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbssel</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txprbssel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprogdivresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txprogdivresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txsyncdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.transceiver_debug" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.TRANSCEIVER_CTRL_STATUS_PORTS&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
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+      <spirit:name>pcie4_gt_if</spirit:name>
+      <spirit:displayName>pcie4_gt_if</spirit:displayName>
+      <spirit:description>GT Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_gt_if" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_gt_if_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtce_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtce_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtcemask_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtcemask_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtdiv_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtdiv_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtreset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtreset_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtrstmask_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtrstmask_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllfreqlock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllfreqlock_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cplllock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cplllock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllpd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonfiforeset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonfiforeset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonitorclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonitorout_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpaddr_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpaddr_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpdi_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpdi_in</spirit:name>
+          </spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>drpdo_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpdo_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpen_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+          <spirit:logicalPort>
+            <spirit:name>drprdy_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drprdy_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drprst_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drprst_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpwe_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpwe_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_int_clock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_int_clock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_pclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_pclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_userclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_userclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_rst_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_rst_idle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_txoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_txoutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eyescanreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>eyescanreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtpowergood_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtpowergood_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk0_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk00_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk00_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk01_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk01_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrxreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrxreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gttxreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gttxreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_reset_rx_done_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_reset_rx_done_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_reset_tx_done_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_reset_tx_done_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_rx_active_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_rx_active_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_tx_active_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_tx_active_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>loopback_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>loopback_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieeqrxeqadaptdone_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieeqrxeqadaptdone_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierategen3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierategen3_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateidle_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateidle_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpll0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpll0_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpll1_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpll1_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpllpd_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpllpd_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpllreset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpllreset_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierstidle_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierstidle_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pciersttxsyncstart_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pciersttxsyncstart_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pciesynctxsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pciesynctxsyncdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieusergen3rdy_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieusergen3rdy_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserphystatusrst_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserphystatusrst_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratedone_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserratedone_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratestart_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserratestart_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phystatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phystatus_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0freqlock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0freqlock_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0pd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0pd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1freqlock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1freqlock_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1pd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1pd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rcalenb_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rcalenb_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>resetovrd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>resetovrd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rx8b10ben_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rx8b10ben_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbufreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufstatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbufstatus_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbyteisaligned_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbyteisaligned_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbyterealign_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbyterealign_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrfreqreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrfreqreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrlock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrlock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxclkcorcnt_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxclkcorcnt_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadet_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcommadet_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadeten_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcommadeten_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl0_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl0_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl1_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl1_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl2_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl2_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl3_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdata_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfeagchold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfeagchold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfecfokhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfecfokhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfekhhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfekhhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfelfhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelpmreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfelpmreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap2hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap2hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap3hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap3hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap4hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap4hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap5hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap5hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap6hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap6hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap7hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap7hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap8hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap8hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap9hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap9hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap10hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap10hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap11hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap11hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap12hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap12hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap13hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap13hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap14hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap14hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap15hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap15hold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfeuthold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfeuthold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfevphold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfevphold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdlysresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxelecidle_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxelecidle_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmen_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmgchold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmgchold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmhfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmhfhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmlfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmlfhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmoshold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmoshold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxmcommaalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxmcommaalignen_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoshold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoshold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkfabric_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclkfabric_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkpcs_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclkpcs_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcommaalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpcommaalignen_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcsreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpcsreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxphaligndone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmareset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpmareset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpmaresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpolarity_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpolarity_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbscntreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbscntreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbserr_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbserr_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbslocked_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbslocked_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbssel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbssel_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprogdivreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprogdivreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrate_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxrate_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxratedone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxratedone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxratemode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxratemode_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrecclkout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxrecclkout_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxslide_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxslide_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxstatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxstatus_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxsyncdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxtermination_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxtermination_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxuserrdy_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxuserrdy_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxusrclk2_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxusrclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxvalid_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tx8b10ben_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tx8b10ben_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl0_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl1_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl1_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl2_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdata_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdata_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdeemph_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdeemph_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdetectrx_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdetectrx_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdiffctrl_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdiffctrl_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlybypass_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlybypass_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyen_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyhold_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyovrden_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyovrden_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlysreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlysresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyupdown_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyupdown_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txelecidle_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txelecidle_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txmaincursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txmaincursor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txmargin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txmargin_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkfabric_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclkfabric_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkpcs_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclkpcs_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclksel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclksel_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpcsreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpcsreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpdelecidlemode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpdelecidlemode_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphalign_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphalign_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphaligndone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphaligndone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphalignen_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlypd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlypd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlyreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlyreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlytstclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlytstclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinit_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphinit_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinitdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphinitdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphovrden_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphovrden_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpisopd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpisopd_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmareset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpmareset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmaresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpmaresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpostcursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpostcursor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbsforceerr_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprbsforceerr_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbssel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprbssel_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprecursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprecursor_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprgdivresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprgdivresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprogdivreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprogdivreset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txrate_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txrate_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txresetdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txswing_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txswing_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncallin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncallin_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncdone_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncin_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncmode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncmode_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncout_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txuserrdy_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txuserrdy_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txusrclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txusrclk2_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txusrclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_gt_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_pclk2_gt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_phy_clk_int_clock</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_int_clock" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_phy_clk_pclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_pclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_pclk2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_coreclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_phy_clk_phy_userclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_userclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_mcapclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>cap_req</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cap_req" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>cap_gnt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cap_gnt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>cap_rel</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cap_rel" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>mcap_design_switch</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcap_design_switch" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_CONFIGURATION&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>free_run_clock</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.free_run_clock" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GT_DRP_CLK_SRC&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>phy_rdy_out</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>prst_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.prst_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_CLKMUX&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>PL_LINK_CAP_MAX_LINK_SPEED</spirit:name>
+        <spirit:displayName>Pl Link Cap Max Link Speed</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PL_LINK_CAP_MAX_LINK_WIDTH</spirit:name>
+        <spirit:displayName>Pl Link Cap Max Link Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CRM_USER_CLK_FREQ</spirit:name>
+        <spirit:displayName>User Clk Freq</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CRM_USER_CLK_FREQ">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CRM_CORE_CLK_FREQ_500</spirit:name>
+        <spirit:displayName>Core Clk Freq</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CRM_CORE_CLK_FREQ_500">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PLL_TYPE</spirit:name>
+        <spirit:displayName>PLL Type</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PLL_TYPE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF0_LINK_CAP_ASPM_SUPPORT</spirit:name>
+        <spirit:displayName>ASPM Support</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_LINK_CAP_ASPM_SUPPORT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI4_DATA_WIDTH</spirit:name>
+        <spirit:displayName>C Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI4_DATA_WIDTH">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PHY_REFCLK_FREQ</spirit:name>
+        <spirit:displayName>Ref Clk Freq</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PHY_REFCLK_FREQ">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI4_TKEEP_WIDTH</spirit:name>
+        <spirit:displayName>Keep Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.AXI4_TKEEP_WIDTH" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.AXI4_DATA_WIDTH&apos;)) div 32)">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI4_RQ_TUSER_WIDTH</spirit:name>
+        <spirit:displayName>RQ User Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI4_RQ_TUSER_WIDTH">62</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI4_CQ_TUSER_WIDTH</spirit:name>
+        <spirit:displayName>CQ User Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI4_CQ_TUSER_WIDTH">88</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI4_RC_TUSER_WIDTH</spirit:name>
+        <spirit:displayName>RC User Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI4_RC_TUSER_WIDTH">75</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI4_CC_TUSER_WIDTH</spirit:name>
+        <spirit:displayName>CC User Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI4_CC_TUSER_WIDTH">33</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ARI_CAP_ENABLE</spirit:name>
+        <spirit:displayName>Ari Cap Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ARI_CAP_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_ARI_CAP_NEXT_FUNC</spirit:name>
+        <spirit:displayName>Pf0 ARI Cap Next Func</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_ARI_CAP_NEXT_FUNC" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_ARI_CAP_NEXT_FUNC</spirit:name>
+        <spirit:displayName>Pf1 ARI Cap Next Func</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_ARI_CAP_NEXT_FUNC" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_ARI_CAP_NEXT_FUNC</spirit:name>
+        <spirit:displayName>Pf2 ARI Cap Next Func</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_ARI_CAP_NEXT_FUNC" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_ARI_CAP_NEXT_FUNC</spirit:name>
+        <spirit:displayName>Pf3 ARI Cap Next Func</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_ARI_CAP_NEXT_FUNC" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXISTEN_IF_CC_ALIGNMENT_MODE</spirit:name>
+        <spirit:displayName>Axisten If Cc Alignment Mode</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_CC_ALIGNMENT_MODE" spirit:bitStringLength="2">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXISTEN_IF_CQ_ALIGNMENT_MODE</spirit:name>
+        <spirit:displayName>Axisten If Cq Alignment Mode</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE" spirit:bitStringLength="2">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXISTEN_IF_RC_ALIGNMENT_MODE</spirit:name>
+        <spirit:displayName>Axisten If Rc Alignment Mode</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_RC_ALIGNMENT_MODE" spirit:bitStringLength="2">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXISTEN_IF_RQ_ALIGNMENT_MODE</spirit:name>
+        <spirit:displayName>Axisten If Rq Alignment Mode</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE" spirit:bitStringLength="2">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_EXT_512_CQ_STRADDLE</spirit:name>
+        <spirit:displayName>Axisten If CQ Straddle</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_EXT_512_CQ_STRADDLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_EXT_512_CC_STRADDLE</spirit:name>
+        <spirit:displayName>Axisten If CC Straddle</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_EXT_512_CC_STRADDLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_EXT_512_RQ_STRADDLE</spirit:name>
+        <spirit:displayName>Axisten If RQ Straddle</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_EXT_512_RQ_STRADDLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_EXT_512_RC_STRADDLE</spirit:name>
+        <spirit:displayName>Axisten If RC Straddle</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_EXT_512_RC_STRADDLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE</spirit:name>
+        <spirit:displayName>Axisten If 512 4TLP/2TLP Rc Straddle</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_RC_STRADDLE</spirit:name>
+        <spirit:displayName>Axisten If Rc Straddle</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_RC_STRADDLE">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE</spirit:name>
+        <spirit:displayName>Pf0 Aer Cap Ecrc Gen and Check Capable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_AER_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Aer Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_AER_CAP_NEXTPTR" spirit:bitStringLength="12">0x1C0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_PCIE_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>pcie Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_PCIE_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIE_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>pcie Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIE_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_PCIE_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>pcie Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_PCIE_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_PCIE_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>pcie Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_PCIE_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF0_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR</spirit:name>
+        <spirit:displayName>vf0 ext space Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF0_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF1_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR</spirit:name>
+        <spirit:displayName>vf1/ ext space Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF1_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF2_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR</spirit:name>
+        <spirit:displayName>vf2 ext space Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF2_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF3_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR</spirit:name>
+        <spirit:displayName>vf3 ext space Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF3_EXT_PCIE_CFG_SPACE_ENABLED_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_ARI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Ari Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_ARI_CAP_NEXTPTR" spirit:bitStringLength="12">0x1C0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE" spirit:bitStringLength="9">0x009</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_CAPABILITY_POINTER</spirit:name>
+        <spirit:displayName>Pf0 Capability Pointer</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_CAPABILITY_POINTER" spirit:bitStringLength="8">0x40</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_CLASS_CODE</spirit:name>
+        <spirit:displayName>Pf0 Class Code</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_CLASS_CODE" spirit:bitStringLength="24">0x070001</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_VENDOR_ID</spirit:name>
+        <spirit:displayName>Pf0 Vendor Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf0 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEVICE_ID" spirit:bitStringLength="16">0x9038</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap2 128b Cas Atomic Completer Support</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap2 32b Atomic Completer Support</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap2 64b Atomic Completer Support</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap2 Tph Completer Support</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_DEV_CAP_EXT_TAG_SUPPORTED</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap Ext Tag Supported</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP_EXT_TAG_SUPPORTED">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap Function Level Reset Capable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_DEV_CAP_MAX_PAYLOAD_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Dev Cap Max Payload Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEV_CAP_MAX_PAYLOAD_SIZE" spirit:bitStringLength="3">0x3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DSN_CAP_ENABLE</spirit:name>
+        <spirit:displayName>Dsn Cap Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DSN_CAP_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_VC_CAP_ENABLE</spirit:name>
+        <spirit:displayName>Vc Cap Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_VC_CAP_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_DSN_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Dsn Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DSN_CAP_NEXTPTR" spirit:bitStringLength="12">0x1C0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Expansion Rom Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_EXPANSION_ROM_ENABLE</spirit:name>
+        <spirit:displayName>Pf0 Expansion Rom Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_INTERRUPT_PIN</spirit:name>
+        <spirit:displayName>Pf0 Interrupt Pin</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_INTERRUPT_PIN" spirit:bitStringLength="3">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_LINK_STATUS_SLOT_CLOCK_CONFIG</spirit:name>
+        <spirit:displayName>Pf0 Link Status Slot Clock Config</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_MSIX_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF0_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF0_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF0_MSI_CAP_MULTIMSGCAP</spirit:name>
+        <spirit:displayName>Pf0 Msi Cap Multimsgcap</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_MSI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Msi Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSI_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_PM_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Pm Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_PM_CAP_NEXTPTR" spirit:bitStringLength="8">0x48</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_PM_CAP_PMESUPPORT_D0</spirit:name>
+        <spirit:displayName>Pf0 Pm Cap Pmesupport D0</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_PM_CAP_PMESUPPORT_D1</spirit:name>
+        <spirit:displayName>Pf0 Pm Cap Pmesupport D1</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_PM_CAP_PMESUPPORT_D3HOT</spirit:name>
+        <spirit:displayName>Pf0 Pm Cap Pmesupport D3hot</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_PM_CAP_SUPP_D1_STATE</spirit:name>
+        <spirit:displayName>Pf0 Pm Cap Supp D1 State</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf0 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR0_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Sriov Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_CAP_INITIAL_VF</spirit:name>
+        <spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Sriov Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_CAP_TOTAL_VF</spirit:name>
+        <spirit:displayName>Pf0 Sriov Cap Total Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_CAP_TOTAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_CAP_VER</spirit:name>
+        <spirit:displayName>Pf0 Sriov Cap Ver</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_CAP_VER" spirit:bitStringLength="4">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_FIRST_VF_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_FUNC_DEP_LINK</spirit:name>
+        <spirit:displayName>Pf0 Sriov Func Dep Link</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Sriov Supported Page Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE" spirit:bitStringLength="32">0x00000553</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SRIOV_VF_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf0 Sriov Vf Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SUBSYSTEM_VENDOR_ID</spirit:name>
+        <spirit:displayName>Pf0 Subsystem Vendor Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf0 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_TPHR_CAP_ENABLE</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_TPHR_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_TPHR_CAP_ST_MODE_SEL</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap St Mode Sel</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_MODE_SEL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_TPHR_CAP_ST_TABLE_LOC</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap St Table Loc</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_LOC" spirit:bitStringLength="2">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_TPHR_CAP_ST_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap St Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_ST_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_TPHR_CAP_VER</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap Ver</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_VER" spirit:bitStringLength="4">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_TPHR_CAP_ST_MODE_SEL</spirit:name>
+        <spirit:displayName>Pf1 Tphr Cap St Mode Sel</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_TPHR_CAP_ST_MODE_SEL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_TPHR_CAP_ST_MODE_SEL</spirit:name>
+        <spirit:displayName>Pf2 Tphr Cap St Mode Sel</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_TPHR_CAP_ST_MODE_SEL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_TPHR_CAP_ST_MODE_SEL</spirit:name>
+        <spirit:displayName>Pf3 Tphr Cap St Mode Sel</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_TPHR_CAP_ST_MODE_SEL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_TPHR_CAP_DEV_SPECIFIC_MODE</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap Dev Specific Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_DEV_SPECIFIC_MODE">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_TPHR_CAP_INT_VEC_MODE</spirit:name>
+        <spirit:displayName>Pf0 Tphr Cap Int Vec Mode</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_TPHR_CAP_INT_VEC_MODE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SECONDARY_PCIE_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Secondary Pcie Extended Capability Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SECONDARY_PCIE_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>MCAP_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>MCAP Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MCAP_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_VC_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf0 Vc Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_VC_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>SPARE_WORD1</spirit:name>
+        <spirit:displayName>Secondary Pcie Extended Capability Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SPARE_WORD1" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_AER_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Aer Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_AER_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_ARI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Ari Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_ARI_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE" spirit:bitStringLength="9">0x009</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_CAPABILITY_POINTER</spirit:name>
+        <spirit:displayName>Pf1 Capability Pointer</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_CAPABILITY_POINTER" spirit:bitStringLength="8">0x40</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_CLASS_CODE</spirit:name>
+        <spirit:displayName>Pf1 Class Code</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_CLASS_CODE" spirit:bitStringLength="24">0x058000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf1 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_DEVICE_ID" spirit:bitStringLength="16">0x9011</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_DEV_CAP_MAX_PAYLOAD_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Dev Cap Max Payload Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_DEV_CAP_MAX_PAYLOAD_SIZE" spirit:bitStringLength="3">0x3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_DSN_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Dsn Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_DSN_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Expansion Rom Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF1_EXPANSION_ROM_ENABLE</spirit:name>
+        <spirit:displayName>Pf1 Expansion Rom Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_INTERRUPT_PIN</spirit:name>
+        <spirit:displayName>Pf1 Interrupt Pin</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_INTERRUPT_PIN" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_MSIX_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Msix Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF1_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf1 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf1 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF1_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf1 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf1 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF1_MSI_CAP_MULTIMSGCAP</spirit:name>
+        <spirit:displayName>Pf1 Msi Cap Multimsgcap</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_MSI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Msi Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSI_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PM_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Pm Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PM_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf1 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR0_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf1 Sriov Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_CAP_INITIAL_VF</spirit:name>
+        <spirit:displayName>Pf1 Sriov Cap Initial Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Sriov Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_CAP_TOTAL_VF</spirit:name>
+        <spirit:displayName>Pf1 Sriov Cap Total Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_CAP_TOTAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_CAP_VER</spirit:name>
+        <spirit:displayName>Pf1 Sriov Cap Ver</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_CAP_VER" spirit:bitStringLength="4">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_FIRST_VF_OFFSET</spirit:name>
+        <spirit:displayName>Pf1 Sriov First Vf Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_FUNC_DEP_LINK</spirit:name>
+        <spirit:displayName>Pf1 Sriov Func Dep Link</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK" spirit:bitStringLength="16">0x0001</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Sriov Supported Page Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE" spirit:bitStringLength="32">0x00000553</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SRIOV_VF_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf1 Sriov Vf Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf1 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_TPHR_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf1 Tphr Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_TPHR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_AER_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Aer Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_AER_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_ARI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Ari Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_ARI_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR0_APERTURE_SIZE" spirit:bitStringLength="9">0x009</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR1_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR2_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR3_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR4_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR5_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_CAPABILITY_POINTER</spirit:name>
+        <spirit:displayName>Pf2 Capability Pointer</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_CAPABILITY_POINTER" spirit:bitStringLength="8">0x40</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_CLASS_CODE</spirit:name>
+        <spirit:displayName>Pf2 Class Code</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_CLASS_CODE" spirit:bitStringLength="24">0x058000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf2 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_DEVICE_ID" spirit:bitStringLength="16">0x9438</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_DEV_CAP_MAX_PAYLOAD_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Dev Cap Max Payload Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_DEV_CAP_MAX_PAYLOAD_SIZE" spirit:bitStringLength="3">0x3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_DSN_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Dsn Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_DSN_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Expansion Rom Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF2_EXPANSION_ROM_ENABLE</spirit:name>
+        <spirit:displayName>Pf2 Expansion Rom Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_INTERRUPT_PIN</spirit:name>
+        <spirit:displayName>Pf2 Interrupt Pin</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_INTERRUPT_PIN" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_MSIX_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Msix Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSIX_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF2_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf2 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf2 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF2_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf2 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf2 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF2_MSI_CAP_MULTIMSGCAP</spirit:name>
+        <spirit:displayName>Pf2 Msi Cap Multimsgcap</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSI_CAP_MULTIMSGCAP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_MSI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Msi Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSI_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_PM_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Pm Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_PM_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf2 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR0_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf2 Sriov Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_CAP_INITIAL_VF</spirit:name>
+        <spirit:displayName>Pf2 Sriov Cap Initial Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_CAP_INITIAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Sriov Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_CAP_TOTAL_VF</spirit:name>
+        <spirit:displayName>Pf2 Sriov Cap Total Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_CAP_TOTAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_CAP_VER</spirit:name>
+        <spirit:displayName>Pf2 Sriov Cap Ver</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_CAP_VER" spirit:bitStringLength="4">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_FIRST_VF_OFFSET</spirit:name>
+        <spirit:displayName>Pf2 Sriov First Vf Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_FIRST_VF_OFFSET" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_FUNC_DEP_LINK</spirit:name>
+        <spirit:displayName>Pf2 Sriov Func Dep Link</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_FUNC_DEP_LINK" spirit:bitStringLength="16">0x0002</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+        <spirit:displayName>Pf2 Sriov Supported Page Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_SUPPORTED_PAGE_SIZE" spirit:bitStringLength="32">0x00000553</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SRIOV_VF_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf2 Sriov Vf Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SRIOV_VF_DEVICE_ID" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_TPHR_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf2 Tphr Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_TPHR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_AER_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Aer Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_AER_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_ARI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Ari Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_ARI_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR0_APERTURE_SIZE" spirit:bitStringLength="9">0x009</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR1_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR2_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR3_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR4_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR5_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_CAPABILITY_POINTER</spirit:name>
+        <spirit:displayName>Pf3 Capability Pointer</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_CAPABILITY_POINTER" spirit:bitStringLength="8">0x40</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_CLASS_CODE</spirit:name>
+        <spirit:displayName>Pf3 Class Code</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_CLASS_CODE" spirit:bitStringLength="24">0x058000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf3 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_DEVICE_ID" spirit:bitStringLength="16">0x9638</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_DEV_CAP_MAX_PAYLOAD_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Dev Cap Max Payload Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_DEV_CAP_MAX_PAYLOAD_SIZE" spirit:bitStringLength="3">0x3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_DSN_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Dsn Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_DSN_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Expansion Rom Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF3_EXPANSION_ROM_ENABLE</spirit:name>
+        <spirit:displayName>Pf3 Expansion Rom Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_INTERRUPT_PIN</spirit:name>
+        <spirit:displayName>Pf3 Interrupt Pin</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_INTERRUPT_PIN" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_MSIX_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Msix Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSIX_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF3_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf3 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf3 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF3_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf3 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf3 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF3_MSI_CAP_MULTIMSGCAP</spirit:name>
+        <spirit:displayName>Pf3 Msi Cap Multimsgcap</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSI_CAP_MULTIMSGCAP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_MSI_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Msi Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSI_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_PM_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Pm Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_PM_CAP_NEXTPTR" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf3 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR0_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf3 Sriov Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_CAP_INITIAL_VF</spirit:name>
+        <spirit:displayName>Pf3 Sriov Cap Initial Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_CAP_INITIAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Sriov Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_CAP_TOTAL_VF</spirit:name>
+        <spirit:displayName>Pf3 Sriov Cap Total Vf</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_CAP_TOTAL_VF" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_CAP_VER</spirit:name>
+        <spirit:displayName>Pf3 Sriov Cap Ver</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_CAP_VER" spirit:bitStringLength="4">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_FIRST_VF_OFFSET</spirit:name>
+        <spirit:displayName>Pf3 Sriov First Vf Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_FIRST_VF_OFFSET" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_FUNC_DEP_LINK</spirit:name>
+        <spirit:displayName>Pf3 Sriov Func Dep Link</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_FUNC_DEP_LINK" spirit:bitStringLength="16">0x0003</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+        <spirit:displayName>Pf3 Sriov Supported Page Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_SUPPORTED_PAGE_SIZE" spirit:bitStringLength="32">0x00000553</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SRIOV_VF_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf3 Sriov Vf Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SRIOV_VF_DEVICE_ID" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_TPHR_CAP_NEXTPTR</spirit:name>
+        <spirit:displayName>Pf3 Tphr Cap Nextptr</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_TPHR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PL_UPSTREAM_FACING</spirit:name>
+        <spirit:displayName>Pl Upstream Facing</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_UPSTREAM_FACING">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PL_DISABLE_LANE_REVERSAL</spirit:name>
+        <spirit:displayName>Pl Disable Lane Reversal</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_DISABLE_LANE_REVERSAL">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_MSI_CAP_PERVECMASKCAP</spirit:name>
+        <spirit:displayName>en pf0 msi per vec masking</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSI_CAP_PERVECMASKCAP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF1_MSI_CAP_PERVECMASKCAP</spirit:name>
+        <spirit:displayName>en pf1 msi per vec masking</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSI_CAP_PERVECMASKCAP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF2_MSI_CAP_PERVECMASKCAP</spirit:name>
+        <spirit:displayName>en pf2 msi per vec masking</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_MSI_CAP_PERVECMASKCAP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF3_MSI_CAP_PERVECMASKCAP</spirit:name>
+        <spirit:displayName>en pf3 msi per vec masking</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_MSI_CAP_PERVECMASKCAP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>SRIOV_CAP_ENABLE</spirit:name>
+        <spirit:displayName>Sriov Cap Enable</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SRIOV_CAP_ENABLE" spirit:bitStringLength="4">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_CREDITS_CD</spirit:name>
+        <spirit:displayName>Tl Credits Cd</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_CREDITS_CD" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_CREDITS_CH</spirit:name>
+        <spirit:displayName>Tl Credits Ch</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_CREDITS_CH" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_CREDITS_NPD</spirit:name>
+        <spirit:displayName>Tl Credits Npd</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_CREDITS_NPD" spirit:bitStringLength="12">0x004</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_CREDITS_NPH</spirit:name>
+        <spirit:displayName>Tl Credits Nph</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_CREDITS_NPH" spirit:bitStringLength="8">0x20</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_CREDITS_PD</spirit:name>
+        <spirit:displayName>Tl Credits Pd</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_CREDITS_PD" spirit:bitStringLength="12">0x3E0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_CREDITS_PH</spirit:name>
+        <spirit:displayName>Tl Credits Ph</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_CREDITS_PH" spirit:bitStringLength="8">0x20</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXTENDED_CFG_EXTEND_INTERFACE_ENABLE</spirit:name>
+        <spirit:displayName>Tl Extended Cfg Extend Interface Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXTENDED_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_XVC_VSEC_ENABLE</spirit:name>
+        <spirit:displayName>Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>LEGACY_CFG_EXTEND_INTERFACE_ENABLE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LEGACY_CFG_EXTEND_INTERFACE_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ACS_EXT_CAP_ENABLE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ACS_EXT_CAP_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>ACS_CAP_NEXTPTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ACS_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TL_LEGACY_MODE_ENABLE</spirit:name>
+        <spirit:displayName>Tl Legacy Mode Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>TL_PF_ENABLE_REG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF0_CAPABILITY_POINTER</spirit:name>
+        <spirit:displayName>Vf0 Capability Pointer</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF0_CAPABILITY_POINTER" spirit:bitStringLength="8">0x70</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>TL_COMPLETION_RAM_SIZE</spirit:name>
+        <spirit:displayName>Completion Space</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_COMPLETION_RAM_SIZE" spirit:bitStringLength="2">0x2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x0y0_xdc</spirit:name>
+        <spirit:displayName>Generate X0Y0 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x0y0_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x0y1_xdc</spirit:name>
+        <spirit:displayName>Generate X0Y1 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x0y1_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x0y2_xdc</spirit:name>
+        <spirit:displayName>Generate X0Y2 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x0y2_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x0y3_xdc</spirit:name>
+        <spirit:displayName>Generate X0Y3 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x0y3_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x0y4_xdc</spirit:name>
+        <spirit:displayName>Generate X0Y4 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x0y4_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x0y5_xdc</spirit:name>
+        <spirit:displayName>Generate X0Y5 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x0y5_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x1y0_xdc</spirit:name>
+        <spirit:displayName>Generate X1Y0 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x1y0_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x1y1_xdc</spirit:name>
+        <spirit:displayName>Generate X1Y1 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x1y1_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x1y2_xdc</spirit:name>
+        <spirit:displayName>Generate X1Y2 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x1y2_xdc">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x1y3_xdc</spirit:name>
+        <spirit:displayName>Generate X1Y3 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x1y3_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x1y4_xdc</spirit:name>
+        <spirit:displayName>Generate X1Y4 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x1y4_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>gen_x1y5_xdc</spirit:name>
+        <spirit:displayName>Generate X1Y5 XDC</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.gen_x1y5_xdc">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>xlnx_ref_board</spirit:name>
+        <spirit:displayName>Xlnx Ref Board</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.xlnx_ref_board">15</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>pcie_blk_locn</spirit:name>
+        <spirit:displayName>Pcie Blk Locn</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.pcie_blk_locn">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PIPE_SIM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_ENABLE_CLIENT_TAG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_CLIENT_TAG">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PCIE_FAST_CONFIG</spirit:name>
+        <spirit:displayName>PCIE FAST CONFIG</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_FAST_CONFIG">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_STARTUP_PRIMITIVE</spirit:name>
+        <spirit:displayName>EXT STARTUP PRIMITIVE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PL_INTERFACE</spirit:name>
+        <spirit:displayName>PL INTERFACE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_INTERFACE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PCIE_CONFIGURATION</spirit:name>
+        <spirit:displayName>PCIE CONFIGURATION</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_CONFIGURATION">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_STATUS_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_STATUS_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TX_FC_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TX_FC_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_EXT_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_EXT_IF">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_FC_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_FC_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PER_FUNC_STATUS_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PER_FUNC_STATUS_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_MGMT_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_MGMT_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RCV_MSG_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RCV_MSG_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_TX_MSG_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_TX_MSG_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_CTL_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_CTL_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_PM_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_PM_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PCIE_ID_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_ID_IF">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSI_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSI_EN">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSIX_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PCIE4_DRP</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE4_DRP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DIS_GT_WIZARD</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DIS_GT_WIZARD">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>BMD_PIO_MODE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BMD_PIO_MODE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SRIOV_EXD_MODE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SRIOV_EXD_MODE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DBG_CHECKER</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DBG_CHECKER">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_IBERT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_IBERT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>GEN4_EIEOS_0S7</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GEN4_EIEOS_0S7">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CTRL_SKIP_MASK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CTRL_SKIP_MASK">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_JTAG_DBG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_JTAG_DBG">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_LTSSM_DBG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_LTSSM_DBG">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>BROADCOM_SBR_WA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BROADCOM_SBR_WA">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TWO_PORT_SWITCH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TWO_PORT_SWITCH">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TWO_PORT_CONFIG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TWO_PORT_CONFIG">X8G3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TRANSCEIVER_CTRL_STATUS_PORTS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TRANSCEIVER_CTRL_STATUS_PORTS">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SHARED_LOGIC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>GTWIZ_IN_CORE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GTWIZ_IN_CORE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>GTCOM_IN_CORE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GTCOM_IN_CORE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_RX_PARITY_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_RX_PARITY_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_TX_PARITY_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_TX_PARITY_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_MSIX_RX_PARITY_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_MSIX_RX_PARITY_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>LL_TX_TLP_PARITY_CHK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LL_TX_TLP_PARITY_CHK">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>LL_RX_TLP_PARITY_GEN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LL_RX_TLP_PARITY_GEN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TL2CFG_IF_PARITY_CHK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL2CFG_IF_PARITY_CHK">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DEDICATE_PERST</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEDICATE_PERST">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SYS_RESET_POLARITY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYS_RESET_POLARITY">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MCAP_ENABLEMENT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MCAP_ENABLEMENT">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>MCAP_FPGA_BITSTREAM_VERSION</spirit:name>
+        <spirit:displayName>MCAP Bitstream Version Register Value</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MCAP_FPGA_BITSTREAM_VERSION" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_CH_GT_DRP</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_CH_GT_DRP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_GT_SELECTION</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_GT_SELECTION">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SELECT_QUAD</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELECT_QUAD">GTY_Quad_227</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>silicon_revision</spirit:name>
+        <spirit:displayName>Silicon Revision</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.silicon_revision">Beta</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DEV_PORT_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEV_PORT_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG0_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG0_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG0_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG0_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG0_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG0_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG0_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG0_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG0_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG0_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG1_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG1_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG1_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG1_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG1_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG1_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG1_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG1_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG1_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG1_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG2_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG2_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG2_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG2_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG2_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG2_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG2_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG2_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG2_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG2_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG3_MSIX_CAP_PBA_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG3_MSIX_CAP_PBA_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG3_MSIX_CAP_PBA_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG3_MSIX_CAP_PBA_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VFG3_MSIX_CAP_TABLE_BIR</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG3_MSIX_CAP_TABLE_BIR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG3_MSIX_CAP_TABLE_OFFSET</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG3_MSIX_CAP_TABLE_OFFSET" spirit:bitStringLength="29">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VFG3_MSIX_CAP_TABLE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VFG3_MSIX_CAP_TABLE_SIZE" spirit:bitStringLength="11">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_PARITY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_PARITY">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>INS_LOSS_PROFILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INS_LOSS_PROFILE">ADD-IN_CARD</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSI_X_OPTIONS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSI_X_OPTIONS">None</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>COMPLETER_MODEL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COMPLETER_MODEL">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DBG_DESCRAMBLE_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DBG_DESCRAMBLE_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>MSI_INT</spirit:name>
+        <spirit:displayName>MSI Ints</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSI_INT">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>VU9P_BOARD</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VU9P_BOARD">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PHY_LP_TXPRESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PHY_LP_TXPRESET">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IS_BOARD_PROJECT</spirit:name>
+        <spirit:displayName>Is Board Flow Enabled</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_BOARD_PROJECT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>GT_DRP_CLK_SRC</spirit:name>
+        <spirit:displayName>GT DRP Clk Source</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GT_DRP_CLK_SRC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FREE_RUN_FREQ</spirit:name>
+        <spirit:displayName>Free Run Freq</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREE_RUN_FREQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PM_ENABLE_L23_ENTRY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PM_ENABLE_L23_ENTRY">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AWS_MODE_VALUE</spirit:name>
+        <spirit:displayName>aws mode value</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AWS_MODE_VALUE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MULT_PF_DES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MULT_PF_DES">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_SYS_CLK_BUFG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_SYS_CLK_BUFG">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXISTEN_IF_ENABLE_MSG_ROUTE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_MSG_ROUTE" spirit:bitStringLength="18">0x20000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXISTEN_IF_ENABLE_RX_MSG_INTFC</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_RX_MSG_INTFC">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_MORE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_MORE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DISABLE_BRAM_PIPELINE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DISABLE_BRAM_PIPELINE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DISABLE_EQ_SYNCHRONIZER</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DISABLE_EQ_SYNCHRONIZER">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_AUTO_RXEQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_AUTO_RXEQ">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>THREE_PORT_SWITCH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.THREE_PORT_SWITCH">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_MULTIPF_AER</spirit:name>
+        <spirit:displayName>multi pf aer fix</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_MULTIPF_AER">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_MSIX_32VEC</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_MSIX_32VEC">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_CLKMUX</spirit:name>
+        <spirit:displayName>CLK-MUXING during perst</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_CLKMUX">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RBAR_ENABLE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RBAR_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR0_UPPER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR0 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR0_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR0_LOWER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR0 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR0_LOWER" spirit:bitStringLength="32">0x0000fff0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR1_UPPER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR1 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR1_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR1_LOWER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR1 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR1_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR2_UPPER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR2 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR2_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR2_LOWER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR2 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR2_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR3_UPPER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR3 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR3_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR3_LOWER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR3 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR3_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR4_UPPER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR4 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR4_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR4_LOWER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR4 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR4_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR5_UPPER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR5 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR5_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_CAP_BAR5_LOWER</spirit:name>
+        <spirit:displayName>PF0 Resizable BAR5 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_CAP_BAR5_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR0_UPPER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR0 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR0_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR0_LOWER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR0 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR0_LOWER" spirit:bitStringLength="32">0x0000fff0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR1_UPPER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR1 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR1_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR1_LOWER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR1 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR1_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR2_UPPER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR2 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR2_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR2_LOWER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR2 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR2_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR3_UPPER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR3 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR3_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR3_LOWER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR3 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR3_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR4_UPPER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR4 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR4_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR4_LOWER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR4 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR4_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR5_UPPER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR5 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR5_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_CAP_BAR5_LOWER</spirit:name>
+        <spirit:displayName>PF1 Resizable BAR5 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_CAP_BAR5_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR0_UPPER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR0 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR0_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR0_LOWER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR0 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR0_LOWER" spirit:bitStringLength="32">0x0000fff0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR1_UPPER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR1 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR1_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR1_LOWER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR1 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR1_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR2_UPPER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR2 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR2_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR2_LOWER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR2 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR2_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR3_UPPER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR3 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR3_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR3_LOWER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR3 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR3_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR4_UPPER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR4 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR4_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR4_LOWER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR4 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR4_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR5_UPPER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR5 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR5_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_CAP_BAR5_LOWER</spirit:name>
+        <spirit:displayName>PF2 Resizable BAR5 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_CAP_BAR5_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR0_UPPER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR0 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR0_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR0_LOWER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR0 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR0_LOWER" spirit:bitStringLength="32">0x0000fff0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR1_UPPER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR1 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR1_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR1_LOWER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR1 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR1_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR2_UPPER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR2 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR2_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR2_LOWER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR2 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR2_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR3_UPPER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR3 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR3_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR3_LOWER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR3 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR3_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR4_UPPER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR4 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR4_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR4_LOWER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR4 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR4_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR5_UPPER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR5 Capability upper 16 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR5_UPPER" spirit:bitStringLength="16">0x0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_CAP_BAR5_LOWER</spirit:name>
+        <spirit:displayName>PF3 Resizable BAR5 Capability lower 32 bits</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_CAP_BAR5_LOWER" spirit:bitStringLength="32">0x00000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>RBAR_CAP_NEXTPTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RBAR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_NUM_BAR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_NUM_BAR" spirit:bitStringLength="3">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_NUM_BAR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_NUM_BAR" spirit:bitStringLength="3">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_NUM_BAR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_NUM_BAR" spirit:bitStringLength="3">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_NUM_BAR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_NUM_BAR" spirit:bitStringLength="3">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_BAR_INDEX_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_0" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_BAR_INDEX_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_1" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_BAR_INDEX_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_2" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_BAR_INDEX_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_3" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_BAR_INDEX_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_4" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_RBAR_BAR_INDEX_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_RBAR_BAR_INDEX_5" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_BAR_INDEX_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_0" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_BAR_INDEX_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_RBAR_BAR_INDEX_1" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_BAR_INDEX_3</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_BAR_INDEX_4</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_RBAR_BAR_INDEX_5</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_BAR_INDEX_0</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_BAR_INDEX_1</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_BAR_INDEX_2</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_BAR_INDEX_3</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_BAR_INDEX_4</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_RBAR_BAR_INDEX_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_RBAR_BAR_INDEX_5" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_BAR_INDEX_0</spirit:name>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_BAR_INDEX_1</spirit:name>
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+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_BAR_INDEX_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_BAR_INDEX_2" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_BAR_INDEX_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_BAR_INDEX_3" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_BAR_INDEX_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_BAR_INDEX_4" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_RBAR_BAR_INDEX_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_RBAR_BAR_INDEX_5" spirit:bitStringLength="3">0x7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>USE_STANDARD_INTERFACES</spirit:name>
+        <spirit:displayName>Use standard interfaces</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_STANDARD_INTERFACES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DMA_2RP</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_2RP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SRIOV_ACTIVE_VFS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SRIOV_ACTIVE_VFS">252</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>MASTER_GT_QUAD_INX</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MASTER_GT_QUAD_INX">3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>MASTER_GT_CONTAINER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MASTER_GT_CONTAINER">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>QDMA_TPH_MSIX_BRAMS_DIS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.QDMA_TPH_MSIX_BRAMS_DIS">FALSE</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_002f5e3f</spirit:name>
+      <spirit:enumeration>PCI_Express_Endpoint_device</spirit:enumeration>
+      <spirit:enumeration>Legacy_PCI_Express_Endpoint_device</spirit:enumeration>
+      <spirit:enumeration>Root_Port_of_PCI_Express_Root_Complex</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_0cee66fe</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
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+      <spirit:enumeration>64</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_0f93492c</spirit:name>
+      <spirit:enumeration>Chip-to-Chip</spirit:enumeration>
+      <spirit:enumeration>Add-in_Card</spirit:enumeration>
+      <spirit:enumeration>Backplane</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_165ed04b</spirit:name>
+      <spirit:enumeration>64</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_1e9fb93b</spirit:name>
+      <spirit:enumeration>X1</spirit:enumeration>
+      <spirit:enumeration>X2</spirit:enumeration>
+      <spirit:enumeration>X4</spirit:enumeration>
+      <spirit:enumeration>X8</spirit:enumeration>
+      <spirit:enumeration>X16</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_24b724fb</spirit:name>
+      <spirit:enumeration>Basic</spirit:enumeration>
+      <spirit:enumeration>Advanced</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_34d65ff4</spirit:name>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_35d06715</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_38306dd1</spirit:name>
+      <spirit:enumeration>SOFT</spirit:enumeration>
+      <spirit:enumeration>HARD</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_3ca2cbc7</spirit:name>
+      <spirit:enumeration>BAR_0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_3d9ff82c</spirit:name>
+      <spirit:enumeration>500</spirit:enumeration>
+      <spirit:enumeration>250</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_52d29139</spirit:name>
+      <spirit:enumeration>Bytes</spirit:enumeration>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+      <spirit:enumeration>Gigabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_574f38f3</spirit:name>
+      <spirit:enumeration>2.5_GT/s</spirit:enumeration>
+      <spirit:enumeration>5.0_GT/s</spirit:enumeration>
+      <spirit:enumeration>8.0_GT/s</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_589df8e9</spirit:name>
+      <spirit:enumeration>RAM</spirit:enumeration>
+      <spirit:enumeration>Other_memory_controller</spirit:enumeration>
+      <spirit:enumeration>Flash</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5e2921cd</spirit:name>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5e45706a</spirit:name>
+      <spirit:enumeration>1_vector</spirit:enumeration>
+      <spirit:enumeration>2_vectors</spirit:enumeration>
+      <spirit:enumeration>4_vectors</spirit:enumeration>
+      <spirit:enumeration>8_vectors</spirit:enumeration>
+      <spirit:enumeration>16_vectors</spirit:enumeration>
+      <spirit:enumeration>32_vectors</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_61bc5fcf</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
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+      <spirit:enumeration>252</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_list_6b979ebc</spirit:name>
+      <spirit:enumeration>250</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
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+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6eff49bd</spirit:name>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_75aee2a8</spirit:name>
+      <spirit:enumeration>X8G3</spirit:enumeration>
+      <spirit:enumeration>X16G3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_796ca877</spirit:name>
+      <spirit:enumeration>sample_smoke_test0</spirit:enumeration>
+      <spirit:enumeration>sample_smoke_test1</spirit:enumeration>
+      <spirit:enumeration>legacy_smoke_test</spirit:enumeration>
+      <spirit:enumeration>msi_smoke_test</spirit:enumeration>
+      <spirit:enumeration>msix_smoke_test</spirit:enumeration>
+      <spirit:enumeration>pio_writeReadBack_test0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_7a7dde49</spirit:name>
+      <spirit:enumeration>true</spirit:enumeration>
+      <spirit:enumeration>false</spirit:enumeration>
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+      <spirit:name>choice_list_7d45a81a</spirit:name>
+      <spirit:enumeration>128_bytes</spirit:enumeration>
+      <spirit:enumeration>256_bytes</spirit:enumeration>
+      <spirit:enumeration>512_bytes</spirit:enumeration>
+      <spirit:enumeration>1024_bytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8061eec5</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>Tandem_PROM</spirit:enumeration>
+      <spirit:enumeration>Tandem_PCIe</spirit:enumeration>
+      <spirit:enumeration>Tandem_PCIe_with_Field_Updates</spirit:enumeration>
+      <spirit:enumeration>DFX_over_PCIe</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_81a1639d</spirit:name>
+      <spirit:enumeration>DWORD_Aligned</spirit:enumeration>
+      <spirit:enumeration>Address_Aligned</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_847d868a</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
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+      <spirit:name>choice_list_88156f2e</spirit:name>
+      <spirit:enumeration>QPLL1</spirit:enumeration>
+      <spirit:enumeration>QPLL0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8b5e4915</spirit:name>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_list_8eea463a</spirit:name>
+      <spirit:enumeration>X1Y2</spirit:enumeration>
+      <spirit:enumeration>X1Y4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_914704bd</spirit:name>
+      <spirit:enumeration>100_MHz</spirit:enumeration>
+      <spirit:enumeration>125_MHz</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_97bc19ec</spirit:name>
+      <spirit:enumeration>256_bit</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_9aec9108</spirit:name>
+      <spirit:enumeration>Internal</spirit:enumeration>
+      <spirit:enumeration>External</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a30da595</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pcie_perstn</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a44ca313</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pci_express_x1</spirit:enumeration>
+      <spirit:enumeration>pci_express_x16</spirit:enumeration>
+      <spirit:enumeration>pci_express_x2</spirit:enumeration>
+      <spirit:enumeration>pci_express_x4</spirit:enumeration>
+      <spirit:enumeration>pci_express_x8</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_aa031417</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
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+      <spirit:enumeration>3</spirit:enumeration>
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+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_abc20383</spirit:name>
+      <spirit:enumeration>GTY_Quad_227</spirit:enumeration>
+      <spirit:enumeration>GTY_Quad_226</spirit:enumeration>
+      <spirit:enumeration>GTY_Quad_225</spirit:enumeration>
+      <spirit:enumeration>GTY_Quad_224</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_bdd7203f</spirit:name>
+      <spirit:enumeration>True</spirit:enumeration>
+      <spirit:enumeration>False</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_bea500ca</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>MSI-X_External</spirit:enumeration>
+      <spirit:enumeration>MSI-X_Internal</spirit:enumeration>
+      <spirit:enumeration>MSI-X_AXI4-Stream</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c15e8c67</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
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+      <spirit:name>choice_list_c3d223d9</spirit:name>
+      <spirit:enumeration>Memory</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_list_ca005b72</spirit:name>
+      <spirit:enumeration>No_ASPM</spirit:enumeration>
+      <spirit:enumeration>L1_Supported</spirit:enumeration>
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+      <spirit:name>choice_list_d123c74c</spirit:name>
+      <spirit:enumeration>Bytes</spirit:enumeration>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d53faa96</spirit:name>
+      <spirit:enumeration>100_MHz</spirit:enumeration>
+      <spirit:enumeration>125_MHz</spirit:enumeration>
+      <spirit:enumeration>250_MHz</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d85ad257</spirit:name>
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+      <spirit:enumeration>16450_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Parallel_port</spirit:enumeration>
+      <spirit:enumeration>IEEE_1284_controller</spirit:enumeration>
+      <spirit:enumeration>Multiport_serial_controller</spirit:enumeration>
+      <spirit:enumeration>16650_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>IEEE_1284_target_device</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16550_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>ECP_1.X_compliant_parallel_port</spirit:enumeration>
+      <spirit:enumeration>16850_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16750_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>Smart_Card</spirit:enumeration>
+      <spirit:enumeration>Bi_directional_parallel_port</spirit:enumeration>
+      <spirit:enumeration>Other_communications_device</spirit:enumeration>
+      <spirit:enumeration>GPIB(IEEE_488.1/2)_controller</spirit:enumeration>
+      <spirit:enumeration>16550_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16450_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>16750_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16650_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>Generic_modem</spirit:enumeration>
+      <spirit:enumeration>16950_compatible_serial_controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_dff1a45d</spirit:name>
+      <spirit:enumeration>Wireless_controller</spirit:enumeration>
+      <spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Data_acquisition_and_signal_processing_controllers</spirit:enumeration>
+      <spirit:enumeration>Processing_accelerators</spirit:enumeration>
+      <spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
+      <spirit:enumeration>Docking_stations</spirit:enumeration>
+      <spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
+      <spirit:enumeration>Memory_controller</spirit:enumeration>
+      <spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
+      <spirit:enumeration>Encryption/Decryption_controllers</spirit:enumeration>
+      <spirit:enumeration>Display_controller</spirit:enumeration>
+      <spirit:enumeration>Multimedia_device</spirit:enumeration>
+      <spirit:enumeration>Input_devices</spirit:enumeration>
+      <spirit:enumeration>Mass_storage_controller</spirit:enumeration>
+      <spirit:enumeration>Processors</spirit:enumeration>
+      <spirit:enumeration>Device_does_not_fit_in_any_defined_classes</spirit:enumeration>
+      <spirit:enumeration>Bridge_device</spirit:enumeration>
+      <spirit:enumeration>Network_controller</spirit:enumeration>
+      <spirit:enumeration>Base_system_peripherals</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9cf6440</spirit:name>
+      <spirit:enumeration>Disabled</spirit:enumeration>
+      <spirit:enumeration>32bit_Enabled</spirit:enumeration>
+      <spirit:enumeration>64bit_Enabled</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ec64e624</spirit:name>
+      <spirit:enumeration>N/A</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ecc4b9b7</spirit:name>
+      <spirit:enumeration>AU200</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f1174048</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>INTA</spirit:enumeration>
+      <spirit:enumeration>INTB</spirit:enumeration>
+      <spirit:enumeration>INTC</spirit:enumeration>
+      <spirit:enumeration>INTD</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f149a468</spirit:name>
+      <spirit:enumeration>Extreme</spirit:enumeration>
+      <spirit:enumeration>Good</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fc3456a9</spirit:name>
+      <spirit:enumeration>Disabled</spirit:enumeration>
+      <spirit:enumeration>Enabled</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3c87fcdb</spirit:name>
+      <spirit:enumeration spirit:text="Include GT Wizard in core">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Include GT Wizard in example design">0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_53749dec</spirit:name>
+      <spirit:enumeration spirit:text="Include Shared Logic in core">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Include Shared Logic in example design">0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_6f00a734</spirit:name>
+      <spirit:enumeration spirit:text="Include GT COMMON in example design">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Include GT COMMON inside GT Wizard">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="No sharing when inside GT Wizard and PCIe">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratesubcores_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>ip_0/xdma_pcie4_ip_gt.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_0/xdma_pcie4_ip_gt.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>The Xilinx UltraScale+ PCI Express Integrated Block (1-lane, 2-lane, 4-lane, 8-lane and 16-lane) in conjunction with flexible Ultra series architectural features such as integrated GTs (Gigabit Transceivers) and BRAM (Block RAMs) are used to implement a PCI Express Base Specification v3.1 compliant PCI Express Endpoint.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>device_port_type</spirit:name>
+      <spirit:displayName>Device Port Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.device_port_type" spirit:choiceRef="choice_list_002f5e3f" spirit:order="2">PCI_Express_Endpoint_device</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xlnx_ref_board</spirit:name>
+      <spirit:displayName>Xlnx Ref Board</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xlnx_ref_board" spirit:choiceRef="choice_list_ecc4b9b7" spirit:order="3">AU200</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xlnx_ref_board">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>testname</spirit:name>
+      <spirit:displayName>test</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.testname" spirit:choiceRef="choice_list_796ca877" spirit:order="3.1">sample_smoke_test0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PL_LINK_CAP_MAX_LINK_SPEED</spirit:name>
+      <spirit:displayName>Pl Link Cap Max Link Speed</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED" spirit:choiceRef="choice_list_574f38f3" spirit:order="13">8.0_GT/s</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PL_LINK_CAP_MAX_LINK_WIDTH</spirit:name>
+      <spirit:displayName>Pl Link Cap Max Link Width</spirit:displayName>
+      <spirit:description>The Xilinx Ultrascale Series Gen3 Integrated Block for PCI Expressification v3.0 compliant PCI Express Endpoint.</spirit:description>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH" spirit:choiceRef="choice_list_1e9fb93b" spirit:order="12">X8</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>REF_CLK_FREQ</spirit:name>
+      <spirit:displayName>Ref Clk Freq</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.REF_CLK_FREQ" spirit:choiceRef="choice_list_d53faa96" spirit:order="9">100_MHz</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_EXT_512_CQ_STRADDLE</spirit:name>
+      <spirit:displayName>Axisten If Rc Straddle</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_EXT_512_CQ_STRADDLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="289">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.AXISTEN_IF_EXT_512_CQ_STRADDLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_EXT_512_CC_STRADDLE</spirit:name>
+      <spirit:displayName>Axisten If Rc Straddle</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_EXT_512_CC_STRADDLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="290">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_EXT_512_RQ_STRADDLE</spirit:name>
+      <spirit:displayName>Axisten If Rc Straddle</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_EXT_512_RQ_STRADDLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="291">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.AXISTEN_IF_EXT_512_RQ_STRADDLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_EXT_512_RC_STRADDLE</spirit:name>
+      <spirit:displayName>Axisten If Rc Straddle</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_EXT_512_RC_STRADDLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="16">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE</spirit:name>
+      <spirit:displayName>Axisten If 512 4TLP/2TLP Rc Straddle</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="291.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_RC_STRADDLE</spirit:name>
+      <spirit:displayName>Axisten If Rc Straddle</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_RC_STRADDLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="302">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_if_enable_client_tag</spirit:name>
+      <spirit:displayName>Enable Client Tag</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_enable_client_tag" spirit:choiceRef="choice_list_7a7dde49" spirit:order="15.5">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE</spirit:name>
+      <spirit:displayName>Pf0 Aer Cap Ecrc Gen and Check Capable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="273">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>type1_membase_memlimit_enable</spirit:name>
+      <spirit:displayName>Type1 Config MemBase and MemLimit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.type1_membase_memlimit_enable" spirit:choiceRef="choice_list_fc3456a9" spirit:order="273.1">Enabled</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>type1_prefetchable_membase_memlimit</spirit:name>
+      <spirit:displayName>Type1 Config Prefetchable MemBase and MemLimit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.type1_prefetchable_membase_memlimit" spirit:choiceRef="choice_list_e9cf6440" spirit:order="273.2">64bit_Enabled</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_CLASS_CODE</spirit:name>
+      <spirit:displayName>Pf0 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_CLASS_CODE" spirit:order="34.03">070001</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_CLASS_CODE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf0 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEVICE_ID" spirit:order="25">9038</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT</spirit:name>
+      <spirit:displayName>Pf0 Dev Cap2 128b Cas Atomic Completer Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT" spirit:choiceRef="choice_list_7a7dde49" spirit:order="262">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT</spirit:name>
+      <spirit:displayName>Pf0 Dev Cap2 32b Atomic Completer Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT" spirit:choiceRef="choice_list_7a7dde49" spirit:order="260">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT</spirit:name>
+      <spirit:displayName>Pf0 Dev Cap2 64b Atomic Completer Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT" spirit:choiceRef="choice_list_7a7dde49" spirit:order="261">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT</spirit:name>
+      <spirit:displayName>Pf0 Dev Cap2 Tph Completer Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT" spirit:choiceRef="choice_list_7a7dde49" spirit:order="263">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE</spirit:name>
+      <spirit:displayName>Pf0 Dev Cap Function Level Reset Capable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="23">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>Pf0 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="167">INTA</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_LINK_STATUS_SLOT_CLOCK_CONFIG</spirit:name>
+      <spirit:displayName>Pf0 Link Status Slot Clock Config</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG" spirit:choiceRef="choice_list_7a7dde49" spirit:order="10">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_PBA_BIR</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_PBA_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET" spirit:order="218">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_PBA_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_TABLE_BIR</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET" spirit:order="216">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE" spirit:order="215">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>Pf0 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="205">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_PM_CAP_PMESUPPORT_D1</spirit:name>
+      <spirit:displayName>Pf0 Pm Cap Pmesupport D1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D1" spirit:choiceRef="choice_list_7a7dde49" spirit:order="258">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_PM_CAP_PMESUPPORT_D3HOT</spirit:name>
+      <spirit:displayName>Pf0 Pm Cap Pmesupport D3hot</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D3HOT" spirit:choiceRef="choice_list_7a7dde49" spirit:order="259">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_PM_CAP_SUPP_D1_STATE</spirit:name>
+      <spirit:displayName>Pf0 Pm Cap Supp D1 State</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_PM_CAP_SUPP_D1_STATE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="256">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_REVISION_ID</spirit:name>
+      <spirit:displayName>Pf0 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_REVISION_ID" spirit:order="26">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_61bc5fcf" spirit:order="121">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_FIRST_VF_OFFSET" spirit:choiceRef="choice_list_0cee66fe" spirit:order="122.5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET" spirit:order="123">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_SRIOV_FIRST_VF_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf0 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK" spirit:order="122">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf0 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125">00000553</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_SRIOV_SUPPORTED_PAGE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf0 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID" spirit:order="124">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>Pf0 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SUBSYSTEM_ID" spirit:order="28">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_CLASS_CODE</spirit:name>
+      <spirit:displayName>Pf1 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_CLASS_CODE" spirit:order="43.03">058000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf1 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_DEVICE_ID" spirit:order="303">9011</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>Pf1 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="203">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_PBA_BIR</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="225">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_PBA_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_TABLE_BIR</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="223">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE" spirit:order="221">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET" spirit:order="222">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET" spirit:order="224">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_PBA_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>Pf1 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="207">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_REVISION_ID</spirit:name>
+      <spirit:displayName>Pf1 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_REVISION_ID" spirit:order="36">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf1 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="123.1">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_CAP_VER</spirit:name>
+      <spirit:displayName>Pf1 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_CAP_VER" spirit:order="126">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf1 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET" spirit:order="123.11">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_FIRST_VF_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf1 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK" spirit:order="128">0001</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf1 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="131">00000553</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_SUPPORTED_PAGE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf1 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID" spirit:order="130">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>Pf1 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_ID" spirit:order="37">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_CLASS_CODE</spirit:name>
+      <spirit:displayName>Pf2 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_CLASS_CODE" spirit:order="43.23">058000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf2 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_DEVICE_ID" spirit:order="25.2">9438</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>Pf2 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="167.2">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_PBA_BIR</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_PBA_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219.2">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_PBA_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_TABLE_BIR</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217.2">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_SIZE" spirit:order="220.2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_OFFSET" spirit:order="216.2">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_PBA_OFFSET" spirit:order="224.2">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_PBA_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>Pf2 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="205.2">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_REVISION_ID</spirit:name>
+      <spirit:displayName>Pf2 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_REVISION_ID" spirit:order="26.2">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf2 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121.2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_CAP_VER</spirit:name>
+      <spirit:displayName>Pf2 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_CAP_VER" spirit:order="126.2">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf2 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_FIRST_VF_OFFSET" spirit:order="123.2">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_FIRST_VF_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf2 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_FUNC_DEP_LINK" spirit:order="122.2">0002</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf2 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125.2">00000553</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_SUPPORTED_PAGE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf2 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_VF_DEVICE_ID" spirit:order="124.2">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_ID" spirit:order="28.2">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_CLASS_CODE</spirit:name>
+      <spirit:displayName>Pf3 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_CLASS_CODE" spirit:order="43.33">058000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf3 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_DEVICE_ID" spirit:order="25.3">9638</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>Pf3 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="167.3">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_PBA_BIR</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_PBA_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219.3">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_PBA_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_TABLE_BIR</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_BIR" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217.3">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_BIR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_SIZE" spirit:order="220.3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_OFFSET" spirit:order="216.3">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_PBA_OFFSET" spirit:order="218.3">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_PBA_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>Pf3 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="205.3">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_REVISION_ID</spirit:name>
+      <spirit:displayName>Pf3 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_REVISION_ID" spirit:order="26.3">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf3 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121.3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_CAP_VER</spirit:name>
+      <spirit:displayName>Pf3 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_CAP_VER" spirit:order="126.3">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf3 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_FIRST_VF_OFFSET" spirit:order="123.3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_FIRST_VF_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf3 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_FUNC_DEP_LINK" spirit:order="122.3">0003</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf3 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125.3">00000553</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_SUPPORTED_PAGE_SIZE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf3 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_VF_DEVICE_ID" spirit:order="124.3">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_ID" spirit:order="28.3">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TL_PF_ENABLE_REG</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TL_PF_ENABLE_REG" spirit:choiceRef="choice_list_aa031417" spirit:order="20">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SRIOV_CAP_ENABLE</spirit:name>
+      <spirit:displayName>Sriov Cap Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_CAP_ENABLE" spirit:choiceRef="choice_list_7a7dde49" spirit:order="22">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xdma_pcie4_ip</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="28.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.7">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_PM_CAP_PMESUPPORT_D0</spirit:name>
+      <spirit:displayName>Pf0 Pm Cap Pmesupport D0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_PM_CAP_PMESUPPORT_D0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="257">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>Pf0 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" spirit:order="27">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>Pf1 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID" spirit:order="27.103">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID" spirit:order="27.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>Pf3 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID" spirit:order="27.3">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="201">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="201.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="201.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_sub</spirit:name>
+      <spirit:displayName>Pf0 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_sub" spirit:order="34.01">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="193">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="193.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="193.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_vc_cap_enabled</spirit:name>
+      <spirit:displayName>Pf0 Vc Cap Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_vc_cap_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="268">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="199">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="199.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="199.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="168">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="168.2">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="168.3">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="162">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="198.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="198.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pcie_blk_locn</spirit:name>
+      <spirit:displayName>Pcie Blk Locn</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_blk_locn" spirit:choiceRef="choice_list_8eea463a" spirit:order="4">X1Y2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="140">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_base</spirit:name>
+      <spirit:displayName>Pf1 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_base" spirit:order="42.1">05</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_base</spirit:name>
+      <spirit:displayName>Pf2 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_base" spirit:order="42.21">05</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_base</spirit:name>
+      <spirit:displayName>Pf3 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_base" spirit:order="42.31">05</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="189">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="189.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="189.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="170">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="170.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="170.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_type</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="101">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_type</spirit:name>
+      <spirit:displayName>Pf2 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="101.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_type</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="101.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf2 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="94.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="94.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="94">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_type</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="95">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="96">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="97">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="98">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_size</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="99">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_interface</spirit:name>
+      <spirit:displayName>Pf0 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_interface" spirit:order="34.02">01</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="142">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_type</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="107">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_type</spirit:name>
+      <spirit:displayName>Pf2 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="95.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf2 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="96.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="97.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_scale</spirit:name>
+      <spirit:displayName>Pf2 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="98.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_size</spirit:name>
+      <spirit:displayName>Pf2 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="99.2">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_type</spirit:name>
+      <spirit:displayName>Pf2 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="107.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_type</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="95.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="96.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="97.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="98.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_size</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="99.3">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_type</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="107.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_base_class_menu</spirit:name>
+      <spirit:displayName>Pf0 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="33">Simple_communication_controllers</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf0 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sub_class_interface_menu" spirit:choiceRef="choice_list_d992adf6" spirit:order="34">16450_compatible_serial_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="172">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf1 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="117">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="171">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_type</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="113">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="164">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="174">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_interface</spirit:name>
+      <spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_interface" spirit:order="43.02">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="146">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_enabled</spirit:name>
+      <spirit:displayName>Pf1 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="220">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="114">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="176">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="102">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="147">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="100">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="148">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="178">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="104">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="138">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_RQ_ALIGNMENT_MODE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE" spirit:choiceRef="choice_list_81a1639d" spirit:order="15">DWORD_Aligned</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXISTEN_IF_CQ_ALIGNMENT_MODE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE" spirit:choiceRef="choice_list_81a1639d" spirit:order="16">Address_Aligned</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>alignment_mode_256b</spirit:name>
+      <spirit:displayName>Alignment Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.alignment_mode_256b" spirit:choiceRef="choice_list_81a1639d" spirit:order="299">DWORD_Aligned</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="195">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="180">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="152">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="182">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="108">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="143">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="44">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="45">Memory</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="46">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="48">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="49">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="50">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="51">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="52">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="53">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="54">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="55">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="56">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="57">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="58">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="60">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="61">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="62">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="63">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="64">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="65">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="66">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="67">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="68">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="69">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="70">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="71">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="72">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="73">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="74">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="75">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="76">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="77">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="78">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="154">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="106">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="177">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="149">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="184">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="110">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="155">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="144">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_dev_cap_max_payload</spirit:name>
+      <spirit:displayName>Pf0 Dev Cap Max Payload</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_dev_cap_max_payload" spirit:choiceRef="choice_list_7d45a81a" spirit:order="19">1024_bytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x0y0</spirit:name>
+      <spirit:displayName>Gen X0y0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x0y0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="5">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x0y0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x0y1</spirit:name>
+      <spirit:displayName>Gen X0y1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x0y1" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x0y1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x0y2</spirit:name>
+      <spirit:displayName>Gen X0y2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x0y2" spirit:choiceRef="choice_list_7a7dde49" spirit:order="7">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x0y2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x0y3</spirit:name>
+      <spirit:displayName>Gen X0y3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x0y3" spirit:choiceRef="choice_list_7a7dde49" spirit:order="8">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x0y3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x0y4</spirit:name>
+      <spirit:displayName>Gen X0y4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x0y4" spirit:choiceRef="choice_list_7a7dde49" spirit:order="328">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x0y4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x0y5</spirit:name>
+      <spirit:displayName>Gen X0y5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x0y5" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x0y5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x1y0</spirit:name>
+      <spirit:displayName>Gen X1y0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x1y0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x1y0">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x1y1</spirit:name>
+      <spirit:displayName>Gen X1y1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x1y1" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x1y1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x1y2</spirit:name>
+      <spirit:displayName>Gen X1y2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x1y2" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.4">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x1y2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x1y3</spirit:name>
+      <spirit:displayName>Gen X1y3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x1y3" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.5">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x1y3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x1y4</spirit:name>
+      <spirit:displayName>Gen X1y4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x1y4" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x1y4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_x1y5</spirit:name>
+      <spirit:displayName>Gen X1y5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_x1y5" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.7">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.gen_x1y5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="161">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf1 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="118">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf1 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="119">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="186">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="158">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="166">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="153">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="188">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="160">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_base_class_menu</spirit:name>
+      <spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="42">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="43">Other_memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="133">Memory</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="112">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="103">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="173">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="190">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="115">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_sub</spirit:name>
+      <spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_sub" spirit:order="43.01">80</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>extended_tag_field</spirit:name>
+      <spirit:displayName>Extended Tag Field</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.extended_tag_field" spirit:choiceRef="choice_list_7a7dde49" spirit:order="21">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="139">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="80">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="81">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="179">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="150">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="200">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="145">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vendor_id</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.vendor_id" spirit:order="24">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_vendor_id</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_vendor_id" spirit:order="24.1">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_vendor_id</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_vendor_id" spirit:order="24.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_vendor_id</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_vendor_id" spirit:order="24.3">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_tphr_enable</spirit:name>
+      <spirit:displayName>Pf0 Tphr Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_tphr_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="284">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="185">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="151">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="191">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="82">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_type</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="83">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="84">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="85">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="86">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_size</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_size" spirit:choiceRef="choice_list_165ed04b" spirit:order="87">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_type</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="89">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="90">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="91">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="92">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_size</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="93">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="192">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="157">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="194">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="183">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_cap_ver</spirit:name>
+      <spirit:displayName>Pf0 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_cap_ver" spirit:order="120">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="197">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msi_enabled</spirit:name>
+      <spirit:displayName>Pf1 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="206">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msi_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="165">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="163">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_pcie_cfg_space_enabled</spirit:name>
+      <spirit:displayName>Ext Pcie Cfg Space Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ext_pcie_cfg_space_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="286">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>legacy_ext_pcie_cfg_space_enabled</spirit:name>
+      <spirit:displayName>Legacy Ext Pcie Cfg Space Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.legacy_ext_pcie_cfg_space_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="286.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_xvc_vsec_enable</spirit:name>
+      <spirit:displayName>Enable to add the PCIe XVC-VSEC to the Examlpe Design</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_xvc_vsec_enable" spirit:order="287.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.ext_xvc_vsec_enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>acs_ext_cap_enable</spirit:name>
+      <spirit:displayName>ACS Ext Capability</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.acs_ext_cap_enable" spirit:order="287.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="196">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="202">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_ari_enabled</spirit:name>
+      <spirit:displayName>Pf0 Ari Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_ari_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="277">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>perf_level</spirit:name>
+      <spirit:displayName>Perf Level</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.perf_level" spirit:choiceRef="choice_list_f149a468" spirit:order="265">Extreme</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_base</spirit:name>
+      <spirit:displayName>Pf0 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_base" spirit:order="33.1">07</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_if_width</spirit:name>
+      <spirit:displayName>Axisten If Width</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_width" spirit:choiceRef="choice_list_97bc19ec" spirit:order="14">256_bit</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="156">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="169">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_size</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="105">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="159">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_aer_enabled</spirit:name>
+      <spirit:displayName>Pf0 Aer Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_aer_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="271">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_dsn_enabled</spirit:name>
+      <spirit:displayName>Pf0 Dsn Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_dsn_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="266">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="175">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_size</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="111">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msi_enabled</spirit:name>
+      <spirit:displayName>Pf0 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="204">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="198">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="181">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_enabled</spirit:name>
+      <spirit:displayName>Pf0 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="214">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_size</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="116">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="109">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="141">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf1 Sriov Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="187">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="172.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf2 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="117.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="171.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_type</spirit:name>
+      <spirit:displayName>Pf2 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="113.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="174.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_interface</spirit:name>
+      <spirit:displayName>Pf2 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_interface" spirit:order="43.22">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_msix_enabled</spirit:name>
+      <spirit:displayName>Pf2 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="215.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="114.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="176.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf2 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="102.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf2 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="100.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="178.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_scale</spirit:name>
+      <spirit:displayName>Pf2 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="104.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="195.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="180.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="182.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf2 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="108.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf2 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="106.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="177.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="184.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_scale</spirit:name>
+      <spirit:displayName>Pf2 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="110.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf2 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="118.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf2 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="119.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="186.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="188.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_base_class_menu</spirit:name>
+      <spirit:displayName>Pf2 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="42.2">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf2 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="43.2">Other_memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf2 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="112.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="103.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="173.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="190.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_scale</spirit:name>
+      <spirit:displayName>Pf2 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="115.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_sub</spirit:name>
+      <spirit:displayName>Pf2 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_sub" spirit:order="43.21">80</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="179.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="200.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="185.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="191.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf2 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="82.2">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_type</spirit:name>
+      <spirit:displayName>Pf2 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="83.2">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf2 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="84.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="85.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_scale</spirit:name>
+      <spirit:displayName>Pf2 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="86.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_size</spirit:name>
+      <spirit:displayName>Pf2 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_size" spirit:choiceRef="choice_list_165ed04b" spirit:order="87.2">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf2 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_type</spirit:name>
+      <spirit:displayName>Pf2 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="89.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf2 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="90.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="91.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_scale</spirit:name>
+      <spirit:displayName>Pf2 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="92.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_size</spirit:name>
+      <spirit:displayName>Pf2 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="93.2">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="192.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="194.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="183.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="197.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_msi_enabled</spirit:name>
+      <spirit:displayName>Pf2 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="206.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_msi_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="196.2">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="202.2">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="169.2">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_size</spirit:name>
+      <spirit:displayName>Pf2 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="105.2">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="175.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_size</spirit:name>
+      <spirit:displayName>Pf2 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="111.2">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="181.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_size</spirit:name>
+      <spirit:displayName>Pf2 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="116.2">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf2 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="109.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf2 Sriov Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="187.2">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="172.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf3 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="117.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="171.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_type</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="113.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="174.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_interface</spirit:name>
+      <spirit:displayName>Pf3 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_interface" spirit:order="43.32">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_msix_enabled</spirit:name>
+      <spirit:displayName>Pf3 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="215.3">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="114.3">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="176.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="102.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="100.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="178.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="104.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="195.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="180.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="182.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="108.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="106.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="177.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="184.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="110.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf3 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="118.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf3 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="119.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="186.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="188.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_base_class_menu</spirit:name>
+      <spirit:displayName>Pf3 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="42.3">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf3 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="43.3">Other_memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="112.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="103.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="173.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="190.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="115.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_sub</spirit:name>
+      <spirit:displayName>Pf3 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_sub" spirit:order="43.31">80</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="179.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="200.3">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="185.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="191.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="82.3">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_type</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="83.3">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="84.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="85.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="86.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_size</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_size" spirit:choiceRef="choice_list_165ed04b" spirit:order="87.3">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_type</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="89.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="90.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="91.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="92.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_size</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="93.3">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="192.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="194.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="183.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="197.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_msi_enabled</spirit:name>
+      <spirit:displayName>Pf3 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="206.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_msi_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="196.3">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="202.3">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="169.3">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_size</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="105.3">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="175.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_size</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="111.3">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="181.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_size</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_size" spirit:choiceRef="choice_list_34d65ff4" spirit:order="116.3">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="109.3">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf3 Sriov Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="187.3">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mode_selection</spirit:name>
+      <spirit:displayName>Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mode_selection" spirit:choiceRef="choice_list_24b724fb" spirit:order="22.2">Advanced</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pipe_sim</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pipe_sim" spirit:order="294">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_ext_clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_ext_clk" spirit:order="295">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_msi_per_vec_masking</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_msi_per_vec_masking" spirit:order="296">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>coreclk_freq</spirit:name>
+      <spirit:displayName>CORE CLOCK FREQ</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.coreclk_freq" spirit:choiceRef="choice_list_3d9ff82c" spirit:order="333">500</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.coreclk_freq">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>plltype</spirit:name>
+      <spirit:displayName>PLL TYPE</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.plltype" spirit:choiceRef="choice_list_88156f2e" spirit:order="334">QPLL1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_freq</spirit:name>
+      <spirit:displayName>AXISTEN IF FREQ</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_freq" spirit:choiceRef="choice_list_6b979ebc" spirit:order="297">250</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>aspm_support</spirit:name>
+      <spirit:displayName>ASPM Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.aspm_support" spirit:choiceRef="choice_list_ca005b72" spirit:order="298">No_ASPM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SRIOV_CAP_ENABLE_EXT</spirit:name>
+      <spirit:displayName>SRIOV Cap Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_CAP_ENABLE_EXT" spirit:choiceRef="choice_list_7a7dde49" spirit:order="287">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_fc_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_fc_if" spirit:order="303">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_ext_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_ext_if" spirit:order="304">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_status_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_status_if" spirit:order="305">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>per_func_status_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.per_func_status_if" spirit:order="306">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_mgmt_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_mgmt_if" spirit:order="307">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rcv_msg_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rcv_msg_if" spirit:order="308">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_tx_msg_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_tx_msg_if" spirit:order="309">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_ctl_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_ctl_if" spirit:order="310">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tx_fc_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.tx_fc_if" spirit:order="311">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_pcie_drp</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_pcie_drp" spirit:order="314">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_parity</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.en_parity" spirit:choiceRef="choice_list_7a7dde49" spirit:order="300">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_pl_ifc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_pl_ifc" spirit:order="318">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_pcie_conf</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_pcie_conf" spirit:order="322">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dis_gt_wizard</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.dis_gt_wizard" spirit:order="323">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bmd_pio_mode</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.bmd_pio_mode" spirit:order="12.9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>sriov_exd_mode</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.sriov_exd_mode" spirit:order="12.8">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dbg_checker</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.dbg_checker" spirit:order="13.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.dbg_checker">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_ibert</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ibert" spirit:order="13.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>two_port_switch</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.two_port_switch" spirit:order="323.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>two_port_config</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.two_port_config" spirit:choiceRef="choice_list_75aee2a8" spirit:order="323.3">X8G3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_PPM_OFFSET</spirit:name>
+      <spirit:description>Specify the PPM offset between received data and transmitted data</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PPM_OFFSET" spirit:order="323.7" spirit:minimum="0" spirit:maximum="600" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_SSC_PPM</spirit:name>
+      <spirit:description>Specify the spread spectrum clocking modulation in PPM</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_SSC_PPM" spirit:order="323.8" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INS_LOSS_NYQ</spirit:name>
+      <spirit:description>Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.INS_LOSS_NYQ" spirit:order="323.9" spirit:minimum="0">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ins_loss_profile</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ins_loss_profile" spirit:choiceRef="choice_list_0f93492c" spirit:order="323.6" spirit:configGroups="1 UnGrouped">Add-in_Card</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.ins_loss_profile">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_gen4</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_gen4" spirit:order="12.1">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>local_test</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.local_test" spirit:order="12.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_transceiver_status_ports</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_transceiver_status_ports" spirit:order="324">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_transceiver_status_ports">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic" spirit:choiceRef="choice_pairs_53749dec" spirit:order="350">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gtwiz_in_core</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtwiz_in_core" spirit:choiceRef="choice_pairs_3c87fcdb" spirit:order="350.1">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gtcom_in_core</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtcom_in_core" spirit:choiceRef="choice_pairs_6f00a734" spirit:order="350.2">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dedicate_perst</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.dedicate_perst" spirit:order="326">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>sys_reset_polarity</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sys_reset_polarity" spirit:choiceRef="choice_list_6eff49bd" spirit:order="327">ACTIVE_LOW</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mcap_enablement</spirit:name>
+      <spirit:displayName>MCAP Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mcap_enablement" spirit:choiceRef="choice_list_8061eec5" spirit:order="330">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mcap_fpga_bitstream_version</spirit:name>
+      <spirit:displayName>MCAP Bitstream Version Register Value</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mcap_fpga_bitstream_version" spirit:order="330.1">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.mcap_fpga_bitstream_version">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_code</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_code" spirit:order="1.1">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_ext_ch_gt_drp</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_ext_ch_gt_drp" spirit:order="331">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_startup_primitive</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_startup_primitive" spirit:order="332">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_gt_selection</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_gt_selection" spirit:order="3.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>select_quad</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.select_quad" spirit:choiceRef="choice_list_abc20383" spirit:order="4.5">GTY_Quad_227</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.select_quad">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>copy_pf0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.copy_pf0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>copy_sriov_pf0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.copy_sriov_pf0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6.5">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_pm_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_pm_if" spirit:order="433">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pcie_id_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_id_if" spirit:order="434">FALSE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PL_DISABLE_LANE_REVERSAL</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PL_DISABLE_LANE_REVERSAL" spirit:order="435">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MSI_X_OPTIONS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MSI_X_OPTIONS" spirit:choiceRef="choice_list_bea500ca" spirit:order="200.1">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>completer_model</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.completer_model" spirit:order="436">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_dbg_descramble</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_dbg_descramble" spirit:order="437">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_jtag_dbg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_jtag_dbg" spirit:order="437.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_jtag_dbg">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_ltssm_dbg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ltssm_dbg" spirit:order="437.2">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_ltssm_dbg">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_credits_cd</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_credits_cd" spirit:order="438">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_credits_ch</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_credits_ch" spirit:order="439">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>set_finite_credit</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.set_finite_credit" spirit:order="440">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen4_eieos_0s7</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.gen4_eieos_0s7" spirit:order="441">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vu9p_board</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vu9p_board" spirit:order="442">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ku15p_board</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ku15p_board" spirit:order="442.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PHY_LP_TXPRESET</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHY_LP_TXPRESET" spirit:choiceRef="choice_list_8b5e4915" spirit:order="443">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYS_RST_N_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SYS_RST_N_BOARD_INTERFACE" spirit:choiceRef="choice_list_a30da595" spirit:order="443">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_BOARD_INTERFACE" spirit:choiceRef="choice_list_a44ca313" spirit:order="444">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gt_drp_clk_src</spirit:name>
+      <spirit:displayName>GT DRP Clk Source</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gt_drp_clk_src" spirit:choiceRef="choice_list_9aec9108" spirit:order="446">Internal</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>free_run_freq</spirit:name>
+      <spirit:displayName>Free Run Freq</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.free_run_freq" spirit:choiceRef="choice_list_914704bd" spirit:order="447">100_MHz</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_l23_entry</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_l23_entry" spirit:order="448">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>aws_mode_value</spirit:name>
+      <spirit:displayName>aws mode value</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.aws_mode_value" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="449">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_sys_clk_bufg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_sys_clk_bufg" spirit:order="450">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mult_pf_des</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.mult_pf_des" spirit:order="451">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_if_enable_msg_route</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_enable_msg_route" spirit:order="452">20000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axisten_if_enable_msg_route">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_more_clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_more_clk" spirit:order="353">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ctrl_skip_mask</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ctrl_skip_mask" spirit:order="354">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_bram_pipeline</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_bram_pipeline" spirit:order="453">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_eq_synchronizer</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_eq_synchronizer" spirit:order="454">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_if_enable_rx_msg_intfc</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_enable_rx_msg_intfc" spirit:choiceRef="choice_list_7a7dde49" spirit:order="291">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_if_enable_msg_route_override</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_enable_msg_route_override" spirit:order="456">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_auto_rxeq</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_auto_rxeq" spirit:choiceRef="choice_list_bdd7203f" spirit:order="457">False</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>msix_type</spirit:name>
+      <spirit:displayName>MSI-X Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_type" spirit:choiceRef="choice_list_38306dd1" spirit:order="458">HARD</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>three_port_switch</spirit:name>
+      <spirit:displayName>Three Port Switch Enable</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.three_port_switch" spirit:choiceRef="choice_list_7a7dde49" spirit:order="459">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_gt_loc</spirit:name>
+      <spirit:displayName>Disable GT loc constraint delivery</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_gt_loc" spirit:choiceRef="choice_list_7a7dde49" spirit:order="460">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disconnect_hot_reset</spirit:name>
+      <spirit:displayName>disconnect hot_reset from user_reset</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disconnect_hot_reset" spirit:choiceRef="choice_list_7a7dde49" spirit:order="460.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ku15p_gt_long_route</spirit:name>
+      <spirit:displayName>Enables KU15P GT long route</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ku15p_gt_long_route" spirit:choiceRef="choice_list_7a7dde49" spirit:order="460.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_mark_debug</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_mark_debug" spirit:choiceRef="choice_list_7a7dde49" spirit:order="461">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_multipf_aer</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_multipf_aer" spirit:choiceRef="choice_list_7a7dde49" spirit:order="462">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>master_cal_only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.master_cal_only" spirit:choiceRef="choice_list_7a7dde49" spirit:order="463">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_multi_pcie</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_multi_pcie" spirit:choiceRef="choice_list_7a7dde49" spirit:order="464">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rbar_enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rbar_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="465">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF0</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="466">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF1</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="467">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF2</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="468">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF3</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="469">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_index</spirit:name>
+      <spirit:displayName>PF0 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_index" spirit:order="470">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_index</spirit:name>
+      <spirit:displayName>PF0 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_index" spirit:order="471">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_index</spirit:name>
+      <spirit:displayName>PF0 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_index" spirit:order="472">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_index</spirit:name>
+      <spirit:displayName>PF0 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_index" spirit:order="473">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_index</spirit:name>
+      <spirit:displayName>PF0 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_index" spirit:order="474">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_index</spirit:name>
+      <spirit:displayName>PF0 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_index" spirit:order="475">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_index</spirit:name>
+      <spirit:displayName>PF0 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_index" spirit:order="476">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_index</spirit:name>
+      <spirit:displayName>PF1 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_index" spirit:order="477">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_index</spirit:name>
+      <spirit:displayName>PF1 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_index" spirit:order="478">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_index</spirit:name>
+      <spirit:displayName>PF1 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_index" spirit:order="479">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_index</spirit:name>
+      <spirit:displayName>PF1 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_index" spirit:order="480">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_index</spirit:name>
+      <spirit:displayName>PF1 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_index" spirit:order="481">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_index</spirit:name>
+      <spirit:displayName>PF2 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_index" spirit:order="482">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_index</spirit:name>
+      <spirit:displayName>PF2 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_index" spirit:order="483">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_index</spirit:name>
+      <spirit:displayName>PF2 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_index" spirit:order="484">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_index</spirit:name>
+      <spirit:displayName>PF2 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_index" spirit:order="485">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_index</spirit:name>
+      <spirit:displayName>PF2 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_index" spirit:order="486">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_index</spirit:name>
+      <spirit:displayName>PF2 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_index" spirit:order="487">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_index</spirit:name>
+      <spirit:displayName>PF3 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_index" spirit:order="488">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_index</spirit:name>
+      <spirit:displayName>PF3 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_index" spirit:order="489">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_index</spirit:name>
+      <spirit:displayName>PF3 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_index" spirit:order="490">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_index</spirit:name>
+      <spirit:displayName>PF3 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_index" spirit:order="491">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_index</spirit:name>
+      <spirit:displayName>PF3 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_index" spirit:order="492">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_index</spirit:name>
+      <spirit:displayName>PF3 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_index" spirit:order="493">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar0" spirit:order="494">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar1" spirit:order="495">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar2" spirit:order="496">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar3" spirit:order="497">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar4" spirit:order="498">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar5" spirit:order="499">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar0" spirit:order="500">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar1" spirit:order="501">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar2" spirit:order="502">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar3" spirit:order="503">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar4" spirit:order="504">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar5" spirit:order="505">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar0" spirit:order="506">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar1" spirit:order="507">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar2" spirit:order="508">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar3" spirit:order="509">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar4" spirit:order="510">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar5" spirit:order="511">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar0" spirit:order="512">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar1" spirit:order="513">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar2" spirit:order="514">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar3" spirit:order="515">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar4" spirit:order="516">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar5" spirit:order="517">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG0_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>vfg0 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG0_MSIX_CAP_PBA_OFFSET" spirit:order="518">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG1_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>vfg1 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG1_MSIX_CAP_PBA_OFFSET" spirit:order="519">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG2_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>vfg2 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG2_MSIX_CAP_PBA_OFFSET" spirit:order="520">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG3_MSIX_CAP_PBA_OFFSET</spirit:name>
+      <spirit:displayName>vfg3 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG3_MSIX_CAP_PBA_OFFSET" spirit:order="521">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG0_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>vfg0 Msix Cap table Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG0_MSIX_CAP_TABLE_OFFSET" spirit:order="522">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG1_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>vfg1 Msix Cap table Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG1_MSIX_CAP_TABLE_OFFSET" spirit:order="523">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG2_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>vfg2 Msix Cap table Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG2_MSIX_CAP_TABLE_OFFSET" spirit:order="524">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG3_MSIX_CAP_TABLE_OFFSET</spirit:name>
+      <spirit:displayName>vfg3 Msix Cap table Offset</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG3_MSIX_CAP_TABLE_OFFSET" spirit:order="525">00000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG0_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>vfg0 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG0_MSIX_CAP_TABLE_SIZE" spirit:order="526">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG1_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>vfg1 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG1_MSIX_CAP_TABLE_SIZE" spirit:order="527">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG2_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>vfg2 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG2_MSIX_CAP_TABLE_SIZE" spirit:order="528">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VFG3_MSIX_CAP_TABLE_SIZE</spirit:name>
+      <spirit:displayName>vfg3 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VFG3_MSIX_CAP_TABLE_SIZE" spirit:order="529">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_clkmux</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_clkmux" spirit:choiceRef="choice_list_7a7dde49" spirit:order="530">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_msix_pfs_for_vfs</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.use_msix_pfs_for_vfs" spirit:choiceRef="choice_list_7a7dde49" spirit:order="532">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_standard_interfaces</spirit:name>
+      <spirit:displayName>use standard interfaces for IPI design</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_standard_interfaces" spirit:choiceRef="choice_list_7a7dde49" spirit:order="533">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dma_2rp</spirit:name>
+      <spirit:displayName>Truncate ports for 2RP DMA design</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dma_2rp" spirit:choiceRef="choice_list_7a7dde49" spirit:order="534">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>double_quad</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.double_quad" spirit:order="535">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_epyc_chipset_fix</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_epyc_chipset_fix" spirit:order="536">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_user_clock_root</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_user_clock_root" spirit:order="537">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_msix_32vec</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_msix_32vec" spirit:order="539">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>broadcom_sbr_wa</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.broadcom_sbr_wa" spirit:order="540">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MASTER_GT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MASTER_GT" spirit:order="538">GTHE4_CHANNEL_X49Y99</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>qdma_tph_msix_brams_dis</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.qdma_tph_msix_brams_dis" spirit:choiceRef="choice_list_7a7dde49" spirit:order="539">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>user_interface_signals</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.user_interface_signals" spirit:order="541">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>link_training_signals</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.link_training_signals" spirit:order="541.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>transmit_fc_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.transmit_fc_interface" spirit:order="541.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_fc_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_fc_interface" spirit:order="541.3">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_status_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_status_interface" spirit:order="541.4">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_mgmt_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_mgmt_interface" spirit:order="541.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rx_mesg_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rx_mesg_interface" spirit:order="541.6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_tx_mesg_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_tx_mesg_interface" spirit:order="541.7">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_interface" spirit:order="541.8">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.config_interface">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_ctrl_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_ctrl_interface" spirit:order="541.9">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>config_pwr_mgmt_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.config_pwr_mgmt_interface" spirit:order="541.11">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>interrupt_interface</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.interrupt_interface" spirit:order="541.12">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>descrambler_pipe_debug_signals</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.descrambler_pipe_debug_signals" spirit:order="541.13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.descrambler_pipe_debug_signals">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>descrambler_user_interface_signals</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.descrambler_user_interface_signals" spirit:order="541.14">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>exdes_simulation_tab</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.exdes_simulation_tab" spirit:order="542">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_tx_mux_strict_priority</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_tx_mux_strict_priority" spirit:order="543">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_usp_ct1h</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_usp_ct1h" spirit:order="544">false</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>UltraScale+ Integrated Block (PCIE4) for PCI Express</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>9</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXISTEN_IF_CQ_ALIGNMENT_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXISTEN_IF_RQ_ALIGNMENT_MODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INS_LOSS_NYQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_CLASS_CODE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_INTERRUPT_PIN" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_REVISION_ID" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_Use_Class_Code_Lookup_Assistant" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PHY_LP_TXPRESET" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.REF_CLK_FREQ" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RX_SSC_PPM" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.acs_ext_cap_enable" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.aspm_support" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_enable_client_tag" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_enable_msg_route" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_enable_msg_route_override" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_if_width" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.broadcom_sbr_wa" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cfg_ext_if" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.coreclk_freq" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ctrl_skip_mask" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dedicate_perst" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.device_port_type" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_bram_pipeline" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_eq_synchronizer" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_gt_loc" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.disable_user_clock_root" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_dbg_descramble" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_ext_ch_gt_drp" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_ext_clk" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_gt_selection" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_l23_entry" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_parity" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_pcie_drp" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.en_transceiver_status_ports" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_auto_rxeq" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_code" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_epyc_chipset_fix" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_gen4" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_ibert" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_jtag_dbg" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_ltssm_dbg" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_mark_debug" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_more_clk" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_msix_32vec" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_multi_pcie" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_pcie_cfg_space_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_startup_primitive" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_sys_clk_bufg" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ext_xvc_vsec_enable" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.extended_tag_field" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.free_run_freq" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gen4_eieos_0s7" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_drp_clk_src" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gtcom_in_core" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gtwiz_in_core" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ins_loss_profile" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.local_test" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.master_cal_only" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mcap_enablement" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.mode_selection" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.msix_type" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_blk_locn" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_id_if" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_64bit" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_scale" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar0_size" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar1_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar2_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar3_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar4_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_bar5_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_base_class_menu" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_base" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_interface" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_sub" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msi_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_num" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar1_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar2_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar3_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar4_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar5_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_num" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar0_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar1_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar2_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar3_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar4_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_bar5_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_num" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar0_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar1_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar2_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar3_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar4_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_bar5_index" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_expansion_rom_enabled" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar0" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar1" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar2" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar3" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar4" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar5" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_num" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pipe_sim" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.rbar_enable" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.set_finite_credit" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.sys_reset_polarity" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.tl_credits_cd" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.tl_credits_ch" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.tl_tx_mux_strict_priority" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.vendor_id" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.vu9p_board" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xlnx_ref_board" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="42e44025"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d1923d79"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="27001fcb"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a51cc25f"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="a18b2b04"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci
new file mode 100644
index 0000000..c39c603
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci
@@ -0,0 +1,328 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xdma_v4_1_8_blk_mem_64_reg_be</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     2.618 mW</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">8</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xdma_v4_1_8_blk_mem_64_reg_be</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;va
+lue_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}
+,&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;8&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_ri
+ght&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;71&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;
+value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;8&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;71&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml
new file mode 100644
index 0000000..5356d3b
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml
@@ -0,0 +1,4188 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>xdma_v4_1_8_blk_mem_64_reg_be</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">8</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
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+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">xdma_v4_1_8_blk_mem_64_reg_be.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     2.618 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f92be8b1</spirit:name>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+      <spirit:enumeration>72</spirit:enumeration>
+      <spirit:enumeration>144</spirit:enumeration>
+      <spirit:enumeration>288</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_eab86dfe</spirit:name>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xdma_v4_1_8_blk_mem_64_reg_be</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Simple_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="9" spirit:maximum="4608" spirit:rangeType="long">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">512</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_f92be8b1" spirit:order="22">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">READ_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_f92be8b1" spirit:order="25">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_f92be8b1" spirit:order="26">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_eab86dfe" spirit:order="27">READ_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_27c66b0d" spirit:order="3">Stand_Alone</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">no_mem_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52ed1045"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9c3516e3"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci
new file mode 100644
index 0000000..8122d37
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci
@@ -0,0 +1,328 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xdma_v4_1_8_blk_mem_64_noreg_be</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     2.618 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">xdma_v4_1_8_blk_mem_64_noreg_be.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xdma_v4_1_8_blk_mem_64_noreg_be</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fsgd2104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;clkb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;enb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addrb&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;doutb&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;va
+lue_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}}
+,&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;8&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_ri
+ght&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;71&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;BRAM_PORTB&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;
+value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addrb&quot;,&quot;physical_left&quot;:&quot;8&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;8&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clkb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;doutb&quot;,&quot;physical_left&quot;:&quot;71&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;71&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;enb&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml
new file mode 100644
index 0000000..ea36ea9
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml
@@ -0,0 +1,4188 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>xdma_v4_1_8_blk_mem_64_noreg_be</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
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+      </spirit:portMaps>
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+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">true</xilinx:isEnabled>
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+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
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+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        <spirit:name>ena</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
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+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">8</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">71</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>douta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
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+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
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+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.douta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rstb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+          <xilinx:portInfo>
+            <xilinx:enablement>
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+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>enb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+            <xilinx:enablement>
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+      <spirit:port>
+        <spirit:name>regceb</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
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+        <spirit:name>web</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectsbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectsbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_injectdbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_injectdbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_INJECTERR&apos;)) = 3) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_sbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_sbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_dbiterr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_dbiterr" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdaddrecc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRB_WIDTH&apos;))-1">8</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdaddrecc" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_ECC&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_SOFTECC&apos;)) = 1) and spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="STRING">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_ELABORATION_DIR</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_SLAVE_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_AXI_ID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MEM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_BYTE_SIZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">xdma_v4_1_8_blk_mem_64_noreg_be.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">72</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">512</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">9</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     2.618 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f92be8b1</spirit:name>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>36</spirit:enumeration>
+      <spirit:enumeration>72</spirit:enumeration>
+      <spirit:enumeration>144</spirit:enumeration>
+      <spirit:enumeration>288</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_eab86dfe</spirit:name>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xdma_v4_1_8_blk_mem_64_noreg_be</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Simple_Dual_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="9" spirit:maximum="4608" spirit:rangeType="long">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">512</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_f92be8b1" spirit:order="22">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">READ_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_f92be8b1" spirit:order="25">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_f92be8b1" spirit:order="26">72</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_eab86dfe" spirit:order="27">READ_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Use_ENB_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">no_coe_file_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
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+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
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+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
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+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">true</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
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+    <spirit:parameter>
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+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_27c66b0d" spirit:order="3">Stand_Alone</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">no_mem_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
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+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
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+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">false</xilinx:isEnabled>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
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+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
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+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
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+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a1d35893"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4ba6d99f"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="3031f2fd"/>
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+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e6bad347"/>
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+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xci b/projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xci
new file mode 100644
index 0000000..e9737de
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xci
@@ -0,0 +1,2283 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
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+      <spirit:instanceName>xdma</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xdma" spirit:version="4.1"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TSTRB">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_B.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_RX.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_RX.DATACHECK">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_RX.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_RX.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_TX.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_TX.DATACHECK">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_TX.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCIE4_CXS_TX.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.AXI_CTL_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST_N.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST_N.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.S_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.USER_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DISABLE_EQ_SYNCHRONIZER">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_IBERT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_JTAG_DBG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_LTSSM_DBG">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ENABLE_MORE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_AXI_MASTER_IF">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_AXI_SLAVE_IF">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_GT_SELECTION">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR3_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE">0x0A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR4_CONTROL">0x6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE">0x0A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_BAR5_CONTROL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_CLASS_CODE">0x070001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_DEVICE_ID">0x9111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_ENABLED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE">0x000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_MSIX_TAR_ID">0x09</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_6">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF1_VENDOR_ID">0x10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF2_DEVICE_ID">0x9211</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF2_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF2_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF3_DEVICE_ID">0x9311</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF3_REVISION_ID">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF3_SUBSYSTEM_ID">0x0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PF_SWAP">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_DEBUG_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_LINE_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PIPE_SIM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PLL_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PL_UPSTREAM_FACING">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RBAR_ENABLE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RD_CH0_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RD_CH1_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RD_CH2_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RD_CH3_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RQ_SEQ_NUM_IGNORE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RUNBIT_FIX">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.RX_DETECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SELECT_QUAD">GTY_Quad_227</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_BOTH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_CLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_GTC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SHELL_BRIDGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SILICON_REV">Pre-Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SOFT_RESET_EN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPLIT_DMA">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SPLIT_DMA_SINGLE_PF">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SRIOV_ACTIVE_VFS">252</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYS_RESET_POLARITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ULTRASCALE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ULTRASCALE_PLUS">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USER_CLK_FREQ">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_STANDARD_INTERFACES">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USRINT_EXPN">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USR_IRQ_EXDES">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.V7_GEN3">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VCU118_BOARD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_EXT_PF0">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_EXT_PF1">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_EXT_PF2">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_EXT_PF3">0x00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_INT_PF0">0x01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_INT_PF1">0x01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_INT_PF2">0x01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VF_BARLITE_INT_PF3">0x01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VU9P_BOARD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VU9P_TUL_EX">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.WR_CH0_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.WR_CH1_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.WR_CH2_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.WR_CH3_ENABLED">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_APERTURE_SIZE">0x09</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_AXILITE_MASTER">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_AXILITE_SLAVE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_AXIST_BYPASS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_AXI_INTF_MM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_CONTROL">0x4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_DSC_BYPASS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_NON_INCREMENTAL_EXDES">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_NUM_PCIE_TAG">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_NUM_USR_IRQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_PCIE_64BIT_EN">xdma_pcie_64bit_en</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_RNUM_CHNL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_RNUM_RIDS">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_STS_PORTS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_ST_INFINITE_DESC_EXDES">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_WNUM_CHNL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.XDMA_WNUM_RIDS">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.xlnx_ref_board">AU200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.BASEADDR">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.HIGHADDR">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.PF1_Use_Class_Code_Lookup_Assistant">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.Shared_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axi_addr_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axi_data_width">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axi_id_width">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar2pciebar_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar2pciebar_1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar2pciebar_2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar2pciebar_3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar2pciebar_4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar2pciebar_5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_highaddr_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_highaddr_1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_highaddr_2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_highaddr_3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_highaddr_4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_highaddr_5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axibar_num">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axilite_master_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axilite_master_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axilite_master_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axist_bypass_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axist_bypass_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axist_bypass_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.axisten_freq">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.bar0_indicator">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.bar1_indicator">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.bar2_indicator">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.bar3_indicator">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.bar4_indicator">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.bar5_indicator">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.c_m_axi_num_read">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.c_m_axi_num_write">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.c_s_axi_num_read">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.c_s_axi_num_write">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.cfg_mgmt_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.comp_timeout">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.dedicate_perst">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.device_port_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.drp_clk_sel">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.ecc_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_axi_master_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_axi_mm_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_axi_slave_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_axi_st_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_ext_ch_gt_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_pcie_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.en_transceiver_status_ports">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.enable_ibert">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.enable_jtag_dbg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.enable_ltssm_dbg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.free_run_freq">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.functional_mode">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.include_baroffset_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.mode_selection">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.parity_settings">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pcie_blk_locn">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_axil_master">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_axist_bypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pciebar2axibar_xdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_Use_Class_Code_Lookup_Assistant">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar0_64bit">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar0_scale">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar0_size">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar0_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar1_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar1_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar1_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar1_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar2_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar2_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar2_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar3_scale">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar4_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar4_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar4_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar5_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar5_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar5_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_bar5_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_base_class_menu">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_base">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_base_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_interface">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_interface_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_sub">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_class_code_sub_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_device_id">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_interrupt_pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_msi_cap_multimsgcap">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_revision_id">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_sub_class_interface_menu">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_sub_class_interface_menu_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_subsystem_id">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf0_subsystem_vendor_id">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_bar0_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_bar1_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_bar2_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_bar3_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_bar4_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_bar5_type">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_base">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_base_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_interface">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_interface_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_sub">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_class_code_sub_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_pciebar2axibar_6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_sub_class_interface_menu">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf1_sub_class_interface_menu_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_bar0_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_bar1_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_bar2_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_bar3_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_bar4_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_bar5_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_class_code_base_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_class_code_interface_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_class_code_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_class_code_sub_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_pciebar2axibar_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_pciebar2axibar_1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_pciebar2axibar_2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_pciebar2axibar_3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_pciebar2axibar_4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_pciebar2axibar_5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf2_sub_class_interface_menu_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_bar0_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_bar1_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_bar2_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_bar3_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_bar4_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_bar5_type">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_class_code_base_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_class_code_interface_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_class_code_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_class_code_sub_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_pciebar2axibar_0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_pciebar2axibar_1">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pf3_sub_class_interface_menu_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pipe_sim">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pl_link_cap_max_link_speed">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.pl_link_cap_max_link_width">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.ref_clk_freq">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.s_axi_id_width">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.sys_reset_polarity">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.timeout0_sel">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.timeout1_sel">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.timeout_mult">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.vendor_id">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_axi_intf_mm">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_axilite_slave">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_num_usr_irq">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_rnum_chnl">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_scale">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_size">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xdma_wnum_chnl">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.xlnx_ref_board">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BASEADDR">0x00001000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xdma</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HIGHADDR">0x00001FFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_X_OPTIONS">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID_mqdma">9038</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR_mqdma">BAR_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID_mqdma">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID_mqdma">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR_mqdma">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET_mqdma">00000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE_mqdma">000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID_mqdma">10EE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHY_LP_TXPRESET">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_PPM_OFFSET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_SSC_PPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYS_RST_N_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Both">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Both_7xG2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Clk_7xG2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Gtc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Gtc_7xG2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.acs_ext_cap_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_aclk_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_addr_width">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_bypass_64bit_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_bypass_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_data_width">256_bit</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_id_width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_vip_in_exdes">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axil_master_64bit_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axil_master_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axilite_master_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axilite_master_scale">Megabytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axilite_master_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_pipe_line_stage">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axist_bypass_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axist_bypass_scale">Megabytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axist_bypass_size">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">27FFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axsize_byte_access_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar0_indicator">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar1_indicator">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar2_indicator">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar3_indicator">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar4_indicator">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar5_indicator">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar_indicator">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.barlite2">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bridge_registers_offset_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.broadcom_sbr_wa">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ats_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ats_switch_unique_bdf">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_num_read">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_num_readq">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_num_write">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_pri_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axi_num_read">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axi_num_write">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axi_supports_narrow_burst">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_smmu_en">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.comp_timeout">50ms</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.copy_pf0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.copy_sriov_pf0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.coreclk_freq">500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ctrl_skip_mask">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dedicate_perst">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_bram_pipeline">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_eq_synchronizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_gt_loc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_user_clock_root">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dma_2rp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dma_reset_source_sel">User_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.drp_clk_sel">Internal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_rd">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_rd_out">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_wr">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_wr_out">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_master_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_mm_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_slave_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_st_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_bridge">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_coreclk_es1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dbg_descramble">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_debug_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dma_and_bridge">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_gt_selection">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_l23_entry">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ats_switch">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_auto_rxeq">False</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ccix">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_code">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_dvsec">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_epyc_chipset_fix">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_gen4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ibert">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_jtag_dbg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_lane_reversal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ltssm_dbg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_mark_debug">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_more_clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_multi_pcie">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_pcie_debug">False</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_resource_reduction">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_slave_read_64os">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_startup_primitive">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_sys_clk_bufg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_xvc_vsec_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flr_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.free_run_freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.functional_mode">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen4_eieos_0s7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_pipe_debug">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtcom_in_core_usp">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core_us">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core_usp">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.include_baroffset_reg">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ins_loss_profile">Add-in_Card</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.intx_rx_pin_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.legacy_cfg_ext_if">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.local_test">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.m_axib_num_write_scale">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.master_cal_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_enablement">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Basic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mpsoc_pl_rp_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msi_rx_pin_en">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_pcie_internal">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_rx_decode_en">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_rx_pin_en">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_type">HARD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mult_pf_des">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.num_queues">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.old_bridge_timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.parity_settings">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X1Y2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_extended_tag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_id_if">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_6">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axil_master">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axist_bypass">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_xdma">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.performance">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_cap_ecrc_gen_and_check_capable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ats_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type_mqdma">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code">070001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">07</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base_mqdma">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface_mqdma">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_mqdma">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub_mqdma">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_device_id">9038</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_interrupt_pin">INTA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_link_status_slot_clock_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_cap_multimsgcap">1_vector</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_pba_bir">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_pba_offset">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_table_bir">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_table_offset">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_table_size">000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_impl_locn">Internal</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pri_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_revision_id">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">16450_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_subsystem_id">0007</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_subsystem_vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vendor_id_mqdma">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Megabytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type_mqdma">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code">070001</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">07</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base_mqdma">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">01</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface_mqdma">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_mqdma">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub_mqdma">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_device_id">1041</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_pba_bir">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_pba_offset">00009FE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_table_bir">BAR_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_table_offset">00009000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_table_size">01F</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_6">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">16450_compatible_serial_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_vendor_id_mqdma">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_enabled_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_type_mqdma">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_base_class_menu">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_base_mqdma">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_interface_mqdma">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_mqdma">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_sub_mqdma">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_device_id">1040</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_msi_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_msix_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_type">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_vendor_id_mqdma">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_enabled_mqdma">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_index">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_type_mqdma">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_64bit_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_index">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_size">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_size_mqdma">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_type">Memory</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_type_mqdma">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_base_class_menu">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_base">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_base_mqdma">05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_interface">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_interface_mqdma">00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_mqdma">058000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_sub">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_sub_mqdma">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_device_id">1039</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_size">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_msi_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_msix_enabled_mqdma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_num">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_enabled">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_type">DMA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_64bit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_enabled">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_size">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_type">N/A</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_vendor_id_mqdma">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf_swap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_line_stage">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_link_cap_max_link_speed">8.0_GT/s</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_link_cap_max_link_width">X8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.plltype">QPLL1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.post_synth_sim_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prog_usr_irq_vec_map">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rbar_enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcfg_nph_fix_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ref_clk_freq">100_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.runbit_fix">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rx_detect">Default</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.s_axi_id_width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.select_quad">GTY_Quad_227</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.set_finite_credit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shell_bridge">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Pre-Production</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.soft_reset_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.split_dma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.split_dma_single_pf">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_reset_polarity">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.timeout0_sel">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.timeout1_sel">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.timeout_mult">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_credits_cd">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_credits_ch">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf_enable_reg">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_tx_mux_strict_priority">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.two_bypass_bar">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.type1_membase_memlimit_enable">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.type1_prefetchable_membase_memlimit">Disabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_standard_interfaces">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.user_pf_two_axilite_bar_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.usplus_es1_seqnum_bypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.usr_irq_exdes">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.usrint_expn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vcu118_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vcu1525_ddr_ex">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu9p_board">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu9p_tul_ex">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_axi_intf_mm">AXI_Stream</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_axilite_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_dsc_bypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_non_incremental_exdes">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_num_usr_irq">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_scale">Kilobytes</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_sts_ports">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:au200:part0:1.3</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcu200</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TKEEP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TLAST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF2_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF3_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axi_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.coreclk_freq" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_device_id" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pl_link_cap_max_link_speed" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pl_link_cap_max_link_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_axi_intf_mm" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;sys_clk&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_clk_gt&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;sys_rst_n&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;user_lnk_up&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_txp&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_txn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_rxp&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;pci_exp_rxn&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;axi_aclk&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;axi_aresetn&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;usr_irq_req&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;usr_irq_ack&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;msi_enable&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;msi_vector_widt
+h&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_addr&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;18&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_write&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_write_data&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_byte_enable&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_read&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_read_data&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;cfg_mgmt_read_write_done&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_c2h_tdata_0&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_c2h_tlast_0&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_c2h_tvalid_0&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_c2h_tready_0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;s_axis_c2h_tkeep_0&quot;:{&quot;direction&quot;:&quot;in&quot;,
+&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_h2c_tdata_0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_h2c_tlast_0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_h2c_tvalid_0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_h2c_tready_0&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;m_axis_h2c_tkeep_0&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.SYS_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{
+&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;sys_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.sys_clk_gt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]
+,&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;sys_clk_gt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;CLK.axi_aclk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_
+ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;axi_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;125000000&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;axi_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.axi_aresetn&quot;:{&quot;vlnv&quot;:&quot;xilinx.co
+m:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;axi_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.sys_rst_n&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;SYS_RST_N_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PCIE_PERST&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0
+&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;RST&quot;:{&quot;physical_name&quot;:&quot;sys_rst_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;RST.user_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;S_AXIS_C2H_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;cons
+tant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;defaul
+t&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;s_axis_c2h_tdata_0&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;s_axis_c2h_tkeep_0&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;s_axis_c2h_tlast_0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;s_axis_c2h_tready_0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;s_axis_c2h_tvalid_0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;M_AXIS_H2C_0&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:axis:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:axis_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;TDATA_NUM_BYTES&quot;:[{&quot;value&quot;:&quot;32
+&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TDEST_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;TUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TREADY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TSTRB&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TKEEP&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;HAS_TLAST&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;auto&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;value_sr
+c&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;LAYERED_METADATA&quot;:[{&quot;value&quot;:&quot;undef&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{&quot;TDATA&quot;:{&quot;physical_name&quot;:&quot;m_axis_h2c_tdata_0&quot;,&quot;physical_left&quot;:&quot;255&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;255&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TKEEP&quot;:{&quot;physical_name&quot;:&quot;m_axis_h2c_tkeep_0&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TLAST&quot;:{&quot;physical_name&quot;:&quot;m_axis_h2c_tlast_0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TREADY&quot;:{&quot;physical_name&quot;:&quot;m_axis_h2c_tready_0&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;TVALID&quot;:{&quot;physical_name&quot;:&quot;m_axis_h2c_tvalid_0&quot;,&quot;physical_left&quot;
+:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie_cfg_mgmt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie_cfg_mgmt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie_cfg_mgmt_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_addr&quot;,&quot;physical_left&quot;:&quot;18&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;18&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;BYTE_EN&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_byte_enable&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_DATA&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_read_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_EN&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_read&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;READ_WRITE_DONE&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_read_write_done&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_DATA&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_write_data&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_l
+eft&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WRITE_EN&quot;:{&quot;physical_name&quot;:&quot;cfg_mgmt_write&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}},&quot;pcie_mgt&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:pcie_7x_mgt:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:pcie_7x_mgt_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;PCIE_BOARD_INTERFACE&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}]},&quot;port_maps&quot;:{&quot;rxn&quot;:{&quot;physical_name&quot;:&quot;pci_exp_rxn&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;rxp&quot;:{&quot;physical_name&quot;:&quot;pci_exp_rxp&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;txn&quot;:{&quot;physical_name&quot;:&quot;pci_exp_txn&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;txp&quot;:{&quot;physical_name&quot;:&quot;pci_exp_txp&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xml b/projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xml
new file mode 100644
index 0000000..9131881
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/xdma/xdma.xml
@@ -0,0 +1,60383 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>xdma</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.SYS_CLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.SYS_CLK" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.sys_clk_gt</spirit:name>
+      <spirit:displayName>CLK.sys_clk_gt</spirit:displayName>
+      <spirit:description>sys_clk_gt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_clk_gt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.sys_clk_gt" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.axi_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.ASSOCIATED_BUSIF">M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.ASSOCIATED_RESET">axi_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.FREQ_HZ">125000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.axi_ctl_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>axi_ctl_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.ASSOCIATED_BUSIF">S_AXI_LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.FREQ_HZ">125000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.ASSOCIATED_RESET">axi_ctl_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.axi_ctl_aclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_ACLK_LOOPBACK&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.axi_aresetn</spirit:name>
+      <spirit:displayName>RST.axi_aresetn</spirit:displayName>
+      <spirit:description>axi_aresetn interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.AXI_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.AXI_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.sys_rst_n</spirit:name>
+      <spirit:displayName>RST.sys_rst_n</spirit:displayName>
+      <spirit:description>sys_rst interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.BOARD.ASSOCIATED_PARAM">SYS_RST_N_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.TYPE">PCIE_PERST</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.axi_ctl_aresetn</spirit:name>
+      <spirit:displayName>RST.axi_ctl_aresetn</spirit:displayName>
+      <spirit:description>axi_ctl_aresetn interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>axi_ctl_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.AXI_CTL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.AXI_CTL_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.axi_ctl_aresetn" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out_msi_vec0to31</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out_msi_vec0to31</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out_msi_vec0to31</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC0TO31.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC0TO31.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msi_vec0to31" xilinx:dependency="((spirit:decode((id(&apos;MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH&apos;))>1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out_msi_vec32to63</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out_msi_vec32to63</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out_msi_vec32to63</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC32TO63.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC32TO63.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msi_vec32to63" xilinx:dependency="((spirit:decode((id(&apos;MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH&apos;))>1)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out_msix_0</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out_msix_0</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out_msix_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_0.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_0.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_0" xilinx:dependency="((spirit:decode((id(&apos;MODELPARAM_VALUE.MSIX_RX_DECODE_EN&apos;)) = &quot;TRUE&quot;)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out_msix_1</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out_msix_1</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out_msix_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_1.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_1.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_1" xilinx:dependency="((spirit:decode((id(&apos;MODELPARAM_VALUE.MSIX_RX_DECODE_EN&apos;)) = &quot;TRUE&quot;)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out_msix_2</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out_msix_2</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out_msix_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_2.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_2.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_2" xilinx:dependency="((spirit:decode((id(&apos;MODELPARAM_VALUE.MSIX_RX_DECODE_EN&apos;)) = &quot;TRUE&quot;)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.interrupt_out_msix_3</spirit:name>
+      <spirit:displayName>INTERRUPT.interrupt_out_msix_3</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt_out_msix_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_3.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_3.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_3" xilinx:dependency="((spirit:decode((id(&apos;MODELPARAM_VALUE.MSIX_RX_DECODE_EN&apos;)) = &quot;TRUE&quot;)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.rd_interrupt</spirit:name>
+      <spirit:displayName>INTERRUPT.rd_interrupt</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rd_interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.RD_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.RD_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.rd_interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_DVSEC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.wr_interrupt</spirit:name>
+      <spirit:displayName>INTERRUPT.wr_interrupt</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wr_interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.WR_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.WR_INTERRUPT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.wr_interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_DVSEC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>INTERRUPT.ats_pri_en</spirit:name>
+      <spirit:displayName>INTERRUPT.ats_pri_en</spirit:displayName>
+      <spirit:description>Interrupt interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ats_pri_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.ATS_PRI_EN.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.ATS_PRI_EN.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.ats_pri_en" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_DVSEC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.user_clk</spirit:name>
+      <spirit:displayName>CLK.user_clk</spirit:displayName>
+      <spirit:description>user_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>user_clk_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_BUSIF">m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc:pcie4_cxs_rx:pcie4_cxs_tx</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.FREQ_HZ">250000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_RESET">user_reset_sd</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.user_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.core_clk</spirit:name>
+      <spirit:displayName>CLK.core_clk</spirit:displayName>
+      <spirit:description>core_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>core_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.FREQ_HZ">500000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.core_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot; &amp;&amp; (spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_MORE&apos;)) = &quot;TRUE&quot;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.gt_drp_clk</spirit:name>
+      <spirit:displayName>CLK.gt_drp_clk</spirit:displayName>
+      <spirit:description>gt_drp_clk interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_drp_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.FREQ_HZ">125000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.gt_drp_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot; &amp;&amp; spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_MORE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.user_reset</spirit:name>
+      <spirit:displayName>RST.user_reset</spirit:displayName>
+      <spirit:description>user_reset interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>user_reset_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.USER_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.USER_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST.VALUE_SRC</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST.VALUE_SRC" spirit:choiceRef="choice_list_9e15bd51">CONSTANT</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 1 and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULTQ_EN&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ) and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0 )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_B</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_B"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axib_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_READ_OUTSTANDING">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_WRITE_OUTSTANDING">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.SUPPORTS_NARROW_BURST" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_SUPPORTS_NARROW_BURST&apos;))" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_B" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EN_AXI_SLAVE_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_BYPASS</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_BYPASS"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_READ_OUTSTANDING">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_WRITE_OUTSTANDING">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_READ_THREADS">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_WRITE_THREADS">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_BYPASS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE&apos;)) = &quot;TRUE&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXIST_BYPASS&apos;)) = &quot;TRUE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 1  or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_B</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_B"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axib_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_READ_OUTSTANDING">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_WRITE_OUTSTANDING">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_READ_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_WRITE_THREADS">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_B" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 0) and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_AXI_MASTER_IF&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_LITE</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_LITE"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axil_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_LITE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXILITE_MASTER&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULTQ_EN&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_LITE</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_LITE"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axil_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_LITE" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXILITE_SLAVE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_C2H_0</spirit:name>
+      <spirit:displayName>S_AXIS_C2H_0</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tdata_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tkeep_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tlast_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tready_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tuser_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tvalid_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_WCHNL_0&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_H2C_0</spirit:name>
+      <spirit:displayName>M_AXIS_H2C_0</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tdata_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tkeep_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tlast_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tready_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tuser_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tvalid_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDATA_NUM_BYTES">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_RCHNL_0&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_C2H_1</spirit:name>
+      <spirit:displayName>S_AXIS_C2H_1</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tdata_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tkeep_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tlast_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tready_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tuser_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tvalid_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_WCHNL_1&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_H2C_1</spirit:name>
+      <spirit:displayName>M_AXIS_H2C_1</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tdata_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tkeep_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tlast_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tready_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tuser_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tvalid_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_RCHNL_1&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_C2H_2</spirit:name>
+      <spirit:displayName>S_AXIS_C2H_2</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tdata_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tkeep_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tlast_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tready_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tuser_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tvalid_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_WCHNL_2&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_H2C_2</spirit:name>
+      <spirit:displayName>M_AXIS_H2C_2</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tdata_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tkeep_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tlast_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tready_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tuser_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tvalid_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_RCHNL_2&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_C2H_3</spirit:name>
+      <spirit:displayName>S_AXIS_C2H_3</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tdata_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tkeep_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tlast_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tready_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tuser_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_c2h_tvalid_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_WCHNL_3&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_H2C_3</spirit:name>
+      <spirit:displayName>M_AXIS_H2C_3</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tdata_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tkeep_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tlast_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tready_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tuser_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_h2c_tvalid_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_AXI_INTF_MM&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.EN_RCHNL_3&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SHELL_BRIDGE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axis_cq</spirit:name>
+      <spirit:displayName>m_axis_cq</spirit:displayName>
+      <spirit:description>The Completer Request interface is used to transmit Completion TLP&apos;s to the Client Application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tdata_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tkeep_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tlast_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tready_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tuser_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cq_tvalid_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_cq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_cc</spirit:name>
+      <spirit:displayName>s_axis_cc</spirit:displayName>
+      <spirit:description>The Completer Completion Interface is used to transmit Completion TLP&apos;s</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tdata_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tkeep_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tlast_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tready_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tuser_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cc_tvalid_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axis_cc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axis_rq</spirit:name>
+      <spirit:displayName>s_axis_rq</spirit:displayName>
+      <spirit:description>The Requestor Request interface received requests TLP&apos;s from the Client Application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tdata_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tkeep_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tlast_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tready_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tuser_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rq_tvalid_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axis_rq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axis_rc</spirit:name>
+      <spirit:displayName>m_axis_rc</spirit:displayName>
+      <spirit:description>The Requestor Completer interface transmits completions to the client application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tdata_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tkeep_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tlast_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tready_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tuser_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rc_tvalid_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_rc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_mesg_tx</spirit:name>
+      <spirit:displayName>pcie4_cfg_mesg_tx</spirit:displayName>
+      <spirit:description>Configuration Transmit Message Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_mesg_tx" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_mesg_tx_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_done_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TRANSMIT_TYPE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_transmit_type_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mesg_tx" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_mesg_rcvd</spirit:name>
+      <spirit:displayName>pcie4_cfg_mesg_rcvd</spirit:displayName>
+      <spirit:description>Configuration Received Message Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msg_received" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msg_received_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>recd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_received_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>recd_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_received_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>recd_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_msg_received_type_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mesg_rcvd" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_status</spirit:name>
+      <spirit:displayName>pcie4_cfg_status</spirit:displayName>
+      <spirit:description>Configuration Status Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_status" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_status_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req_count</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req_count_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>current_speed</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_current_speed_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_fatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_fatal_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_nonfatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_nonfatal_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_function_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>local_error_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ltssm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ltssm_state_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_payload</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_payload_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_read_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_read_req_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>negotiated_width</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_negotiated_width_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_down</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_down_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pl_status_change</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pl_status_change_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num0_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num1_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld0_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld1_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tfc_npd_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_tfc_npd_av_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tfc_nph_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_tfc_nph_av_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_status" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_status_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_status</spirit:displayName>
+      <spirit:description>Configuration Status Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_status" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_status_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_np_req_count</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_cq_np_req_count_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>current_speed</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_current_speed_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_fatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_fatal_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_nonfatal_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_nonfatal_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_function_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>local_error_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ltssm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ltssm_state_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_payload</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_payload_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>max_read_req</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_max_read_req_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>negotiated_width</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_negotiated_width_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_down</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_down_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phy_link_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_phy_link_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pl_status_change</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_pl_status_change_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num0_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num1_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld0_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_seq_num_vld1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_rq_seq_num_vld1_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_status_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_transmit_fc_if</spirit:name>
+      <spirit:displayName>pcie4_transmit_fc</spirit:displayName>
+      <spirit:description>Transmit Flow Control Interfce</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>npd_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_tfc_npd_av_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>nph_av</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie_tfc_nph_av_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_transmit_fc_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_rbar</spirit:name>
+      <spirit:displayName>pcie4_rbar</spirit:displayName>
+      <spirit:description>Resizable bar Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_rbar" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_rbar_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bar_size</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_bar_size_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar0_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar1_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar2_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar3_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar4_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_bar5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar5_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_rbar" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RBAR_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_control</spirit:name>
+      <spirit:displayName>pcie4_cfg_control</spirit:displayName>
+      <spirit:description>It allows a broad range of information exchange between user application and the core</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_control" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_control_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_bus_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_bus_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_device_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_device_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_port_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_port_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dsn_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_in_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_uncor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_uncor_in_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_done_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_in_process_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>hot_reset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_hot_reset_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>link_training_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_link_training_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_in_process_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_control" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_control_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_control</spirit:displayName>
+      <spirit:description>It allows a broad range of information exchange between user application and the core</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_control" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_control_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_bus_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_bus_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_device_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_device_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ds_port_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ds_port_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dsn_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_cor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_in_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>err_uncor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_uncor_in_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_done_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_flr_in_process_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>hot_reset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_hot_reset_out_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>link_training_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_link_training_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rbar_function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rbar_size</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_bar_size_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_flr_in_process</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vf_flr_in_process_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar0_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar1_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar2_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar3_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar4_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_enable_rbar5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rbar_write_enable_bar5_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_control_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_fc</spirit:name>
+      <spirit:displayName>pcie_cfg_fc</spirit:displayName>
+      <spirit:description>Configuration Flow Control INTERFACE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>NPH</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_nph_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SEL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_fc_sel_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_fc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msi</spirit:name>
+      <spirit:displayName>pcie4_cfg_msi</spirit:displayName>
+      <spirit:description>PCIE MSI interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msi" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msi_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>attr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask_update</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_mask_update_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_pending_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pending_status_data_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_pending_status_data_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pending_status_function_num</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_pending_status_function_num_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_present</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_tag</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msi" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msix_external</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_external</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_external" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_external_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_external" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_external_msix_with_msi_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix_with_msi</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix_with_msi_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_external_msix</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_external_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_external_msix_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_PCIE_INTERNAL&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msix_internal</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_internal</spirit:displayName>
+      <spirit:description>PCIE MSIx Int Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_internal" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_internal_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>attr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mint_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_present</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_tag</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_internal" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_PCIE_INTERNAL&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_msix_internal_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_internal</spirit:displayName>
+      <spirit:description>PCIE MSIx Int Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>attr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mint_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_present</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_st_tag</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tph_type</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vec_pending_status</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vec_pending_status_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_internal_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_PCIE_INTERNAL&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_external_msix_without_msi_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_external_msix_without_msi</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vf_mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix_without_msi_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSI_ENABLED&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_PCIE_INTERNAL&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cfg_interrupt</spirit:name>
+      <spirit:displayName>pcie4_cfg_interrupt</spirit:displayName>
+      <spirit:description>PCIE Legacy Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTx_VECTOR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_int_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>PENDING</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_pending_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>SENT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_sent_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_cfg_mgmt_sd</spirit:name>
+      <spirit:displayName>pcie4_cfg_mgmt</spirit:displayName>
+      <spirit:description>PCIE Configuration Management Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_mgmt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_mgmt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_addr_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_byte_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEBUG_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_type1_cfg_reg_access_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FUNCTION_NUMBER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_WRITE_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_write_done_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_mgmt_sd" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_MGMT_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;FALSE&quot;) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_cfg_mgmt_if</spirit:name>
+      <spirit:displayName>pcie4_cfg_mgmt</spirit:displayName>
+      <spirit:description>PCIE Configuration Management Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_mgmt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_mgmt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_addr_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_byte_enable_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEBUG_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_type1_cfg_reg_access_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FUNCTION_NUMBER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_function_number_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_WRITE_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_write_done_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_data_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_mgmt_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_MGMT_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.USE_STANDARD_INTERFACES&apos;)) = &quot;TRUE&quot;) )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_cfg_mgmt</spirit:name>
+      <spirit:displayName>pcie_cfg_mgmt</spirit:displayName>
+      <spirit:description>PCIE Configuration Management Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_mgmt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_mgmt_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BYTE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>READ_WRITE_DONE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_read_write_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TYPE1_CFG_REG_ACCESS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_type1_cfg_reg_access</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WRITE_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_mgmt_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_mgmt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_MGMT_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.DMA_EN&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULTQ_EN&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.FUNC_MODE&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_mgt</spirit:name>
+      <spirit:displayName>pcie_7x_mgt</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_7x_mgt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_7x_mgt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_rxn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxp</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_rxp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txn</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_txn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txp</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pci_exp_txp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PCIE_MGT.BOARD.ASSOCIATED_PARAM">PCIE_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_mgt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>drp</spirit:name>
+      <spirit:displayName>drp</spirit:displayName>
+      <spirit:description>DRP interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drp_addr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drp_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DI</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drp_di</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DO</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drp_do</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DRDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drp_rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DWE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drp_we</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.drp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE3_DRP&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_debug_ports</spirit:name>
+      <spirit:displayName>pcie_debug_ports</spirit:displayName>
+      <spirit:description>PCIe Debug Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_debug" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_debug_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_current_speed</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_current_speed_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_err_cor</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_cor_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_err_fatal</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_fatal_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_err_nonfatal</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_err_nonfatal_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_local_error</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_local_error_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_local_error_valid_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_ltssm_state</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ltssm_state_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_negotiated_width</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_negotiated_width_o</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_debug_ports" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id</spirit:name>
+      <spirit:displayName>pcie4_pcie_id</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_vend_id</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_vend_id</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>vend_id</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_vend_id</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf0</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf0</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 0 or  spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf1</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf1</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 1 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf2</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf2</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 2 or spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_pcie_id_pf3</spirit:name>
+      <spirit:displayName>pcie4_pcie_id_pf3</spirit:displayName>
+      <spirit:description>PCIE 4 PCIE ID interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dev_id_pf3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_dev_id_pf3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rev_id_pf3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_rev_id_pf3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>subsys_id_pf3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_subsys_id_pf3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_ID_IF&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.TL_PF_ENABLE_REG&apos;)) = 3)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_7x_transceiver_debug</spirit:name>
+      <spirit:displayName>pcie3_7x_transceiver_debug</spirit:displayName>
+      <spirit:description>Transceiver Debug Interface of pcie3_7x</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_7x_transceiver_debug" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_7x_transceiver_debug_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpll_lock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_cpll_lock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_4</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_5</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_6</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_7</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_8</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>debug_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_debug_9</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorout</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_dmonitorout</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drp_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_drp_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eyescandataerror</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_eyescandataerror</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gt_ch_drp_rdy</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_ch_drp_rdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>loopback</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_loopback</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll_lock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_qpll_lock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qrst_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_qrst_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qrst_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_qrst_idle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rate_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rate_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rate_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rate_idle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rst_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rst_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rst_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rst_idle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufstatus</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxbufstatus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadet</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxcommadet</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdisperr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxdisperr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxdlysresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxnotintable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxnotintable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxphaligndone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxpmaresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbscntreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxprbscntreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbserr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxprbserr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbssel</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxprbssel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxstatus</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxstatus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxsyncdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxsyncdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sync_fsm_rx</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_sync_fsm_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sync_fsm_tx</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_sync_fsm_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txdlysresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txinhibit</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txinhibit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphaligndone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txphaligndone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinitdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txphinitdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbsforceerr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txprbsforceerr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbssel</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txprbssel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_7x_transceiver_debug" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_us_transceiver_debug</spirit:name>
+      <spirit:displayName>pcie3_us_transceiver_debug</spirit:displayName>
+      <spirit:description>Transceiver Debug Interface of pcie3_us</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_us_transceiver_debug" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_us_transceiver_debug_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtdiv</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_bufgtdiv</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpll_lock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_cplllock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonfiforeset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_dmonfiforeset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_dmonitorclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorout</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_dmonitorout</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
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+            <spirit:name>eyescandataerror</spirit:name>
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+            <spirit:name>gt_eyescandataerror</spirit:name>
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+            <spirit:name>gtpowergood</spirit:name>
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+            <spirit:name>gt_gtpowergood</spirit:name>
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+            <spirit:name>gt_loopback</spirit:name>
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+            <spirit:name>pcieuserratedone</spirit:name>
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+            <spirit:name>gt_pcieuserratedone</spirit:name>
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+            <spirit:name>pcieuserratestart</spirit:name>
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+            <spirit:name>gt_pcieuserratestart</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>phystatus</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_phystatus</spirit:name>
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+            <spirit:name>prst_n</spirit:name>
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+            <spirit:name>phy_prst_n</spirit:name>
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+            <spirit:name>qpll_lock</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_qpll1lock</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rate_idle</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_pcierateidle</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rrst_n</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>phy_rrst_n</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rst_fsm</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>phy_rst_fsm</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rst_idle</spirit:name>
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+            <spirit:name>phy_rst_idle</spirit:name>
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+            <spirit:name>rxbufstatus</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxbufstatus</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxcdrlock</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxcdrlock</spirit:name>
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+            <spirit:name>rxcommadet</spirit:name>
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+            <spirit:name>gt_rxcommadet</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxdlysresetdone</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxeq_fsm</spirit:name>
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+            <spirit:name>phy_rxeq_fsm</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxoutclk</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclk</spirit:name>
+          </spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxphaligndone</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone</spirit:name>
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+            <spirit:name>gt_rxpmaresetdone</spirit:name>
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+            <spirit:name>rxprbscntreset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbscntreset</spirit:name>
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+            <spirit:name>rxprbserr</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbserr</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxprbssel</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbssel</spirit:name>
+          </spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>rxrecclkout</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxrecclkout</spirit:name>
+          </spirit:physicalPort>
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+          <spirit:logicalPort>
+            <spirit:name>rxresetdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxresetdone</spirit:name>
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+            <spirit:name>rxstatus</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxstatus</spirit:name>
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+            <spirit:name>rxsyncdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxsyncdone</spirit:name>
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+            <spirit:name>rxvalid</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxvalid</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone</spirit:name>
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+            <spirit:name>gt_txdlysresetdone</spirit:name>
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+            <spirit:name>txelecidle</spirit:name>
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+            <spirit:name>gt_txelecidle</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>txeq_ctrl</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_ctrl</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>txeq_fsm</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_fsm</spirit:name>
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+            <spirit:name>txeq_preset</spirit:name>
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+            <spirit:name>phy_txeq_preset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_txinhibit</spirit:name>
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+            <spirit:name>txphaligndone</spirit:name>
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+            <spirit:name>gt_txphaligndone</spirit:name>
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+            <spirit:name>txphinitdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_txphinitdone</spirit:name>
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+            <spirit:name>txprbsforceerr</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_txprbsforceerr</spirit:name>
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+            <spirit:name>txprbssel</spirit:name>
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+            <spirit:name>gt_txprbssel</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>txresetdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_txresetdone</spirit:name>
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+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_transceiver_debug" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;)">false</xilinx:isEnabled>
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+      <spirit:displayName>pcie4_us_plus_transceiver_debug</spirit:displayName>
+      <spirit:description>Transceiver Debug Interface of pcie4_us_plus</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie4_us_plus_transceiver_debug" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie4_us_plus_transceiver_debug_rtl" spirit:version="1.0"/>
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+            <spirit:name>bufgtdiv</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_bufgtdiv</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>cpll_lock</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_cplllock</spirit:name>
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+            <spirit:name>dmonfiforeset</spirit:name>
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+            <spirit:name>dmonitorclk</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_dmonitorclk</spirit:name>
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+            <spirit:name>dmonitorout</spirit:name>
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+            <spirit:name>gt_dmonitorout</spirit:name>
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+            <spirit:name>eyescandataerror</spirit:name>
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+            <spirit:name>gt_eyescandataerror</spirit:name>
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+            <spirit:name>gt_gen34_eios_det</spirit:name>
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+            <spirit:name>gtpowergood</spirit:name>
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+            <spirit:name>gt_gtpowergood</spirit:name>
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+            <spirit:name>loopback</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_loopback</spirit:name>
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+            <spirit:name>pcieuserratedone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_pcieuserratedone</spirit:name>
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+            <spirit:name>pcieuserratestart</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_pcieuserratestart</spirit:name>
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+            <spirit:name>phystatus</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_phystatus</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>prst_n</spirit:name>
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+            <spirit:name>qpll0_lock</spirit:name>
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+            <spirit:name>gt_qpll0lock</spirit:name>
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+            <spirit:name>qpll1_lock</spirit:name>
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+            <spirit:name>gt_qpll1lock</spirit:name>
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+            <spirit:name>rate_idle</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_pcierateidle</spirit:name>
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+            <spirit:name>rrst_n</spirit:name>
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+            <spirit:name>phy_rrst_n</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rst_fsm</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>phy_rst_fsm</spirit:name>
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+            <spirit:name>rst_idle</spirit:name>
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+            <spirit:name>phy_rst_idle</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxbufreset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxbufreset</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxbufstatus</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxbufstatus</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxcdrlock</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxcdrlock</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrreset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxcdrreset</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxcommadet</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxcommadet</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelpmreset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxdfelpmreset</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxdlysresetdone</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxeq_fsm</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>phy_rxeq_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkfabric</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclkfabric</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxoutclkpcs</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxoutclkpcs</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcsreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxpcsreset</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxphaligndone</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxpmareset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxpmareset</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxpmaresetdone</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxprbscntreset</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbscntreset</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxprbserr</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbserr</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>rxprbslocked</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbslocked</spirit:name>
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+            <spirit:name>rxprbssel</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxprbssel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrecclkout</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxrecclkout</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxstatus</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxstatus</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxsyncdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxsyncdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxvalid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_rxvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txdlysresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txelecidle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txelecidle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txeq_ctrl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_ctrl</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txeq_fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txeq_preset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phy_txeq_preset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txinhibit</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txinhibit</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txoutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkfabric</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txoutclkfabric</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkpcs</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txoutclkpcs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpcsreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txpcsreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphaligndone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txphaligndone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinitdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txphinitdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmareset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txpmareset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmaresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txpmaresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbsforceerr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txprbsforceerr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbssel</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txprbssel</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprogdivresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txprogdivresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txresetdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txresetdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncdone</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gt_txsyncdone</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_us_plus_transceiver_debug" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_us_gt_if</spirit:name>
+      <spirit:displayName>pcie3_us_gt_if</spirit:displayName>
+      <spirit:description>GT Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_ultrascale" spirit:name="pcie3_us_gt_if" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_ultrascale" spirit:name="pcie3_us_gt_if_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtce_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtce_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtcemask_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtcemask_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtdiv_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtdiv_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtreset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtreset_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtrstmask_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtrstmask_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cplllock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cplllock_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllpd_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonfiforeset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonfiforeset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonitorclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonitorout_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpaddr_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpaddr_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpdi_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpdi_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpdo_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpdo_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpen_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drprdy_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drprdy_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpwe_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpwe_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eyescandataerror_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>eyescandataerror_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eyescanreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>eyescanreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gthrxn_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gthrxn_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gthrxp_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gthrxp_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gthtxn_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gthtxn_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gthtxp_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gthtxp_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtpowergood_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtpowergood_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk0_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk01_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk01_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrxreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrxreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gttxreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gttxreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_reset_rx_done_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_reset_rx_done_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_reset_tx_done_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_reset_tx_done_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_rx_active_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_rx_active_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_tx_active_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_tx_active_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_tx_reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_tx_reset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>loopback_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>loopback_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieeqrxeqadaptdone_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieeqrxeqadaptdone_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierategen3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierategen3_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateidle_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateidle_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpllpd_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpllpd_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpllreset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpllreset_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierstidle_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierstidle_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pciersttxsyncstart_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pciersttxsyncstart_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pciesynctxsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pciesynctxsyncdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieusergen3rdy_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieusergen3rdy_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserphystatusrst_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserphystatusrst_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratedone_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserratedone_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratestart_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserratestart_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcsrsvdin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcsrsvdin_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcsrsvdout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcsrsvdout_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phystatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phystatus_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0clk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0clk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0refclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0refclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1clk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1clk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1lock_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1outclk_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1outrefclk_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1pd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1pd_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1refclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1refclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1reset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpllrsvd2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpllrsvd2_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpllrsvd3_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpllrsvd3_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rx8b10ben_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rx8b10ben_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbufreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufstatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbufstatus_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbyteisaligned_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbyteisaligned_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbyterealign_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbyterealign_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrlock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrlock_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxclkcorcnt_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxclkcorcnt_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadet_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcommadet_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadeten_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcommadeten_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl0_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl0_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl1_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl1_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl2_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl2_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl3_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdata_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfeagchold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfeagchold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfecfokhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfecfokhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfekhhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfekhhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfelfhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap2hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap2hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap3hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap3hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap4hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap4hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap5hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap5hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap6hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap6hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap7hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap7hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap8hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap8hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap9hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap9hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap10hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap10hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap11hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap11hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap12hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap12hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap13hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap13hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap14hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap14hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap15hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap15hold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfeuthold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfeuthold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfevphold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfevphold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdlysresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxelecidle_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxelecidle_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmen_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmgchold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmgchold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmhfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmhfhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmlfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmlfhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmoshold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmoshold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxmcommaalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxmcommaalignen_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoshold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoshold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclk_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcommaalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpcommaalignen_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpd_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxphaligndone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpmaresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpolarity_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpolarity_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbscntreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbscntreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbserr_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbserr_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbslocked_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbslocked_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbssel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbssel_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprgdivresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprgdivresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprogdivreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprogdivreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrate_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxrate_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxratedone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxratedone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxratemode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxratemode_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxslide_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxslide_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxstatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxstatus_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxsyncdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxuserrdy_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxuserrdy_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxusrclk2_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxusrclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxvalid_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tx8b10ben_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tx8b10ben_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl0_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl1_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl1_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl2_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdata_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdata_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdeemph_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdeemph_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdetectrx_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdetectrx_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdiffctrl_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdiffctrl_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlybypass_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlybypass_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyen_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyhold_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyovrden_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyovrden_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlysreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlysresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyupdown_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyupdown_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txelecidle_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txelecidle_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txinhibit_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txinhibit_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txmaincursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txmaincursor_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txmargin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txmargin_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclk_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclksel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclksel_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpd_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+          <spirit:logicalPort>
+            <spirit:name>txphalign_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphalign_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphaligndone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphaligndone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphalignen_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlypd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlypd_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlyreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlyreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlytstclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlytstclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinit_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphinit_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinitdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphinitdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphovrden_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphovrden_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmaresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpmaresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpostcursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpostcursor_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbsforceerr_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprbsforceerr_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbssel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprbssel_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprecursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprecursor_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprgdivresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprgdivresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprogdivreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprogdivreset_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txrate_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txrate_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txresetdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txswing_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txswing_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncallin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncallin_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncdone_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncin_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncmode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncmode_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncout_us_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txuserrdy_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txuserrdy_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txusrclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txusrclk2_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txusrclk_us_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_gt_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_gt_if</spirit:name>
+      <spirit:displayName>pcie4_gt_if</spirit:displayName>
+      <spirit:description>GT Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_gt_if" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_gt_if_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtce_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtce_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtcemask_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtcemask_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtdiv_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtdiv_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtreset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtreset_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>bufgtrstmask_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>bufgtrstmask_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllfreqlock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllfreqlock_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cplllock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cplllock_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllpd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cpllreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cpllreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonfiforeset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonfiforeset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonitorclk_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dmonitorout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dmonitorout_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpaddr_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpaddr_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpclk_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpdi_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpdi_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpdo_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpdo_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpen_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drprdy_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drprdy_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drprst_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drprst_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>drpwe_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>drpwe_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_int_clock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_int_clock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_pclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_pclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_phy_userclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_phy_userclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_rst_idle</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_rst_idle</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ext_phy_clk_txoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_phy_clk_txoutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eyescanreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>eyescanreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtpowergood_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtpowergood_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk0_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk00_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk00_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrefclk01_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrefclk01_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtrxreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtrxreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gttxreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gttxreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_reset_rx_done_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_reset_rx_done_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_reset_tx_done_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_reset_tx_done_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_rx_active_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_rx_active_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gtwiz_userclk_tx_active_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>gtwiz_userclk_tx_active_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>loopback_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>loopback_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieeqrxeqadaptdone_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieeqrxeqadaptdone_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierategen3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierategen3_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateidle_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateidle_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpll0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpll0_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpll1_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpll1_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpllpd_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpllpd_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierateqpllreset_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierateqpllreset_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcierstidle_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcierstidle_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pciersttxsyncstart_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pciersttxsyncstart_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pciesynctxsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pciesynctxsyncdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieusergen3rdy_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieusergen3rdy_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserphystatusrst_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserphystatusrst_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratedone_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserratedone_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pcieuserratestart_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcieuserratestart_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>phystatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>phystatus_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0freqlock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0freqlock_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0lock_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0outclk_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0outrefclk_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0pd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0pd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll0reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll0reset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1freqlock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1freqlock_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1lock_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1outclk_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1outrefclk_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1pd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1pd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpll1reset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll1reset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rcalenb_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rcalenb_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>resetovrd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>resetovrd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rx8b10ben_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rx8b10ben_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbufreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbufstatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbufstatus_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbyteisaligned_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbyteisaligned_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxbyterealign_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxbyterealign_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrfreqreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrfreqreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrlock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrlock_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcdrreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcdrreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxclkcorcnt_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxclkcorcnt_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadet_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcommadet_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxcommadeten_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxcommadeten_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl0_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl0_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl1_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl1_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl2_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl2_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxctrl3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxctrl3_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdata_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfeagchold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfeagchold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfecfokhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfecfokhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfekhhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfekhhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfelfhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfelpmreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfelpmreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap2hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap2hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap3hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap3hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap4hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap4hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap5hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap5hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap6hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap6hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap7hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap7hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap8hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap8hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap9hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap9hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap10hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap10hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap11hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap11hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap12hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap12hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap13hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap13hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap14hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap14hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfetap15hold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfetap15hold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfeuthold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfeuthold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdfevphold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdfevphold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxdlysresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxdlysresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxelecidle_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxelecidle_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmen_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmgchold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmgchold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmhfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmhfhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmlfhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmlfhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxlpmoshold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxlpmoshold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxmcommaalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxmcommaalignen_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoshold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoshold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclk_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkfabric_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclkfabric_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclkpcs_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxoutclkpcs_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcommaalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpcommaalignen_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpcsreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpcsreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxphaligndone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxphaligndone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmareset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpmareset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpmaresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpmaresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxpolarity_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxpolarity_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbscntreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbscntreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbserr_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbserr_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbslocked_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbslocked_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprbssel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprbssel_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxprogdivreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxprogdivreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrate_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxrate_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxratedone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxratedone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxratemode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxratemode_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxrecclkout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxrecclkout_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxslide_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxslide_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxstatus_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxstatus_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxsyncdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxtermination_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxtermination_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxuserrdy_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxuserrdy_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxusrclk2_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxusrclk_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rxvalid_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>tx8b10ben_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tx8b10ben_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl0_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl0_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl1_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl1_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txctrl2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txctrl2_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdata_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdata_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdeemph_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdeemph_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdetectrx_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdetectrx_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdiffctrl_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdiffctrl_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlybypass_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlybypass_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyen_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyhold_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyhold_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyovrden_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyovrden_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlysreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlysresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlysresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txdlyupdown_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txdlyupdown_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txelecidle_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txelecidle_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txmaincursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txmaincursor_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txmargin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txmargin_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclk_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkfabric_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclkfabric_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclkpcs_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclkpcs_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclksel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txoutclksel_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpcsreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpcsreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpdelecidlemode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpdelecidlemode_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphalign_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphalign_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphaligndone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphaligndone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphalignen_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphalignen_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlypd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlypd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlyreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlyreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphdlytstclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphdlytstclk_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinit_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphinit_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphinitdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphinitdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txphovrden_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txphovrden_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpisopd_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpisopd_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmareset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpmareset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpmaresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpmaresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txpostcursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txpostcursor_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbsforceerr_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprbsforceerr_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprbssel_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprbssel_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprecursor_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprecursor_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprgdivresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprgdivresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txprogdivreset_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txprogdivreset_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txrate_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txrate_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txresetdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txresetdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txswing_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txswing_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncallin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncallin_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncdone_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncdone_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncin_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncin_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncmode_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncmode_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txsyncout_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txsyncout_usp_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txuserrdy_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txuserrdy_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txusrclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txusrclk2_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>txusrclk_usp_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_gt_if" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_ext_ch_gt</spirit:name>
+      <spirit:displayName>pcie_ext_ch_gt</spirit:displayName>
+      <spirit:description>GT DRP interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DI</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpdi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DO</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpdo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DRDY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drprdy</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DWE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpwe</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_ch_gt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EXT_CH_GT_DRP&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_cfg_ext</spirit:name>
+      <spirit:displayName>pcie4_cfg_ext</spirit:displayName>
+      <spirit:description>Configuration Extend Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_ext" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_ext_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>function_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_function_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read_data_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_read_data_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read_received</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_read_received</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>register_number</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_register_number</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_byte_enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_write_byte_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_write_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write_received</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_ext_write_received</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_ext" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CFG_EXT_IF&apos;)) = &quot;TRUE&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.LEGACY_CFG_EXT_IF&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.ext_ch_gt_drpclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_ch_gt_drpclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.ASSOCIATED_BUSIF">pcie_ext_ch_gt</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.FREQ_HZ">100000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.ext_ch_gt_drpclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;)) = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.EXT_CH_GT_DRP&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_ext_pipe_rp_usp</spirit:name>
+      <spirit:displayName>pcie3_ext_pipe_rp_usp</spirit:displayName>
+      <spirit:description>PCIE3 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_pipe_rp_usp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 2)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_ext_pipe_ep_usp</spirit:name>
+      <spirit:displayName>pcie3_ext_pipe_ep_usp</spirit:displayName>
+      <spirit:description>PCIE3 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_pipe_ep_usp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_ext_pipe_ep_legacy_usp</spirit:name>
+      <spirit:displayName>pcie3_ext_pipe_ep_legacy_usp</spirit:displayName>
+      <spirit:description>PCIE3 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_8</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_8_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_9</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_9_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_10</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_10_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_11</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_11_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_12</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_12_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_13</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_13_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_14</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_14_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_15</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_15_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_pipe_ep_legacy_usp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_ext_pipe_rp</spirit:name>
+      <spirit:displayName>pcie3_ext_pipe_rp</spirit:displayName>
+      <spirit:description>PCIE3 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_ext_pipe_rp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 2)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_ext_pipe_ep</spirit:name>
+      <spirit:displayName>pcie3_ext_pipe_ep</spirit:displayName>
+      <spirit:description>PCIE3 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_ext_pipe_ep" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_ext_pipe_ep_legacy</spirit:name>
+      <spirit:displayName>pcie3_ext_pipe_ep_legacy</spirit:displayName>
+      <spirit:description>PCIE3 External PIPE Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_IN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>COMMANDS_OUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>common_commands_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_tx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_0</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_0_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_1_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_2_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_3_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_4</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_4_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_5</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_5_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_6</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_6_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TX_7</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rx_7_sigs</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_ext_pipe_ep_legacy" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PIPE_SIM&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.DEV_PORT_TYPE&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_c2h_0</spirit:name>
+      <spirit:displayName>dsc_bypass_c2h_0</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ctl_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_dst_addr_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_len_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_load_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ready_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_src_addr_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.WR_CH0_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_c2h_1</spirit:name>
+      <spirit:displayName>dsc_bypass_c2h_1</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ctl_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_dst_addr_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_len_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_load_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ready_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_src_addr_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.WR_CH1_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_c2h_2</spirit:name>
+      <spirit:displayName>dsc_bypass_c2h_2</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ctl_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_dst_addr_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_len_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_load_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ready_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_src_addr_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.WR_CH2_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_c2h_3</spirit:name>
+      <spirit:displayName>dsc_bypass_c2h_3</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ctl_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_dst_addr_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_len_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_load_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_ready_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_dsc_byp_src_addr_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.WR_CH3_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_h2c_0</spirit:name>
+      <spirit:displayName>dsc_bypass_h2c_0</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ctl_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_dst_addr_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_len_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_load_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ready_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_src_addr_0</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RD_CH0_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_h2c_1</spirit:name>
+      <spirit:displayName>dsc_bypass_h2c_1</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ctl_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_dst_addr_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_len_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_load_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ready_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_src_addr_1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RD_CH1_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_h2c_2</spirit:name>
+      <spirit:displayName>dsc_bypass_h2c_2</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ctl_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_dst_addr_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_len_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_load</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_load_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ready_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_src_addr_2</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RD_CH2_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
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+    <spirit:busInterface>
+      <spirit:name>dsc_bypass_h2c_3</spirit:name>
+      <spirit:displayName>dsc_bypass_h2c_3</spirit:displayName>
+      <spirit:description>Descriptor Bypass Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ctl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ctl_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_dst_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_dst_addr_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_len</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_len_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
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+            <spirit:name>dsc_byp_load</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_ready_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dsc_byp_src_addr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>h2c_dsc_byp_src_addr_3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RD_CH3_ENABLED&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
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+      <spirit:name>dma_status_ports</spirit:name>
+      <spirit:displayName>dma_status_ports</spirit:displayName>
+      <spirit:description>XDMA Status Ports Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_status_ports" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_status_ports_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>c2h_sts0</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>c2h_sts_0</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>c2h_sts1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_sts_1</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>c2h_sts2</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>c2h_sts_2</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>c2h_sts3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>c2h_sts_3</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>h2c_sts0</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>h2c_sts_0</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>h2c_sts1</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>h2c_sts_1</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>h2c_sts2</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>h2c_sts_2</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>h2c_sts3</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>h2c_sts_3</spirit:name>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dma_status_ports" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.XDMA_STS_PORTS&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
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+      <spirit:displayName>cap</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cap" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cap_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
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+          <spirit:logicalPort>
+            <spirit:name>GNT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cap_gnt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cap_rel</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cap_req</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cap" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
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+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>startup</spirit:name>
+      <spirit:displayName>startup</spirit:displayName>
+      <spirit:description>STARTUP Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="startup" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="startup_rtl" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>cfgclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_cfgclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfgmclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_cfgmclk</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>di</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_di</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>do</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_do</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dts</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>startup_dts</spirit:name>
+          </spirit:physicalPort>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>eos</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_eos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fcsbo</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_fcsbo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fcsbts</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_fcsbts</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gsr</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_gsr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gts</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_gts</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>keyclearb</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_keyclearb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pack</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_pack</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>preq</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_preq</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>userdoneo</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_usrdoneo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>usrcclko</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_usrcclko</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>usrclkts</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_usrcclkts</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>usrdonets</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>startup_usrdonets</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
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+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.startup" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE&apos;)) = &quot;FALSE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;NONE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.MCAP_ENABLEMENT&apos;)) != &quot;PR&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>atspri_s_axis_rq</spirit:name>
+      <spirit:displayName>atspri_s_axis_rq</spirit:displayName>
+      <spirit:description>The Requestor Request interface received requests TLP&apos;s from the Client Application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_s_axis_rq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_s_axis_rq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_s_axis_rq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_s_axis_rq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_s_axis_rq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_s_axis_rq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.atspri_s_axis_rq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ATS_ENABLE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>atspri_m_axis_cq</spirit:name>
+      <spirit:displayName>atspri_m_axis_cq</spirit:displayName>
+      <spirit:description>The Completer Request interface is used to transmit Completion TLP&apos;s to the Client Application</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_m_axis_cq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_m_axis_cq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_m_axis_cq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_m_axis_cq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_m_axis_cq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>atspri_m_axis_cq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.atspri_m_axis_cq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ATS_ENABLE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cfg_status_ats</spirit:name>
+      <spirit:displayName>cfg_status_ats</spirit:displayName>
+      <spirit:description>Configuration Status Interface For ATS</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_ats" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_ats_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_ats_en</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_ats_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_ats_stu</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_ats_stu</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cfg_status_ats" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ATS_ENABLE&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cfg_status_pri</spirit:name>
+      <spirit:displayName>cfg_status_pri</spirit:displayName>
+      <spirit:description>Configuration Status Interface For PRI</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_pri" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_pri_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_clr_s</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_clr_s</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_ost_pr_alloc</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_ost_pr_alloc</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_pr_en</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_pr_en</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_pr_rf</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_pr_rf</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_pr_rst</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_pr_rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_pr_uprgi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_pr_uprgi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_set_rf</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_set_rf</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_set_s</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_set_s</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cfg_status_set_uprgi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_status_set_uprgi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cfg_status_pri" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_ATS_ENABLE&apos;)) = &quot;TRUE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRI_ENABLE&apos;)) = &quot;TRUE&quot;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dma_debug_ports</spirit:name>
+      <spirit:displayName>XDMA Debug Ports</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_debug_ports" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_debug_ports_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cc_tdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cc_tdata_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cc_tkeep_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cc_tkeep_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cc_tlast_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cc_tlast_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cc_tready_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cc_tready_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cc_tuser_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cc_tuser_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cc_tvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_cc_tvalid_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_tdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cq_tdata_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_tkeep_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cq_tkeep_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_tlast_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cq_tlast_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_tready_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cq_tready_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_tuser_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cq_tuser_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cq_tvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_cq_tvalid_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rc_tdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rc_tdata_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rc_tkeep_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rc_tkeep_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rc_tlast_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rc_tlast_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rc_tready_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rc_tready_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rc_tuser_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rc_tuser_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rc_tvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_rc_tvalid_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tdata_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rq_tdata_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tkeep_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rq_tkeep_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tlast_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rq_tlast_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tready_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rq_tready_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tuser_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rq_tuser_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rq_tvalid_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_rq_tvalid_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dma_debug_ports" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.EN_DEBUG_PORTS&apos;)) = &quot;TRUE&quot; or spirit:decode(id(&apos;MODELPARAM_VALUE.MULT_PF_DES&apos;)) = &quot;TRUE&quot; ) and (spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_us_ext_shared_logic</spirit:name>
+      <spirit:displayName>pcie3_us_ext_shared_logic</spirit:displayName>
+      <spirit:description>PCIE3 Ultrascale External Shared Logic Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="ext_shared_logic" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="ext_shared_logic_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1pd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1pd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1rate</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1rate</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1refclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1refclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_qpll1reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_ext_shared_logic" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) = 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_us_int_shared_logic</spirit:name>
+      <spirit:displayName>pcie3_us_int_shared_logic</spirit:displayName>
+      <spirit:description>PCIE3 Ultrascale Internal Shared Logic Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="int_shared_logic" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="int_shared_logic_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_int_shared_logic" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) = 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_usp_ext_gtcom</spirit:name>
+      <spirit:displayName>pcie4_usp_ext_gtcommon</spirit:displayName>
+      <spirit:description>PCIE4 Ultrascale+ External GT COMMON Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="ext_gtcom" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="ext_gtcom_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll0lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll0outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll0outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0pd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll0pd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll0reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll0reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1pd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll1pd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpll1reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpll1reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpllxrate</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpllxrate</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpllxrcalenb</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpllxrcalenb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>exts_qpllxrefclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_usp_qpllxrefclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_usp_ext_gtcom" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.GTCOM_IN_CORE&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) != 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_usp_int_gtcom</spirit:name>
+      <spirit:displayName>pcie4_usp_int_gtcommon</spirit:displayName>
+      <spirit:description>PCIE4 Ultrascale+ Internal GT COMMON Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="int_gtcom" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="int_gtcom_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll0lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_usp_qpll0lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll0outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_usp_qpll0outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll0outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_usp_qpll0outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1lock_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_usp_qpll1lock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1outclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_usp_qpll1outclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ints_qpll1outrefclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_usp_qpll1outrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_usp_int_gtcom" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.GTCOM_IN_CORE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.GTWIZ_IN_CORE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) != 0)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pipe_clock</spirit:name>
+      <spirit:displayName>pipe_clock</spirit:displayName>
+      <spirit:description>PCIExpress Enternal PIPE Clock interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pipe_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pipe_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_dclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gen3_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_gen3_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mmcm_lock_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_mmcm_lock_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mmcm_rst_n</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_mmcm_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>oobclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_oobclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_pclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pclk_sel_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_pclk_sel_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxoutclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxoutclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxusrclk_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_rxusrclk_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>txoutclk_out</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_txoutclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>userclk1_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_userclk1_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>userclk2_in</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pipe_userclk2_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pipe_clock" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC_CLK&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_sharedlogic_int_clk</spirit:name>
+      <spirit:displayName>pcie3_sharedlogic_int_clk</spirit:displayName>
+      <spirit:description>PCIe3 Shared logic interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_sharedlogic_int_clk" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_sharedlogic_int_clk_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>dclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_dclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>oobclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_oobclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pclk_sel_slave</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_pclk_sel_slave</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pclk_slave</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_pclk_out_slave</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>pipe_rxusrclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_pipe_rxusrclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplllock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qplllock_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplloutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qplloutclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplloutrefclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_qplloutrefclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rxoutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_rxoutclk_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>usrclk1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_userclk1_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>usrclk2</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>int_userclk2_out</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_sharedlogic_int_clk" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC_BOTH&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2&apos;)) = &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie3_qpll_drp</spirit:name>
+      <spirit:displayName>pcie3_qpll_drp</spirit:displayName>
+      <spirit:description>PCIe Gen3 external gt_common Interface</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_qpll_drp" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_qpll_drp_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>crscode</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_crscode</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>done</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_done</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fsm</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_fsm</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>gen3</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_gen3</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ovrd</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_ovrd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplld</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_qplld</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplllock</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_qplllock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplloutclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_qplloutclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qplloutrefclk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_qplloutrefclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>qpllreset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_qpllreset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>rst_n</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>start</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>qpll_drp_start</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_qpll_drp" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC_GTC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;FALSE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_cfg_msix_ext_usp</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_ext_usp</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msi_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_msix_ext_usp" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_IMPL_EXT&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;TRUE&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot; ))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie_cfg_msix_ext_us</spirit:name>
+      <spirit:displayName>pcie4_cfg_msix_ext_us</spirit:displayName>
+      <spirit:description>PCIE MSI-X Interrupt</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>data</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>enable</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>fail</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_fail</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>int_vector</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_int</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>mask</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_mask</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sent</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cfg_interrupt_msix_sent</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_msix_ext_us" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_ENABLED&apos;)) = &quot;TRUE&quot; and (spirit:decode(id(&apos;MODELPARAM_VALUE.MSIX_IMPL_EXT&apos;)) = &quot;TRUE&quot;) and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK.s_aclk</spirit:name>
+      <spirit:displayName>CLK.s_aclk</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.FREQ_HZ">250000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.s_aclk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_DVSEC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.s_aresetn</spirit:name>
+      <spirit:displayName>RST.s_aresetn</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.s_aresetn" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_DVSEC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_DVSEC&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) != &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cxs_tx</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_active_ack_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_active_req_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_cntl_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_cntl_chk_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdgnt_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdgnt_chk_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdrtn_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdrtn_chk_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_data_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_data_chk_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEACT_HINT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_deact_hint_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_valid_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_valid_chk_tx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_FLIT_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_TX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;))">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_PKT_PER_FLIT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_TX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;)) = 512 ) ? 4 : 2)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATACHECK</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.DATACHECK">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cxs_tx" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cxs_rx</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_active_ack_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_active_req_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_cntl_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_cntl_chk_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdgnt_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdgnt_chk_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdrtn_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_crdrtn_chk_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_data_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_data_chk_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEACT_HINT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_deact_hint_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_valid_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cxs0_valid_chk_rx</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_FLIT_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_RX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;))">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_PKT_PER_FLIT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_RX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;)) = 512 ) ? 4 : 2)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATACHECK</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.DATACHECK">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cxs_rx" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cxs_tx</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_active_ack_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_active_req_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_cntl_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_cntl_chk_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdgnt_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdgnt_chk_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdrtn_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdrtn_chk_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_data_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_data_chk_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEACT_HINT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_deact_hint_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_valid_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_valid_chk_tx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_FLIT_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;))">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_PKT_PER_FLIT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;)) = 512 ) ? 4 : 2)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATACHECK</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.DATACHECK">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cxs_tx" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>pcie4_cxs_rx</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_ACK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_active_ack_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ACTIVE_REQ</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_active_req_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_cntl_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CNTL_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_cntl_chk_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdgnt_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDGNT_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdgnt_chk_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdrtn_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CRDRTN_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_crdrtn_chk_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_data_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_data_chk_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DEACT_HINT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_deact_hint_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_valid_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>VALID_CHK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>pcie4_cxs0_valid_chk_rx_sd</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_FLIT_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;))">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_PKT_PER_FLIT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.AXI_DATA_WIDTH&apos;)) = 512 ) ? 4 : 2)">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATACHECK</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.DATACHECK">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cxs_rx" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit::decode(id(&apos;MODELPARAM_VALUE.SPLIT_DMA&apos;)) = &quot;TRUE&quot;)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc0_ats_m_axis_cq</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_cq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_cq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_cq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_cq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_cq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_cq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_m_axis_cq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc0_ats_m_axis_rc</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_rc_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_rc_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_rc_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_rc_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_rc_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_m_axis_rc_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_m_axis_rc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc0_ats_s_axis_cc</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_cc_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_cc_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_cc_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_cc_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_cc_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_cc_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_s_axis_cc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc0_ats_s_axis_rq</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_rq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_rq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_rq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_rq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_rq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc0_ats_s_axis_rq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_s_axis_rq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc1_ats_m_axis_cq</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_cq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_cq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_cq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_cq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_cq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_cq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_m_axis_cq" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_OF_SC&apos;)) = 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc1_ats_m_axis_rc</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_rc_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_rc_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_rc_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_rc_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_rc_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_m_axis_rc_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_m_axis_rc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_OF_SC&apos;)) = 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc1_ats_s_axis_cc</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_cc_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_cc_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_cc_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_cc_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_cc_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_cc_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_s_axis_cc" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CCIX_ENABLE&apos;)) = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.PCIE_BLK_TYPE&apos;)) = 1 and spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_OF_SC&apos;)) = 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.ENABLE_ATS_SWITCH&apos;)) = &quot;TRUE&quot; )">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sc1_ats_s_axis_rq</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_rq_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_rq_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_rq_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_rq_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_rq_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sc1_ats_s_axis_rq_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TREADY">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TLAST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+        <spirit:name>m_axib_ruser</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+            <xilinx:enablement>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
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+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1lock_out" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.SHARED_LOGIC&apos;)) = 0 and spirit:decode(id(&apos;MODELPARAM_VALUE.PLL_TYPE&apos;)) = 2 and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE&apos;))  = &quot;TRUE&quot; and spirit:decode(id(&apos;MODELPARAM_VALUE.ULTRASCALE_PLUS&apos;))  = &quot;FALSE&quot;)">false</xilinx:isEnabled>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_elaboratesubcores</spirit:viewNameRef>
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+        <spirit:name>gt_qpll0lock</spirit:name>
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+        <spirit:name>COMPONENT_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COMPONENT_NAME">xdma_0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PL_UPSTREAM_FACING</spirit:name>
+        <spirit:displayName>Pl Upstream Facing</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_UPSTREAM_FACING">true</spirit:value>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>TL_LEGACY_MODE_ENABLE</spirit:name>
+        <spirit:displayName>Tl Legacy Mode Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">false</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PL_LINK_CAP_MAX_LINK_WIDTH</spirit:name>
+        <spirit:displayName>Pl Link Cap Max Link Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PL_LINK_CAP_MAX_LINK_SPEED</spirit:name>
+        <spirit:displayName>Pl Link Cap Max Link Speed</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">4</spirit:value>
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+        <spirit:name>REF_CLK_FREQ</spirit:name>
+        <spirit:displayName>Ref Clk Freq</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DRP_CLK_SEL</spirit:name>
+        <spirit:displayName>DRP CLK SEL</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DRP_CLK_SEL">0</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FREE_RUN_FREQ</spirit:name>
+        <spirit:displayName>Ref Clk Freq</spirit:displayName>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ADDR_WIDTH">64</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>AXI data width</spirit:displayName>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>CORE_CLK_FREQ</spirit:name>
+        <spirit:displayName>Core Clk Freq</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CORE_CLK_FREQ">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PLL_TYPE</spirit:name>
+        <spirit:displayName>PLL Type</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PLL_TYPE">2</spirit:value>
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+        <spirit:name>USER_CLK_FREQ</spirit:name>
+        <spirit:displayName>User Clk Freq</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USER_CLK_FREQ">2</spirit:value>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SILICON_REV</spirit:name>
+        <spirit:displayName>Silicon Revision</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SILICON_REV">Pre-Production</spirit:value>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PIPE_SIM</spirit:name>
+        <spirit:displayName>Enable External PIPE Interface</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_SIM">false</spirit:value>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_CH_GT_DRP</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_CH_GT_DRP">false</spirit:value>
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+        <spirit:name>PCIE3_DRP</spirit:name>
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+        <spirit:name>DEDICATE_PERST</spirit:name>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MCAP_ENABLEMENT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MCAP_ENABLEMENT">NONE</spirit:value>
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+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_STARTUP_PRIMITIVE</spirit:name>
+        <spirit:displayName>EXT STARTUP PRIMITIVE</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">false</spirit:value>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_VENDOR_ID</spirit:name>
+        <spirit:displayName>pf0 Vendor Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf0 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEVICE_ID" spirit:bitStringLength="16">0x9038</spirit:value>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf0 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
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+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SUBSYSTEM_VENDOR_ID</spirit:name>
+        <spirit:displayName>Pf0 Subsystem Vendor Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf0 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_CLASS_CODE</spirit:name>
+        <spirit:displayName>Pf0 Class Code</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_CLASS_CODE" spirit:bitStringLength="24">0x070001</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_VENDOR_ID</spirit:name>
+        <spirit:displayName>pf1 Vendor Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf1 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_DEVICE_ID" spirit:bitStringLength="16">0x9111</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf1 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SUBSYSTEM_VENDOR_ID</spirit:name>
+        <spirit:displayName>Pf1 Subsystem Vendor Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf1 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_CLASS_CODE</spirit:name>
+        <spirit:displayName>Pf1 Class Code</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_CLASS_CODE" spirit:bitStringLength="24">0x070001</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf2 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_DEVICE_ID" spirit:bitStringLength="16">0x9211</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf2 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF2_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_DEVICE_ID</spirit:name>
+        <spirit:displayName>Pf3 Device Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_DEVICE_ID" spirit:bitStringLength="16">0x9311</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_REVISION_ID</spirit:name>
+        <spirit:displayName>Pf3 Revision Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF3_SUBSYSTEM_ID</spirit:name>
+        <spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXILITE_MASTER_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_MASTER_APERTURE_SIZE" spirit:bitStringLength="8">0x0D</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXILITE_MASTER_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_MASTER_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>XDMA_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_APERTURE_SIZE" spirit:bitStringLength="8">0x09</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>XDMA_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXIST_BYPASS_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXIST_BYPASS_APERTURE_SIZE" spirit:bitStringLength="8">0x0D</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXIST_BYPASS_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXIST_BYPASS_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_INTERRUPT_PIN</spirit:name>
+        <spirit:displayName>pf1 Interrupt Pin</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_INTERRUPT_PIN" spirit:bitStringLength="3">0x1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF0_MSI_CAP_MULTIMSGCAP</spirit:name>
+        <spirit:displayName>pf0 Msi Cap Multimsgcap</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_COMP_TIMEOUT</spirit:name>
+        <spirit:displayName>c_comp_timeout</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMP_TIMEOUT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_TIMEOUT0_SEL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TIMEOUT0_SEL" spirit:bitStringLength="4">0xE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_TIMEOUT1_SEL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TIMEOUT1_SEL" spirit:bitStringLength="4">0xF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_TIMEOUT_MULT</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TIMEOUT_MULT" spirit:bitStringLength="3">0x3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_OLD_BRIDGE_TIMEOUT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OLD_BRIDGE_TIMEOUT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SHARED_LOGIC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SHARED_LOGIC_CLK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_CLK">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SHARED_LOGIC_BOTH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_BOTH">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SHARED_LOGIC_GTC</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_GTC">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SHARED_LOGIC_GTC_7XG2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SHARED_LOGIC_CLK_7XG2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SHARED_LOGIC_BOTH_7XG2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_TRANSCEIVER_STATUS_PORTS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>IS_BOARD_PROJECT</spirit:name>
+        <spirit:displayName>Is Board Flow Enabled</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_BOARD_PROJECT">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_GT_SELECTION</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_GT_SELECTION">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SELECT_QUAD</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELECT_QUAD">GTY_Quad_227</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ULTRASCALE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ULTRASCALE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ULTRASCALE_PLUS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ULTRASCALE_PLUS">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>V7_GEN3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.V7_GEN3">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSI_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSI_ENABLED">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DEV_PORT_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEV_PORT_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_AXI_INTF_MM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXI_INTF_MM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_PCIE_64BIT_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_PCIE_64BIT_EN">xdma_pcie_64bit_en</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_AXILITE_MASTER</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXILITE_MASTER">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_AXIST_BYPASS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXIST_BYPASS">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_RNUM_CHNL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_RNUM_CHNL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_WNUM_CHNL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_WNUM_CHNL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_AXILITE_SLAVE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXILITE_SLAVE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_NUM_USR_IRQ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_NUM_USR_IRQ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_RNUM_RIDS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_RNUM_RIDS">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_WNUM_RIDS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_WNUM_RIDS">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ID_WIDTH">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXIBAR_NUM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_NUM" spirit:minimum="0" spirit:maximum="6" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>XDMA_NUM_PCIE_TAG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_NUM_PCIE_TAG">256</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_AXI_MASTER_IF</spirit:name>
+        <spirit:displayName>Enable AXI Master IF</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_AXI_MASTER_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_0</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_0">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_1">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_2">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_3">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_4</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_4">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_5</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_5">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_6</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_6">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_WCHNL_7</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_7">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_0</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_0">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_1">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_2">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_3">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_4</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_4">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_5</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_5">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_6</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_6">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_RCHNL_7</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_7">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_DSC_BYPASS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_DSC_BYPASS">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_METERING_ON</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_METERING_ON">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>RX_DETECT</spirit:name>
+        <spirit:displayName>Receiver Detect</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_DETECT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_ATS_ENABLE</spirit:name>
+        <spirit:displayName>ATS Extended Capability Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ATS_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_ATS_CAP_NEXTPTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ATS_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PR_CAP_NEXTPTR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_PRI_ENABLE</spirit:name>
+        <spirit:displayName>Page Request Extended Capability Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRI_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DSC_BYPASS_RD</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DSC_BYPASS_RD">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DSC_BYPASS_WR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DSC_BYPASS_WR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_STS_PORTS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_STS_PORTS">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSIX_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>WR_CH0_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH0_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>WR_CH1_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH1_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>WR_CH2_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH2_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>WR_CH3_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH3_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RD_CH0_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH0_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RD_CH1_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH1_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RD_CH2_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH2_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RD_CH3_ENABLED</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH3_ENABLED">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_MGMT_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_MGMT_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>RQ_SEQ_NUM_IGNORE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RQ_SEQ_NUM_IGNORE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CFG_EXT_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_EXT_IF">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>LEGACY_CFG_EXT_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LEGACY_CFG_EXT_IF">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PARITY_CHECK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PARITY_CHECK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PARITY_GEN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PARITY_GEN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PARITY_PROP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PARITY_PROP">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ECC_ENABLE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ENABLE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_DEBUG_PORTS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_DEBUG_PORTS">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>VU9P_BOARD</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VU9P_BOARD">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_JTAG_DBG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_JTAG_DBG">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_LTSSM_DBG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_LTSSM_DBG">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_IBERT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_IBERT">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>MM_SLAVE_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MM_SLAVE_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DMA_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_EN">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_HIGHADDR_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_HIGHADDR_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_HIGHADDR_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_HIGHADDR_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_HIGHADDR_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR_HIGHADDR_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR2PCIEBAR_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR2PCIEBAR_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR2PCIEBAR_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR2PCIEBAR_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR2PCIEBAR_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_AXIBAR2PCIEBAR_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_AXI_SLAVE_IF</spirit:name>
+        <spirit:displayName>Enable AXI Slave IF</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_AXI_SLAVE_IF">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INCLUDE_BAROFFSET_REG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLUDE_BAROFFSET_REG">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_BASEADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="32">0x00001000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_HIGHADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="32">0x00001FFF</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_ID_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_NUM_READ</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_NUM_READ">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_NUM_READ</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_READ">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_NUM_READQ</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_READQ">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_NUM_WRITE</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_NUM_WRITE">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_NUM_WRITE</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_WRITE">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_NUM_WRITE_SCALE</spirit:name>
+        <spirit:displayName>AXI Address width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_WRITE_SCALE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSIX_IMPL_EXT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_IMPL_EXT">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXI_ACLK_LOOPBACK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ACLK_LOOPBACK">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Expansion Rom Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF0_EXPANSION_ROM_ENABLE</spirit:name>
+        <spirit:displayName>Pf0 Expansion Rom Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PCIEBAR_NUM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIEBAR_NUM" spirit:minimum="0" spirit:maximum="6" spirit:rangeType="long">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_PCIEBAR2AXIBAR_6</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_6" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>BARLITE1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>BARLITE2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE2">7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>VCU118_BOARD</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VCU118_BOARD">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SPLIT_DMA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SPLIT_DMA">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>USE_STANDARD_INTERFACES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_STANDARD_INTERFACES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DMA_2RP</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_2RP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SRIOV_ACTIVE_VFS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SRIOV_ACTIVE_VFS">252</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PIPE_LINE_STAGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_LINE_STAGE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXIS_PIPE_LINE_STAGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXIS_PIPE_LINE_STAGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MULT_PF_DES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MULT_PF_DES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF_SWAP</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF_SWAP">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF0_MSIX_TAR_ID</spirit:name>
+        <spirit:displayName>PF0 MSIX target ID</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_TAR_ID" spirit:bitStringLength="6">0x08</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_MSIX_TAR_ID</spirit:name>
+        <spirit:displayName>PF1 MSIX target ID</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_TAR_ID" spirit:bitStringLength="6">0x09</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RUNBIT_FIX</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RUNBIT_FIX">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>USRINT_EXPN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USRINT_EXPN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>xlnx_ref_board</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.xlnx_ref_board">AU200</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>GTWIZ_IN_CORE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GTWIZ_IN_CORE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>GTCOM_IN_CORE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GTCOM_IN_CORE">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>INS_LOSS_PROFILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INS_LOSS_PROFILE">Add-in_Card</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FUNC_MODE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FUNC_MODE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PF1_ENABLED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_ENABLED">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DMA_RESET_SOURCE_SEL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_RESET_SOURCE_SEL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR0_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x12</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR0_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR1_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR1_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR2_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR2_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR2_CONTROL" spirit:bitStringLength="3">0x6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR3_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar3 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR3_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar3 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR4_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar4 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR4_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar4 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR4_CONTROL" spirit:bitStringLength="3">0x6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR5_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf0 Bar5 Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_BAR5_CONTROL</spirit:name>
+        <spirit:displayName>Pf0 Bar5 Control</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
+        <spirit:displayName>Pf1 Expansion Rom Aperture Size</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PF1_EXPANSION_ROM_ENABLE</spirit:name>
+        <spirit:displayName>Pf1 Expansion Rom Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_4</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_5</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>PF1_PCIEBAR2AXIBAR_6</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_6" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MSIX_INT_TABLE_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSIX_INT_TABLE_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>VU9P_TUL_EX</spirit:name>
+        <spirit:displayName>VU9P TUL board</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VU9P_TUL_EX">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>PCIE_BLK_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_BLK_TYPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CCIX_ENABLE</spirit:name>
+        <spirit:displayName>Ccix Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CCIX_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>CCIX_DVSEC</spirit:name>
+        <spirit:displayName>Ccix Dvsec Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CCIX_DVSEC">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_SYS_CLK_BUFG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_SYS_CLK_BUFG">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_OF_SC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OF_SC">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>USR_IRQ_EXDES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USR_IRQ_EXDES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXI_VIP_IN_EXDES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_VIP_IN_EXDES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PIPE_DEBUG_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_DEBUG_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_NON_INCREMENTAL_EXDES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_NON_INCREMENTAL_EXDES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>XDMA_ST_INFINITE_DESC_EXDES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_ST_INFINITE_DESC_EXDES">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EXT_XVC_VSEC_ENABLE</spirit:name>
+        <spirit:displayName>Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ACS_EXT_CAP_ENABLE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ACS_EXT_CAP_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>EN_PCIE_DEBUG_PORTS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>MULTQ_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MULTQ_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DMA_MM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_MM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>DMA_ST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_ST">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_PCIE_PFS_SUPPORTED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIE_PFS_SUPPORTED">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SRIOV_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SRIOV_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_EXT_PF0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF0" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_EXT_PF1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF1" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_EXT_PF2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF2" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_EXT_PF3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF3" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_INT_PF0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF0" spirit:bitStringLength="6">0x01</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_INT_PF1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF1" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_INT_PF2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF2" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>BARLITE_INT_PF3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF3" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>NUM_VFS_PF0</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF0">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>NUM_VFS_PF1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>NUM_VFS_PF2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>NUM_VFS_PF3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FIRSTVF_OFFSET_PF0</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF0">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FIRSTVF_OFFSET_PF1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF1">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FIRSTVF_OFFSET_PF2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF2">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FIRSTVF_OFFSET_PF3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF3">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_EXT_PF0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF0" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_EXT_PF1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF1" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_EXT_PF2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF2" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_EXT_PF3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF3" spirit:bitStringLength="6">0x00</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_INT_PF0</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF0" spirit:bitStringLength="6">0x01</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_INT_PF1</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF1" spirit:bitStringLength="6">0x01</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_INT_PF2</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF2" spirit:bitStringLength="6">0x01</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>VF_BARLITE_INT_PF3</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF3" spirit:bitStringLength="6">0x01</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_C2H_NUM_CHNL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_C2H_NUM_CHNL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_H2C_NUM_CHNL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_H2C_NUM_CHNL">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>H2C_XDMA_CHNL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.H2C_XDMA_CHNL" spirit:bitStringLength="8">0x0F</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C2H_XDMA_CHNL</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2H_XDMA_CHNL" spirit:bitStringLength="8">0x0F</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>AXISTEN_IF_ENABLE_MSG_ROUTE</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_MSG_ROUTE" spirit:bitStringLength="18">0x00000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_MORE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_MORE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DISABLE_BRAM_PIPELINE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DISABLE_BRAM_PIPELINE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>DISABLE_EQ_SYNCHRONIZER</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DISABLE_EQ_SYNCHRONIZER">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_ENABLE_RESOURCE_REDUCTION</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_RESOURCE_REDUCTION">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>GEN4_EIEOS_0S7</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GEN4_EIEOS_0S7">TRUE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_SUPPORTS_NARROW_BURST</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_SUPPORTS_NARROW_BURST">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>ENABLE_ATS_SWITCH</spirit:name>
+        <spirit:displayName>ATS Switch Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_ATS_SWITCH">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_ATS_SWITCH_UNIQUE_BDF</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ATS_SWITCH_UNIQUE_BDF">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_LAST_CORE_CAP_ADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LAST_CORE_CAP_ADDR" spirit:bitStringLength="12">0x100</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic_vector">
+        <spirit:name>C_VSEC_CAP_ADDR</spirit:name>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VSEC_CAP_ADDR" spirit:bitStringLength="12">0x128</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SOFT_RESET_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SOFT_RESET_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>INTERRUPT_OUT_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MSI_RX_PIN_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSI_RX_PIN_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_MSIX_RX_PIN_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSIX_RX_PIN_EN">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_INTX_RX_PIN_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTX_RX_PIN_EN">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>MSIX_RX_DECODE_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_RX_DECODE_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>PCIE_ID_IF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_ID_IF">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>TL_PF_ENABLE_REG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>AXSIZE_BYTE_ACCESS_EN</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXSIZE_BYTE_ACCESS_EN">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>SPLIT_DMA_SINGLE_PF</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SPLIT_DMA_SINGLE_PF">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RBAR_ENABLE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RBAR_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SMMU_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SMMU_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_AWUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_AWUSER_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_ARUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ARUSER_WIDTH">8</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SLAVE_READ_64OS_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SLAVE_READ_64OS_EN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>FLR_ENABLE</spirit:name>
+        <spirit:displayName>FLR Enable</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FLR_ENABLE">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SHELL_BRIDGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHELL_BRIDGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>MSIX_PCIE_INTERNAL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_PCIE_INTERNAL">0</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_03bd623c</spirit:name>
+      <spirit:enumeration>BAR_0</spirit:enumeration>
+      <spirit:enumeration>BAR_1</spirit:enumeration>
+      <spirit:enumeration>BAR_3:2</spirit:enumeration>
+      <spirit:enumeration>BAR_5:4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_08bf412c</spirit:name>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_0be33969</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+      <spirit:enumeration>10</spirit:enumeration>
+      <spirit:enumeration>11</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_0d378f84</spirit:name>
+      <spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
+      <spirit:enumeration>Mass_storage_controller</spirit:enumeration>
+      <spirit:enumeration>Network_controller</spirit:enumeration>
+      <spirit:enumeration>Display_controller</spirit:enumeration>
+      <spirit:enumeration>Multimedia_device</spirit:enumeration>
+      <spirit:enumeration>Memory_controller</spirit:enumeration>
+      <spirit:enumeration>Base_system_peripherals</spirit:enumeration>
+      <spirit:enumeration>Input_devices</spirit:enumeration>
+      <spirit:enumeration>Docking_stations</spirit:enumeration>
+      <spirit:enumeration>Processors</spirit:enumeration>
+      <spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
+      <spirit:enumeration>Wireless_controller</spirit:enumeration>
+      <spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
+      <spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Processing_accelerators</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_0f93492c</spirit:name>
+      <spirit:enumeration>Chip-to-Chip</spirit:enumeration>
+      <spirit:enumeration>Add-in_Card</spirit:enumeration>
+      <spirit:enumeration>Backplane</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_110bd32e</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_1cfc6134</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_1e9fb93b</spirit:name>
+      <spirit:enumeration>X1</spirit:enumeration>
+      <spirit:enumeration>X2</spirit:enumeration>
+      <spirit:enumeration>X4</spirit:enumeration>
+      <spirit:enumeration>X8</spirit:enumeration>
+      <spirit:enumeration>X16</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_24b724fb</spirit:name>
+      <spirit:enumeration>Basic</spirit:enumeration>
+      <spirit:enumeration>Advanced</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_2dba17cd</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>Check_Parity</spirit:enumeration>
+      <spirit:enumeration>Propagate_Parity</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_34d65ff4</spirit:name>
+      <spirit:enumeration>128</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_35d06715</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_38306dd1</spirit:name>
+      <spirit:enumeration>SOFT</spirit:enumeration>
+      <spirit:enumeration>HARD</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_3ca2cbc7</spirit:name>
+      <spirit:enumeration>BAR_0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_3cee6ea1</spirit:name>
+      <spirit:enumeration>16450_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>16550_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>16650_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>16750_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>16850_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>16950_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Bi_directional_parallel_port</spirit:enumeration>
+      <spirit:enumeration>ECP_1.X_compliant_parallel_port</spirit:enumeration>
+      <spirit:enumeration>GPIB(IEEE_488.1/2)_controller</spirit:enumeration>
+      <spirit:enumeration>Generic_XT_compatible_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Generic_modem</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16450_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16550_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16650_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>Hayes_compatible_modem_with_16750_compatible_interface</spirit:enumeration>
+      <spirit:enumeration>IEEE_1284_controller</spirit:enumeration>
+      <spirit:enumeration>IEEE_1284_target_device</spirit:enumeration>
+      <spirit:enumeration>Multiport_serial_controller</spirit:enumeration>
+      <spirit:enumeration>Other_communications_device</spirit:enumeration>
+      <spirit:enumeration>Parallel_port</spirit:enumeration>
+      <spirit:enumeration>Smart_Card</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4665eb01</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_47140c0d</spirit:name>
+      <spirit:enumeration>0000</spirit:enumeration>
+      <spirit:enumeration>0001</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_4e419c85</spirit:name>
+      <spirit:enumeration>Default</spirit:enumeration>
+      <spirit:enumeration>Falling_Edge</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_52d29139</spirit:name>
+      <spirit:enumeration>Bytes</spirit:enumeration>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+      <spirit:enumeration>Gigabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_574f38f3</spirit:name>
+      <spirit:enumeration>2.5_GT/s</spirit:enumeration>
+      <spirit:enumeration>5.0_GT/s</spirit:enumeration>
+      <spirit:enumeration>8.0_GT/s</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_57749bc8</spirit:name>
+      <spirit:enumeration>DMA</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_589df8e9</spirit:name>
+      <spirit:enumeration>RAM</spirit:enumeration>
+      <spirit:enumeration>Other_memory_controller</spirit:enumeration>
+      <spirit:enumeration>Flash</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5e150e6c</spirit:name>
+      <spirit:enumeration>50us</spirit:enumeration>
+      <spirit:enumeration>50ms</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5e2921cd</spirit:name>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5e45706a</spirit:name>
+      <spirit:enumeration>1_vector</spirit:enumeration>
+      <spirit:enumeration>2_vectors</spirit:enumeration>
+      <spirit:enumeration>4_vectors</spirit:enumeration>
+      <spirit:enumeration>8_vectors</spirit:enumeration>
+      <spirit:enumeration>16_vectors</spirit:enumeration>
+      <spirit:enumeration>32_vectors</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_640e51e1</spirit:name>
+      <spirit:enumeration>DMA</spirit:enumeration>
+      <spirit:enumeration>AXI_Bridge</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6727dfa6</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6a0870a7</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+      <spirit:enumeration>10</spirit:enumeration>
+      <spirit:enumeration>11</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>17</spirit:enumeration>
+      <spirit:enumeration>18</spirit:enumeration>
+      <spirit:enumeration>19</spirit:enumeration>
+      <spirit:enumeration>20</spirit:enumeration>
+      <spirit:enumeration>21</spirit:enumeration>
+      <spirit:enumeration>22</spirit:enumeration>
+      <spirit:enumeration>23</spirit:enumeration>
+      <spirit:enumeration>24</spirit:enumeration>
+      <spirit:enumeration>25</spirit:enumeration>
+      <spirit:enumeration>26</spirit:enumeration>
+      <spirit:enumeration>27</spirit:enumeration>
+      <spirit:enumeration>28</spirit:enumeration>
+      <spirit:enumeration>29</spirit:enumeration>
+      <spirit:enumeration>30</spirit:enumeration>
+      <spirit:enumeration>31</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6b979ebc</spirit:name>
+      <spirit:enumeration>250</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6eff49bd</spirit:name>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_7a7dde49</spirit:name>
+      <spirit:enumeration>true</spirit:enumeration>
+      <spirit:enumeration>false</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8061eec5</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>Tandem_PROM</spirit:enumeration>
+      <spirit:enumeration>Tandem_PCIe</spirit:enumeration>
+      <spirit:enumeration>Tandem_PCIe_with_Field_Updates</spirit:enumeration>
+      <spirit:enumeration>DFX_over_PCIe</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8112d406</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_81ddc592</spirit:name>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+      <spirit:enumeration>Gigabytes</spirit:enumeration>
+      <spirit:enumeration>Terabytes</spirit:enumeration>
+      <spirit:enumeration>Petabytes</spirit:enumeration>
+      <spirit:enumeration>Exabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_847d868a</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_86c5d341</spirit:name>
+      <spirit:enumeration>500</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_88156f2e</spirit:name>
+      <spirit:enumeration>QPLL1</spirit:enumeration>
+      <spirit:enumeration>QPLL0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8a9e69a3</spirit:name>
+      <spirit:enumeration>AXI_Lite_Master</spirit:enumeration>
+      <spirit:enumeration>DMA</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8aad6ae4</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8af5a703</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8b5e4915</spirit:name>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_8eea463a</spirit:name>
+      <spirit:enumeration>X1Y2</spirit:enumeration>
+      <spirit:enumeration>X1Y4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_914704bd</spirit:name>
+      <spirit:enumeration>100_MHz</spirit:enumeration>
+      <spirit:enumeration>125_MHz</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_91b49d0b</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+      <spirit:enumeration>10</spirit:enumeration>
+      <spirit:enumeration>11</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>13</spirit:enumeration>
+      <spirit:enumeration>14</spirit:enumeration>
+      <spirit:enumeration>15</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_96d6a000</spirit:name>
+      <spirit:enumeration>Wireless_controller</spirit:enumeration>
+      <spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Data_acquisition_and_signal_processing_controllers</spirit:enumeration>
+      <spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
+      <spirit:enumeration>Docking_stations</spirit:enumeration>
+      <spirit:enumeration>Processing_accelerators</spirit:enumeration>
+      <spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
+      <spirit:enumeration>Memory_controller</spirit:enumeration>
+      <spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
+      <spirit:enumeration>Encryption/Decryption_controllers</spirit:enumeration>
+      <spirit:enumeration>Display_controller</spirit:enumeration>
+      <spirit:enumeration>Multimedia_device</spirit:enumeration>
+      <spirit:enumeration>Input_devices</spirit:enumeration>
+      <spirit:enumeration>Mass_storage_controller</spirit:enumeration>
+      <spirit:enumeration>Processors</spirit:enumeration>
+      <spirit:enumeration>Device_does_not_fit_in_any_defined_classes</spirit:enumeration>
+      <spirit:enumeration>Bridge_device</spirit:enumeration>
+      <spirit:enumeration>Network_controller</spirit:enumeration>
+      <spirit:enumeration>Base_system_peripherals</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_97bc19ec</spirit:name>
+      <spirit:enumeration>256_bit</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_9aec9108</spirit:name>
+      <spirit:enumeration>Internal</spirit:enumeration>
+      <spirit:enumeration>External</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_9e15bd51</spirit:name>
+      <spirit:enumeration>CONSTANT</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_9f5580fd</spirit:name>
+      <spirit:enumeration>Pre-Production</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a30da595</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pcie_perstn</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a44ca313</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+      <spirit:enumeration>pci_express_x1</spirit:enumeration>
+      <spirit:enumeration>pci_express_x16</spirit:enumeration>
+      <spirit:enumeration>pci_express_x2</spirit:enumeration>
+      <spirit:enumeration>pci_express_x4</spirit:enumeration>
+      <spirit:enumeration>pci_express_x8</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a71f3969</spirit:name>
+      <spirit:enumeration>AXI_Memory_Mapped</spirit:enumeration>
+      <spirit:enumeration>AXI_Stream</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_aa031417</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ab8591cd</spirit:name>
+      <spirit:enumeration>PCI_Express_Endpoint_device</spirit:enumeration>
+      <spirit:enumeration>PCI_Express_Endpoint_device</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_abc20383</spirit:name>
+      <spirit:enumeration>GTY_Quad_227</spirit:enumeration>
+      <spirit:enumeration>GTY_Quad_226</spirit:enumeration>
+      <spirit:enumeration>GTY_Quad_225</spirit:enumeration>
+      <spirit:enumeration>GTY_Quad_224</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ae9f88f6</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_b0ffef10</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>7</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_bdd7203f</spirit:name>
+      <spirit:enumeration>True</spirit:enumeration>
+      <spirit:enumeration>False</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_bea500ca</spirit:name>
+      <spirit:enumeration>None</spirit:enumeration>
+      <spirit:enumeration>MSI-X_External</spirit:enumeration>
+      <spirit:enumeration>MSI-X_Internal</spirit:enumeration>
+      <spirit:enumeration>MSI-X_AXI4-Stream</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c15e8c67</spirit:name>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c3d223d9</spirit:name>
+      <spirit:enumeration>Memory</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c63ab5b1</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>5</spirit:enumeration>
+      <spirit:enumeration>6</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ca005b72</spirit:name>
+      <spirit:enumeration>No_ASPM</spirit:enumeration>
+      <spirit:enumeration>L1_Supported</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ca108395</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d123c74c</spirit:name>
+      <spirit:enumeration>Bytes</spirit:enumeration>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d1e1a340</spirit:name>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+      <spirit:enumeration>Gigabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d53faa96</spirit:name>
+      <spirit:enumeration>100_MHz</spirit:enumeration>
+      <spirit:enumeration>125_MHz</spirit:enumeration>
+      <spirit:enumeration>250_MHz</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_d85ad257</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_df7cde9e</spirit:name>
+      <spirit:enumeration>RAM</spirit:enumeration>
+      <spirit:enumeration>Flash</spirit:enumeration>
+      <spirit:enumeration>Other_memory_controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_dff1a45d</spirit:name>
+      <spirit:enumeration>Wireless_controller</spirit:enumeration>
+      <spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Data_acquisition_and_signal_processing_controllers</spirit:enumeration>
+      <spirit:enumeration>Processing_accelerators</spirit:enumeration>
+      <spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
+      <spirit:enumeration>Docking_stations</spirit:enumeration>
+      <spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
+      <spirit:enumeration>Memory_controller</spirit:enumeration>
+      <spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
+      <spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
+      <spirit:enumeration>Encryption/Decryption_controllers</spirit:enumeration>
+      <spirit:enumeration>Display_controller</spirit:enumeration>
+      <spirit:enumeration>Multimedia_device</spirit:enumeration>
+      <spirit:enumeration>Input_devices</spirit:enumeration>
+      <spirit:enumeration>Mass_storage_controller</spirit:enumeration>
+      <spirit:enumeration>Processors</spirit:enumeration>
+      <spirit:enumeration>Device_does_not_fit_in_any_defined_classes</spirit:enumeration>
+      <spirit:enumeration>Bridge_device</spirit:enumeration>
+      <spirit:enumeration>Network_controller</spirit:enumeration>
+      <spirit:enumeration>Base_system_peripherals</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e7c484ae</spirit:name>
+      <spirit:enumeration>TRUE</spirit:enumeration>
+      <spirit:enumeration>FALSE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e7f13338</spirit:name>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9cf6440</spirit:name>
+      <spirit:enumeration>Disabled</spirit:enumeration>
+      <spirit:enumeration>32bit_Enabled</spirit:enumeration>
+      <spirit:enumeration>64bit_Enabled</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ec64e624</spirit:name>
+      <spirit:enumeration>N/A</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ecc4b9b7</spirit:name>
+      <spirit:enumeration>AU200</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f1174048</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>INTA</spirit:enumeration>
+      <spirit:enumeration>INTB</spirit:enumeration>
+      <spirit:enumeration>INTC</spirit:enumeration>
+      <spirit:enumeration>INTD</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_f94ec5c4</spirit:name>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fab783d7</spirit:name>
+      <spirit:enumeration>User_Reset</spirit:enumeration>
+      <spirit:enumeration>Phy_Ready</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fc3456a9</spirit:name>
+      <spirit:enumeration>Disabled</spirit:enumeration>
+      <spirit:enumeration>Enabled</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fde36331</spirit:name>
+      <spirit:enumeration>Kilobytes</spirit:enumeration>
+      <spirit:enumeration>Megabytes</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_fe1fb7c4</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>12</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3c87fcdb</spirit:name>
+      <spirit:enumeration spirit:text="Include GT Wizard in core">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Include GT Wizard in example design">0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_53749dec</spirit:name>
+      <spirit:enumeration spirit:text="Include Shared Logic in core">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="Include Shared Logic in example design">0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_6f00a734</spirit:name>
+      <spirit:enumeration spirit:text="Include GT COMMON in example design">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="Include GT COMMON inside GT Wizard">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="No sharing when inside GT Wizard and PCIe">2</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_elaboratesubcores_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>ip_0/xdma_pcie4_ip.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_0/xdma_pcie4_ip.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci</spirit:name>
+        <spirit:userFileType>xci</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xml</spirit:name>
+        <spirit:userFileType>xml</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>The Xilinx PCI Express DMA</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xdma</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>functional_mode</spirit:name>
+      <spirit:displayName>Functional Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.functional_mode" spirit:choiceRef="choice_list_640e51e1" spirit:order="2">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.functional_mode">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mode_selection</spirit:name>
+      <spirit:displayName>Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mode_selection" spirit:choiceRef="choice_list_24b724fb" spirit:order="1.5">Basic</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.mode_selection">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>device_port_type</spirit:name>
+      <spirit:displayName>Device Port Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.device_port_type" spirit:choiceRef="choice_list_ab8591cd" spirit:order="3">PCI_Express_Endpoint_device</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.device_port_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pcie_blk_locn</spirit:name>
+      <spirit:displayName>Pcie Blk Locn</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_blk_locn" spirit:choiceRef="choice_list_8eea463a" spirit:order="4">X1Y2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pcie_blk_locn">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pl_link_cap_max_link_width</spirit:name>
+      <spirit:displayName>Pl Link Cap Max Link Width</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pl_link_cap_max_link_width" spirit:choiceRef="choice_list_1e9fb93b" spirit:order="5">X8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pl_link_cap_max_link_width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pl_link_cap_max_link_speed</spirit:name>
+      <spirit:displayName>Pl Link Cap Max Link Speed</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pl_link_cap_max_link_speed" spirit:choiceRef="choice_list_574f38f3" spirit:order="6">8.0_GT/s</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pl_link_cap_max_link_speed">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ref_clk_freq</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ref_clk_freq" spirit:choiceRef="choice_list_d53faa96" spirit:order="7" spirit:configGroups="1 UnGrouped">100_MHz</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.ref_clk_freq">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>drp_clk_sel</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.drp_clk_sel" spirit:choiceRef="choice_list_9aec9108" spirit:order="7.1" spirit:configGroups="1 UnGrouped">Internal</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.drp_clk_sel">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>free_run_freq</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.free_run_freq" spirit:choiceRef="choice_list_914704bd" spirit:order="7.2" spirit:configGroups="1 UnGrouped">100_MHz</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.free_run_freq">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_addr_width</spirit:name>
+      <spirit:displayName>AXI Address width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_addr_width" spirit:order="8" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axi_addr_width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_data_width</spirit:name>
+      <spirit:displayName>AXI Data width</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axi_data_width" spirit:choiceRef="choice_list_97bc19ec" spirit:order="9">256_bit</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axi_data_width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_freq</spirit:name>
+      <spirit:displayName>AXIsten if freq</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_freq" spirit:choiceRef="choice_list_6b979ebc" spirit:order="10">250</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axisten_freq">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_axi_slave_if</spirit:name>
+      <spirit:displayName>Enable AXI Slave Interface</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_slave_if" spirit:order="11">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_slave_if">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_axi_master_if</spirit:name>
+      <spirit:displayName>Enable AXI Master Interface</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_master_if" spirit:order="12">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_master_if">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pipe_sim</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pipe_sim" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pipe_sim">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_ext_ch_gt_drp</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_ext_ch_gt_drp" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_ext_ch_gt_drp">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_pcie_drp</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_pcie_drp" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_pcie_drp">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dedicate_perst</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.dedicate_perst" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.dedicate_perst">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>sys_reset_polarity</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sys_reset_polarity" spirit:choiceRef="choice_list_6eff49bd" spirit:order="17">ACTIVE_LOW</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.sys_reset_polarity">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mcap_enablement</spirit:name>
+      <spirit:displayName>MCAP Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mcap_enablement" spirit:choiceRef="choice_list_8061eec5" spirit:order="18">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mcap_fpga_bitstream_version</spirit:name>
+      <spirit:displayName>MCAP Bitstream Version Register Value</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mcap_fpga_bitstream_version" spirit:order="18.1">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.mcap_fpga_bitstream_version">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_startup_primitive</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_startup_primitive" spirit:order="19">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.ext_startup_primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_code</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_code" spirit:order="1.1">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vendor_id</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.vendor_id" spirit:order="20">10EE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.vendor_id">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_device_id</spirit:name>
+      <spirit:displayName>PF0 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_device_id" spirit:order="21">9038</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_device_id">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_revision_id</spirit:name>
+      <spirit:displayName>PF0 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_revision_id" spirit:order="22">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_revision_id">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_subsystem_vendor_id</spirit:name>
+      <spirit:displayName>PF0 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_subsystem_vendor_id" spirit:order="23">10EE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_subsystem_vendor_id">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_subsystem_id</spirit:name>
+      <spirit:displayName>PF0 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_subsystem_id" spirit:order="24">0007</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_subsystem_id">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="25">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_Use_Class_Code_Lookup_Assistant">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_base_class_menu</spirit:name>
+      <spirit:displayName>Pf0 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_base_class_menu" spirit:choiceRef="choice_list_0d378f84" spirit:order="26">Simple_communication_controllers</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_base_class_menu">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_base</spirit:name>
+      <spirit:displayName>Pf0 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_base" spirit:order="27">07</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_base">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf0 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sub_class_interface_menu" spirit:choiceRef="choice_list_3cee6ea1" spirit:order="28">16450_compatible_serial_controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_sub_class_interface_menu">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_sub</spirit:name>
+      <spirit:displayName>pf0 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_sub" spirit:order="29">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_sub">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_interface</spirit:name>
+      <spirit:displayName>pf0 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_interface" spirit:order="30">01</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_interface">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code</spirit:name>
+      <spirit:displayName>pf0 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code" spirit:order="31">070001</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axilite_master_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axilite_master_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axilite_master_en">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axilite_master_size</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axilite_master_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="34">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axilite_master_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axilite_master_scale</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axilite_master_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="35">Megabytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axilite_master_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="36">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_en">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_size</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="37">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_scale</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="38">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axist_bypass_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axist_bypass_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="39">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axist_bypass_en">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axist_bypass_size</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axist_bypass_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="40">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axist_bypass_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axist_bypass_scale</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axist_bypass_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="41">Megabytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axist_bypass_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_axil_master</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_axil_master" spirit:order="42" spirit:configGroups="1 UnGrouped">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_axil_master">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_xdma</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_xdma" spirit:order="43" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_xdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_axist_bypass</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_axist_bypass" spirit:order="44" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_axist_bypass">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_interrupt_pin</spirit:name>
+      <spirit:displayName>pf0 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_interrupt_pin" spirit:choiceRef="choice_list_f1174048" spirit:order="45">INTA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_interrupt_pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msi_enabled</spirit:name>
+      <spirit:displayName>pf0 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="46">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_msi_enabled">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msi_cap_multimsgcap</spirit:name>
+      <spirit:displayName>pf0 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msi_cap_multimsgcap" spirit:choiceRef="choice_list_5e45706a" spirit:order="47">1_vector</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_msi_cap_multimsgcap">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>comp_timeout</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.comp_timeout" spirit:choiceRef="choice_list_5e150e6c" spirit:order="48" spirit:configGroups="1 UnGrouped">50ms</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.comp_timeout">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>timeout0_sel</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.timeout0_sel" spirit:choiceRef="choice_list_91b49d0b" spirit:order="48.1" spirit:configGroups="1 UnGrouped">14</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.timeout0_sel">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>timeout1_sel</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.timeout1_sel" spirit:choiceRef="choice_list_91b49d0b" spirit:order="48.2" spirit:configGroups="1 UnGrouped">15</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.timeout1_sel">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>timeout_mult</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.timeout_mult" spirit:choiceRef="choice_list_4665eb01" spirit:order="48.3" spirit:configGroups="1 UnGrouped">3</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.timeout_mult">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>old_bridge_timeout</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.old_bridge_timeout" spirit:order="48.4">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic" spirit:choiceRef="choice_pairs_53749dec" spirit:order="49">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.Shared_Logic">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Clk" spirit:order="50">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic_Both</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Both" spirit:order="51">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic_Gtc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Gtc" spirit:order="52">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic_Gtc_7xG2</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Gtc_7xG2" spirit:order="52.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic_Clk_7xG2</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Clk_7xG2" spirit:order="50.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Shared_Logic_Both_7xG2</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Both_7xG2" spirit:order="51.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_transceiver_status_ports</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_transceiver_status_ports" spirit:order="53">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_transceiver_status_ports">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_rnum_chnl</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_rnum_chnl" spirit:choiceRef="choice_list_aa031417" spirit:order="54">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_rnum_chnl">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_wnum_chnl</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_wnum_chnl" spirit:choiceRef="choice_list_aa031417" spirit:order="55">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_wnum_chnl">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_axilite_slave</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_axilite_slave" spirit:order="56">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_axilite_slave">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_num_usr_irq</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_num_usr_irq" spirit:choiceRef="choice_list_0be33969" spirit:order="57">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_num_usr_irq">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_rnum_rids</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_rnum_rids" spirit:order="58" spirit:minimum="2" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_wnum_rids</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_wnum_rids" spirit:order="59" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYS_RST_N_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SYS_RST_N_BOARD_INTERFACE" spirit:choiceRef="choice_list_a30da595" spirit:order="60">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PCIE_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_BOARD_INTERFACE" spirit:choiceRef="choice_list_a44ca313" spirit:order="61">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_gt_selection</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_gt_selection" spirit:order="3.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>select_quad</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.select_quad" spirit:choiceRef="choice_list_abc20383" spirit:order="4.5">GTY_Quad_227</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.select_quad">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_PPM_OFFSET</spirit:name>
+      <spirit:description>Specify the PPM offset between received data and transmitted data</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PPM_OFFSET" spirit:order="62" spirit:minimum="0" spirit:maximum="1250" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RX_SSC_PPM</spirit:name>
+      <spirit:description>Specify the spread spectrum clocking modulation in PPM</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_SSC_PPM" spirit:order="63" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INS_LOSS_NYQ</spirit:name>
+      <spirit:description>Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB</spirit:description>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.INS_LOSS_NYQ" spirit:order="64">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PHY_LP_TXPRESET</spirit:name>
+      <spirit:displayName>Phy Lp Txpreset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHY_LP_TXPRESET" spirit:choiceRef="choice_list_8b5e4915" spirit:order="65">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>coreclk_freq</spirit:name>
+      <spirit:displayName>CORE CLOCK FREQ</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.coreclk_freq" spirit:choiceRef="choice_list_86c5d341" spirit:order="66">500</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.coreclk_freq">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>plltype</spirit:name>
+      <spirit:displayName>PLL TYPE</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.plltype" spirit:choiceRef="choice_list_88156f2e" spirit:order="67">QPLL1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_axi_intf_mm</spirit:name>
+      <spirit:displayName>XDMA Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_axi_intf_mm" spirit:choiceRef="choice_list_a71f3969" spirit:order="68">AXI_Stream</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_axi_intf_mm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_pcie_64bit_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_pcie_64bit_en" spirit:order="69">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>silicon_rev</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.silicon_rev" spirit:choiceRef="choice_list_9f5580fd" spirit:order="70">Pre-Production</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_dsc_bypass</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_dsc_bypass" spirit:order="71">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>performance</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.performance" spirit:order="72">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pcie_extended_tag</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_extended_tag" spirit:order="73">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rx_detect</spirit:name>
+      <spirit:displayName>Receiver Detect</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.rx_detect" spirit:choiceRef="choice_list_4e419c85" spirit:order="74">Default</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_link_status_slot_clock_config</spirit:name>
+      <spirit:displayName>Pf0 Link Status Slot Clock Config</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_link_status_slot_clock_config" spirit:choiceRef="choice_list_7a7dde49" spirit:order="75">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dsc_bypass_rd</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_rd" spirit:choiceRef="choice_list_47140c0d" spirit:order="76">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dsc_bypass_wr</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_wr" spirit:choiceRef="choice_list_47140c0d" spirit:order="77">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_sts_ports</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_sts_ports" spirit:order="78">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_enabled</spirit:name>
+      <spirit:displayName>Pf0 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_cap_table_size</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_table_size" spirit:order="80">000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_msix_cap_table_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_cap_table_offset</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_table_offset" spirit:order="81">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_msix_cap_table_offset">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_cap_table_bir</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_table_bir" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="82">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_msix_cap_table_bir">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_cap_pba_offset</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_pba_offset" spirit:order="83">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_msix_cap_pba_offset">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_cap_pba_bir</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_pba_bir" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="84">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_msix_cap_pba_bir">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_enabled</spirit:name>
+      <spirit:displayName>Pf1 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_cap_table_size</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_table_size" spirit:order="80.5">01F</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_cap_table_offset</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_table_offset" spirit:order="81.5">00009000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_cap_table_bir</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_table_bir" spirit:choiceRef="choice_list_03bd623c" spirit:order="82.5">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_table_bir">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_cap_pba_offset</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_pba_offset" spirit:order="83.5">00009FE0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_cap_pba_bir</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_pba_bir" spirit:choiceRef="choice_list_03bd623c" spirit:order="84.5">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_pba_bir">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_mgmt_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_mgmt_if" spirit:order="85">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.cfg_mgmt_if">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ins_loss_profile</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ins_loss_profile" spirit:choiceRef="choice_list_0f93492c" spirit:order="63.5">Add-in_Card</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axil_master_64bit_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axil_master_64bit_en" spirit:order="86">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axil_master_64bit_en">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_bypass_64bit_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_bypass_64bit_en" spirit:order="87">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axi_bypass_64bit_en">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axil_master_prefetchable</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axil_master_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axil_master_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_pcie_prefetchable</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_pcie_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.xdma_pcie_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_bypass_prefetchable</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axi_bypass_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="89">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axi_bypass_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>cfg_ext_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_ext_if" spirit:order="90">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>legacy_cfg_ext_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.legacy_cfg_ext_if" spirit:order="90.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.legacy_cfg_ext_if">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>parity_settings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.parity_settings" spirit:choiceRef="choice_list_2dba17cd" spirit:order="91">None</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.parity_settings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecc_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecc_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="91.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.ecc_en">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_debug_ports</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_debug_ports" spirit:order="92">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_id_width</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axi_id_width" spirit:choiceRef="choice_list_110bd32e" spirit:order="93">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axi_id_width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vu9p_board</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vu9p_board" spirit:order="93.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>type1_membase_memlimit_enable</spirit:name>
+      <spirit:displayName>Type1 Config MemBase and MemLimit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.type1_membase_memlimit_enable" spirit:choiceRef="choice_list_fc3456a9" spirit:order="93.2">Disabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.type1_membase_memlimit_enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>type1_prefetchable_membase_memlimit</spirit:name>
+      <spirit:displayName>Type1 Config Prefetchable MemBase and MemLimit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.type1_prefetchable_membase_memlimit" spirit:choiceRef="choice_list_e9cf6440" spirit:order="93.3">Disabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.type1_prefetchable_membase_memlimit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_jtag_dbg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_jtag_dbg" spirit:order="94">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_jtag_dbg">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_ltssm_dbg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ltssm_dbg" spirit:order="94.11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_ltssm_dbg">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_ibert</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ibert" spirit:order="94.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_ibert">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_num</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_num" spirit:order="95" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="6" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_num">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_0" spirit:order="96" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_1" spirit:order="97" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_2" spirit:order="98" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_3" spirit:order="99" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_4" spirit:order="100" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_5" spirit:order="101" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_highaddr_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_0" spirit:order="102" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_highaddr_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_1" spirit:order="103" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_highaddr_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_2" spirit:order="104" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_highaddr_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_3" spirit:order="105" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_highaddr_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_4" spirit:order="106" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar_highaddr_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_5" spirit:order="107" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar2pciebar_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_0" spirit:order="108" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar2pciebar_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_1" spirit:order="109" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar2pciebar_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_2" spirit:order="110" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar2pciebar_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_3" spirit:order="111" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar2pciebar_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_4" spirit:order="112" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axibar2pciebar_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_5" spirit:order="113" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>include_baroffset_reg</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.include_baroffset_reg" spirit:choiceRef="choice_list_7a7dde49" spirit:order="116" spirit:configGroups="1 UnGrouped">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.include_baroffset_reg">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BASEADDR</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.BASEADDR" spirit:order="117" spirit:configGroups="1 UnGrouped">0x00001000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.BASEADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>HIGHADDR</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.HIGHADDR" spirit:order="118" spirit:configGroups="1 UnGrouped">0x00001FFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.HIGHADDR">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>s_axi_id_width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.s_axi_id_width" spirit:choiceRef="choice_list_6a0870a7" spirit:order="119" spirit:configGroups="1 UnGrouped">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.s_axi_id_width">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_m_axi_num_write</spirit:name>
+      <spirit:displayName>AXI Master outstanding write Transactions Selection</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_m_axi_num_write" spirit:choiceRef="choice_list_8112d406" spirit:order="120">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_m_axi_num_write">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_m_axi_num_read</spirit:name>
+      <spirit:displayName>AXI Master outstanding read Transactions Selection</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_m_axi_num_read" spirit:choiceRef="choice_list_ca108395" spirit:order="121">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_m_axi_num_read">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_m_axi_num_readq</spirit:name>
+      <spirit:displayName>AXI Master outstanding read Transactions Selection</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_m_axi_num_readq" spirit:choiceRef="choice_list_110bd32e" spirit:order="121.1">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_s_axi_num_write</spirit:name>
+      <spirit:displayName>AXI Slave outstanding write Transactions Selection</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_s_axi_num_write" spirit:choiceRef="choice_list_ca108395" spirit:order="122">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_s_axi_num_write">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_s_axi_num_read</spirit:name>
+      <spirit:displayName>AXI Slave outstanding read Transactions Selection</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_s_axi_num_read" spirit:choiceRef="choice_list_ca108395" spirit:order="123">8</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_s_axi_num_read">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_impl_locn</spirit:name>
+      <spirit:displayName>Pf0 Msix Implementation Location</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_impl_locn" spirit:choiceRef="choice_list_9aec9108" spirit:order="124">Internal</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_msix_impl_locn">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_aclk_loopback</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_aclk_loopback" spirit:order="125">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="126">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_enabled">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="127">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_size" spirit:choiceRef="choice_list_08bf412c" spirit:order="128">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_size">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="129">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_scale">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="130">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_64bit">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="131">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_enabled">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="133">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="134">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="135">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="136">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="137">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="138">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="139">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="140">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="141">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="142">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="143">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="144">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="145">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="146">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="147">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="148">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="149">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="150">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="151">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="152">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="153">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="154">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="155">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="156">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="157">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="158">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="159">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_64bit</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="160">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="161">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_0" spirit:order="162" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_1" spirit:order="163" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_2" spirit:order="164" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_3" spirit:order="165" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_4" spirit:order="166" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_5" spirit:order="167" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pciebar2axibar_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_6" spirit:order="167.1" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar_indicator" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="168">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.bar_indicator">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar0_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar0_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="169">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar0_indicator">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar1_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar1_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="170">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar1_indicator">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar2_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar2_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="171">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar2_indicator">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar3_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar3_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="172">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar3_indicator">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar4_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar4_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="173">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar4_indicator">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bar5_indicator</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar5_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="174">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar5_indicator">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>barlite2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.barlite2" spirit:choiceRef="choice_list_b0ffef10" spirit:order="174.5">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_dbg_descramble</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_dbg_descramble" spirit:order="175">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vcu118_board</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vcu118_board" spirit:order="176">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_pf_enable_reg</spirit:name>
+      <spirit:displayName>NUM PF Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.tl_pf_enable_reg" spirit:choiceRef="choice_list_8aad6ae4" spirit:order="177">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_vendor_id</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_vendor_id" spirit:order="178">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_device_id</spirit:name>
+      <spirit:displayName>PF1 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_device_id" spirit:order="179">1041</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code</spirit:name>
+      <spirit:displayName>Pf1 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code" spirit:order="190">070001</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_REVISION_ID</spirit:name>
+      <spirit:displayName>Pf1 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_REVISION_ID" spirit:order="181">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>Pf1 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID" spirit:order="182">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>Pf1 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_ID" spirit:order="183">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="184">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PF1_Use_Class_Code_Lookup_Assistant">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_base_class_menu</spirit:name>
+      <spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_base_class_menu" spirit:choiceRef="choice_list_0d378f84" spirit:order="185">Simple_communication_controllers</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_base</spirit:name>
+      <spirit:displayName>Pf1 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_base" spirit:order="186">07</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_base">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_sub</spirit:name>
+      <spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_sub" spirit:order="187">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_sub">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sub_class_interface_menu" spirit:choiceRef="choice_list_3cee6ea1" spirit:order="188">16450_compatible_serial_controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_sub_class_interface_menu">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_interface</spirit:name>
+      <spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_interface" spirit:order="189">01</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_interface">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>Pf1 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="191">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msi_enabled</spirit:name>
+      <spirit:displayName>Pf1 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="192">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>Pf1 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="193">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="194">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="195">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar0_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_size</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_size" spirit:choiceRef="choice_list_1cfc6134" spirit:order="196">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="197">Megabytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="198">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="199">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="200">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="201">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar1_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_size</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="202">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="203">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="204">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="205">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="206">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="207">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar2_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_size</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="208">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_scale" spirit:choiceRef="choice_list_81ddc592" spirit:order="209">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="210">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="211">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="212">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="213">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_size</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="214">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="215">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="216">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="217">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="218">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="219.5">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar4_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_size</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="220">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_scale" spirit:choiceRef="choice_list_81ddc592" spirit:order="221">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf1 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="222">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="223">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="224">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="225">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_size</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="226">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_scale</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="227">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf1 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="228">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_device_id</spirit:name>
+      <spirit:displayName>PF2 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_device_id" spirit:order="229">1040</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code</spirit:name>
+      <spirit:displayName>pf2 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code" spirit:order="240">058000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_REVISION_ID</spirit:name>
+      <spirit:displayName>pf2 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_REVISION_ID" spirit:order="231">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>pf2 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID" spirit:order="232">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>pf2 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_ID" spirit:order="233">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="234">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_base_class_menu</spirit:name>
+      <spirit:displayName>pf2 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="235">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_base</spirit:name>
+      <spirit:displayName>pf2 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_base" spirit:order="236">05</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_sub</spirit:name>
+      <spirit:displayName>pf2 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_sub" spirit:order="237">80</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>pf2 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="238">Other_memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_interface</spirit:name>
+      <spirit:displayName>pf2 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_interface" spirit:order="239">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>pf2 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="241">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_msi_enabled</spirit:name>
+      <spirit:displayName>pf2 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="242">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>pf2 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="243">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_enabled</spirit:name>
+      <spirit:displayName>pf2 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="244">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="245">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar0_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_size</spirit:name>
+      <spirit:displayName>pf2 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="246">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_scale</spirit:name>
+      <spirit:displayName>pf2 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="247">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_64bit</spirit:name>
+      <spirit:displayName>pf2 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="248">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_prefetchable</spirit:name>
+      <spirit:displayName>pf2 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="249">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_enabled</spirit:name>
+      <spirit:displayName>pf2 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="250">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="251">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar1_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_size</spirit:name>
+      <spirit:displayName>pf2 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="252">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_scale</spirit:name>
+      <spirit:displayName>pf2 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="253">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_64bit</spirit:name>
+      <spirit:displayName>pf2 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="254">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_prefetchable</spirit:name>
+      <spirit:displayName>pf2 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="255">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_enabled</spirit:name>
+      <spirit:displayName>pf2 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="256">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="257">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar2_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_size</spirit:name>
+      <spirit:displayName>pf2 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="258">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_scale</spirit:name>
+      <spirit:displayName>pf2 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="259">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_64bit</spirit:name>
+      <spirit:displayName>pf2 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="260">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_prefetchable</spirit:name>
+      <spirit:displayName>pf2 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="261">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_enabled</spirit:name>
+      <spirit:displayName>pf2 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="262">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="263">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar3_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_size</spirit:name>
+      <spirit:displayName>pf2 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="264">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_scale</spirit:name>
+      <spirit:displayName>pf2 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="265">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_64bit</spirit:name>
+      <spirit:displayName>pf2 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="266">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_prefetchable</spirit:name>
+      <spirit:displayName>pf2 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="267">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_enabled</spirit:name>
+      <spirit:displayName>pf2 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="268">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="269">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar4_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_size</spirit:name>
+      <spirit:displayName>pf2 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="270">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_scale</spirit:name>
+      <spirit:displayName>pf2 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="271">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_64bit</spirit:name>
+      <spirit:displayName>pf2 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="272">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_prefetchable</spirit:name>
+      <spirit:displayName>pf2 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="273">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_enabled</spirit:name>
+      <spirit:displayName>pf2 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="274">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="275">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar5_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_size</spirit:name>
+      <spirit:displayName>pf2 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="276">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_scale</spirit:name>
+      <spirit:displayName>pf2 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="277">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_prefetchable</spirit:name>
+      <spirit:displayName>pf2 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="278">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_device_id</spirit:name>
+      <spirit:displayName>PF3 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_device_id" spirit:order="279">1039</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code</spirit:name>
+      <spirit:displayName>Pf3 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code" spirit:order="290">058000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_REVISION_ID</spirit:name>
+      <spirit:displayName>Pf3 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_REVISION_ID" spirit:order="281">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SUBSYSTEM_VENDOR_ID</spirit:name>
+      <spirit:displayName>Pf3 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID" spirit:order="282">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SUBSYSTEM_ID</spirit:name>
+      <spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_ID" spirit:order="283">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_Use_Class_Code_Lookup_Assistant</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="284">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_base_class_menu</spirit:name>
+      <spirit:displayName>Pf3 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="285">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_base</spirit:name>
+      <spirit:displayName>Pf3 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_base" spirit:order="286.1">05</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_sub</spirit:name>
+      <spirit:displayName>Pf3 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_sub" spirit:order="287">80</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sub_class_interface_menu</spirit:name>
+      <spirit:displayName>Pf3 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="288">Other_memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_interface</spirit:name>
+      <spirit:displayName>Pf3 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_interface" spirit:order="289">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_INTERRUPT_PIN</spirit:name>
+      <spirit:displayName>Pf3 Interrupt Pin</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="291">NONE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_msi_enabled</spirit:name>
+      <spirit:displayName>Pf3 Msi Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="292">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSI_CAP_MULTIMSGCAP</spirit:name>
+      <spirit:displayName>Pf3 Msi Cap Multimsgcap</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="293">1_vector</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="294">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="295">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar0_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_size</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="296">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="297">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="298">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="299">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="300">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="301">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar1_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_size</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="302">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="303">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="304">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="305">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="306">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="307">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar2_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_size</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="308">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="309">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="310">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="311">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="312">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="313">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar3_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_size</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="314">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="315">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="316">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="317">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="318">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="319">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar4_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_size</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="320">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="321">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf3 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="322">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="323">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="324">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="325">Memory</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar5_type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_size</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="326">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_scale</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="327">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf3 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="328">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>split_dma</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.split_dma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>split_dma_single_pf</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.split_dma_single_pf" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mult_pf_des</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.mult_pf_des" spirit:order="329.5">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf_swap</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pf_swap" spirit:order="329.6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>prog_usr_irq_vec_map</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.prog_usr_irq_vec_map" spirit:order="329.61">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rcfg_nph_fix_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rcfg_nph_fix_en" spirit:order="329.62">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>post_synth_sim_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.post_synth_sim_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.7">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>user_pf_two_axilite_bar_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.user_pf_two_axilite_bar_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.75">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>two_bypass_bar</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.two_bypass_bar" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.8">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xlnx_ref_board</spirit:name>
+      <spirit:displayName>Xlnx Ref Board</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xlnx_ref_board" spirit:choiceRef="choice_list_ecc4b9b7" spirit:order="330">AU200</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xlnx_ref_board">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_l23_entry</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_l23_entry" spirit:order="331">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_0" spirit:order="332" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_1" spirit:order="333" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_2" spirit:order="334" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_2">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_3" spirit:order="335" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_4" spirit:order="336" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_4">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_5" spirit:order="337" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_pciebar2axibar_6</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_6" spirit:order="337.1" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_6">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_pciebar2axibar_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_0" spirit:order="338" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_pciebar2axibar_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_1" spirit:order="339" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_pciebar2axibar_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_2" spirit:order="340" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_pciebar2axibar_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_3" spirit:order="341" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_pciebar2axibar_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_4" spirit:order="342" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_pciebar2axibar_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_5" spirit:order="343" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_pciebar2axibar_0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_0" spirit:order="344" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_pciebar2axibar_1</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_1" spirit:order="345" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_pciebar2axibar_2</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_2" spirit:order="346" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_2">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_pciebar2axibar_3</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_3" spirit:order="347" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_3">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_pciebar2axibar_4</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_4" spirit:order="348" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_4">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_pciebar2axibar_5</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_5" spirit:order="349" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_5">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gtwiz_in_core_us</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtwiz_in_core_us" spirit:choiceRef="choice_pairs_3c87fcdb" spirit:order="350">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gtwiz_in_core_usp</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtwiz_in_core_usp" spirit:choiceRef="choice_pairs_3c87fcdb" spirit:order="351.1">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dma_reset_source_sel</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dma_reset_source_sel" spirit:choiceRef="choice_list_fab783d7" spirit:order="352">User_Reset</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_dma_and_bridge</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_dma_and_bridge" spirit:order="353">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_coreclk_es1</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_coreclk_es1" spirit:order="354">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pipe_line_stage</spirit:name>
+      <spirit:displayName>number of Pipe Line Stages</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pipe_line_stage" spirit:choiceRef="choice_list_c63ab5b1" spirit:order="355">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pipe_line_stage">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axis_pipe_line_stage</spirit:name>
+      <spirit:displayName>number of Pipe Line Stages on PCIe axis interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axis_pipe_line_stage" spirit:choiceRef="choice_list_c63ab5b1" spirit:order="355">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axis_pipe_line_stage">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vu9p_tul_ex</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vu9p_tul_ex" spirit:order="356">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>vcu1525_ddr_ex</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vcu1525_ddr_ex" spirit:order="356.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_bridge</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_bridge" spirit:order="357">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_ccix</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ccix" spirit:choiceRef="choice_list_e7c484ae" spirit:order="358">FALSE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_dvsec</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_dvsec" spirit:choiceRef="choice_list_e7c484ae" spirit:order="358.1">FALSE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_sys_clk_bufg</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_sys_clk_bufg" spirit:order="359">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>usr_irq_exdes</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.usr_irq_exdes" spirit:order="360">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axi_vip_in_exdes</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_vip_in_exdes" spirit:order="360">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_non_incremental_exdes</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_non_incremental_exdes" spirit:order="360.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>xdma_st_infinite_desc_exdes</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_st_infinite_desc_exdes" spirit:order="360.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gtcom_in_core_usp</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtcom_in_core_usp" spirit:choiceRef="choice_pairs_6f00a734" spirit:order="361">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_mqdma</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_mqdma" spirit:order="361">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SRIOV_CAP_ENABLE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_CAP_ENABLE" spirit:order="362">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.SRIOV_CAP_ENABLE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ext_xvc_vsec_enable</spirit:name>
+      <spirit:displayName>Enable to add the PCIe XVC-VSEC to the Examlpe Design</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ext_xvc_vsec_enable" spirit:order="397.1">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.ext_xvc_vsec_enable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>acs_ext_cap_enable</spirit:name>
+      <spirit:displayName>ACS Ext Capability</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.acs_ext_cap_enable" spirit:order="397.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="398">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_type_mqdma" spirit:choiceRef="choice_list_8a9e69a3" spirit:order="399">DMA</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="400">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="401">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="402">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="403">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="404">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="405">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="406">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="407">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="408">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="409">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="410">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="411">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="412">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="413">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="414">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="415">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="416">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="417">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="418">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="419">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="420">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="421">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="422">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="423">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="424">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="425">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="426">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="427">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="428">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="429">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="430">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="431">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="432">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="433">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_type_mqdma" spirit:choiceRef="choice_list_57749bc8" spirit:order="434">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="435">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="436">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="437">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="438">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="439">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="440">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="441">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="442">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="443">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="444">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="445">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="446">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="447">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="448">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="449">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="450">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="451">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="452">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="453">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="454">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="455">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="456">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="457">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="458">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="459">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="460">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="461">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="462">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="463">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="464">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="465">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="466">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="467">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="468">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_type_mqdma" spirit:choiceRef="choice_list_57749bc8" spirit:order="469">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="470">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="471">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="472">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="473">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="474">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="475">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="371">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="372">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="373">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="374">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="375">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="376">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="377">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="378">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="379">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="380">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="381">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="381">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="382">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="383">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="384">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="385">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="386">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="387">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="388">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="389">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="390">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="391">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="392">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="393">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="394">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="395">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="396">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="363">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_type_mqdma" spirit:choiceRef="choice_list_57749bc8" spirit:order="364">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="365">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="366">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="367">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="368">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="369">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="370">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="371">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="372">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="373">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="374">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="375">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="376">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="377">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="378">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="379">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="380">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="381">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="381">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="382">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="383">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="384">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="385">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="386">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="387">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_64bit_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="388">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_64bit_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="389">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="390">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="391">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="392">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_enabled_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_type_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="393">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_type_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_prefetchable_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="394">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_scale_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="395">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_scale_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_size_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="396">128</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_size_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>copy_pf0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.copy_pf0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>copy_sriov_pf0</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.copy_sriov_pf0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6.5">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_scale" spirit:choiceRef="choice_list_fde36331" spirit:order="80">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="80">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="80">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_enabled</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_scale</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_scale" spirit:choiceRef="choice_list_d123c74c" spirit:order="80">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_expansion_rom_size</spirit:name>
+      <spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_type" spirit:choiceRef="choice_list_8a9e69a3" spirit:order="133">DMA</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_type" spirit:choiceRef="choice_list_57749bc8" spirit:order="133">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_type" spirit:choiceRef="choice_list_57749bc8" spirit:order="133">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_type" spirit:choiceRef="choice_list_57749bc8" spirit:order="133">DMA</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar0_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar1_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar2_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar3_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_64bit">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_prefetchable">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar4_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_enabled</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_enabled">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_type</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_64bit</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_prefetchable</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_size</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sriov_bar5_scale</spirit:name>
+      <spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_scale">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pcie_id_if</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_id_if" spirit:order="24.1">FALSE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_vendor_id_mqdma</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_vendor_id_mqdma" spirit:order="24.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_vendor_id_mqdma</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_vendor_id_mqdma" spirit:order="24.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_vendor_id_mqdma</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_vendor_id_mqdma" spirit:order="24.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_vendor_id_mqdma</spirit:name>
+      <spirit:displayName>Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_vendor_id_mqdma" spirit:order="24.3">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_DEVICE_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEVICE_ID_mqdma" spirit:order="25.2">9038</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_DEVICE_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_DEVICE_ID_mqdma" spirit:order="25.2">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_DEVICE_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_DEVICE_ID_mqdma" spirit:order="25.2">9038</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_DEVICE_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_DEVICE_ID_mqdma" spirit:order="25.3">9038</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_REVISION_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_REVISION_ID_mqdma" spirit:order="26.2">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_REVISION_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_REVISION_ID_mqdma" spirit:order="26.2">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_REVISION_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_REVISION_ID_mqdma" spirit:order="26.2">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_REVISION_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Revision Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_REVISION_ID_mqdma" spirit:order="26.3">00</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.2">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Subsystem Vendor Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.3">10EE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SUBSYSTEM_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SUBSYSTEM_ID_mqdma" spirit:order="28.2">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SUBSYSTEM_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_ID_mqdma" spirit:order="28.2">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SUBSYSTEM_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_ID_mqdma" spirit:order="28.2">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SUBSYSTEM_ID_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_ID_mqdma" spirit:order="28.3">0007</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.7">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_base_class_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_base_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_base_mqdma" spirit:order="186">05</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_base_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_sub_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_sub_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sub_class_interface_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_interface_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_interface_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_class_code_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_mqdma" spirit:order="190">058000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_base_class_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_base_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_base_mqdma" spirit:order="186">05</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_base_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_sub_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_sub_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_sub_class_interface_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_interface_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_interface_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_class_code_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_mqdma" spirit:order="190">058000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_base_class_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_base_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_base_mqdma" spirit:order="186">05</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_base_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_sub_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_sub_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_sub_class_interface_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_interface_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_interface_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_class_code_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_mqdma" spirit:order="190">058000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_base_class_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_base_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Base</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_base_mqdma" spirit:order="186">05</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_base_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_sub_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_sub_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_sub_class_interface_menu_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_interface_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_interface_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_class_code_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Class Code</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_mqdma" spirit:order="190">058000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_FIRST_VF_OFFSET" spirit:choiceRef="choice_list_ae9f88f6" spirit:order="122.5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_sriov_cap_ver</spirit:name>
+      <spirit:displayName>Pf0 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_cap_ver" spirit:order="120">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_fe1fb7c4" spirit:order="121">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf0 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK" spirit:order="122">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET" spirit:order="123">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf0 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID" spirit:order="124">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf0 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125">00000553</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_CAP_VER</spirit:name>
+      <spirit:displayName>Pf1 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_CAP_VER" spirit:order="126">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_CAP_VER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf1 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET" spirit:order="123.11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf1 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK" spirit:order="128">0001</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_FUNC_DEP_LINK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf1 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="131">00000553</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf1 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID" spirit:order="130">0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_VF_DEVICE_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_CAP_VER</spirit:name>
+      <spirit:displayName>Pf2 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_CAP_VER" spirit:order="126.2">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_CAP_VER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf2 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_FIRST_VF_OFFSET" spirit:order="123.2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf2 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_FUNC_DEP_LINK" spirit:order="122.2">0002</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_FUNC_DEP_LINK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf2 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125.2">00000553</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf2 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_VF_DEVICE_ID" spirit:order="124.2">0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_VF_DEVICE_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_CAP_INITIAL_VF</spirit:name>
+      <spirit:displayName>Pf3 Sriov Cap Initial Vf</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121.3">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_CAP_VER</spirit:name>
+      <spirit:displayName>Pf3 Sriov Cap Ver</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_CAP_VER" spirit:order="126.3">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_CAP_VER">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_FIRST_VF_OFFSET</spirit:name>
+      <spirit:displayName>Pf3 Sriov First Vf Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_FIRST_VF_OFFSET" spirit:order="123.3">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_FUNC_DEP_LINK</spirit:name>
+      <spirit:displayName>Pf3 Sriov Func Dep Link</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_FUNC_DEP_LINK" spirit:order="122.3">0003</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_FUNC_DEP_LINK">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
+      <spirit:displayName>Pf3 Sriov Supported Page Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125.3">00000553</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_SRIOV_VF_DEVICE_ID</spirit:name>
+      <spirit:displayName>Pf3 Sriov Vf Device Id</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_VF_DEVICE_ID" spirit:order="124.3">0000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_VF_DEVICE_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_ari_enabled</spirit:name>
+      <spirit:displayName>Pf0 Ari Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_ari_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="277">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_msix_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="214">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_msix_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="220">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_msix_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="215.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_msix_enabled_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Msix Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="215.3">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="215">000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="221">000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="220.2">000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Table Size</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="220.3">000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="216">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="222">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="216.2">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Table Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="216.3">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="218">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="224">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="224.2">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Pba Offset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="218.3">00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF0_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF1_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf1 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="225">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF2_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf2 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219.2">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PF3_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
+      <spirit:displayName>Pf3 Msix Cap Pba Bir</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219.3">BAR_0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MSI_X_OPTIONS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MSI_X_OPTIONS" spirit:choiceRef="choice_list_bea500ca" spirit:order="200.1">None</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.MSI_X_OPTIONS">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dsc_bypass_rd_out</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_rd_out" spirit:choiceRef="choice_list_47140c0d" spirit:order="76">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dsc_bypass_wr_out</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_wr_out" spirit:choiceRef="choice_list_47140c0d" spirit:order="77">0000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>num_queues</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.num_queues" spirit:order="59" spirit:minimum="1" spirit:maximum="2048" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_auto_rxeq</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_auto_rxeq" spirit:choiceRef="choice_list_bdd7203f" spirit:order="476">False</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_pcie_debug</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_pcie_debug" spirit:choiceRef="choice_list_bdd7203f" spirit:order="477">False</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axisten_if_enable_msg_route</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_enable_msg_route" spirit:order="478">27FFF</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_axi_mm_mqdma</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_mm_mqdma" spirit:order="479">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_mm_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>en_axi_st_mqdma</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_st_mqdma" spirit:order="480">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_st_mqdma">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_more_clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_more_clk" spirit:order="479">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_credits_cd</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_credits_cd" spirit:order="480">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_credits_ch</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_credits_ch" spirit:order="481">15</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>set_finite_credit</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.set_finite_credit" spirit:order="482">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_bram_pipeline</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_bram_pipeline" spirit:order="483">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_eq_synchronizer</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_eq_synchronizer" spirit:order="484">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_resource_reduction</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_resource_reduction" spirit:order="485">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_ats_enable</spirit:name>
+      <spirit:displayName>ATS Extended Capability Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_ats_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="486">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_pri_enable</spirit:name>
+      <spirit:displayName>Page Request Extended Capability Enable</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_pri_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="487">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>usplus_es1_seqnum_bypass</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.usplus_es1_seqnum_bypass" spirit:choiceRef="choice_list_7a7dde49" spirit:order="488">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>bridge_registers_offset_enable</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bridge_registers_offset_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="489">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_gen4</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_gen4" spirit:order="490">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>local_test</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.local_test" spirit:order="490.2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen4_eieos_0s7</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.gen4_eieos_0s7" spirit:order="491">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_s_axi_supports_narrow_burst</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.c_s_axi_supports_narrow_burst" spirit:order="492">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_ats_switch</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ats_switch" spirit:choiceRef="choice_list_e7c484ae" spirit:order="493">FALSE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_ats_switch_unique_bdf</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_ats_switch_unique_bdf" spirit:choiceRef="choice_list_8af5a703" spirit:order="493.1">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ctrl_skip_mask</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ctrl_skip_mask" spirit:order="494">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_ats_enabled</spirit:name>
+      <spirit:displayName>Pf0 Ats Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_ats_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="458">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_pri_enabled</spirit:name>
+      <spirit:displayName>Pf0 Pri Enabled</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_pri_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="459">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>aspm_support</spirit:name>
+      <spirit:displayName>ASPM Support</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.aspm_support" spirit:choiceRef="choice_list_ca005b72" spirit:order="460">No_ASPM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_aer_cap_ecrc_gen_and_check_capable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_aer_cap_ecrc_gen_and_check_capable" spirit:order="461">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>gen_pipe_debug</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_pipe_debug" spirit:choiceRef="choice_list_7a7dde49" spirit:order="462">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>soft_reset_en</spirit:name>
+      <spirit:displayName>DMA Bridge Reset</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.soft_reset_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="463">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>msi_rx_pin_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msi_rx_pin_en" spirit:choiceRef="choice_list_e7c484ae" spirit:order="464">FALSE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>msix_rx_pin_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_rx_pin_en" spirit:choiceRef="choice_list_e7c484ae" spirit:order="464.1">TRUE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>msix_rx_decode_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_rx_decode_en" spirit:choiceRef="choice_list_e7c484ae" spirit:order="464.2">FALSE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.msix_rx_decode_en">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>intx_rx_pin_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.intx_rx_pin_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="464.3">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>msix_type</spirit:name>
+      <spirit:displayName>MSI-X Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_type" spirit:choiceRef="choice_list_38306dd1" spirit:order="465">HARD</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>runbit_fix</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.runbit_fix" spirit:order="495">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>axsize_byte_access_en</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axsize_byte_access_en" spirit:order="495.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_lane_reversal</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_lane_reversal" spirit:order="496">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_mark_debug</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_mark_debug" spirit:choiceRef="choice_list_7a7dde49" spirit:order="497">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>master_cal_only</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.master_cal_only" spirit:choiceRef="choice_list_7a7dde49" spirit:order="498">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_multi_pcie</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_multi_pcie" spirit:choiceRef="choice_list_7a7dde49" spirit:order="499">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>rbar_enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rbar_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="500">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF0</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="501">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF1</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="502">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF2</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="503">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_num</spirit:name>
+      <spirit:displayName>Number of Resizable BARs for PF3</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="504">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar0_index</spirit:name>
+      <spirit:displayName>PF0 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_index" spirit:order="505">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar1_index</spirit:name>
+      <spirit:displayName>PF0 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_index" spirit:order="506">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar2_index</spirit:name>
+      <spirit:displayName>PF0 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_index" spirit:order="507">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar3_index</spirit:name>
+      <spirit:displayName>PF0 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_index" spirit:order="508">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar4_index</spirit:name>
+      <spirit:displayName>PF0 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_index" spirit:order="509">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_bar5_index</spirit:name>
+      <spirit:displayName>PF0 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_index" spirit:order="510">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar0_index</spirit:name>
+      <spirit:displayName>PF0 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_index" spirit:order="511">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar1_index</spirit:name>
+      <spirit:displayName>PF1 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_index" spirit:order="512">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar2_index</spirit:name>
+      <spirit:displayName>PF1 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_index" spirit:order="513">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar3_index</spirit:name>
+      <spirit:displayName>PF1 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_index" spirit:order="514">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar4_index</spirit:name>
+      <spirit:displayName>PF1 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_index" spirit:order="515">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_bar5_index</spirit:name>
+      <spirit:displayName>PF1 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_index" spirit:order="516">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar0_index</spirit:name>
+      <spirit:displayName>PF2 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_index" spirit:order="517">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar1_index</spirit:name>
+      <spirit:displayName>PF2 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_index" spirit:order="518">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar2_index</spirit:name>
+      <spirit:displayName>PF2 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_index" spirit:order="519">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar3_index</spirit:name>
+      <spirit:displayName>PF2 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_index" spirit:order="520">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar4_index</spirit:name>
+      <spirit:displayName>PF2 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_index" spirit:order="521">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_bar5_index</spirit:name>
+      <spirit:displayName>PF2 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_index" spirit:order="522">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar0_index</spirit:name>
+      <spirit:displayName>PF3 BAR0 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_index" spirit:order="523">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar1_index</spirit:name>
+      <spirit:displayName>PF3 BAR1 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_index" spirit:order="524">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar2_index</spirit:name>
+      <spirit:displayName>PF3 BAR2 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_index" spirit:order="525">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar3_index</spirit:name>
+      <spirit:displayName>PF3 BAR3 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_index" spirit:order="526">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar4_index</spirit:name>
+      <spirit:displayName>PF3 BAR4 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_index" spirit:order="527">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_bar5_index</spirit:name>
+      <spirit:displayName>PF3 BAR5 index</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_index" spirit:order="528">7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar0" spirit:order="529">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar1" spirit:order="530">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar2" spirit:order="531">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar3" spirit:order="532">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar4" spirit:order="533">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf0_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF0 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar5" spirit:order="534">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar0" spirit:order="535">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar1" spirit:order="536">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar2" spirit:order="537">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar3" spirit:order="538">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar4" spirit:order="539">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf1_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF1 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar5" spirit:order="540">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar0" spirit:order="541">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar1" spirit:order="542">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar2" spirit:order="543">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar3" spirit:order="544">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar4" spirit:order="545">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf2_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF2 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar5" spirit:order="546">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar0</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR0</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar0" spirit:order="547">0x00000000fff0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar1</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR1</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar1" spirit:order="548">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar2</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR2</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar2" spirit:order="549">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar3</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR3</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar3" spirit:order="550">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar4</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR4</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar4" spirit:order="551">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>pf3_rbar_cap_bar5</spirit:name>
+      <spirit:displayName>PF3 RBAR CAP BAR5</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar5" spirit:order="552">0x000000000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>mpsoc_pl_rp_enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.mpsoc_pl_rp_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="553">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>c_smmu_en</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_smmu_en" spirit:choiceRef="choice_list_8af5a703" spirit:order="555">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_slave_read_64os</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_slave_read_64os" spirit:choiceRef="choice_list_7a7dde49" spirit:order="556">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>m_axib_num_write_scale</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.m_axib_num_write_scale" spirit:choiceRef="choice_list_8aad6ae4" spirit:order="556.1">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_gt_loc</spirit:name>
+      <spirit:displayName>Disable GT loc constraint delivery</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_gt_loc" spirit:choiceRef="choice_list_7a7dde49" spirit:order="557">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_standard_interfaces</spirit:name>
+      <spirit:displayName>use standard interfaces for IPI design</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_standard_interfaces" spirit:choiceRef="choice_list_7a7dde49" spirit:order="558">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>dma_2rp</spirit:name>
+      <spirit:displayName>Truncate ports for 2RP DMA design</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dma_2rp" spirit:choiceRef="choice_list_7a7dde49" spirit:order="559">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>disable_user_clock_root</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_user_clock_root" spirit:order="560">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>flr_enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.flr_enable" spirit:order="561">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>enable_epyc_chipset_fix</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_epyc_chipset_fix" spirit:order="562">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>usrint_expn</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.usrint_expn" spirit:order="563">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>shell_bridge</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.shell_bridge" spirit:order="564">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>msix_pcie_internal</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.msix_pcie_internal" spirit:order="565">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>broadcom_sbr_wa</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.broadcom_sbr_wa" spirit:order="566">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>tl_tx_mux_strict_priority</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_tx_mux_strict_priority" spirit:order="567">false</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>DMA/Bridge Subsystem for PCI Express</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>8</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TLAST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_CACHE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_LOCK" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_CACHE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_LOCK" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TLAST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TKEEP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TLAST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_REGION" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.PROTOCOL" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF2_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF3_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axi_data_width" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.coreclk_freq" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_device_id" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pl_link_cap_max_link_speed" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pl_link_cap_max_link_width" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_axi_intf_mm" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="c9c86e51"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="3b0b31fa"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="87cd4491"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1465500e"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="5e10ebf9"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="264ec767"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="558eda95"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci
new file mode 100644
index 0000000..c067a3c
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci
@@ -0,0 +1,330 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>zq_calib_mem</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     5.931282 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">zq_calib_mem.mif</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../../../../coe/pr_zq.coe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">zq_calib_mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;clka&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;ena&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;wea&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;addra&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;dina&quot;:{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;},&quot;douta&quot;:{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;}},&quot;interfaces&quot;:{&quot;CLK.ACLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s_aresetn&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.000&quot;},{&quot;val
+ue_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;RST.ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;},{&quot;value_src&quot;:&quot;constant&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;immediate&quot;}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;user&quot;}]},&quot;port_maps&quot;:{}},&quot;BRAM_PORTA&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:bram:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:bram_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;MEM_SIZE&quot;:[{&quot;value&quot;:&quot;8192&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permissio
+n&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MEM_ECC&quot;:[{&quot;value&quot;:&quot;NONE&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;MASTER_TYPE&quot;:[{&quot;value&quot;:&quot;OTHER&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}],&quot;READ_LATENCY&quot;:[{&quot;value&quot;:&quot;1&quot;},{&quot;value_src&quot;:&quot;default&quot;},{&quot;value_permission&quot;:&quot;user&quot;},{&quot;resolve_type&quot;:&quot;generated&quot;}]},&quot;port_maps&quot;:{&quot;ADDR&quot;:{&quot;physical_name&quot;:&quot;addra&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;CLK&quot;:{&quot;physical_name&quot;:&quot;clka&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DIN&quot;:{&quot;physical_name&quot;:&quot;dina&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;DOUT&quot;:{&quot;physical_name&quot;:&quot;douta&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;EN&quot;:{&quot;physical_name&quot;:&quot;ena&quot;,&quot;physical_lef
+t&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;},&quot;WE&quot;:{&quot;physical_name&quot;:&quot;wea&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;}}}}}}"/>
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+</spirit:design>
diff --git a/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml
new file mode 100644
index 0000000..5be6cc5
--- /dev/null
+++ b/projects/U200/U200.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xml
@@ -0,0 +1,4185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>zq_calib_mem</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>CLK.ACLK</spirit:name>
+      <spirit:displayName>ACLK</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Clock Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
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+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST.ARESETN</spirit:name>
+      <spirit:displayName>ARESETN</spirit:displayName>
+      <spirit:description>AXI4 Interconnect Reset Input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXI_SLAVE</spirit:displayName>
+      <spirit:description>AXI_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXILite_SLAVE_S_AXI</spirit:name>
+      <spirit:displayName>AXILite_SLAVE</spirit:displayName>
+      <spirit:description>AXILite_SLAVE</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXILite_SLAVE_S_AXI" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_AXI_TYPE&apos;)))= 0))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTA</spirit:name>
+      <spirit:displayName>BRAM_PORTA</spirit:displayName>
+      <spirit:description>BRAM_PORTA</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addra</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clka</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dina</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>douta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ena</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rsta</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>wea</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTA" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;))=0">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>BRAM_PORTB</spirit:name>
+      <spirit:displayName>BRAM_PORTB</spirit:displayName>
+      <spirit:description>BRAM_PORTB</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>addrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DIN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dinb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DOUT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>doutb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>enb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rstb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>web</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>MEM_SIZE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MEM_ECC</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MASTER_TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_LATENCY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.BRAM_PORTB" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)))=0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 0) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)))!= 3))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_1</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Mem0</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>memory</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_1.MEM0.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clka</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clka" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rsta</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rsta" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_RSTA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ena</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ena" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_ENA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>regcea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.regcea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_HAS_REGCEA&apos;)) != 0) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>wea</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">0</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wea" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>addra</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ADDRA_WIDTH&apos;))-1">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addra" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1)">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dina</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WRITE_WIDTH_A&apos;))-1">63</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dina" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 3) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_MEM_TYPE&apos;)) != 4) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_TYPE&apos;)) != 1))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_arready</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_rid</spirit:name>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_rready</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_injectsbiterr</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>s_axi_injectdbiterr</spirit:name>
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+          <spirit:direction>in</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:direction>out</spirit:direction>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>C_XDEVICEFAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtexuplus</spirit:value>
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+        <spirit:name>C_AXI_TYPE</spirit:name>
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+        <spirit:name>C_USE_BRAM_BLOCK</spirit:name>
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+        <spirit:name>C_ENABLE_32BIT_ADDRESS</spirit:name>
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+        <spirit:name>C_CTRL_ECC_ALGO</spirit:name>
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+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ALGORITHM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRIM_TYPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_LOAD_INIT_FILE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE_NAME</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE_NAME">zq_calib_mem.mif</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INIT_FILE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INIT_FILE">zq_calib_mem.mem</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEFAULT_DATA</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITA_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEA</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_A</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_A">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRA_WIDTH">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_RSTB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RST_PRIORITY_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RSTRAM_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INITB_VAL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_ENB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_REGCEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_BYTE_WEB</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WEB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_WRITE_MODE_B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_WIDTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_WIDTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_WRITE_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_WRITE_DEPTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_DEPTH_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_DEPTH_B">64</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ADDRB_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDRB_WIDTH">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MEM_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_MUX_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MUX_PIPELINE_STAGES</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_INPUT_REGS_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_SOFTECC_OUTPUT_REGS_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SOFTECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_ECC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_ECC">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_ECC_PIPE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_A</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_READ_LATENCY_B</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_INJECTERR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SIM_COLLISION_CHECK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_COMMON_CLK</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_COLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_URAM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_URAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRA_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_RDADDRB_CHG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_DEEPSLEEP_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SHUTDOWN_PIN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_EN_SAFETY_CKT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DISABLE_WARN_BHV_RANGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_36K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_COUNT_18K_BRAM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_EST_POWER_SUMMARY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     5.931282 mW</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_0e6ad450</spirit:name>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>4</spirit:enumeration>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>16</spirit:enumeration>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
+      <spirit:enumeration>128</spirit:enumeration>
+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
+      <spirit:enumeration>2048</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5453281d</spirit:name>
+      <spirit:enumeration>Native</spirit:enumeration>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_5f2d7eda</spirit:name>
+      <spirit:enumeration>16kx1</spirit:enumeration>
+      <spirit:enumeration>8kx2</spirit:enumeration>
+      <spirit:enumeration>4kx4</spirit:enumeration>
+      <spirit:enumeration>2kx9</spirit:enumeration>
+      <spirit:enumeration>1kx18</spirit:enumeration>
+      <spirit:enumeration>512x36</spirit:enumeration>
+      <spirit:enumeration>256x72</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_6e3ded9c</spirit:name>
+      <spirit:enumeration>0</spirit:enumeration>
+      <spirit:enumeration>1</spirit:enumeration>
+      <spirit:enumeration>2</spirit:enumeration>
+      <spirit:enumeration>3</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_89a27b2f</spirit:name>
+      <spirit:enumeration>8</spirit:enumeration>
+      <spirit:enumeration>9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_c8df20f0</spirit:name>
+      <spirit:enumeration>NONE</spirit:enumeration>
+      <spirit:enumeration>ECCH32-7</spirit:enumeration>
+      <spirit:enumeration>ECCH64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO32-7</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO64-8</spirit:enumeration>
+      <spirit:enumeration>ECCHSIAO128-9</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e9412e2c</spirit:name>
+      <spirit:enumeration>BRAM</spirit:enumeration>
+      <spirit:enumeration>URAM</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_07c32259</spirit:name>
+      <spirit:enumeration spirit:text="Write First">WRITE_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="Read First">READ_FIRST</spirit:enumeration>
+      <spirit:enumeration spirit:text="No Change">NO_CHANGE</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_27c66b0d</spirit:name>
+      <spirit:enumeration spirit:text="Stand Alone">Stand_Alone</spirit:enumeration>
+      <spirit:enumeration spirit:text="BRAM Controller">BRAM_Controller</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2adcaf32</spirit:name>
+      <spirit:enumeration spirit:text="Synchronous">SYNC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Asynchronous">ASYNC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_2d73cdeb</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENB Pin">Use_ENB_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3949ecbf</spirit:name>
+      <spirit:enumeration spirit:text="Always Enabled">Always_Enabled</spirit:enumeration>
+      <spirit:enumeration spirit:text="Use ENA Pin">Use_ENA_Pin</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3e9ce7ae</spirit:name>
+      <spirit:enumeration spirit:text="Minimum Area">Minimum_Area</spirit:enumeration>
+      <spirit:enumeration spirit:text="Low Power">Low_Power</spirit:enumeration>
+      <spirit:enumeration spirit:text="Fixed Primitives">Fixed_Primitives</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_44b9b2d1</spirit:name>
+      <spirit:enumeration spirit:text="All">ALL</spirit:enumeration>
+      <spirit:enumeration spirit:text="None">NONE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Warning Only">WARNING_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Generate X-Only">GENERATE_X_ONLY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_63de7f78</spirit:name>
+      <spirit:enumeration spirit:text="CE (Latch or Register Enable)">CE</spirit:enumeration>
+      <spirit:enumeration spirit:text="SR (Set Reset)">SR</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_716d2fba</spirit:name>
+      <spirit:enumeration spirit:text="Single Bit Error Injection">Single_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Double Bit Error Injection">Double_Bit_Error_Injection</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single and Double Bit Error Injection">Single_and_Double_Bit_Error_Injection</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_b91edaa2</spirit:name>
+      <spirit:enumeration spirit:text="Memory Slave">Memory_Slave</spirit:enumeration>
+      <spirit:enumeration spirit:text="Peripheral Slave">Peripheral_Slave</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c1013cbe</spirit:name>
+      <spirit:enumeration spirit:text="No ECC">No_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="Soft ECC">Soft_ECC</spirit:enumeration>
+      <spirit:enumeration spirit:text="BuiltIn ECC">BuiltIn_ECC</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e4c322cb</spirit:name>
+      <spirit:enumeration spirit:text="AXI4">AXI4_Full</spirit:enumeration>
+      <spirit:enumeration spirit:text="AXI4 Lite">AXI4_Lite</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e932d933</spirit:name>
+      <spirit:enumeration spirit:text="Single Port RAM">Single_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Simple Dual Port RAM">Simple_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="True Dual Port RAM">True_Dual_Port_RAM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Single Port ROM">Single_Port_ROM</spirit:enumeration>
+      <spirit:enumeration spirit:text="Dual Port ROM">Dual_Port_ROM</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">zq_calib_mem</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Interface_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Interface_Type" spirit:choiceRef="choice_list_5453281d" spirit:order="2">Native</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Interface_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Type" spirit:choiceRef="choice_pairs_e4c322cb" spirit:order="4">AXI4_Full</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_Slave_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_Slave_Type" spirit:choiceRef="choice_pairs_b91edaa2" spirit:order="5">Memory_Slave</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_Slave_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_AXI_ID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_AXI_ID" spirit:order="6">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_AXI_ID">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_ID_Width</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_ID_Width" spirit:order="7" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.AXI_ID_Width">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Memory_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Memory_Type" spirit:choiceRef="choice_pairs_e932d933" spirit:order="8">Single_Port_RAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Memory_Type">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_type_to_Implement</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_type_to_Implement" spirit:choiceRef="choice_list_e9412e2c" spirit:order="8.001">BRAM</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PRIM_type_to_Implement">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_32bit_Address</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_32bit_Address" spirit:order="9">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_32bit_Address">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ecctype</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecctype" spirit:choiceRef="choice_pairs_c1013cbe" spirit:order="10">No_ECC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ecctype">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ECC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECC" spirit:order="11">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.ECC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.softecc" spirit:order="12">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SLEEP_PIN" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SLEEP_PIN">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_DEEPSLEEP_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_DEEPSLEEP_PIN" spirit:order="14">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_DEEPSLEEP_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SHUTDOWN_PIN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SHUTDOWN_PIN" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SHUTDOWN_PIN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_ECC_PIPE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_ECC_PIPE" spirit:order="16">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_ECC_PIPE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_A" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RD_ADDR_CHNG_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RD_ADDR_CHNG_B" spirit:order="18">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RD_ADDR_CHNG_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Error_Injection_Pins</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Error_Injection_Pins" spirit:order="13">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Error_Injection_Pins">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Error_Injection_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Error_Injection_Type" spirit:choiceRef="choice_pairs_716d2fba" spirit:order="14">Single_Bit_Error_Injection</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Error_Injection_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_Byte_Write_Enable</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_Byte_Write_Enable">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Byte_Size</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Algorithm</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Algorithm" spirit:choiceRef="choice_pairs_3e9ce7ae" spirit:order="20">Minimum_Area</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Algorithm">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Primitive</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Primitive" spirit:choiceRef="choice_list_5f2d7eda" spirit:order="21">8kx2</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Primitive">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Assume_Synchronous_Clk</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Assume_Synchronous_Clk" spirit:order="17">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Assume_Synchronous_Clk">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Depth_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Depth_A" spirit:order="19" spirit:minimum="2" spirit:maximum="1048576" spirit:rangeType="long">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Depth_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_0e6ad450" spirit:order="22">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_A" spirit:choiceRef="choice_pairs_3949ecbf" spirit:order="24">Use_ENA_Pin</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_A">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Write_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="25">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Write_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Read_Width_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_0e6ad450" spirit:order="26">64</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Read_Width_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Operating_Mode_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Operating_Mode_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_B" spirit:choiceRef="choice_pairs_2d73cdeb" spirit:order="28">Always_Enabled</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Enable_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" spirit:order="29">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Primitives">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortA_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortA_Output_of_Memory_Core" spirit:order="30">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortA_Output_of_Memory_Core">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEA_Pin" spirit:order="31">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEA_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Primitives</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" spirit:order="32">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Primitives">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Register_PortB_Output_of_Memory_Core</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Register_PortB_Output_of_Memory_Core" spirit:order="33">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Register_PortB_Output_of_Memory_Core">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_REGCEB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_REGCEB_Pin" spirit:order="34">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_REGCEB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_porta_input_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_porta_input_of_softecc" spirit:order="35">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_porta_input_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>register_portb_output_of_softecc</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.register_portb_output_of_softecc" spirit:order="36">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.register_portb_output_of_softecc">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Pipeline_Stages</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Pipeline_Stages" spirit:choiceRef="choice_list_6e3ded9c" spirit:order="37">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Pipeline_Stages">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Load_Init_File</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Load_Init_File" spirit:order="38">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Load_Init_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Coe_File</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Coe_File" spirit:order="39">../../../../coe/pr_zq.coe</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Coe_File">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Fill_Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Fill_Remaining_Memory_Locations" spirit:order="40">true</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Fill_Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Remaining_Memory_Locations</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Remaining_Memory_Locations" spirit:order="41">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Remaining_Memory_Locations">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTA_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTA_Pin" spirit:order="42">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTA_Pin">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_A</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_A" spirit:order="43">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_A" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="44">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_A</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_A" spirit:order="45">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Use_RSTB_Pin</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_RSTB_Pin" spirit:order="46">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Use_RSTB_Pin">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Memory_Latch_B</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Memory_Latch_B" spirit:order="47">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Memory_Latch_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Priority_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Priority_B" spirit:choiceRef="choice_pairs_63de7f78" spirit:order="48">CE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Priority_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Output_Reset_Value_B</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Output_Reset_Value_B" spirit:order="49">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Output_Reset_Value_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Reset_Type</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Reset_Type" spirit:choiceRef="choice_pairs_2adcaf32" spirit:order="50">SYNC</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Reset_Type">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Additional_Inputs_for_Power_Estimation</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Additional_Inputs_for_Power_Estimation" spirit:order="51">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Additional_Inputs_for_Power_Estimation">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Clock" spirit:order="52" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Write_Rate" spirit:order="53" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">50</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Clock</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Clock" spirit:order="54" spirit:minimum="0" spirit:maximum="800" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Clock">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Write_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Write_Rate" spirit:order="55" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Write_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_A_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_A_Enable_Rate" spirit:order="56" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">100</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_A_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Port_B_Enable_Rate</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Port_B_Enable_Rate" spirit:order="57" spirit:minimum="0" spirit:maximum="100" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Port_B_Enable_Rate">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Collision_Warnings</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Collision_Warnings" spirit:choiceRef="choice_pairs_44b9b2d1" spirit:order="58">ALL</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Collision_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Collision_Warnings" spirit:order="59">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Collision_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Disable_Out_of_Range_Warnings</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Disable_Out_of_Range_Warnings" spirit:order="60">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Disable_Out_of_Range_Warnings">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>use_bram_block</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_bram_block" spirit:choiceRef="choice_pairs_27c66b0d" spirit:order="3">Stand_Alone</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.use_bram_block">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MEM_FILE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MEM_FILE" spirit:order="61">no_mem_loaded</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.MEM_FILE">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CTRL_ECC_ALGO</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CTRL_ECC_ALGO" spirit:choiceRef="choice_list_c8df20f0" spirit:order="62">NONE</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.CTRL_ECC_ALGO">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EN_SAFETY_CKT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.EN_SAFETY_CKT" spirit:order="63">false</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.EN_SAFETY_CKT">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_A</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_A" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_A">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_LATENCY_B</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.READ_LATENCY_B" spirit:order="63" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.READ_LATENCY_B">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Block Memory Generator</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto"/>
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diff --git a/projects/U200/U200.xpr b/projects/U200/U200.xpr
new file mode 100644
index 0000000..b2488d2
--- /dev/null
+++ b/projects/U200/U200.xpr
@@ -0,0 +1,947 @@
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+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
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+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design" EnableStepBool="1"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="axis_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcu200-fsgd2104-2-e" ConstrsSet="axis_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_clock_converter_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../home/ataberk/C:/Users/hasan/git/SoftMC_DDR4/projects/U200/U200.srcs/utils_1/imports/axis_clock_converter_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="phy_ddr4_impl_1" Type="Ft2:EntireDesign" Part="xcu200-fsgd2104-2-e" ConstrsSet="phy_ddr4" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="phy_ddr4_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../home/ataberk/C:/Users/aolgu/Desktop/SoftMC_DDR4/projects/U200/U200.srcs/utils_1/imports/phy_ddr4_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="rdback_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcu200-fsgd2104-2-e" ConstrsSet="rdback_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rdback_fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../home/ataberk/C:/Users/aolgu/Desktop/SoftMC_DDR4/projects/U200/U200.srcs/utils_1/imports/rdback_fifo_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="phy_ddr4_udimm_impl_1" Type="Ft2:EntireDesign" Part="xcu200-fsgd2104-2-e" ConstrsSet="phy_ddr4_udimm" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="phy_ddr4_udimm_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../home/ataberk/C:/Users/aolgu/Desktop/SoftMC_DDR4/projects/U200/U200.srcs/utils_1/imports/phy_ddr4_udimm_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="phy_rdimm_x8_dual_impl_1" Type="Ft2:EntireDesign" Part="xcu200-fsgd2104-2-e" ConstrsSet="phy_rdimm_x8_dual" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="phy_rdimm_x8_dual_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../home/ataberk/C:/Users/aolgu/Desktop/SoftMC_DDR4/projects/U200/U200.srcs/utils_1/imports/phy_rdimm_x8_dual_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="xdma_impl_1" Type="Ft2:EntireDesign" Part="xcu200-fsgd2104-2-e" ConstrsSet="xdma" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="xdma_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../../home/ataberk/C:/Users/aolgu/Desktop/SoftMC_DDR4/projects/U200/U200.srcs/utils_1/imports/xdma_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="0"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ANY"/>
+    <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="1"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="0"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ANY"/>
+    <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="2"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="0"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ANY"/>
+    <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="25"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="0"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ANY"/>
+    <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="26"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="0"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ANY"/>
+    <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="3"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="0"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ANY"/>
+    <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="4"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/projects/U200/alveo-u200-master.xdc b/projects/U200/alveo-u200-master.xdc
new file mode 100644
index 0000000..d75a057
--- /dev/null
+++ b/projects/U200/alveo-u200-master.xdc
@@ -0,0 +1,1041 @@
+############################################################################
+##DISCLAIMER:
+##  XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE,
+##  SCHEMATIC, AND/OR SPECIFICATION (THE “DOCUMENTATION”)TO YOU SOLELY
+##  FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX
+##  HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH,
+##  DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM
+##  OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC,
+##  MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE
+##  PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY
+##  LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION.
+##  XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE
+##  DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO
+##  OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION,
+##  OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY
+##  DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR
+##  ASSISTANCETHAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE
+##  DOCUMENTATION.
+##  THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF
+##  ANY OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY
+##  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+##  NONINFRINGEMENT STATUTORY, REGARDING THEDOCUMENTATION, INCLUDING
+##  ANY WARRANTIES OF KIND.
+##  XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR THE
+##  DOCUMENTATION. INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING
+##  FROM YOUR USE OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR
+##  INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS,
+##  ARISING FROM YOUR USE OF THE DOCUMENTATION.
+##
+##
+##   AU200/250 - Master XDC
+##
+##       FPGA PIN reference are with respect to the U200 FPGA Bank naming
+##            The FPGA A200 and A250 are pin for pin compatible devices.
+##               +----------------+---------------+---------------+---------------+
+##               | A250 Bank      | A200 Bank     | Usage         | Voltage       |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 61,62,63  | Bank 40,41,42 | DDR4 C0 Int.  | 1.2V          |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 65,66,67  | Bank 65,66,67 | DDR4 C1 Int.  | 1.2V          |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 69,70,71  | Bank 46,47,48 | DDR4 C2 Int.  | 1.2V          |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 72,73,74  | Bank 70,71,72 | DDR4 C3 Int.  | 1.2V          |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 64        | Bank 64       | Misc. IO      | 1.2V          |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 231       | Bank 231      | QSFP0         | NA            |
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 230       | Bank 230      | QSFP1         | NA            |  
+##               +----------------+---------------+---------------+---------------+ 
+##               | Bank 224-227   | Bank 224-227  | PCIE          | NA            |  
+##               +----------------+---------------+---------------+---------------+ 
+##
+##
+##   Key Notes:
+##       1) Power warning constraint set to warn user if design exceeds 160 Watts
+##       3) Refer to XAPP1321 for DDR4 Self refresh and fast calibration.
+##
+##   Clock Trees
+##
+##    1) SI570 - SiLabs 570BAB000544DG @ 156.250Mhz Programmable Oscillator (Re-programming I2C access via Bank 64 I2C )
+##
+##      - OUT---> SI570_OUTPUT_P/SI570_OUTPUT_N @ 156.250Mhz LVDS
+##           |
+##           |--> SI53340-B-GM --> OUT0  USER_SI570_CLOCK_P/USER_SI570_CLOCK_N 156.250Mhz - General Perpose System Clock.
+##                             |   PINS: IO_L12P_T1U_N10_GC_64_AU19/IO_L12N_T1U_N11_GC_64_AV19
+##                             |
+##                             |-> OUT1  Not Connected
+##                             |   PINS: NA
+##                             |
+##                             |-> OUT2  MGT_SI570_CLOCK0_C_P/MGT_SI570_CLOCK0_C_N 156.250Mhz - QSFP0 REFCLK0
+##                             |   PINS: MGTREFCLK0P_231_M11/MGTREFCLK0N_231_M10
+##                             |
+##                             |-> OUT3  MGT_SI570_CLOCK1_C_P/MGT_SI570_CLOCK1_C_N 156.250Mhz - QSFP0 REFCLK1
+##                                 PINS: MGTREFCLK0P_230_T11/MGTREFCLK0N_230_T10
+##
+##    2) SI335A - SiLabs SI5335A-B06201-GM Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP0 REFCLK1
+##
+##      - FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups)
+##                                     FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS
+##                PINS: "QSFP0_FS[0]"         - IO_L10P_T1U_N6_QBC_AD4P_64_AT20
+##                PINS: "QSFP0_FS[1]"         - IO_L9N_T1L_N5_AD12N_64_AU22
+##
+##      - RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. 
+##                PINS: "QSFP0_RECLK_RESET"   - IO_L9P_T1L_N4_AD12P_64_AT22
+##
+##      - OUT0--> SYSCLK_300_P/SYSCLK_300_N @ 300.0000Mhz to 1-to-4 Clock buffer (Fixed and Unchanged by FS[1:0])
+##           |
+##           |--> SI53340-B-GM --> OUT0  SYSCLK0_300_P/SYSCLK0_300_N 300.000Mhz - System Clock for first DDR4 MIG interface
+##                             |   PINS: IO_L13P_T2L_N0_GC_QBC_63_AY37/IO_L13N_T2L_N1_GC_QBC_63_AY38
+##                             |
+##                             |-> OUT1  SYSCLK1_300_P/SYSCLK1_300_N 300.000Mhz - System Clock for second DDR4 MIG interface.
+##                             |   PINS: IO_L11P_T1U_N8_GC_64_AW20/IO_L11N_T1U_N9_GC_64_AW19
+##                             |
+##                             |-> OUT2  SYSCLK2_300_P/SYSCLK2_300_N 300.000Mhz - System Clock for third DDR4 MIG interface.
+##                             |   PINS: IO_L13P_T2L_N0_GC_QBC_70_F32/IO_L13N_T2L_N1_GC_QBC_70_E32
+##                             |
+##                             |-> OUT3  SYSCLK3_300_P/SYSCLK3_300_N 300.000Mhz - System Clock for fourth DDR4 MIG interface.
+##                                 PINS: IO_L13P_T2L_N0_GC_QBC_72_J16/IO_L13N_T2L_N1_GC_QBC_72_H16
+##
+##
+##      - OUT1--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 161.1328125Mhz (Selectable based on state of FS[1:0])
+##                PINS: MGTREFCLK1P_231_K11/MGTREFCLK1N_231_K10
+##
+##      - OUT2--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 90.0000Mhz (Fixed and Unchanged by FS[1:0])
+##                PINS: Not Connected
+##
+##      - OUT3--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 33.0000Mhz (Fixed and Unchanged by FS[1:0])
+##                PINS: Not Connected
+##
+##    3) SI335A - SiLabs SI5335A-B06201-GM Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP1 REFCLK1
+##
+##      - FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups)
+##                                     FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS
+##                PINS: "QSFP1_FS[0]"         - IO_L8P_T1L_N2_AD5P_64_AR22
+##                PINS: "QSFP1_FS[1]"         - IO_L7N_T1L_N1_QBC_AD13N_64_AU20
+##
+##      - RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. 
+##                PINS: "QSFP1_RECLK_RESET"   - IO_L8N_T1L_N3_AD5N_64_AR21
+##
+##      - OUT0--> 300.0000Mhz (Fixed and Unchanged by FS[1:0])
+##                PINS: Not Connected
+##
+##      - OUT1--> QSFP1_CLOCK_P/QSFP1_CLOCK_N @ 161.1328125Mhz (Selectable based on state of FS[1:0])
+##                PINS: MGTREFCLK1P_230_P11/MGTREFCLK1N_230_P10
+##
+##      - OUT2--> 90.0000Mhz (Fixed and Unchanged by FS[1:0])
+##                PINS: Not Connected
+##
+##      - OUT3--> 33.0000Mhz (Fixed and Unchanged by FS[1:0])
+##                PINS: Not Connected
+##
+##   4) PCIE Fingers PEX_REFCLK_P/PEX_REFCLK_P 100.000Mhz
+##           PINS: MGTREFCLK0P_226_AM11/MGTREFCLK0N_226_AM10
+##
+##  Revision 1.00 - Intial Release for AU200/250
+##  Revision 2.00 - Updated XDC with card details.
+##  Revision 2.01 - Fixed modified QSFP1 IO Standards from POD12_DCI to LVCMOS18
+##                  Added Configuration Constraints
+##  Revision 2.02 - Fixed Bank 64 IOstandards from LVCMOS18 to LVCMOS12.
+##
+#################################################################################
+# Bitstream Generation for QSPI                              
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable    [current_design]                  ;# Golden image is the fall back image if  new bitstream is corrupted.    
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design] 
+#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0          [current_design]                 ;# Customer can try but may not be reliable over all conditions.
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]  
+set_property BITSTREAM.GENERAL.COMPRESS TRUE           [current_design]  
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B         [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes       [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
+
+#
+# Power Constraint to warn User if Design will possibly be over cards power limit, this assume the 2x4 PCIe AUX power is connected to the board.
+#
+set_operating_conditions -design_power_budget 160
+#
+# LVDS Input SYSTEM CLOCKS for Memory Interfaces
+#
+set_property -dict {PACKAGE_PIN AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK0_300_N    ]; # Bank 42 VCCO - VCC1V2 Net "SYSCLK0_300_N" - IO_L13N_T2L_N1_GC_QBC_42
+set_property -dict {PACKAGE_PIN AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK0_300_P    ]; # Bank 42 VCCO - VCC1V2 Net "SYSCLK0_300_P" - IO_L13P_T2L_N0_GC_QBC_42
+set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVDS           } [get_ports SYSCLK1_300_N    ]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_N" - IO_L11N_T1U_N9_GC_64
+set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVDS           } [get_ports SYSCLK1_300_P    ]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_P" - IO_L11P_T1U_N8_GC_64
+set_property -dict {PACKAGE_PIN E32  IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK2_300_N    ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_N" - IO_L13N_T2L_N1_GC_QBC_47
+set_property -dict {PACKAGE_PIN F32  IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK2_300_P    ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_P" - IO_L13P_T2L_N0_GC_QBC_47
+set_property -dict {PACKAGE_PIN H16  IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK3_300_N    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_N" - IO_L13N_T2L_N1_GC_QBC_70
+set_property -dict {PACKAGE_PIN J16  IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK3_300_P    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_P" - IO_L13P_T2L_N0_GC_QBC_70
+#
+# LVDS Input SYSTEM CLOCKS (1.8V bank 64) General Purpose
+#
+set_property -dict {PACKAGE_PIN AV19 IOSTANDARD LVDS           } [get_ports USER_SI570_CLOCK_N]; # Bank 64 VCCO - VCC1V2 Net "USER_SI570_CLOCK_N"  - IO_L12N_T1U_N11_GC_64
+set_property -dict {PACKAGE_PIN AU19 IOSTANDARD LVDS           } [get_ports USER_SI570_CLOCK_P]; # Bank 64 VCCO - VCC1V2 Net "USER_SI570_CLOCK_P"  - IO_L12P_T1U_N10_GC_64
+#
+# MGT Clocks
+#
+# PCIe Clocks
+#
+# Input Clocks for Gen3 x16
+# PCIE_REFCLK -> PCIe 100Mhz Host clock
+set_property PACKAGE_PIN AM10             [get_ports PCIE_REFCLK_N ]; # Bank 226 Net "PEX_REFCLK_C_N" - MGTREFCLK0N_226
+set_property PACKAGE_PIN AM11             [get_ports PCIE_REFCLK_P ]; # Bank 226 Net "PEX_REFCLK_C_P" - MGTREFCLK0P_226
+#
+# Input Clocks and Controls for QSFP28 Port 0
+#
+# MGT_SI570_CLOCK0   -> MGT Ref Clock 0 156.25MHz Default (User re-programmable)
+# QSFP0_CLOCK        -> MGT Ref Clock 1 User selectable by QSFP0_FS
+#
+set_property PACKAGE_PIN M10 [get_ports MGT_SI570_CLOCK0_N]; # Bank 231 Net "MGT_SI570_CLOCK0_C_N" - MGTREFCLK0N_231
+set_property PACKAGE_PIN M11 [get_ports MGT_SI570_CLOCK0_P]; # Bank 231 Net "MGT_SI570_CLOCK0_C_P" - MGTREFCLK0P_231
+set_property PACKAGE_PIN K10 [get_ports QSFP0_CLOCK_N     ]; # Bank 231 Net "QSFP0_CLOCK_N"        - MGTREFCLK1N_231
+set_property PACKAGE_PIN K11 [get_ports QSFP0_CLOCK_P     ]; # Bank 231 Net "QSFP0_CLOCK_P"        - MGTREFCLK1P_231
+#
+# QSFP0 Control Signals
+#       RESETL  - Active Low Reset output from FPGA to QSFP Module
+#       MODPRSL - Active Low Module Present input from QSFP to FPGA
+#       INTL    - Active Low Interrupt input from QSFP to FPGA
+#       LPMODE  - Active High Control output from FPGA to QSFP Module to put the device in low power mode (Optics Off)
+#       MODSEL  - Active Low Enable output from FPGA to QSFP Module to select device for I2C Sideband Communication
+#
+set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS12       } [get_ports QSFP0_RESETL      ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_RESETL_LS"     - IO_L22P_T3U_N6_DBC_AD0P_64
+set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS12       } [get_ports QSFP0_MODPRSL     ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_MODPRSL_LS"    - IO_L21N_T3L_N5_AD8N_64
+set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS12       } [get_ports QSFP0_INTL        ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_INTL_LS"       - IO_L21P_T3L_N4_AD8P_64
+set_property -dict {PACKAGE_PIN BD18 IOSTANDARD LVCMOS12       } [get_ports QSFP0_LPMODE      ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_LPMODE_LS"     - IO_L20N_T3L_N3_AD1N_64
+set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS12       } [get_ports QSFP0_MODSELL     ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_MODSELL_LS"    - IO_L22N_T3U_N7_DBC_AD0N_64
+#
+# QSFP0 Clock Control Signals
+#       FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups)
+#                                    FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS
+#       RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. 
+#
+set_property -dict {PACKAGE_PIN AT20 IOSTANDARD LVCMOS12       } [get_ports QSFP0_FS[0]       ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_FS0"           - IO_L10P_T1U_N6_QBC_AD4P_64
+set_property -dict {PACKAGE_PIN AU22 IOSTANDARD LVCMOS12       } [get_ports QSFP0_FS[1]       ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_FS1"           - IO_L9N_T1L_N5_AD12N_64
+set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVCMOS12       } [get_ports QSFP0_REFCLK_RESET]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_REFCLK_RESET"  - IO_L9P_T1L_N4_AD12P_64
+#
+# Input Clocks and Controls for QSFP28 Port 1
+#
+# MGT_SI570_CLOCK1   -> MGT Ref Clock 0 156.25MHz Default (User re-programmable)
+# QSFP1_CLOCK        -> MGT Ref Clock 1 User selectable by QSFP0_FS
+#
+set_property PACKAGE_PIN T10 [get_ports MGT_SI570_CLOCK1_N ]; # Bank 230 Net "MGT_SI570_CLOCK1_C_N" - MGTREFCLK0N_230
+set_property PACKAGE_PIN T11 [get_ports MGT_SI570_CLOCK1_P ]; # Bank 230 Net "MGT_SI570_CLOCK1_C_P" - MGTREFCLK0P_230
+set_property PACKAGE_PIN P10 [get_ports QSFP1_CLOCK_N      ]; # Bank 230 Net "QSFP1_CLOCK_N"        - MGTREFCLK1N_230
+set_property PACKAGE_PIN P11 [get_ports QSFP1_CLOCK_P      ]; # Bank 230 Net "QSFP1_CLOCK_P"        - MGTREFCLK1P_230
+##
+## QSFP1 Control Signals
+##       RESETL  - Active Low Reset output from FPGA to QSFP Module
+##       MODPRSL - Active Low Module Present input from QSFP to FPGA
+##       INTL    - Active Low Interrupt input from QSFP to FPGA
+##       LPMODE  - Active High Control output from FPGA to QSFP Module to put the device in low power mode (Optics Off)
+##       MODSEL  - Active Low Enable output from FPGA to QSFP Module to select device for I2C Sideband Communication
+##
+set_property -dict {PACKAGE_PIN BC18 IOSTANDARD LVCMOS12      } [get_ports QSFP1_RESETL      ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_RESETL_LS"     - IO_L15N_T2L_N5_AD11N_64
+set_property -dict {PACKAGE_PIN BC19 IOSTANDARD LVCMOS12      } [get_ports QSFP1_MODPRSL     ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_MODPRSL_LS"    - IO_L15P_T2L_N4_AD11P_64
+set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS12      } [get_ports QSFP1_INTL        ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_INTL_LS"       - IO_L14N_T2L_N3_GC_64
+set_property -dict {PACKAGE_PIN AV22 IOSTANDARD LVCMOS12      } [get_ports QSFP1_LPMODE      ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_LPMODE_LS"     - IO_L14P_T2L_N2_GC_64
+set_property -dict {PACKAGE_PIN AY20 IOSTANDARD LVCMOS12      } [get_ports QSFP1_MODSELL     ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_MODSELL_LS"    - IO_L16P_T2U_N6_QBC_AD3P_64
+##
+##
+## QSFP1 Clock Control Signals
+##      - FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups)
+##                                     FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS
+##      - RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. 
+##                PINS: "QSFP1_RECLK_RESET"   - IO_L8N_T1L_N3_AD5N_64_AR21
+##
+set_property -dict {PACKAGE_PIN AR22 IOSTANDARD LVCMOS12       } [get_ports QSFP1_FS[0]       ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_FS0"           - IO_L8P_T1L_N2_AD5P_64
+set_property -dict {PACKAGE_PIN AU20 IOSTANDARD LVCMOS12       } [get_ports QSFP1_FS[1]       ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_FS1"           - IO_L7N_T1L_N1_QBC_AD13N_64
+set_property -dict {PACKAGE_PIN AR21 IOSTANDARD LVCMOS12       } [get_ports QSFP1_REFCLK_RESET]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_REFCLK_RESET"  - IO_L8N_T1L_N3_AD5N_64
+#
+#  PCIe Connections   Bank 64
+#    PCIE_PERSTN Active low input from PCIe Connector to Ultrascale+ Device to detect presence.
+#
+set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS12       } [get_ports PCIE_PERST        ]; # Bank 64 VCCO - VCC1V2 Net "PCIE_PERST_LS"       - IO_L23P_T3U_N8_64
+#
+#  Bank 65 Ultrascale+ Device SYSMON I2C Slave Interface to Satellite Controller to monitor Ultrascale+ Device Temperatures and Voltages.
+#    SYSMON_SCL   Slave I2C clock connection from Satellite Controller to Ultrascale+ Device
+#    SYSMON_SDA   Slave I2C data connection from Satellite Controller to Ultrascale+ Device
+#
+set_property -dict {PACKAGE_PIN AR26 IOSTANDARD LVCMOS12       } [get_ports SYSMON_SDA       ]; # Bank 65   - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
+set_property -dict {PACKAGE_PIN AR25 IOSTANDARD LVCMOS12       } [get_ports SYSMON_SCL       ]; # Bank 65   - IO_L23P_T3U_N8_I2C_SCLK_65
+#
+# Bank 64 Ultrascale+ Device I2C Slave Interface to Satellite Controller.
+#    I2C_FPGA_SCL       Slave I2C clock connection from Satellite Controller to Ultrascale+ Device
+#    I2C_FPGA_SDA       Slave I2C data connection from Satellite Controller to Ultrascale+ Device
+#    I2C_MAIN_INT_B     Slave I2C active low system interrupt output from Ultrascale+ Device to Satellite Controller
+#
+set_property -dict {PACKAGE_PIN BF19 IOSTANDARD LVCMOS12       } [get_ports I2C_MAIN_RESETN   ]; # Bank 64 VCCO - VCC1V2 Net "I2C_MAIN_RESET_B_LS" - IO_L19N_T3L_N1_DBC_AD9N_64
+set_property -dict {PACKAGE_PIN BF20 IOSTANDARD LVCMOS12       } [get_ports I2C_FPGA_SCL      ]; # Bank 64 VCCO - VCC1V2 Net "I2C_FPGA_SCL_LS"     - IO_L19P_T3L_N0_DBC_AD9P_64
+set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS12       } [get_ports I2C_FPGA_SDA      ]; # Bank 64 VCCO - VCC1V2 Net "I2C_FPGA_SDA_LS"     - IO_T2U_N12_64
+
+#
+# Bank 65  FPGA UART Interface to FTDI FT4232 Port 3 of 4 (User selectable Baud)
+#    USB_UART_RX  Input from FT4232 UART to FPGA
+#    USB_UART_TX  Output from FPGA to FT4232 UART
+#
+set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS12       } [get_ports USB_UART_RX       ]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_RX"         - IO_T3U_N12_64
+set_property -dict {PACKAGE_PIN BF18 IOSTANDARD LVCMOS12       } [get_ports USB_UART_TX       ]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_TX"         - IO_L24N_T3U_N11_64
+#
+# Bank 65 Ultrascale+ Device to Satellite Controller CMS UART Interface (115200, No parity, 8 bits, 1 stop bit)
+#    FPGA_RXD_MSP  Input from Satellite Controller UART to Ultrascale+ Device
+#    FPGA_TXD_MSP  Output from Ultrascale+ Device to Satellite Controller UART
+#    This interface is used for the CMS command path, refer to https://www.xilinx.com/products/intellectual-property/cms-subsystem.html and Xilinx PG348
+#
+set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12       } [get_ports FPGA_TXD_MSP      ]; # Bank 64 VCCO - VCC1V2 Net "FPGA_TXD_MSP"        - IO_L18N_T2U_N11_AD2N_64
+set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12       } [get_ports FPGA_RXD_MSP      ]; # Bank 64 VCCO - VCC1V2 Net "FPGA_RXD_MSP"        - IO_L18P_T2U_N10_AD2P_64
+#
+#  DDR4_RESET_GATE Active High Output from Ultrascale+ Device to hold all External DDR4 interfaces in Self refresh.
+#                  This Output disconnects the Memory interface reset and holds it in active and pulls the Clock Enables signal on the Memory Interfaces.
+#                  Refer to XAPP1321 for details on Save Restore and Self refresh mode.
+#
+set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS12       } [get_ports DDR4_RESET_GATE   ]; # Bank 64 VCCO - VCC1V2 Net "DDR4_RESET_GATE"     - IO_L7P_T1L_N0_QBC_AD13P_64
+#
+#  GPIO_MSP0/1/2/3 General purpose IO interconnects between Ultrascale+ Device and Satellite Controller. Currently not used.
+#
+set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12       } [get_ports GPIO_MSP[0]       ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP0"           - IO_T0U_N12_VRP_64
+set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12       } [get_ports GPIO_MSP[1]       ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP1"           - IO_L6N_T0U_N11_AD6N_64
+set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12       } [get_ports GPIO_MSP[2]       ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP2"           - IO_L6P_T0U_N10_AD6P_64
+set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12       } [get_ports GPIO_MSP[3]       ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP3"           - IO_L5N_T0U_N9_AD14N_64
+#
+#  SW_DP0/1/2/3 General purpose IO interconnects between Ultrascale+ Device and Satellite Controller. Currently not used.
+#
+set_property -dict {PACKAGE_PIN AN22 IOSTANDARD LVCMOS12       } [get_ports SW_DP[0]          ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP0"              - IO_L5P_T0U_N8_AD14P_64
+set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS12       } [get_ports SW_DP[1]          ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP1"              - IO_L4N_T0U_N7_DBC_AD7N_64
+set_property -dict {PACKAGE_PIN AL19 IOSTANDARD LVCMOS12       } [get_ports SW_DP[2]          ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP2"              - IO_L4P_T0U_N6_DBC_AD7P_64
+set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS12       } [get_ports SW_DP[3]          ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP3"              - IO_L3N_T0L_N5_AD15N_64
+#
+#  CPU_RESET_FPGA Connects to SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller
+#                 Designed to be a active low reset input to the FPGA.
+#
+# set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS12    } [get_ports CPU_RESET_FPGA ]; # Bank 64 VCCO - VCC1V2 Net "CPU_RESET_FPGA"         - IO_L2N_T0L_N3_64_AL20
+#
+# Test point inaccessable to user due to Heatsink.
+#
+# set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12    } [get_ports TESTCLK_OUT       ]; # Bank 64 VCCO - VCC1V2 Net "TESTCLK_OUT"         - IO_L1P_T0L_N0_DBC_64
+#
+#
+# Leave Un-instantiated for proper Card operation or signal contention with Satellite Controller
+#
+set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS12       } [get_ports MSP_RSTn          ]; # Bank 64 VCCO - VCC1V2 Net "N32064223"           - IO_L3P_T0L_N4_AD15P_64
+set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS12       } [get_ports SW_SET1_FPGA      ]; # Bank 64 VCCO - VCC1V2 Net "SW_SET1_FPGA"        - IO_L2P_T0L_N2_64
+set_property -dict {PACKAGE_PIN BC21 IOSTANDARD LVCMOS12       } [get_ports STATUS_LED0_FPGA  ]; # Bank 64 VCCO - VCC1V2 Net "STATUS_LED0_FPGA"    - IO_L17N_T2U_N9_AD10N_64
+set_property -dict {PACKAGE_PIN BB21 IOSTANDARD LVCMOS12       } [get_ports STATUS_LED1_FPGA  ]; # Bank 64 VCCO - VCC1V2 Net "STATUS_LED1_FPGA"    - IO_L17P_T2U_N8_AD10P_64
+set_property -dict {PACKAGE_PIN BA20 IOSTANDARD LVCMOS12       } [get_ports STATUS_LED2_FPGA  ]; # Bank 64 VCCO - VCC1V2 Net "STATUS_LED2_FPGA"    - IO_L16N_T2U_N7_QBC_AD3N_64
+#
+# DDR4 RDIMM Controller 3, 72-bit Data Interface, x4 Componets, Single Rank
+#     <<<NOTE>>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order:
+#                JEDEC Order   DQS ->  0  9  1 10  2 11  3 12  4 13  5 14  6 15  7 16  8 17
+#                Xil MIG Order DQS ->  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
+#
+set_property -dict {PACKAGE_PIN B24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[34]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ34"      - IO_L23N_T3U_N9_72
+set_property -dict {PACKAGE_PIN B25  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[35]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ35"      - IO_L23P_T3U_N8_72
+set_property -dict {PACKAGE_PIN A24  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[8] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C4"    - IO_L22N_T3U_N7_DBC_AD0N_72
+set_property -dict {PACKAGE_PIN A25  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[8] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T4"    - IO_L22P_T3U_N6_DBC_AD0P_72
+set_property -dict {PACKAGE_PIN A22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[33]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ33"      - IO_L24N_T3U_N11_72
+set_property -dict {PACKAGE_PIN A23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[32]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ32"      - IO_L24P_T3U_N10_72
+set_property -dict {PACKAGE_PIN C23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[39]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ39"      - IO_L21N_T3L_N5_AD8N_72
+set_property -dict {PACKAGE_PIN C24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[38]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ38"      - IO_L21P_T3L_N4_AD8P_72
+set_property -dict {PACKAGE_PIN B22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[36]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ36"      - IO_L20N_T3L_N3_AD1N_72
+set_property -dict {PACKAGE_PIN C22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[37]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ37"      - IO_L20P_T3L_N2_AD1P_72
+set_property -dict {PACKAGE_PIN D23  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[9] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C13"   - IO_L19N_T3L_N1_DBC_AD9N_72
+set_property -dict {PACKAGE_PIN D24  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[9] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T13"   - IO_L19P_T3L_N0_DBC_AD9P_72
+set_property -dict {PACKAGE_PIN E22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[57]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ57"      - IO_L17N_T2U_N9_AD10N_72
+set_property -dict {PACKAGE_PIN F22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[56]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ56"      - IO_L17P_T2U_N8_AD10P_72
+set_property -dict {PACKAGE_PIN E23  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[14]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C7"    - IO_L16N_T2U_N7_QBC_AD3N_72
+set_property -dict {PACKAGE_PIN F23  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[14]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T7"    - IO_L16P_T2U_N6_QBC_AD3P_72
+set_property -dict {PACKAGE_PIN G21  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[59]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ59"      - IO_L18N_T2U_N11_AD2N_72
+set_property -dict {PACKAGE_PIN G22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[58]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ58"      - IO_L18P_T2U_N10_AD2P_72
+set_property -dict {PACKAGE_PIN E25  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[61]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ61"      - IO_L15N_T2L_N5_AD11N_72
+set_property -dict {PACKAGE_PIN F25  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[62]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ62"      - IO_L15P_T2L_N4_AD11P_72
+set_property -dict {PACKAGE_PIN F24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[60]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ60"      - IO_L14N_T2L_N3_GC_72
+set_property -dict {PACKAGE_PIN G25  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[63]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ63"      - IO_L14P_T2L_N2_GC_72
+set_property -dict {PACKAGE_PIN H22  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[15]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C16"   - IO_L13N_T2L_N1_GC_QBC_72
+set_property -dict {PACKAGE_PIN H23  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[15]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T16"   - IO_L13P_T2L_N0_GC_QBC_72
+set_property -dict {PACKAGE_PIN J23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[9]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ9"       - IO_L11N_T1U_N9_GC_72
+set_property -dict {PACKAGE_PIN J24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[8]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ8"       - IO_L11P_T1U_N8_GC_72
+set_property -dict {PACKAGE_PIN H21  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[2] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C1"    - IO_L10N_T1U_N7_QBC_AD4N_72
+set_property -dict {PACKAGE_PIN J21  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[2] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T1"    - IO_L10P_T1U_N6_QBC_AD4P_72
+set_property -dict {PACKAGE_PIN G24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[11]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ11"      - IO_L12N_T1U_N11_GC_72
+set_property -dict {PACKAGE_PIN H24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[10]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ10"      - IO_L12P_T1U_N10_GC_72
+set_property -dict {PACKAGE_PIN L23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[13]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ13"      - IO_L9N_T1L_N5_AD12N_72
+set_property -dict {PACKAGE_PIN L24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[12]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ12"      - IO_L9P_T1L_N4_AD12P_72
+set_property -dict {PACKAGE_PIN K21  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[15]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ15"      - IO_L8N_T1L_N3_AD5N_72
+set_property -dict {PACKAGE_PIN K22  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[14]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ14"      - IO_L8P_T1L_N2_AD5P_72
+set_property -dict {PACKAGE_PIN L22  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C10"   - IO_L7N_T1L_N1_QBC_AD13N_72
+set_property -dict {PACKAGE_PIN M22  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T10"   - IO_L7P_T1L_N0_QBC_AD13P_72
+set_property -dict {PACKAGE_PIN N24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[1]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ1"       - IO_L5N_T0U_N9_AD14N_72
+set_property -dict {PACKAGE_PIN P24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[0]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ0"       - IO_L5P_T0U_N8_AD14P_72
+set_property -dict {PACKAGE_PIN R22  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C0"    - IO_L4N_T0U_N7_DBC_AD7N_72
+set_property -dict {PACKAGE_PIN T22  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T0"    - IO_L4P_T0U_N6_DBC_AD7P_72
+set_property -dict {PACKAGE_PIN R23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[3]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ3"       - IO_L6N_T0U_N11_AD6N_72
+set_property -dict {PACKAGE_PIN T24  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[2]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ2"       - IO_L6P_T0U_N10_AD6P_72
+set_property -dict {PACKAGE_PIN N23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[4]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ4"       - IO_L3N_T0L_N5_AD15N_72
+set_property -dict {PACKAGE_PIN P23  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[6]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ6"       - IO_L3P_T0L_N4_AD15P_72
+set_property -dict {PACKAGE_PIN P21  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[5]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ5"       - IO_L2N_T0L_N3_72
+set_property -dict {PACKAGE_PIN R21  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[7]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ7"       - IO_L2P_T0L_N2_72
+set_property -dict {PACKAGE_PIN N21  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C9"    - IO_L1N_T0L_N1_DBC_72
+set_property -dict {PACKAGE_PIN N22  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T9"    - IO_L1P_T0L_N0_DBC_72
+set_property -dict {PACKAGE_PIN B21  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[43]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ43"      - IO_L23N_T3U_N9_71
+set_property -dict {PACKAGE_PIN C21  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[42]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ42"      - IO_L23P_T3U_N8_71
+set_property -dict {PACKAGE_PIN B17  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[10]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C5"    - IO_L22N_T3U_N7_DBC_AD0N_71
+set_property -dict {PACKAGE_PIN C17  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[10]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T5"    - IO_L22P_T3U_N6_DBC_AD0P_71
+#set_property -dict {PACKAGE_PIN D18  IOSTANDARD LVCMOS12       } [get_ports c3_ddr4_event_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_EVENT_B"   - IO_T3U_N12_71
+set_property -dict {PACKAGE_PIN C18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[41]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ41"      - IO_L24N_T3U_N11_71
+set_property -dict {PACKAGE_PIN C19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[40]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ40"      - IO_L24P_T3U_N10_71
+set_property -dict {PACKAGE_PIN A20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[46]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ46"      - IO_L21N_T3L_N5_AD8N_71
+set_property -dict {PACKAGE_PIN B20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[47]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ47"      - IO_L21P_T3L_N4_AD8P_71
+set_property -dict {PACKAGE_PIN A17  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[45]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ45"      - IO_L20N_T3L_N3_AD1N_71
+set_property -dict {PACKAGE_PIN A18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[44]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ44"      - IO_L20P_T3L_N2_AD1P_71
+set_property -dict {PACKAGE_PIN A19  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[11]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C14"   - IO_L19N_T3L_N1_DBC_AD9N_71
+set_property -dict {PACKAGE_PIN B19  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[11]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T14"   - IO_L19P_T3L_N0_DBC_AD9P_71
+set_property -dict {PACKAGE_PIN E20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[51]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ51"      - IO_L17N_T2U_N9_AD10N_71
+set_property -dict {PACKAGE_PIN F20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[49]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ49"      - IO_L17P_T2U_N8_AD10P_71
+set_property -dict {PACKAGE_PIN F17  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[12]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C6"    - IO_L16N_T2U_N7_QBC_AD3N_71
+set_property -dict {PACKAGE_PIN F18  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[12]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T6"    - IO_L16P_T2U_N6_QBC_AD3P_71
+set_property -dict {PACKAGE_PIN D21  IOSTANDARD LVCMOS12       } [get_ports c3_ddr4_reset_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_RESET_N"   - IO_T2U_N12_71
+set_property -dict {PACKAGE_PIN E17  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[48]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ48"      - IO_L18N_T2U_N11_AD2N_71
+set_property -dict {PACKAGE_PIN E18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[50]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ50"      - IO_L18P_T2U_N10_AD2P_71
+set_property -dict {PACKAGE_PIN D19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[52]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ52"      - IO_L15N_T2L_N5_AD11N_71
+set_property -dict {PACKAGE_PIN D20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[53]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ53"      - IO_L15P_T2L_N4_AD11P_71
+set_property -dict {PACKAGE_PIN H18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[54]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ54"      - IO_L14N_T2L_N3_GC_71
+set_property -dict {PACKAGE_PIN J18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[55]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ55"      - IO_L14P_T2L_N2_GC_71
+set_property -dict {PACKAGE_PIN G19  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C15"   - IO_L13N_T2L_N1_GC_QBC_71
+set_property -dict {PACKAGE_PIN H19  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T15"   - IO_L13P_T2L_N0_GC_QBC_71
+set_property -dict {PACKAGE_PIN F19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[18]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ18"      - IO_L11N_T1U_N9_GC_71
+set_property -dict {PACKAGE_PIN G20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[16]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ16"      - IO_L11P_T1U_N8_GC_71
+set_property -dict {PACKAGE_PIN K20  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[4] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C2"    - IO_L10N_T1U_N7_QBC_AD4N_71
+set_property -dict {PACKAGE_PIN L20  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[4] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T2"    - IO_L10P_T1U_N6_QBC_AD4P_71
+set_property -dict {PACKAGE_PIN G17  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[19]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ19"      - IO_L12N_T1U_N11_GC_71
+set_property -dict {PACKAGE_PIN H17  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[17]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ17"      - IO_L12P_T1U_N10_GC_71
+set_property -dict {PACKAGE_PIN J19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[23]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ23"      - IO_L9N_T1L_N5_AD12N_71
+set_property -dict {PACKAGE_PIN J20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[20]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ20"      - IO_L9P_T1L_N4_AD12P_71
+set_property -dict {PACKAGE_PIN L18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[22]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ22"      - IO_L8N_T1L_N3_AD5N_71
+set_property -dict {PACKAGE_PIN L19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[21]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ21"      - IO_L8P_T1L_N2_AD5P_71
+set_property -dict {PACKAGE_PIN K17  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C11"   - IO_L7N_T1L_N1_QBC_AD13N_71
+set_property -dict {PACKAGE_PIN K18  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T11"   - IO_L7P_T1L_N0_QBC_AD13P_71
+set_property -dict {PACKAGE_PIN M19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[24]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ24"      - IO_L5N_T0U_N9_AD14N_71
+set_property -dict {PACKAGE_PIN M20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[25]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ25"      - IO_L5P_T0U_N8_AD14P_71
+set_property -dict {PACKAGE_PIN P18  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[6] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C3"    - IO_L4N_T0U_N7_DBC_AD7N_71
+set_property -dict {PACKAGE_PIN P19  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[6] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T3"    - IO_L4P_T0U_N6_DBC_AD7P_71
+set_property -dict {PACKAGE_PIN R17  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[27]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ27"      - IO_L6N_T0U_N11_AD6N_71
+set_property -dict {PACKAGE_PIN R18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[26]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ26"      - IO_L6P_T0U_N10_AD6P_71
+set_property -dict {PACKAGE_PIN N18  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[30]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ30"      - IO_L3N_T0L_N5_AD15N_71
+set_property -dict {PACKAGE_PIN N19  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[31]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ31"      - IO_L3P_T0L_N4_AD15P_71
+set_property -dict {PACKAGE_PIN R20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[28]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ28"      - IO_L2N_T0L_N3_71
+set_property -dict {PACKAGE_PIN T20  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[29]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ29"      - IO_L2P_T0L_N2_71
+set_property -dict {PACKAGE_PIN M17  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C12"   - IO_L1N_T0L_N1_DBC_71
+set_property -dict {PACKAGE_PIN N17  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T12"   - IO_L1P_T0L_N0_DBC_71
+set_property -dict {PACKAGE_PIN B16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN C16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_odt[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT0"      - IO_L23P_T3U_N8_70
+set_property -dict {PACKAGE_PIN C13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[11]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR11"     - IO_L22N_T3U_N7_DBC_AD0N_70
+set_property -dict {PACKAGE_PIN D13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_bg[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG0"       - IO_L22P_T3U_N6_DBC_AD0P_70
+#set_property -dict {PACKAGE_PIN D16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B1"     - IO_T3U_N12_70
+set_property -dict {PACKAGE_PIN A13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[9]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR9"      - IO_L24N_T3U_N11_70
+set_property -dict {PACKAGE_PIN B13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[12]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR12"     - IO_L24P_T3U_N10_70
+set_property -dict {PACKAGE_PIN A15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[3]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR3"      - IO_L21N_T3L_N5_AD8N_70
+set_property -dict {PACKAGE_PIN B15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR1"      - IO_L21P_T3L_N4_AD8P_70
+set_property -dict {PACKAGE_PIN C14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[4]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR4"      - IO_L20N_T3L_N3_AD1N_70
+set_property -dict {PACKAGE_PIN D14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[10]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR10"     - IO_L20P_T3L_N2_AD1P_70
+set_property -dict {PACKAGE_PIN A14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[5]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR5"      - IO_L19N_T3L_N1_DBC_AD9N_70
+set_property -dict {PACKAGE_PIN B14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[6]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR6"      - IO_L19P_T3L_N0_DBC_AD9P_70
+set_property -dict {PACKAGE_PIN E15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[15]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR15"     - IO_L17N_T2U_N9_AD10N_70
+#set_property -dict {PACKAGE_PIN E16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_odt[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT1"      - IO_L17P_T2U_N8_AD10P_70
+#set_property -dict {PACKAGE_PIN G13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C1"     - IO_L16N_T2U_N7_QBC_AD3N_70
+#set_property -dict {PACKAGE_PIN G14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T1"     - IO_L16P_T2U_N6_QBC_AD3P_70
+set_property -dict {PACKAGE_PIN D15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[14]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR14"     - IO_T2U_N12_70
+set_property -dict {PACKAGE_PIN F14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[2]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR2"      - IO_L18N_T2U_N11_AD2N_70
+set_property -dict {PACKAGE_PIN F15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[16]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+set_property -dict {PACKAGE_PIN E13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[7]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR7"      - IO_L15N_T2L_N5_AD11N_70
+set_property -dict {PACKAGE_PIN F13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[8]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR8"      - IO_L15P_T2L_N4_AD11P_70
+set_property -dict {PACKAGE_PIN H13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_act_n    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ACT_B"     - IO_L14N_T2L_N3_GC_70
+set_property -dict {PACKAGE_PIN H14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_ba[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA1"       - IO_L14P_T2L_N2_GC_70
+set_property -dict {PACKAGE_PIN G15  IOSTANDARD LVCMOS12       } [get_ports c3_ddr4_alert_n  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ALERT_B"  - IO_L11N_T1U_N9_GC_70
+#set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR17"    - IO_L11P_T1U_N8_GC_70
+set_property -dict {PACKAGE_PIN L13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C0"    - IO_L10N_T1U_N7_QBC_AD4N_70
+set_property -dict {PACKAGE_PIN L14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T0"    - IO_L10P_T1U_N6_QBC_AD4P_70
+set_property -dict {PACKAGE_PIN K13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cke[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN J13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_bg[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG1"      - IO_L12N_T1U_N11_GC_70
+set_property -dict {PACKAGE_PIN J14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_parity   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_PAR"      - IO_L12P_T1U_N10_GC_70
+set_property -dict {PACKAGE_PIN J15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_ba[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA0"      - IO_L9N_T1L_N5_AD12N_70
+set_property -dict {PACKAGE_PIN K16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[13]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR13"    - IO_L9P_T1L_N4_AD12P_70
+#set_property -dict {PACKAGE_PIN M13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[3]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B3"    - IO_L8N_T1L_N3_AD5N_70
+#set_property -dict {PACKAGE_PIN M14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[2]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B2"    - IO_L8P_T1L_N2_AD5P_70
+set_property -dict {PACKAGE_PIN K15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR0"     - IO_L7N_T1L_N1_QBC_AD13N_70
+#set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE1"     - IO_L7P_T1L_N0_QBC_AD13P_70
+set_property -dict {PACKAGE_PIN N13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_dq[66]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ66"     - IO_L5N_T0U_N9_AD14N_70
+set_property -dict {PACKAGE_PIN N14  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[67]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ67"     - IO_L5P_T0U_N8_AD14P_70
+set_property -dict {PACKAGE_PIN P15  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[16]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_70
+set_property -dict {PACKAGE_PIN R16  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[16]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_70
+set_property -dict {PACKAGE_PIN M16  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[64]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ64"     - IO_L6N_T0U_N11_AD6N_70
+set_property -dict {PACKAGE_PIN N16  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[65]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ65"     - IO_L6P_T0U_N10_AD6P_70
+set_property -dict {PACKAGE_PIN P13  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[70]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ70"     - IO_L3N_T0L_N5_AD15N_70
+set_property -dict {PACKAGE_PIN P14  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[71]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ71"     - IO_L3P_T0L_N4_AD15P_70
+set_property -dict {PACKAGE_PIN R15  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[69]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ69"     - IO_L2N_T0L_N3_70
+set_property -dict {PACKAGE_PIN T15  IOSTANDARD POD12_DCI      } [get_ports c3_ddr4_dq[68]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ68"     - IO_L2P_T0L_N2_70
+set_property -dict {PACKAGE_PIN R13  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C17"  - IO_L1N_T0L_N1_DBC_70
+set_property -dict {PACKAGE_PIN T13  IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T17"  - IO_L1P_T0L_N0_DBC_70        
+##
+## DDR4 RDIMM Controller 1, 72-bit Data Interface, x4 Componets, Single Rank
+##     <<<NOTE>>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order:
+##                JEDEC Order   DQS ->  0  9  1 10  2 11  3 12  4 13  5 14  6 15  7 16  8 17
+##                Xil MIG Order DQS ->  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
+##
+
+set_property -dict {PACKAGE_PIN AN13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[24]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ24"     - IO_L23N_T3U_N9_67
+set_property -dict {PACKAGE_PIN AM13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[26]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ26"     - IO_L23P_T3U_N8_67
+set_property -dict {PACKAGE_PIN AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C3"   - IO_L22N_T3U_N7_DBC_AD0N_67
+set_property -dict {PACKAGE_PIN AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T3"   - IO_L22P_T3U_N6_DBC_AD0P_67
+set_property -dict {PACKAGE_PIN AR13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[25]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ25"     - IO_L24N_T3U_N11_67
+set_property -dict {PACKAGE_PIN AP13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[27]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ27"     - IO_L24P_T3U_N10_67
+set_property -dict {PACKAGE_PIN AM14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[28]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ28"     - IO_L21N_T3L_N5_AD8N_67
+set_property -dict {PACKAGE_PIN AL14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[30]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ30"     - IO_L21P_T3L_N4_AD8P_67
+set_property -dict {PACKAGE_PIN AT15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[31]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ31"     - IO_L20N_T3L_N3_AD1N_67
+set_property -dict {PACKAGE_PIN AR15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[29]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ29"     - IO_L20P_T3L_N2_AD1P_67
+set_property -dict {PACKAGE_PIN AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C12"  - IO_L19N_T3L_N1_DBC_AD9N_67
+set_property -dict {PACKAGE_PIN AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T12"  - IO_L19P_T3L_N0_DBC_AD9P_67
+set_property -dict {PACKAGE_PIN AV13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[9]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ9"      - IO_L17N_T2U_N9_AD10N_67
+set_property -dict {PACKAGE_PIN AU13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[8]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ8"      - IO_L17P_T2U_N8_AD10P_67
+set_property -dict {PACKAGE_PIN AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C1"   - IO_L16N_T2U_N7_QBC_AD3N_67
+set_property -dict {PACKAGE_PIN AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T1"   - IO_L16P_T2U_N6_QBC_AD3P_67
+set_property -dict {PACKAGE_PIN AW13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[10]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ10"     - IO_L18N_T2U_N11_AD2N_67
+set_property -dict {PACKAGE_PIN AW14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[11]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ11"     - IO_L18P_T2U_N10_AD2P_67
+set_property -dict {PACKAGE_PIN AV14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[14]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ14"     - IO_L15N_T2L_N5_AD11N_67
+set_property -dict {PACKAGE_PIN AU14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[12]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ12"     - IO_L15P_T2L_N4_AD11P_67
+set_property -dict {PACKAGE_PIN BA11 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[15]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ15"     - IO_L14N_T2L_N3_GC_67
+set_property -dict {PACKAGE_PIN AY11 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[13]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ13"     - IO_L14P_T2L_N2_GC_67
+set_property -dict {PACKAGE_PIN AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C10"  - IO_L13N_T2L_N1_GC_QBC_67
+set_property -dict {PACKAGE_PIN AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T10"  - IO_L13P_T2L_N0_GC_QBC_67
+set_property -dict {PACKAGE_PIN BA13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[18]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ18"     - IO_L11N_T1U_N9_GC_67
+set_property -dict {PACKAGE_PIN BA14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[19]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ19"     - IO_L11P_T1U_N8_GC_67
+set_property -dict {PACKAGE_PIN BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C2"   - IO_L10N_T1U_N7_QBC_AD4N_67
+set_property -dict {PACKAGE_PIN BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T2"   - IO_L10P_T1U_N6_QBC_AD4P_67
+set_property -dict {PACKAGE_PIN BB12 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[17]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ17"     - IO_L12N_T1U_N11_GC_67
+set_property -dict {PACKAGE_PIN BA12 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[16]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ16"     - IO_L12P_T1U_N10_GC_67
+set_property -dict {PACKAGE_PIN BA7  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[22]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ22"     - IO_L9N_T1L_N5_AD12N_67
+set_property -dict {PACKAGE_PIN BA8  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[23]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ23"     - IO_L9P_T1L_N4_AD12P_67
+set_property -dict {PACKAGE_PIN BC9  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[20]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ20"     - IO_L8N_T1L_N3_AD5N_67
+set_property -dict {PACKAGE_PIN BB9  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[21]   ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ21"     - IO_L8P_T1L_N2_AD5P_67
+set_property -dict {PACKAGE_PIN BA9  IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C11"  - IO_L7N_T1L_N1_QBC_AD13N_67
+set_property -dict {PACKAGE_PIN BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T11"  - IO_L7P_T1L_N0_QBC_AD13P_67
+set_property -dict {PACKAGE_PIN BD7  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[1]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ1"      - IO_L5N_T0U_N9_AD14N_67
+set_property -dict {PACKAGE_PIN BC7  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[2]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ2"      - IO_L5P_T0U_N8_AD14P_67
+set_property -dict {PACKAGE_PIN BF9  IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C0"   - IO_L4N_T0U_N7_DBC_AD7N_67
+set_property -dict {PACKAGE_PIN BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T0"   - IO_L4P_T0U_N6_DBC_AD7P_67
+set_property -dict {PACKAGE_PIN BD8  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[3]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ3"      - IO_L6N_T0U_N11_AD6N_67
+set_property -dict {PACKAGE_PIN BD9  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[0]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ0"      - IO_L6P_T0U_N10_AD6P_67
+set_property -dict {PACKAGE_PIN BF7  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[7]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ7"      - IO_L3N_T0L_N5_AD15N_67
+set_property -dict {PACKAGE_PIN BE7  IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[6]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ6"      - IO_L3P_T0L_N4_AD15P_67
+set_property -dict {PACKAGE_PIN BE10 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[5]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ5"      - IO_L2N_T0L_N3_67
+set_property -dict {PACKAGE_PIN BD10 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[4]    ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ4"      - IO_L2P_T0L_N2_67
+set_property -dict {PACKAGE_PIN BF8  IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C9"   - IO_L1N_T0L_N1_DBC_67
+set_property -dict {PACKAGE_PIN BE8  IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T9"   - IO_L1P_T0L_N0_DBC_67
+set_property -dict {PACKAGE_PIN AM15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[56]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ56"     - IO_L23N_T3U_N9_66
+set_property -dict {PACKAGE_PIN AL15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[57]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ57"     - IO_L23P_T3U_N8_66
+set_property -dict {PACKAGE_PIN AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[14]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C7"   - IO_L22N_T3U_N7_DBC_AD0N_66
+set_property -dict {PACKAGE_PIN AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[14]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T7"   - IO_L22P_T3U_N6_DBC_AD0P_66
+#set_property -dict {PACKAGE_PIN AN18 IOSTANDARD LVCMOS12       } [get_ports c1_ddr4_event_n  ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_EVENT_B"  - IO_T3U_N12_66
+set_property -dict {PACKAGE_PIN AN16 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[59]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ59"     - IO_L24N_T3U_N11_66
+set_property -dict {PACKAGE_PIN AN17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[58]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ58"     - IO_L24P_T3U_N10_66
+set_property -dict {PACKAGE_PIN AL16 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[63]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ63"     - IO_L21N_T3L_N5_AD8N_66
+set_property -dict {PACKAGE_PIN AL17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[62]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ62"     - IO_L21P_T3L_N4_AD8P_66
+set_property -dict {PACKAGE_PIN AR18 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[60]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ60"     - IO_L20N_T3L_N3_AD1N_66
+set_property -dict {PACKAGE_PIN AP18 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[61]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ61"     - IO_L20P_T3L_N2_AD1P_66
+set_property -dict {PACKAGE_PIN AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[15]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C16"  - IO_L19N_T3L_N1_DBC_AD9N_66
+set_property -dict {PACKAGE_PIN AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[15]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T16"  - IO_L19P_T3L_N0_DBC_AD9P_66
+set_property -dict {PACKAGE_PIN AU16 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[50]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ50"     - IO_L17N_T2U_N9_AD10N_66
+set_property -dict {PACKAGE_PIN AU17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[51]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ51"     - IO_L17P_T2U_N8_AD10P_66
+set_property -dict {PACKAGE_PIN AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[12]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C6"   - IO_L16N_T2U_N7_QBC_AD3N_66
+set_property -dict {PACKAGE_PIN AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[12]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T6"   - IO_L16P_T2U_N6_QBC_AD3P_66
+set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVCMOS12       } [get_ports c1_ddr4_reset_n  ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_RESET_N"  - IO_T2U_N12_66
+set_property -dict {PACKAGE_PIN AV16 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[48]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ48"     - IO_L18N_T2U_N11_AD2N_66
+set_property -dict {PACKAGE_PIN AV17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[49]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ49"     - IO_L18P_T2U_N10_AD2P_66
+set_property -dict {PACKAGE_PIN AT17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[55]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ55"     - IO_L15N_T2L_N5_AD11N_66
+set_property -dict {PACKAGE_PIN AT18 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[54]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ54"     - IO_L15P_T2L_N4_AD11P_66
+set_property -dict {PACKAGE_PIN BB16 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[53]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ53"     - IO_L14N_T2L_N3_GC_66
+set_property -dict {PACKAGE_PIN BB17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[52]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ52"     - IO_L14P_T2L_N2_GC_66
+set_property -dict {PACKAGE_PIN AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[13]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C15"  - IO_L13N_T2L_N1_GC_QBC_66
+set_property -dict {PACKAGE_PIN AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[13]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T15"  - IO_L13P_T2L_N0_GC_QBC_66
+set_property -dict {PACKAGE_PIN AY17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[40]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ40"     - IO_L11N_T1U_N9_GC_66
+set_property -dict {PACKAGE_PIN AY18 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[42]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ42"     - IO_L11P_T1U_N8_GC_66
+set_property -dict {PACKAGE_PIN BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[10]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C5"   - IO_L10N_T1U_N7_QBC_AD4N_66
+set_property -dict {PACKAGE_PIN BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[10]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T5"   - IO_L10P_T1U_N6_QBC_AD4P_66
+set_property -dict {PACKAGE_PIN BA17 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[41]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ41"     - IO_L12N_T1U_N11_GC_66
+set_property -dict {PACKAGE_PIN BA18 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[43]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ43"     - IO_L12P_T1U_N10_GC_66
+set_property -dict {PACKAGE_PIN BB15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[45]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ45"     - IO_L9N_T1L_N5_AD12N_66
+set_property -dict {PACKAGE_PIN BA15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[44]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ44"     - IO_L9P_T1L_N4_AD12P_66
+set_property -dict {PACKAGE_PIN BD11 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[47]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ47"     - IO_L8N_T1L_N3_AD5N_66
+set_property -dict {PACKAGE_PIN BC11 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[46]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ46"     - IO_L8P_T1L_N2_AD5P_66
+set_property -dict {PACKAGE_PIN BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[11]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C14"  - IO_L7N_T1L_N1_QBC_AD13N_66
+set_property -dict {PACKAGE_PIN BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[11]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T14"  - IO_L7P_T1L_N0_QBC_AD13P_66
+set_property -dict {PACKAGE_PIN BD13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[35]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ35"     - IO_L5N_T0U_N9_AD14N_66
+set_property -dict {PACKAGE_PIN BD14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[33]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ33"     - IO_L5P_T0U_N8_AD14P_66
+set_property -dict {PACKAGE_PIN BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[8] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C4"   - IO_L4N_T0U_N7_DBC_AD7N_66
+set_property -dict {PACKAGE_PIN BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[8] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T4"   - IO_L4P_T0U_N6_DBC_AD7P_66
+set_property -dict {PACKAGE_PIN BF12 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[34]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ34"     - IO_L6N_T0U_N11_AD6N_66
+set_property -dict {PACKAGE_PIN BE13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[32]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ32"     - IO_L6P_T0U_N10_AD6P_66
+set_property -dict {PACKAGE_PIN BD15 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[36]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ36"     - IO_L3N_T0L_N5_AD15N_66
+set_property -dict {PACKAGE_PIN BD16 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[37]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ37"     - IO_L3P_T0L_N4_AD15P_66
+set_property -dict {PACKAGE_PIN BF13 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[39]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ39"     - IO_L2N_T0L_N3_66
+set_property -dict {PACKAGE_PIN BF14 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[38]   ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ38"     - IO_L2P_T0L_N2_66
+set_property -dict {PACKAGE_PIN BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[9] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C13"  - IO_L1N_T0L_N1_DBC_66
+set_property -dict {PACKAGE_PIN BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[9] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T13"  - IO_L1P_T0L_N0_DBC_66
+set_property -dict {PACKAGE_PIN AM25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[15]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR15"    - IO_L22N_T3U_N7_DBC_AD0N_D05_65
+set_property -dict {PACKAGE_PIN AL25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[14]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR14"    - IO_L22P_T3U_N6_DBC_AD0P_D04_65
+set_property -dict {PACKAGE_PIN AP26 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_ba[1]    ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BA1"      - IO_T3U_N12_PERSTN0_65
+set_property -dict {PACKAGE_PIN AN26 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[3]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR3"     - IO_L24N_T3U_N11_DOUT_CSO_B_65
+set_property -dict {PACKAGE_PIN AM26 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[10]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR10"    - IO_L24P_T3U_N10_EMCCLK_65
+#set_property -dict {PACKAGE_PIN AP24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_odt[1]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ODT1"     - IO_L21N_T3L_N5_AD8N_D07_65
+#set_property -dict {PACKAGE_PIN AP23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_cs_n[3]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B3"    - IO_L21P_T3L_N4_AD8P_D06_65
+#set_property -dict {PACKAGE_PIN AM24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[17]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR17"    - IO_L20N_T3L_N3_AD1N_D09_65
+set_property -dict {PACKAGE_PIN AL24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[13]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR13"    - IO_L20P_T3L_N2_AD1P_D08_65
+set_property -dict {PACKAGE_PIN AN24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[0]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR0"     - IO_L19N_T3L_N1_DBC_AD9N_D11_65
+set_property -dict {PACKAGE_PIN AN23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[16]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR16"    - IO_L19P_T3L_N0_DBC_AD9P_D10_65
+#set_property -dict {PACKAGE_PIN AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_c[1]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_C1"    - IO_L17N_T2U_N9_AD10N_D15_65
+#set_property -dict {PACKAGE_PIN AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_t[1]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_T1"    - IO_L17P_T2U_N8_AD10P_D14_65
+set_property -dict {PACKAGE_PIN AT23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_parity   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_PAR"      - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65
+#set_property -dict {PACKAGE_PIN AR23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_cs_n[2]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B2"    - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65
+#set_property -dict {PACKAGE_PIN AP25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_cs_n[1]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B1"    - IO_T2U_N12_CSI_ADV_B_65
+set_property -dict {PACKAGE_PIN AU24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_ba[0]    ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BA0"      - IO_L18N_T2U_N11_AD2N_D13_65
+set_property -dict {PACKAGE_PIN AT24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[1]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR1"     - IO_L18P_T2U_N10_AD2P_D12_65
+set_property -dict {PACKAGE_PIN AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_c[0]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_C0"    - IO_L15N_T2L_N5_AD11N_A03_D19_65
+set_property -dict {PACKAGE_PIN AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_t[0]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_T0"    - IO_L15P_T2L_N4_AD11P_A02_D18_65
+set_property -dict {PACKAGE_PIN AV24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[6]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR6"     - IO_L14N_T2L_N3_GC_A05_D21_65
+set_property -dict {PACKAGE_PIN AV23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_cs_n[0]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B0"    - IO_L14P_T2L_N2_GC_A04_D20_65
+set_property -dict {PACKAGE_PIN AW26 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_bg[1]    ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BG1"      - IO_L13N_T2L_N1_GC_QBC_A07_D23_65
+set_property -dict {PACKAGE_PIN AW25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_act_n    ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ACT_B"    - IO_L13P_T2L_N0_GC_QBC_A06_D22_65
+set_property -dict {PACKAGE_PIN AY26 IOSTANDARD LVCMOS12       } [get_ports c1_ddr4_alert_n  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ALERT_B"  - IO_L11N_T1U_N9_GC_A11_D27_65
+set_property -dict {PACKAGE_PIN AY25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[8]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR8"     - IO_L11P_T1U_N8_GC_A10_D26_65
+set_property -dict {PACKAGE_PIN AY23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[5]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR5"     - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65
+set_property -dict {PACKAGE_PIN AY22 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[4]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR4"     - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65
+set_property -dict {PACKAGE_PIN BA25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[11]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR11"    - IO_T1U_N12_SMBALERT_65
+set_property -dict {PACKAGE_PIN AW24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[2]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR2"     - IO_L12N_T1U_N11_GC_A09_D25_65
+set_property -dict {PACKAGE_PIN AW23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_odt[0]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ODT0"     - IO_L12P_T1U_N10_GC_A08_D24_65
+set_property -dict {PACKAGE_PIN BB25 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_cke[0]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CKE0"     - IO_L9N_T1L_N5_AD12N_A15_D31_65
+#set_property -dict {PACKAGE_PIN BB24 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_cke[1]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CKE1"     - IO_L9P_T1L_N4_AD12P_A14_D30_65
+set_property -dict {PACKAGE_PIN BA23 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[9]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR9"     - IO_L8N_T1L_N3_AD5N_A17_65
+set_property -dict {PACKAGE_PIN BA22 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[7]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR7"     - IO_L8P_T1L_N2_AD5P_A16_65
+set_property -dict {PACKAGE_PIN BC22 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_bg[0]    ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BG0"      - IO_L7N_T1L_N1_QBC_AD13N_A19_65
+set_property -dict {PACKAGE_PIN BB22 IOSTANDARD SSTL12_DCI     } [get_ports c1_ddr4_adr[12]  ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR12"    - IO_L7P_T1L_N0_QBC_AD13P_A18_65
+set_property -dict {PACKAGE_PIN BF25 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[64]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ64"     - IO_L5N_T0U_N9_AD14N_A23_65
+set_property -dict {PACKAGE_PIN BF24 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[65]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ65"     - IO_L5P_T0U_N8_AD14P_A22_65
+set_property -dict {PACKAGE_PIN BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[16]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_A25_65
+set_property -dict {PACKAGE_PIN BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[16]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_A24_65
+set_property -dict {PACKAGE_PIN BE25 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[67]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ67"     - IO_L6N_T0U_N11_AD6N_A21_65
+set_property -dict {PACKAGE_PIN BD25 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[66]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ66"     - IO_L6P_T0U_N10_AD6P_A20_65
+set_property -dict {PACKAGE_PIN BF23 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[70]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ70"     - IO_L3N_T0L_N5_AD15N_A27_65
+set_property -dict {PACKAGE_PIN BE23 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[71]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ71"     - IO_L3P_T0L_N4_AD15P_A26_65
+set_property -dict {PACKAGE_PIN BD23 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[68]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ68"     - IO_L2N_T0L_N3_FWE_FCS2_B_65
+set_property -dict {PACKAGE_PIN BC23 IOSTANDARD POD12_DCI      } [get_ports c1_ddr4_dq[69]   ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ69"     - IO_L2P_T0L_N2_FOE_B_65
+set_property -dict {PACKAGE_PIN BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[17]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_C17"  - IO_L1N_T0L_N1_DBC_RS1_65
+set_property -dict {PACKAGE_PIN BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[17]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_T17"  - IO_L1P_T0L_N0_DBC_RS0_65
+
+
+##
+## DDR4 RDIMM Controller 2, 72-bit Data Interface, x4 Componets, Single Rank
+##     <<<NOTE>>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order:
+##                JEDEC Order   DQS ->  0  9  1 10  2 11  3 12  4 13  5 14  6 15  7 16  8 17
+##                Xil MIG Order DQS ->  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
+##
+
+set_property -dict {PACKAGE_PIN C26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[25]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ25"    - IO_L23N_T3U_N9_48
+set_property -dict {PACKAGE_PIN D26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[24]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ24"    - IO_L23P_T3U_N8_48
+set_property -dict {PACKAGE_PIN A28  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[6] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C3"  - IO_L22N_T3U_N7_DBC_AD0N_48
+set_property -dict {PACKAGE_PIN A27  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[6] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T3"  - IO_L22P_T3U_N6_DBC_AD0P_48
+set_property -dict {PACKAGE_PIN B27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[26]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ26"    - IO_L24N_T3U_N11_48
+set_property -dict {PACKAGE_PIN B26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[27]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ27"    - IO_L24P_T3U_N10_48
+set_property -dict {PACKAGE_PIN C28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[31]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ31"    - IO_L21N_T3L_N5_AD8N_48
+set_property -dict {PACKAGE_PIN C27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[30]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ30"    - IO_L21P_T3L_N4_AD8P_48
+set_property -dict {PACKAGE_PIN A30  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[29]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ29"    - IO_L20N_T3L_N3_AD1N_48
+set_property -dict {PACKAGE_PIN A29  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[28]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ28"    - IO_L20P_T3L_N2_AD1P_48
+set_property -dict {PACKAGE_PIN B29  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[7] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C12" - IO_L19N_T3L_N1_DBC_AD9N_48
+set_property -dict {PACKAGE_PIN C29  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[7] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T12" - IO_L19P_T3L_N0_DBC_AD9P_48
+set_property -dict {PACKAGE_PIN E27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[17]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ17"    - IO_L17N_T2U_N9_AD10N_48
+set_property -dict {PACKAGE_PIN F27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[16]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ16"    - IO_L17P_T2U_N8_AD10P_48
+set_property -dict {PACKAGE_PIN D30  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[4] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C2"  - IO_L16N_T2U_N7_QBC_AD3N_48
+set_property -dict {PACKAGE_PIN D29  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[4] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T2"  - IO_L16P_T2U_N6_QBC_AD3P_48
+set_property -dict {PACKAGE_PIN D28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[19]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ19"    - IO_L18N_T2U_N11_AD2N_48
+set_property -dict {PACKAGE_PIN E28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[18]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ18"    - IO_L18P_T2U_N10_AD2P_48
+set_property -dict {PACKAGE_PIN F29  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[23]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ23"    - IO_L15N_T2L_N5_AD11N_48
+set_property -dict {PACKAGE_PIN F28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[22]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ22"    - IO_L15P_T2L_N4_AD11P_48
+set_property -dict {PACKAGE_PIN G27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[20]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ20"    - IO_L14N_T2L_N3_GC_48
+set_property -dict {PACKAGE_PIN G26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[21]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ21"    - IO_L14P_T2L_N2_GC_48
+set_property -dict {PACKAGE_PIN H27  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[5] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C11" - IO_L13N_T2L_N1_GC_QBC_48
+set_property -dict {PACKAGE_PIN H26  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[5] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T11" - IO_L13P_T2L_N0_GC_QBC_48
+set_property -dict {PACKAGE_PIN H28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[10]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ10"    - IO_L11N_T1U_N9_GC_48
+set_property -dict {PACKAGE_PIN J28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[8]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ8"     - IO_L11P_T1U_N8_GC_48
+set_property -dict {PACKAGE_PIN J26  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[2] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C1"  - IO_L10N_T1U_N7_QBC_AD4N_48
+set_property -dict {PACKAGE_PIN J25  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[2] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T1"  - IO_L10P_T1U_N6_QBC_AD4P_48
+set_property -dict {PACKAGE_PIN G29  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[11]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ11"    - IO_L12N_T1U_N11_GC_48
+set_property -dict {PACKAGE_PIN H29  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[9]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ9"     - IO_L12P_T1U_N10_GC_48
+set_property -dict {PACKAGE_PIN K27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[15]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ15"    - IO_L9N_T1L_N5_AD12N_48
+set_property -dict {PACKAGE_PIN L27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[13]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ13"    - IO_L9P_T1L_N4_AD12P_48
+set_property -dict {PACKAGE_PIN K26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[14]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ14"    - IO_L8N_T1L_N3_AD5N_48
+set_property -dict {PACKAGE_PIN K25  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[12]   ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ12"    - IO_L8P_T1L_N2_AD5P_48
+set_property -dict {PACKAGE_PIN L28  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[3] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C10" - IO_L7N_T1L_N1_QBC_AD13N_48
+set_property -dict {PACKAGE_PIN M27  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[3] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T10" - IO_L7P_T1L_N0_QBC_AD13P_48
+set_property -dict {PACKAGE_PIN P25  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[1]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ1"     - IO_L5N_T0U_N9_AD14N_48
+set_property -dict {PACKAGE_PIN R25  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[0]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ0"     - IO_L5P_T0U_N8_AD14P_48
+set_property -dict {PACKAGE_PIN M26  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[0] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C0"  - IO_L4N_T0U_N7_DBC_AD7N_48
+set_property -dict {PACKAGE_PIN N26  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[0] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T0"  - IO_L4P_T0U_N6_DBC_AD7P_48
+set_property -dict {PACKAGE_PIN L25  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[3]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ3"     - IO_L6N_T0U_N11_AD6N_48
+set_property -dict {PACKAGE_PIN M25  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[2]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ2"     - IO_L6P_T0U_N10_AD6P_48
+set_property -dict {PACKAGE_PIN P26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[4]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ4"     - IO_L3N_T0L_N5_AD15N_48
+set_property -dict {PACKAGE_PIN R26  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[5]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ5"     - IO_L3P_T0L_N4_AD15P_48
+set_property -dict {PACKAGE_PIN N28  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[7]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ7"     - IO_L2N_T0L_N3_48
+set_property -dict {PACKAGE_PIN N27  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[6]    ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ6"     - IO_L2P_T0L_N2_48
+set_property -dict {PACKAGE_PIN P28  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[1] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C9"  - IO_L1N_T0L_N1_DBC_48
+set_property -dict {PACKAGE_PIN R28  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[1] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T9"  - IO_L1P_T0L_N0_DBC_48
+set_property -dict {PACKAGE_PIN B32  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[7]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR7"    - IO_L23N_T3U_N9_47
+set_property -dict {PACKAGE_PIN B31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_act_n    ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ACT_B"   - IO_L23P_T3U_N8_47
+set_property -dict {PACKAGE_PIN A35  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[14]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR14"   - IO_L22N_T3U_N7_DBC_AD0N_47
+set_property -dict {PACKAGE_PIN A34  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[10]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR10"   - IO_L22P_T3U_N6_DBC_AD0P_47
+set_property -dict {PACKAGE_PIN C31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_bg[0]    ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BG0"     - IO_T3U_N12_47
+set_property -dict {PACKAGE_PIN A33  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[1]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR1"    - IO_L24N_T3U_N11_47
+set_property -dict {PACKAGE_PIN A32  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[8]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR8"    - IO_L24P_T3U_N10_47
+set_property -dict {PACKAGE_PIN C33  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[2]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR2"    - IO_L21N_T3L_N5_AD8N_47
+set_property -dict {PACKAGE_PIN C32  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[6]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR6"    - IO_L21P_T3L_N4_AD8P_47
+set_property -dict {PACKAGE_PIN B36  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_ba[1]    ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BA1"     - IO_L20N_T3L_N3_AD1N_47
+set_property -dict {PACKAGE_PIN B35  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_cs_n[0]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B0"   - IO_L20P_T3L_N2_AD1P_47
+set_property -dict {PACKAGE_PIN B34  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_c[0]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_C0"   - IO_L19N_T3L_N1_DBC_AD9N_47
+set_property -dict {PACKAGE_PIN C34  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_t[0]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_T0"   - IO_L19P_T3L_N0_DBC_AD9P_47
+set_property -dict {PACKAGE_PIN J30  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_bg[1]    ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BG1"     - IO_L17N_T2U_N9_AD10N_47
+set_property -dict {PACKAGE_PIN J29  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[3]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR3"    - IO_L17P_T2U_N8_AD10P_47
+#set_property -dict {PACKAGE_PIN D35  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_c[1]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_C1"   - IO_L16N_T2U_N7_QBC_AD3N_47
+#set_property -dict {PACKAGE_PIN D34  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_t[1]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_T1"   - IO_L16P_T2U_N6_QBC_AD3P_47
+#set_property -dict {PACKAGE_PIN E30  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_cke[1]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CKE1"    - IO_T2U_N12_47
+set_property -dict {PACKAGE_PIN D31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[9]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR9"    - IO_L18N_T2U_N11_AD2N_47
+set_property -dict {PACKAGE_PIN E31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[11]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR11"   - IO_L18P_T2U_N10_AD2P_47
+#set_property -dict {PACKAGE_PIN K31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_cs_n[3]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B3"   - IO_L15N_T2L_N5_AD11N_47
+set_property -dict {PACKAGE_PIN K30  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[16]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR16"   - IO_L15P_T2L_N4_AD11P_47
+set_property -dict {PACKAGE_PIN D33  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_ba[0]    ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BA0"     - IO_L14N_T2L_N3_GC_47
+set_property -dict {PACKAGE_PIN E33  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_odt[0]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ODT0"    - IO_L14P_T2L_N2_GC_47
+set_property -dict {PACKAGE_PIN F30  IOSTANDARD LVCMOS12       } [get_ports c2_ddr4_alert_n  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ALERT_B" - IO_L11N_T1U_N9_GC_47
+set_property -dict {PACKAGE_PIN G30  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_cke[0]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CKE0"    - IO_L11P_T1U_N8_GC_47
+set_property -dict {PACKAGE_PIN G32  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[15]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR15"   - IO_L10N_T1U_N7_QBC_AD4N_47
+set_property -dict {PACKAGE_PIN G31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[5]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR5"    - IO_L10P_T1U_N6_QBC_AD4P_47
+#set_property -dict {PACKAGE_PIN J31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_cs_n[1]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B1"   - IO_T1U_N12_47
+#set_property -dict {PACKAGE_PIN F34  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_odt[1]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ODT1"    - IO_L12N_T1U_N11_GC_47
+set_property -dict {PACKAGE_PIN F33  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[13]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR13"   - IO_L12P_T1U_N10_GC_47
+#set_property -dict {PACKAGE_PIN L30  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_cs_n[2]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B2"   - IO_L9N_T1L_N5_AD12N_47
+set_property -dict {PACKAGE_PIN L29  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[0]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR0"    - IO_L9P_T1L_N4_AD12P_47
+#set_property -dict {PACKAGE_PIN H32  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[17]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR17"   - IO_L8N_T1L_N3_AD5N_47
+set_property -dict {PACKAGE_PIN H31  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[4]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR4"    - IO_L8P_T1L_N2_AD5P_47
+set_property -dict {PACKAGE_PIN M30  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_adr[12]  ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR12"   - IO_L7N_T1L_N1_QBC_AD13N_47
+set_property -dict {PACKAGE_PIN M29  IOSTANDARD SSTL12_DCI     } [get_ports c2_ddr4_parity   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_PAR"     - IO_L7P_T1L_N0_QBC_AD13P_47
+set_property -dict {PACKAGE_PIN P30  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[40]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ40"    - IO_L5N_T0U_N9_AD14N_47
+set_property -dict {PACKAGE_PIN R30  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[41]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ41"    - IO_L5P_T0U_N8_AD14P_47
+set_property -dict {PACKAGE_PIN M31  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[10]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_C5"  - IO_L4N_T0U_N7_DBC_AD7N_47
+set_property -dict {PACKAGE_PIN N31  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[10]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_T5"  - IO_L4P_T0U_N6_DBC_AD7P_47
+set_property -dict {PACKAGE_PIN N29  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[43]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ43"    - IO_L6N_T0U_N11_AD6N_47
+set_property -dict {PACKAGE_PIN P29  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[42]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ42"    - IO_L6P_T0U_N10_AD6P_47
+set_property -dict {PACKAGE_PIN N32  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[47]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ47"    - IO_L3N_T0L_N5_AD15N_47
+set_property -dict {PACKAGE_PIN P31  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[46]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ46"    - IO_L3P_T0L_N4_AD15P_47
+set_property -dict {PACKAGE_PIN L32  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[44]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ44"    - IO_L2N_T0L_N3_47
+set_property -dict {PACKAGE_PIN M32  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[45]   ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ45"    - IO_L2P_T0L_N2_47
+set_property -dict {PACKAGE_PIN R31  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[11]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_C14" - IO_L1N_T0L_N1_DBC_47
+set_property -dict {PACKAGE_PIN T30  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[11]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_T14" - IO_L1P_T0L_N0_DBC_47
+set_property -dict {PACKAGE_PIN B37  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[65]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ65"    - IO_L23N_T3U_N9_46
+set_property -dict {PACKAGE_PIN C36  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[64]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ64"    - IO_L23P_T3U_N8_46
+set_property -dict {PACKAGE_PIN A39  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[16]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C8"  - IO_L22N_T3U_N7_DBC_AD0N_46
+set_property -dict {PACKAGE_PIN B39  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[16]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T8"  - IO_L22P_T3U_N6_DBC_AD0P_46
+#set_property -dict {PACKAGE_PIN D40  IOSTANDARD LVCMOS12       } [get_ports c2_ddr4_event_n  ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_EVENT_B" - IO_T3U_N12_46
+set_property -dict {PACKAGE_PIN A38  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[67]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ67"    - IO_L24N_T3U_N11_46
+set_property -dict {PACKAGE_PIN A37  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[66]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ66"    - IO_L24P_T3U_N10_46
+set_property -dict {PACKAGE_PIN C39  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[68]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ68"    - IO_L21N_T3L_N5_AD8N_46
+set_property -dict {PACKAGE_PIN D39  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[69]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ69"    - IO_L21P_T3L_N4_AD8P_46
+set_property -dict {PACKAGE_PIN A40  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[70]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ70"    - IO_L20N_T3L_N3_AD1N_46
+set_property -dict {PACKAGE_PIN B40  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[71]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ71"    - IO_L20P_T3L_N2_AD1P_46
+set_property -dict {PACKAGE_PIN C38  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[17]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C17" - IO_L19N_T3L_N1_DBC_AD9N_46
+set_property -dict {PACKAGE_PIN C37  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[17]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T17" - IO_L19P_T3L_N0_DBC_AD9P_46
+set_property -dict {PACKAGE_PIN E35  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[35]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ35"    - IO_L17N_T2U_N9_AD10N_46
+set_property -dict {PACKAGE_PIN F35  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[32]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ32"    - IO_L17P_T2U_N8_AD10P_46
+set_property -dict {PACKAGE_PIN E40  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[8] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C4"  - IO_L16N_T2U_N7_QBC_AD3N_46
+set_property -dict {PACKAGE_PIN E39  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[8] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T4"  - IO_L16P_T2U_N6_QBC_AD3P_46
+set_property -dict {PACKAGE_PIN D36  IOSTANDARD LVCMOS12       } [get_ports c2_ddr4_reset_n  ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_RESET_N" - IO_T2U_N12_46
+set_property -dict {PACKAGE_PIN D38  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[34]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ34"    - IO_L18N_T2U_N11_AD2N_46
+set_property -dict {PACKAGE_PIN E38  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_dq[33]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ33"    - IO_L18P_T2U_N10_AD2P_46
+set_property -dict {PACKAGE_PIN F38  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_dq[38]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ38"    - IO_L15N_T2L_N5_AD11N_46
+set_property -dict {PACKAGE_PIN G38  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[39]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ39"    - IO_L15P_T2L_N4_AD11P_46
+set_property -dict {PACKAGE_PIN E37  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[37]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ37"    - IO_L14N_T2L_N3_GC_46
+set_property -dict {PACKAGE_PIN E36  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[36]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ36"    - IO_L14P_T2L_N2_GC_46
+set_property -dict {PACKAGE_PIN F37  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[9] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C13" - IO_L13N_T2L_N1_GC_QBC_46
+set_property -dict {PACKAGE_PIN G37  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[9] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T13" - IO_L13P_T2L_N0_GC_QBC_46
+set_property -dict {PACKAGE_PIN G36  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[57]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ57"    - IO_L11N_T1U_N9_GC_46
+set_property -dict {PACKAGE_PIN H36  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[56]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ56"    - IO_L11P_T1U_N8_GC_46
+set_property -dict {PACKAGE_PIN H38  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[14]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C7"  - IO_L10N_T1U_N7_QBC_AD4N_46
+set_property -dict {PACKAGE_PIN J38  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[14]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T7"  - IO_L10P_T1U_N6_QBC_AD4P_46
+set_property -dict {PACKAGE_PIN H37  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[58]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ58"    - IO_L12N_T1U_N11_GC_46
+set_property -dict {PACKAGE_PIN J36  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[59]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ59"    - IO_L12P_T1U_N10_GC_46
+set_property -dict {PACKAGE_PIN G35  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[62]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ62"    - IO_L9N_T1L_N5_AD12N_46
+set_property -dict {PACKAGE_PIN G34  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[63]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ63"    - IO_L9P_T1L_N4_AD12P_46
+set_property -dict {PACKAGE_PIN K38  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[61]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ61"    - IO_L8N_T1L_N3_AD5N_46
+set_property -dict {PACKAGE_PIN K37  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[60]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ60"    - IO_L8P_T1L_N2_AD5P_46
+set_property -dict {PACKAGE_PIN H34  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[15]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C16" - IO_L7N_T1L_N1_QBC_AD13N_46
+set_property -dict {PACKAGE_PIN H33  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[15]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T16" - IO_L7P_T1L_N0_QBC_AD13P_46
+set_property -dict {PACKAGE_PIN K33  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[51]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ51"    - IO_L5N_T0U_N9_AD14N_46
+set_property -dict {PACKAGE_PIN L33  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[50]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ50"    - IO_L5P_T0U_N8_AD14P_46
+set_property -dict {PACKAGE_PIN L36  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[12]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C6"  - IO_L4N_T0U_N7_DBC_AD7N_46
+set_property -dict {PACKAGE_PIN L35  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[12]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T6"  - IO_L4P_T0U_N6_DBC_AD7P_46
+set_property -dict {PACKAGE_PIN J35  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[48]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ48"    - IO_L6N_T0U_N11_AD6N_46
+set_property -dict {PACKAGE_PIN K35  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[49]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ49"    - IO_L6P_T0U_N10_AD6P_46
+set_property -dict {PACKAGE_PIN J34  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[52]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ52"    - IO_L3N_T0L_N5_AD15N_46
+set_property -dict {PACKAGE_PIN J33  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[53]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ53"    - IO_L3P_T0L_N4_AD15P_46
+set_property -dict {PACKAGE_PIN N34  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[54]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ54"    - IO_L2N_T0L_N3_46
+set_property -dict {PACKAGE_PIN P34  IOSTANDARD POD12_DCI      } [get_ports c2_ddr4_dq[55]   ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ55"    - IO_L2P_T0L_N2_46
+set_property -dict {PACKAGE_PIN L34  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[13]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C15" - IO_L1N_T0L_N1_DBC_46
+set_property -dict {PACKAGE_PIN M34  IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[13]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T15" - IO_L1P_T0L_N0_DBC_46
+##
+## DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank
+##     <<<NOTE>>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order:
+##                JEDEC Order   DQS ->  0  9  1 10  2 11  3 12  4 13  5 14  6 15  7 16  8 17
+##                Xil MIG Order DQS ->  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
+##
+set_property -dict {PACKAGE_PIN AR36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[16]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR16"   - IO_L23N_T3U_N9_42
+set_property -dict {PACKAGE_PIN AP36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[15]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR15"   - IO_L23P_T3U_N8_42
+#set_property -dict {PACKAGE_PIN AN34 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[1]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ODT1"    - IO_L22N_T3U_N7_DBC_AD0N_42
+#set_property -dict {PACKAGE_PIN AM34 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[3]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B3"   - IO_L22P_T3U_N6_DBC_AD0P_42
+set_property -dict {PACKAGE_PIN AR33 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[0]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B0"   - IO_T3U_N12_42
+set_property -dict {PACKAGE_PIN AN36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[13]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR13"   - IO_L24N_T3U_N11_42
+#set_property -dict {PACKAGE_PIN AN35 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[17]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR17"   - IO_L24P_T3U_N10_42
+set_property -dict {PACKAGE_PIN AP35 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[14]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR14"   - IO_L21N_T3L_N5_AD8N_42
+set_property -dict {PACKAGE_PIN AP34 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[0]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ODT0"    - IO_L21P_T3L_N4_AD8P_42
+#set_property -dict {PACKAGE_PIN AP33 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[1]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B1"   - IO_L20N_T3L_N3_AD1N_42
+#set_property -dict {PACKAGE_PIN AN33 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[2]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B2"   - IO_L20P_T3L_N2_AD1P_42
+set_property -dict {PACKAGE_PIN AT35 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[0]    ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BA0"     - IO_L19N_T3L_N1_DBC_AD9N_42
+set_property -dict {PACKAGE_PIN AR35 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[10]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR10"   - IO_L19P_T3L_N0_DBC_AD9P_42
+set_property -dict {PACKAGE_PIN AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[0]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_C0"   - IO_L17N_T2U_N9_AD10N_42
+set_property -dict {PACKAGE_PIN AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[0]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_T0"   - IO_L17P_T2U_N8_AD10P_42
+#set_property -dict {PACKAGE_PIN AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[1]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_C1"   - IO_L16N_T2U_N7_QBC_AD3N_42
+#set_property -dict {PACKAGE_PIN AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[1]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_T1"   - IO_L16P_T2U_N6_QBC_AD3P_42
+set_property -dict {PACKAGE_PIN AT34 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[1]    ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BA1"     - IO_T2U_N12_42
+set_property -dict {PACKAGE_PIN AU36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_parity   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_PAR"     - IO_L18N_T2U_N11_AD2N_42
+set_property -dict {PACKAGE_PIN AT36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[0]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR0"    - IO_L18P_T2U_N10_AD2P_42
+set_property -dict {PACKAGE_PIN AV37 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[2]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR2"    - IO_L15N_T2L_N5_AD11N_42
+set_property -dict {PACKAGE_PIN AV36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[1]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR1"    - IO_L15P_T2L_N4_AD11P_42
+set_property -dict {PACKAGE_PIN AW36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[4]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR4"    - IO_L14N_T2L_N3_GC_42
+set_property -dict {PACKAGE_PIN AW35 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[3]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR3"    - IO_L14P_T2L_N2_GC_42
+set_property -dict {PACKAGE_PIN BA38 IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_alert_n  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L11N_T1U_N9_GC_42
+set_property -dict {PACKAGE_PIN BA37 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[8]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR8"    - IO_L11P_T1U_N8_GC_42
+set_property -dict {PACKAGE_PIN BA40 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[7]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR7"    - IO_L10N_T1U_N7_QBC_AD4N_42
+set_property -dict {PACKAGE_PIN BA39 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[11]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR11"   - IO_L10P_T1U_N6_QBC_AD4P_42
+set_property -dict {PACKAGE_PIN BB37 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[9]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR9"    - IO_T1U_N12_42
+set_property -dict {PACKAGE_PIN AY36 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[5]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR5"    - IO_L12N_T1U_N11_GC_42
+set_property -dict {PACKAGE_PIN AY35 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[6]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR6"    - IO_L12P_T1U_N10_GC_42
+#set_property -dict {PACKAGE_PIN BC40 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[1]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CKE1"    - IO_L9N_T1L_N5_AD12N_42
+set_property -dict {PACKAGE_PIN BC39 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[1]    ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BG1"     - IO_L9P_T1L_N4_AD12P_42
+set_property -dict {PACKAGE_PIN BB40 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[12]  ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR12"   - IO_L8N_T1L_N3_AD5N_42
+set_property -dict {PACKAGE_PIN BB39 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_act_n    ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ACT_B"   - IO_L8P_T1L_N2_AD5P_42
+set_property -dict {PACKAGE_PIN BC38 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[0]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CKE0"    - IO_L7N_T1L_N1_QBC_AD13N_42
+set_property -dict {PACKAGE_PIN BC37 IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[0]    ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BG0"     - IO_L7P_T1L_N0_QBC_AD13P_42
+set_property -dict {PACKAGE_PIN BF43 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[66]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ66"    - IO_L5N_T0U_N9_AD14N_42
+set_property -dict {PACKAGE_PIN BF42 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[67]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ67"    - IO_L5P_T0U_N8_AD14P_42
+set_property -dict {PACKAGE_PIN BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[16]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8"  - IO_L4N_T0U_N7_DBC_AD7N_42
+set_property -dict {PACKAGE_PIN BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[16]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8"  - IO_L4P_T0U_N6_DBC_AD7P_42
+set_property -dict {PACKAGE_PIN BD40 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[64]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ64"    - IO_L6N_T0U_N11_AD6N_42
+set_property -dict {PACKAGE_PIN BD39 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[65]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ65"    - IO_L6P_T0U_N10_AD6P_42
+set_property -dict {PACKAGE_PIN BF41 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[71]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ71"    - IO_L3N_T0L_N5_AD15N_42
+set_property -dict {PACKAGE_PIN BE40 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[70]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ70"    - IO_L3P_T0L_N4_AD15P_42
+set_property -dict {PACKAGE_PIN BF37 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[68]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ68"    - IO_L2N_T0L_N3_42
+set_property -dict {PACKAGE_PIN BE37 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[69]   ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ69"    - IO_L2P_T0L_N2_42
+set_property -dict {PACKAGE_PIN BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[17]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L1N_T0L_N1_DBC_42
+set_property -dict {PACKAGE_PIN BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[17]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L1P_T0L_N0_DBC_42
+set_property -dict {PACKAGE_PIN AU32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[34]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ34"    - IO_L23N_T3U_N9_41
+set_property -dict {PACKAGE_PIN AT32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[35]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ35"    - IO_L23P_T3U_N8_41
+set_property -dict {PACKAGE_PIN AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[8] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4"  - IO_L22N_T3U_N7_DBC_AD0N_41
+set_property -dict {PACKAGE_PIN AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[8] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4"  - IO_L22P_T3U_N6_DBC_AD0P_41
+#set_property -dict {PACKAGE_PIN AT33 IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_event_n  ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_41
+set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[33]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ33"    - IO_L24N_T3U_N11_41
+set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[32]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ32"    - IO_L24P_T3U_N10_41
+set_property -dict {PACKAGE_PIN AR32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[38]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ38"    - IO_L21N_T3L_N5_AD8N_41
+set_property -dict {PACKAGE_PIN AR31 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[39]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ39"    - IO_L21P_T3L_N4_AD8P_41
+set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[37]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ37"    - IO_L20N_T3L_N3_AD1N_41
+set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[36]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ36"    - IO_L20P_T3L_N2_AD1P_41
+set_property -dict {PACKAGE_PIN AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[9] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L19N_T3L_N1_DBC_AD9N_41
+set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[9] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L19P_T3L_N0_DBC_AD9P_41
+set_property -dict {PACKAGE_PIN AV32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[25]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ25"    - IO_L17N_T2U_N9_AD10N_41
+set_property -dict {PACKAGE_PIN AV31 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[24]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ24"    - IO_L17P_T2U_N8_AD10P_41
+set_property -dict {PACKAGE_PIN AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[6] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3"  - IO_L16N_T2U_N7_QBC_AD3N_41
+set_property -dict {PACKAGE_PIN AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[6] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3"  - IO_L16P_T2U_N6_QBC_AD3P_41
+set_property -dict {PACKAGE_PIN AU31 IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_reset_n  ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_41
+set_property -dict {PACKAGE_PIN AW34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[27]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ27"    - IO_L18N_T2U_N11_AD2N_41
+set_property -dict {PACKAGE_PIN AV34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[26]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ26"    - IO_L18P_T2U_N10_AD2P_41
+set_property -dict {PACKAGE_PIN AY31 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[29]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ29"    - IO_L15N_T2L_N5_AD11N_41
+set_property -dict {PACKAGE_PIN AW31 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[28]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ28"    - IO_L15P_T2L_N4_AD11P_41
+set_property -dict {PACKAGE_PIN BA35 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[30]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ30"    - IO_L14N_T2L_N3_GC_41
+set_property -dict {PACKAGE_PIN BA34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[31]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ31"    - IO_L14P_T2L_N2_GC_41
+set_property -dict {PACKAGE_PIN BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_41
+set_property -dict {PACKAGE_PIN BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_41
+set_property -dict {PACKAGE_PIN BB32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[17]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ17"    - IO_L11N_T1U_N9_GC_41
+set_property -dict {PACKAGE_PIN BB31 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[16]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ16"    - IO_L11P_T1U_N8_GC_41
+set_property -dict {PACKAGE_PIN BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[4] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2"  - IO_L10N_T1U_N7_QBC_AD4N_41
+set_property -dict {PACKAGE_PIN BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[4] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2"  - IO_L10P_T1U_N6_QBC_AD4P_41
+set_property -dict {PACKAGE_PIN AY33 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[19]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ19"    - IO_L12N_T1U_N11_GC_41
+set_property -dict {PACKAGE_PIN AY32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[18]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ18"    - IO_L12P_T1U_N10_GC_41
+set_property -dict {PACKAGE_PIN BC33 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[21]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ21"    - IO_L9N_T1L_N5_AD12N_41
+set_property -dict {PACKAGE_PIN BC32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[20]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ20"    - IO_L9P_T1L_N4_AD12P_41
+set_property -dict {PACKAGE_PIN BC34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[23]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ23"    - IO_L8N_T1L_N3_AD5N_41
+set_property -dict {PACKAGE_PIN BB34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[22]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ22"    - IO_L8P_T1L_N2_AD5P_41
+set_property -dict {PACKAGE_PIN BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_41
+set_property -dict {PACKAGE_PIN BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_41
+set_property -dict {PACKAGE_PIN BE33 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[58]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ58"    - IO_L5N_T0U_N9_AD14N_41
+set_property -dict {PACKAGE_PIN BD33 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[57]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ57"    - IO_L5P_T0U_N8_AD14P_41
+set_property -dict {PACKAGE_PIN BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[14]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7"  - IO_L4N_T0U_N7_DBC_AD7N_41
+set_property -dict {PACKAGE_PIN BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[14]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7"  - IO_L4P_T0U_N6_DBC_AD7P_41
+set_property -dict {PACKAGE_PIN BD35 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[59]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ59"    - IO_L6N_T0U_N11_AD6N_41
+set_property -dict {PACKAGE_PIN BD34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[56]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ56"    - IO_L6P_T0U_N10_AD6P_41
+set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[61]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ61"    - IO_L3N_T0L_N5_AD15N_41
+set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[60]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ60"    - IO_L3P_T0L_N4_AD15P_41
+set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[63]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ63"    - IO_L2N_T0L_N3_41
+set_property -dict {PACKAGE_PIN BF34 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[62]   ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ62"    - IO_L2P_T0L_N2_41
+set_property -dict {PACKAGE_PIN BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[15]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_41
+set_property -dict {PACKAGE_PIN BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[15]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_41
+set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[40]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ40"    - IO_L23N_T3U_N9_40
+set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[41]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ41"    - IO_L23P_T3U_N8_40
+set_property -dict {PACKAGE_PIN AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[10]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5"  - IO_L22N_T3U_N7_DBC_AD0N_40
+set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[10]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5"  - IO_L22P_T3U_N6_DBC_AD0P_40
+set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[42]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ42"    - IO_L24N_T3U_N11_40
+set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[43]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ43"    - IO_L24P_T3U_N10_40
+set_property -dict {PACKAGE_PIN AR28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[47]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ47"    - IO_L21N_T3L_N5_AD8N_40
+set_property -dict {PACKAGE_PIN AR27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[46]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ46"    - IO_L21P_T3L_N4_AD8P_40
+set_property -dict {PACKAGE_PIN AN29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[44]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ44"    - IO_L20N_T3L_N3_AD1N_40
+set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[45]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ45"    - IO_L20P_T3L_N2_AD1P_40
+set_property -dict {PACKAGE_PIN AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[11]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_40
+set_property -dict {PACKAGE_PIN AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[11]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_40
+set_property -dict {PACKAGE_PIN AV27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[49]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ49"    - IO_L17N_T2U_N9_AD10N_40
+set_property -dict {PACKAGE_PIN AU27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[50]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ50"    - IO_L17P_T2U_N8_AD10P_40
+set_property -dict {PACKAGE_PIN AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[12]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6"  - IO_L16N_T2U_N7_QBC_AD3N_40
+set_property -dict {PACKAGE_PIN AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[12]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6"  - IO_L16P_T2U_N6_QBC_AD3P_40
+set_property -dict {PACKAGE_PIN AT28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[48]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ48"    - IO_L18N_T2U_N11_AD2N_40
+set_property -dict {PACKAGE_PIN AT27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[51]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ51"    - IO_L18P_T2U_N10_AD2P_40
+set_property -dict {PACKAGE_PIN AV29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[52]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ52"    - IO_L15N_T2L_N5_AD11N_40
+set_property -dict {PACKAGE_PIN AV28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[55]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ55"    - IO_L15P_T2L_N4_AD11P_40
+set_property -dict {PACKAGE_PIN AY30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[53]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ53"    - IO_L14N_T2L_N3_GC_40
+set_property -dict {PACKAGE_PIN AW30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[54]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ54"    - IO_L14P_T2L_N2_GC_40
+set_property -dict {PACKAGE_PIN AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[13]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L13N_T2L_N1_GC_QBC_40
+set_property -dict {PACKAGE_PIN AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[13]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L13P_T2L_N0_GC_QBC_40
+set_property -dict {PACKAGE_PIN BA28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[2]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ2"     - IO_L11N_T1U_N9_GC_40
+set_property -dict {PACKAGE_PIN BA27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[3]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ3"     - IO_L11P_T1U_N8_GC_40
+set_property -dict {PACKAGE_PIN BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[0] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0"  - IO_L10N_T1U_N7_QBC_AD4N_40
+set_property -dict {PACKAGE_PIN BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[0] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0"  - IO_L10P_T1U_N6_QBC_AD4P_40
+set_property -dict {PACKAGE_PIN AW29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[1]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ1"     - IO_L12N_T1U_N11_GC_40
+set_property -dict {PACKAGE_PIN AW28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[0]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ0"     - IO_L12P_T1U_N10_GC_40
+set_property -dict {PACKAGE_PIN BC27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[6]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ6"     - IO_L9N_T1L_N5_AD12N_40
+set_property -dict {PACKAGE_PIN BB27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[7]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ7"     - IO_L9P_T1L_N4_AD12P_40
+set_property -dict {PACKAGE_PIN BB29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[4]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ4"     - IO_L8N_T1L_N3_AD5N_40
+set_property -dict {PACKAGE_PIN BA29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[5]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ5"     - IO_L8P_T1L_N2_AD5P_40
+set_property -dict {PACKAGE_PIN BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9"  - IO_L7N_T1L_N1_QBC_AD13N_40
+set_property -dict {PACKAGE_PIN BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9"  - IO_L7P_T1L_N0_QBC_AD13P_40
+set_property -dict {PACKAGE_PIN BF28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[9]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ9"     - IO_L5N_T0U_N9_AD14N_40
+set_property -dict {PACKAGE_PIN BE28 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[8]    ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ8"     - IO_L5P_T0U_N8_AD14P_40
+set_property -dict {PACKAGE_PIN BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[2] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1"  - IO_L4N_T0U_N7_DBC_AD7N_40
+set_property -dict {PACKAGE_PIN BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[2] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1"  - IO_L4P_T0U_N6_DBC_AD7P_40
+set_property -dict {PACKAGE_PIN BE30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[10]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ10"    - IO_L6N_T0U_N11_AD6N_40
+set_property -dict {PACKAGE_PIN BD30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[11]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ11"    - IO_L6P_T0U_N10_AD6P_40
+set_property -dict {PACKAGE_PIN BF27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[12]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ12"    - IO_L3N_T0L_N5_AD15N_40
+set_property -dict {PACKAGE_PIN BE27 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[13]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ13"    - IO_L3P_T0L_N4_AD15P_40
+set_property -dict {PACKAGE_PIN BF30 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[14]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ14"    - IO_L2N_T0L_N3_40
+set_property -dict {PACKAGE_PIN BF29 IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[15]   ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ15"    - IO_L2P_T0L_N2_40
+set_property -dict {PACKAGE_PIN BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L1N_T0L_N1_DBC_40
+set_property -dict {PACKAGE_PIN BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L1P_T0L_N0_DBC_40
+#
+# MGT Connections
+#
+#set_property PACKAGE_PIN N3  [get_ports QSFP0_RX1_N]; # Bank 231  - MGTYRXN0_231
+#set_property PACKAGE_PIN N4  [get_ports QSFP0_RX1_P]; # Bank 231  - MGTYRXP0_231
+#set_property PACKAGE_PIN M1  [get_ports QSFP0_RX2_N]; # Bank 231  - MGTYRXN1_231
+#set_property PACKAGE_PIN M2  [get_ports QSFP0_RX2_P]; # Bank 231  - MGTYRXP1_231
+#set_property PACKAGE_PIN L3  [get_ports QSFP0_RX3_N]; # Bank 231  - MGTYRXN2_231
+#set_property PACKAGE_PIN L4  [get_ports QSFP0_RX3_P]; # Bank 231  - MGTYRXP2_231
+#set_property PACKAGE_PIN K1  [get_ports QSFP0_RX4_N]; # Bank 231  - MGTYRXN3_231
+#set_property PACKAGE_PIN K2  [get_ports QSFP0_RX4_P]; # Bank 231  - MGTYRXP3_231
+#set_property PACKAGE_PIN N8  [get_ports QSFP0_TX1_N]; # Bank 231  - MGTYTXN0_231
+#set_property PACKAGE_PIN N9  [get_ports QSFP0_TX1_P]; # Bank 231  - MGTYTXP0_231
+#set_property PACKAGE_PIN M6  [get_ports QSFP0_TX2_N]; # Bank 231  - MGTYTXN1_231
+#set_property PACKAGE_PIN M7  [get_ports QSFP0_TX2_P]; # Bank 231  - MGTYTXP1_231
+#set_property PACKAGE_PIN L8  [get_ports QSFP0_TX3_N]; # Bank 231  - MGTYTXN2_231
+#set_property PACKAGE_PIN L9  [get_ports QSFP0_TX3_P]; # Bank 231  - MGTYTXP2_231
+#set_property PACKAGE_PIN K6  [get_ports QSFP0_TX4_N]; # Bank 231  - MGTYTXN3_231
+#set_property PACKAGE_PIN K7  [get_ports QSFP0_TX4_P]; # Bank 231  - MGTYTXP3_231
+#set_property PACKAGE_PIN U3  [get_ports QSFP1_RX1_N]; # Bank 230  - MGTYRXN0_230
+#set_property PACKAGE_PIN U4  [get_ports QSFP1_RX1_P]; # Bank 230  - MGTYRXP0_230
+#set_property PACKAGE_PIN T1  [get_ports QSFP1_RX2_N]; # Bank 230  - MGTYRXN1_230
+#set_property PACKAGE_PIN T2  [get_ports QSFP1_RX2_P]; # Bank 230  - MGTYRXP1_230
+#set_property PACKAGE_PIN R3  [get_ports QSFP1_RX3_N]; # Bank 230  - MGTYRXN2_230
+#set_property PACKAGE_PIN R4  [get_ports QSFP1_RX3_P]; # Bank 230  - MGTYRXP2_230
+#set_property PACKAGE_PIN P1  [get_ports QSFP1_RX4_N]; # Bank 230  - MGTYRXN3_230
+#set_property PACKAGE_PIN P2  [get_ports QSFP1_RX4_P]; # Bank 230  - MGTYRXP3_230
+#set_property PACKAGE_PIN U8  [get_ports QSFP1_TX1_N]; # Bank 230  - MGTYTXN0_230
+#set_property PACKAGE_PIN U9  [get_ports QSFP1_TX1_P]; # Bank 230  - MGTYTXP0_230
+#set_property PACKAGE_PIN T6  [get_ports QSFP1_TX2_N]; # Bank 230  - MGTYTXN1_230
+#set_property PACKAGE_PIN T7  [get_ports QSFP1_TX2_P]; # Bank 230  - MGTYTXP1_230
+#set_property PACKAGE_PIN R8  [get_ports QSFP1_TX3_N]; # Bank 230  - MGTYTXN2_230
+#set_property PACKAGE_PIN R9  [get_ports QSFP1_TX3_P]; # Bank 230  - MGTYTXP2_230
+#set_property PACKAGE_PIN P6  [get_ports QSFP1_TX4_N]; # Bank 230  - MGTYTXN3_230
+#set_property PACKAGE_PIN P7  [get_ports QSFP1_TX4_P]; # Bank 230  - MGTYTXP3_230
+#set_property PACKAGE_PIN AF1 [get_ports PEX_RX0_N  ]; # Bank 227  - MGTYRXN3_227
+#set_property PACKAGE_PIN AF2 [get_ports PEX_RX0_P  ]; # Bank 227  - MGTYRXP3_227
+#set_property PACKAGE_PIN AG3 [get_ports PEX_RX1_N  ]; # Bank 227  - MGTYRXN2_227
+#set_property PACKAGE_PIN AG4 [get_ports PEX_RX1_P  ]; # Bank 227  - MGTYRXP2_227
+#set_property PACKAGE_PIN AH1 [get_ports PEX_RX2_N  ]; # Bank 227  - MGTYRXN1_227
+#set_property PACKAGE_PIN AH2 [get_ports PEX_RX2_P  ]; # Bank 227  - MGTYRXP1_227
+#set_property PACKAGE_PIN AJ3 [get_ports PEX_RX3_N  ]; # Bank 227  - MGTYRXN0_227
+#set_property PACKAGE_PIN AJ4 [get_ports PEX_RX3_P  ]; # Bank 227  - MGTYRXP0_227
+#set_property PACKAGE_PIN AF6 [get_ports PEX_TX0_N  ]; # Bank 227  - MGTYTXN3_227
+#set_property PACKAGE_PIN AF7 [get_ports PEX_TX0_P  ]; # Bank 227  - MGTYTXP3_227
+#set_property PACKAGE_PIN AG8 [get_ports PEX_TX1_N  ]; # Bank 227  - MGTYTXN2_227
+#set_property PACKAGE_PIN AG9 [get_ports PEX_TX1_P  ]; # Bank 227  - MGTYTXP2_227
+#set_property PACKAGE_PIN AH6 [get_ports PEX_TX2_N  ]; # Bank 227  - MGTYTXN1_227
+#set_property PACKAGE_PIN AH7 [get_ports PEX_TX2_P  ]; # Bank 227  - MGTYTXP1_227
+#set_property PACKAGE_PIN AJ8 [get_ports PEX_TX3_N  ]; # Bank 227  - MGTYTXN0_227
+#set_property PACKAGE_PIN AJ9 [get_ports PEX_TX3_P  ]; # Bank 227  - MGTYTXP0_227
+#set_property PACKAGE_PIN AK1 [get_ports PEX_RX4_N  ]; # Bank 226  - MGTYRXN3_226
+#set_property PACKAGE_PIN AK2 [get_ports PEX_RX4_P  ]; # Bank 226  - MGTYRXP3_226
+#set_property PACKAGE_PIN AL3 [get_ports PEX_RX5_N  ]; # Bank 226  - MGTYRXN2_226
+#set_property PACKAGE_PIN AL4 [get_ports PEX_RX5_P  ]; # Bank 226  - MGTYRXP2_226
+#set_property PACKAGE_PIN AM1 [get_ports PEX_RX6_N  ]; # Bank 226  - MGTYRXN1_226
+#set_property PACKAGE_PIN AM2 [get_ports PEX_RX6_P  ]; # Bank 226  - MGTYRXP1_226
+#set_property PACKAGE_PIN AN3 [get_ports PEX_RX7_N  ]; # Bank 226  - MGTYRXN0_226
+#set_property PACKAGE_PIN AN4 [get_ports PEX_RX7_P  ]; # Bank 226  - MGTYRXP0_226
+#set_property PACKAGE_PIN AK6 [get_ports PEX_TX4_N  ]; # Bank 226  - MGTYTXN3_226
+#set_property PACKAGE_PIN AK7 [get_ports PEX_TX4_P  ]; # Bank 226  - MGTYTXP3_226
+#set_property PACKAGE_PIN AL8 [get_ports PEX_TX5_N  ]; # Bank 226  - MGTYTXN2_226
+#set_property PACKAGE_PIN AL9 [get_ports PEX_TX5_P  ]; # Bank 226  - MGTYTXP2_226
+#set_property PACKAGE_PIN AM6 [get_ports PEX_TX6_N  ]; # Bank 226  - MGTYTXN1_226
+#set_property PACKAGE_PIN AM7 [get_ports PEX_TX6_P  ]; # Bank 226  - MGTYTXP1_226
+#set_property PACKAGE_PIN AN8 [get_ports PEX_TX7_N  ]; # Bank 226  - MGTYTXN0_226
+#set_property PACKAGE_PIN AN9 [get_ports PEX_TX7_P  ]; # Bank 226  - MGTYTXP0_226
+#set_property PACKAGE_PIN AT1 [get_ports PEX_RX10_N ]; # Bank 225  - MGTYRXN1_225
+#set_property PACKAGE_PIN AT2 [get_ports PEX_RX10_P ]; # Bank 225  - MGTYRXP1_225
+#set_property PACKAGE_PIN AU3 [get_ports PEX_RX11_N ]; # Bank 225  - MGTYRXN0_225
+#set_property PACKAGE_PIN AU4 [get_ports PEX_RX11_P ]; # Bank 225  - MGTYRXP0_225
+#set_property PACKAGE_PIN AP1 [get_ports PEX_RX8_N  ]; # Bank 225  - MGTYRXN3_225
+#set_property PACKAGE_PIN AP2 [get_ports PEX_RX8_P  ]; # Bank 225  - MGTYRXP3_225
+#set_property PACKAGE_PIN AR3 [get_ports PEX_RX9_N  ]; # Bank 225  - MGTYRXN2_225
+#set_property PACKAGE_PIN AR4 [get_ports PEX_RX9_P  ]; # Bank 225  - MGTYRXP2_225
+#set_property PACKAGE_PIN AT6 [get_ports PEX_TX10_N ]; # Bank 225  - MGTYTXN1_225
+#set_property PACKAGE_PIN AT7 [get_ports PEX_TX10_P ]; # Bank 225  - MGTYTXP1_225
+#set_property PACKAGE_PIN AU8 [get_ports PEX_TX11_N ]; # Bank 225  - MGTYTXN0_225
+#set_property PACKAGE_PIN AU9 [get_ports PEX_TX11_P ]; # Bank 225  - MGTYTXP0_225
+#set_property PACKAGE_PIN AP6 [get_ports PEX_TX8_N  ]; # Bank 225  - MGTYTXN3_225
+#set_property PACKAGE_PIN AP7 [get_ports PEX_TX8_P  ]; # Bank 225  - MGTYTXP3_225
+#set_property PACKAGE_PIN AR8 [get_ports PEX_TX9_N  ]; # Bank 225  - MGTYTXN2_225
+#set_property PACKAGE_PIN AR9 [get_ports PEX_TX9_P  ]; # Bank 225  - MGTYTXP2_225
+#set_property PACKAGE_PIN AV1 [get_ports PEX_RX12_N ]; # Bank 224  - MGTYRXN3_224
+#set_property PACKAGE_PIN AV2 [get_ports PEX_RX12_P ]; # Bank 224  - MGTYRXP3_224
+#set_property PACKAGE_PIN AW3 [get_ports PEX_RX13_N ]; # Bank 224  - MGTYRXN2_224
+#set_property PACKAGE_PIN AW4 [get_ports PEX_RX13_P ]; # Bank 224  - MGTYRXP2_224
+#set_property PACKAGE_PIN BA1 [get_ports PEX_RX14_N ]; # Bank 224  - MGTYRXN1_224
+#set_property PACKAGE_PIN BA2 [get_ports PEX_RX14_P ]; # Bank 224  - MGTYRXP1_224
+#set_property PACKAGE_PIN BC1 [get_ports PEX_RX15_N ]; # Bank 224  - MGTYRXN0_224
+#set_property PACKAGE_PIN BC2 [get_ports PEX_RX15_P ]; # Bank 224  - MGTYRXP0_224
+#set_property PACKAGE_PIN AV6 [get_ports PEX_TX12_N ]; # Bank 224  - MGTYTXN3_224
+#set_property PACKAGE_PIN AV7 [get_ports PEX_TX12_P ]; # Bank 224  - MGTYTXP3_224
+#set_property PACKAGE_PIN BB4 [get_ports PEX_TX13_N ]; # Bank 224  - MGTYTXN2_224
+#set_property PACKAGE_PIN BB5 [get_ports PEX_TX13_P ]; # Bank 224  - MGTYTXP2_224
+#set_property PACKAGE_PIN BD4 [get_ports PEX_TX14_N ]; # Bank 224  - MGTYTXN1_224
+#set_property PACKAGE_PIN BD5 [get_ports PEX_TX14_P ]; # Bank 224  - MGTYTXP1_224
+#set_property PACKAGE_PIN BF4 [get_ports PEX_TX15_N ]; # Bank 224  - MGTYTXN0_224
+#set_property PACKAGE_PIN BF5 [get_ports PEX_TX15_P ]; # Bank 224  - MGTYTXP0_224
diff --git a/projects/U200/apply_patches.sh b/projects/U200/apply_patches.sh
new file mode 100755
index 0000000..9cdff77
--- /dev/null
+++ b/projects/U200/apply_patches.sh
@@ -0,0 +1,10 @@
+# some of the generated files have CR characters in additon to EOL characters
+# which mess with our patch commands.
+dos2unix U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv
+dos2unix U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv
+
+for f in ./patches/*.patch
+do
+    patch -p0 < $f
+done
+
diff --git a/projects/U200/coe/pr_read.coe b/projects/U200/coe/pr_read.coe
new file mode 100644
index 0000000..b9ccb93
--- /dev/null
+++ b/projects/U200/coe/pr_read.coe
@@ -0,0 +1,15 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+0001100000000000000000000000000000000000010000000000000000000000,
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+1111000000000000111100000000000011110000000000001001000001000101,
+1111000000000000111100000000000011110000000000001111000000000000;
diff --git a/projects/U200/coe/pr_ref.coe b/projects/U200/coe/pr_ref.coe
new file mode 100644
index 0000000..8b0a9e1
--- /dev/null
+++ b/projects/U200/coe/pr_ref.coe
@@ -0,0 +1,51 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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diff --git a/projects/U200/coe/pr_zq.coe b/projects/U200/coe/pr_zq.coe
new file mode 100644
index 0000000..16d563c
--- /dev/null
+++ b/projects/U200/coe/pr_zq.coe
@@ -0,0 +1,42 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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diff --git a/projects/U200/coe/simmem.coe b/projects/U200/coe/simmem.coe
new file mode 100644
index 0000000..90d215f
--- /dev/null
+++ b/projects/U200/coe/simmem.coe
@@ -0,0 +1,398 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
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+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001100001000111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001010000000000111,
+0000000000000001000000000000000000000000011000000000000000010110,
+0100000000000000000000000000000000000000000000000001110010000110,
+0000000000000001000000000000000000000000011100000000000000010111,
+0100000000000000000000000000000000000000000000000001101110110111,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+0000000000000110000000000000000000000000110100000000000011110000,
+0000000000000110000000000000000000000000111000000000000000000000,
+0000000000000110000000000000000000000000111100000000000000000000,
+0000000000000000000000000000000000000000000000000000000000000001,
+1111000000000000111100000000000011110000000000001010100000001101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001011000011101101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001000000011111101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000011111101,
+0000000000000111000000000000000000000000000000000000000000000000,
+0000000000000111000000000000000000000000000100000000000000000001,
+0000000000000111000000000000000000000000001000000000000000000010,
+0000000000000111000000000000000000000000001100000000000000000011,
+0000000000000111000000000000000000000000010000000000000000000100,
+0000000000000111000000000000000000000000010100000000000000000101,
+0000000000000111000000000000000000000000011000000000000000000110,
+0000000000000111000000000000000000000000011100000000000000000111,
+0000000000000111000000000000000000000000100000000000000000001000,
+0000000000000111000000000000000000000000100100000000000000001001,
+0000000000000111000000000000000000000000101000000000000000001010,
+0000000000000111000000000000000000000000101100000000000000001011,
+0000000000000111000000000000000000000000110000000000000000001100,
+0000000000000111000000000000000000000000110100000000000000001101,
+0000000000000111000000000000000000000000111000000000000000001110,
+0000000000000111000000000000000000000000111100000000000000001111,
+0000000000000000000000000000000000000000000000000000000000000001,
+1111000000000000111100000000000011110000000000001000000011111101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001001000011111101,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001111000000000000,
+1111000000000000111100000000000011110000000000001010100000001101,
+0000000000000000000000000000000000000000000000000000000000000000;
\ No newline at end of file
diff --git a/projects/U200/constraints/C1_RDIMM_X8_DUAL.xdc b/projects/U200/constraints/C1_RDIMM_X8_DUAL.xdc
new file mode 100644
index 0000000..33f9bd2
--- /dev/null
+++ b/projects/U200/constraints/C1_RDIMM_X8_DUAL.xdc
@@ -0,0 +1,220 @@
+set_property DRIVE 8 [get_ports c0_ddr4_reset_n]
+create_clock -period 3.333 [get_ports c0_sys_clk_p]
+set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks]
+create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p]
+set_clock_groups -asynchronous -group [get_clocks refclk_100 -include_generated_clocks]
+
+set_property -dict {PACKAGE_PIN P24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[0]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ0"       - IO_L5P_T0U_N8_AD14P_72
+set_property -dict {PACKAGE_PIN N24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[1]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ1"       - IO_L5N_T0U_N9_AD14N_72
+set_property -dict {PACKAGE_PIN T24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[2]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ2"       - IO_L6P_T0U_N10_AD6P_72
+set_property -dict {PACKAGE_PIN R23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[3]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ3"       - IO_L6N_T0U_N11_AD6N_72
+set_property -dict {PACKAGE_PIN N23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[4]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ4"       - IO_L3N_T0L_N5_AD15N_72
+set_property -dict {PACKAGE_PIN P21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[5]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ5"       - IO_L2N_T0L_N3_72
+set_property -dict {PACKAGE_PIN P23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[6]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ6"       - IO_L3P_T0L_N4_AD15P_72
+set_property -dict {PACKAGE_PIN R21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[7]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ7"       - IO_L2P_T0L_N2_72
+set_property -dict {PACKAGE_PIN R22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C0"    - IO_L4N_T0U_N7_DBC_AD7N_72
+set_property -dict {PACKAGE_PIN T22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T0"    - IO_L4P_T0U_N6_DBC_AD7P_72
+
+set_property -dict {PACKAGE_PIN G20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[64]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ16"      - IO_L11P_T1U_N8_GC_71
+set_property -dict {PACKAGE_PIN H17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[65]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ17"      - IO_L12P_T1U_N10_GC_71
+set_property -dict {PACKAGE_PIN F19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[66]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ18"      - IO_L11N_T1U_N9_GC_71
+set_property -dict {PACKAGE_PIN G17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[67]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ19"      - IO_L12N_T1U_N11_GC_71
+set_property -dict {PACKAGE_PIN J20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[68]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ20"      - IO_L9P_T1L_N4_AD12P_71
+set_property -dict {PACKAGE_PIN L19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[69]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ21"      - IO_L8P_T1L_N2_AD5P_71
+set_property -dict {PACKAGE_PIN L18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[70]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ22"      - IO_L8N_T1L_N3_AD5N_71
+set_property -dict {PACKAGE_PIN J19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[71]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ23"      - IO_L9N_T1L_N5_AD12N_71
+set_property -dict {PACKAGE_PIN K20  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[8] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C2"    - IO_L10N_T1U_N7_QBC_AD4N_71
+set_property -dict {PACKAGE_PIN L20  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[8] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T2"    - IO_L10P_T1U_N6_QBC_AD4P_71
+set_property -dict {PACKAGE_PIN K18  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[8]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T14"   - IO_L19P_T3L_N0_DBC_AD9P_71
+
+set_property -dict {PACKAGE_PIN M16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[16]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ64"     - IO_L6N_T0U_N11_AD6N_70
+set_property -dict {PACKAGE_PIN N16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[17]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ65"     - IO_L6P_T0U_N10_AD6P_70
+set_property -dict {PACKAGE_PIN N13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[18]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ66"     - IO_L5N_T0U_N9_AD14N_70
+set_property -dict {PACKAGE_PIN N14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[19]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ67"     - IO_L5P_T0U_N8_AD14P_70
+set_property -dict {PACKAGE_PIN T15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[20]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ68"     - IO_L2P_T0L_N2_70
+set_property -dict {PACKAGE_PIN R15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[21]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ69"     - IO_L2N_T0L_N3_70
+set_property -dict {PACKAGE_PIN P13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[22]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ70"     - IO_L3N_T0L_N5_AD15N_70
+set_property -dict {PACKAGE_PIN P14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[23]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ71"     - IO_L3P_T0L_N4_AD15P_70
+set_property -dict {PACKAGE_PIN P15  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[2]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_70
+set_property -dict {PACKAGE_PIN R16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[2]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_70
+set_property -dict {PACKAGE_PIN T13  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[2]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T17"  - IO_L1P_T0L_N0_DBC_70        
+
+set_property -dict {PACKAGE_PIN H16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_sys_clk_n    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_N" - IO_L13N_T2L_N1_GC_QBC_70
+set_property -dict {PACKAGE_PIN J16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_sys_clk_p    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_P" - IO_L13P_T2L_N0_GC_QBC_70
+
+set_property -dict {PACKAGE_PIN B24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[34]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ34"      - IO_L23N_T3U_N9_72
+set_property -dict {PACKAGE_PIN B25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[35]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ35"      - IO_L23P_T3U_N8_72
+set_property -dict {PACKAGE_PIN A24  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[4] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C4"    - IO_L22N_T3U_N7_DBC_AD0N_72
+set_property -dict {PACKAGE_PIN A25  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[4] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T4"    - IO_L22P_T3U_N6_DBC_AD0P_72
+set_property -dict {PACKAGE_PIN A22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[33]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ33"      - IO_L24N_T3U_N11_72
+set_property -dict {PACKAGE_PIN A23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[32]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ32"      - IO_L24P_T3U_N10_72
+set_property -dict {PACKAGE_PIN C23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[39]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ39"      - IO_L21N_T3L_N5_AD8N_72
+set_property -dict {PACKAGE_PIN C24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[38]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ38"      - IO_L21P_T3L_N4_AD8P_72
+set_property -dict {PACKAGE_PIN B22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[36]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ36"      - IO_L20N_T3L_N3_AD1N_72
+set_property -dict {PACKAGE_PIN C22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[37]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ37"      - IO_L20P_T3L_N2_AD1P_72
+set_property -dict {PACKAGE_PIN N22  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C13"   - IO_L19N_T3L_N1_DBC_AD9N_72
+set_property -dict {PACKAGE_PIN M22  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C10"   - IO_L7N_T1L_N1_QBC_AD13N_72
+# set_property -dict {PACKAGE_PIN D24  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dm_dbi[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T13"   - IO_L19P_T3L_N0_DBC_AD9P_72
+set_property -dict {PACKAGE_PIN E22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[57]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ57"      - IO_L17N_T2U_N9_AD10N_72
+set_property -dict {PACKAGE_PIN F22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[56]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ56"      - IO_L17P_T2U_N8_AD10P_72
+set_property -dict {PACKAGE_PIN E23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C7"    - IO_L16N_T2U_N7_QBC_AD3N_72
+set_property -dict {PACKAGE_PIN F23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T7"    - IO_L16P_T2U_N6_QBC_AD3P_72
+set_property -dict {PACKAGE_PIN G21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[59]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ59"      - IO_L18N_T2U_N11_AD2N_72
+set_property -dict {PACKAGE_PIN G22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[58]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ58"      - IO_L18P_T2U_N10_AD2P_72
+set_property -dict {PACKAGE_PIN E25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[61]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ61"      - IO_L15N_T2L_N5_AD11N_72
+set_property -dict {PACKAGE_PIN F25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[62]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ62"      - IO_L15P_T2L_N4_AD11P_72
+set_property -dict {PACKAGE_PIN F24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[60]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ60"      - IO_L14N_T2L_N3_GC_72
+set_property -dict {PACKAGE_PIN G25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[63]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ63"      - IO_L14P_T2L_N2_GC_72
+set_property -dict {PACKAGE_PIN H19  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[6]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C16"   - IO_L13N_T2L_N1_GC_QBC_72
+set_property -dict {PACKAGE_PIN H23  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[7]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C16"   - IO_L13N_T2L_N1_GC_QBC_72
+#set_property -dict {PACKAGE_PIN H23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[15]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T16"   - IO_L13P_T2L_N0_GC_QBC_72
+set_property -dict {PACKAGE_PIN J23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[9]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ9"       - IO_L11N_T1U_N9_GC_72
+set_property -dict {PACKAGE_PIN J24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[8]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ8"       - IO_L11P_T1U_N8_GC_72
+set_property -dict {PACKAGE_PIN H21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C1"    - IO_L10N_T1U_N7_QBC_AD4N_72
+set_property -dict {PACKAGE_PIN J21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T1"    - IO_L10P_T1U_N6_QBC_AD4P_72
+set_property -dict {PACKAGE_PIN G24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[11]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ11"      - IO_L12N_T1U_N11_GC_72
+set_property -dict {PACKAGE_PIN H24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[10]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ10"      - IO_L12P_T1U_N10_GC_72
+set_property -dict {PACKAGE_PIN L23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[13]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ13"      - IO_L9N_T1L_N5_AD12N_72
+set_property -dict {PACKAGE_PIN L24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[12]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ12"      - IO_L9P_T1L_N4_AD12P_72
+set_property -dict {PACKAGE_PIN K21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[15]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ15"      - IO_L8N_T1L_N3_AD5N_72
+set_property -dict {PACKAGE_PIN K22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[14]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ14"      - IO_L8P_T1L_N2_AD5P_72
+#set_property -dict {PACKAGE_PIN L22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C10"   - IO_L7N_T1L_N1_QBC_AD13N_72
+#set_property -dict {PACKAGE_PIN M22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T10"   - IO_L7P_T1L_N0_QBC_AD13P_72
+#set_property -dict {PACKAGE_PIN N21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C9"    - IO_L1N_T0L_N1_DBC_72
+#set_property -dict {PACKAGE_PIN N22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T9"    - IO_L1P_T0L_N0_DBC_72
+set_property -dict {PACKAGE_PIN B21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[43]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ43"      - IO_L23N_T3U_N9_71
+set_property -dict {PACKAGE_PIN C21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[42]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ42"      - IO_L23P_T3U_N8_71
+set_property -dict {PACKAGE_PIN B17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C5"    - IO_L22N_T3U_N7_DBC_AD0N_71
+set_property -dict {PACKAGE_PIN C17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T5"    - IO_L22P_T3U_N6_DBC_AD0P_71
+# set_property -dict {PACKAGE_PIN D18  IOSTANDARD LVCMOS12       } [get_ports c3_ddr4_event_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_EVENT_B"   - IO_T3U_N12_71
+set_property -dict {PACKAGE_PIN C18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[41]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ41"      - IO_L24N_T3U_N11_71
+set_property -dict {PACKAGE_PIN C19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[40]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ40"      - IO_L24P_T3U_N10_71
+set_property -dict {PACKAGE_PIN A20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[46]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ46"      - IO_L21N_T3L_N5_AD8N_71
+set_property -dict {PACKAGE_PIN B20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[47]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ47"      - IO_L21P_T3L_N4_AD8P_71
+set_property -dict {PACKAGE_PIN A17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[45]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ45"      - IO_L20N_T3L_N3_AD1N_71
+set_property -dict {PACKAGE_PIN A18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[44]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ44"      - IO_L20P_T3L_N2_AD1P_71
+set_property -dict {PACKAGE_PIN N17  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[3]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C14"   - IO_L19N_T3L_N1_DBC_AD9N_71
+set_property -dict {PACKAGE_PIN D24  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[4] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C13"   - IO_L19N_T3L_N1_DBC_AD9N_72
+set_property -dict {PACKAGE_PIN B19  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[5]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C14"   - IO_L19N_T3L_N1_DBC_AD9N_71
+set_property -dict {PACKAGE_PIN E20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[51]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ51"      - IO_L17N_T2U_N9_AD10N_71
+set_property -dict {PACKAGE_PIN F20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[49]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ49"      - IO_L17P_T2U_N8_AD10P_71
+set_property -dict {PACKAGE_PIN F17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[6]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C6"    - IO_L16N_T2U_N7_QBC_AD3N_71
+set_property -dict {PACKAGE_PIN F18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[6]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T6"    - IO_L16P_T2U_N6_QBC_AD3P_71
+set_property -dict {PACKAGE_PIN D21  IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_reset_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_RESET_N"   - IO_T2U_N12_71
+set_property -dict {PACKAGE_PIN E17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[48]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ48"      - IO_L18N_T2U_N11_AD2N_71
+set_property -dict {PACKAGE_PIN E18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[50]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ50"      - IO_L18P_T2U_N10_AD2P_71
+set_property -dict {PACKAGE_PIN D19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[52]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ52"      - IO_L15N_T2L_N5_AD11N_71
+set_property -dict {PACKAGE_PIN D20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[53]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ53"      - IO_L15P_T2L_N4_AD11P_71
+set_property -dict {PACKAGE_PIN H18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[54]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ54"      - IO_L14N_T2L_N3_GC_71
+set_property -dict {PACKAGE_PIN J18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[55]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ55"      - IO_L14P_T2L_N2_GC_71
+#set_property -dict {PACKAGE_PIN G19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C15"   - IO_L13N_T2L_N1_GC_QBC_71
+#set_property -dict {PACKAGE_PIN H19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T15"   - IO_L13P_T2L_N0_GC_QBC_71
+#set_property -dict {PACKAGE_PIN K17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C11"   - IO_L7N_T1L_N1_QBC_AD13N_71
+#set_property -dict {PACKAGE_PIN K18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T11"   - IO_L7P_T1L_N0_QBC_AD13P_71
+set_property -dict {PACKAGE_PIN M19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[24]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ24"      - IO_L5N_T0U_N9_AD14N_71
+set_property -dict {PACKAGE_PIN M20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[25]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ25"      - IO_L5P_T0U_N8_AD14P_71
+set_property -dict {PACKAGE_PIN P18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C3"    - IO_L4N_T0U_N7_DBC_AD7N_71
+set_property -dict {PACKAGE_PIN P19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T3"    - IO_L4P_T0U_N6_DBC_AD7P_71
+set_property -dict {PACKAGE_PIN R17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[27]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ27"      - IO_L6N_T0U_N11_AD6N_71
+set_property -dict {PACKAGE_PIN R18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[26]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ26"      - IO_L6P_T0U_N10_AD6P_71
+set_property -dict {PACKAGE_PIN N18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[30]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ30"      - IO_L3N_T0L_N5_AD15N_71
+set_property -dict {PACKAGE_PIN N19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[31]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ31"      - IO_L3P_T0L_N4_AD15P_71
+set_property -dict {PACKAGE_PIN R20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[28]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ28"      - IO_L2N_T0L_N3_71
+set_property -dict {PACKAGE_PIN T20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[29]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ29"      - IO_L2P_T0L_N2_71
+#set_property -dict {PACKAGE_PIN M17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C12"   - IO_L1N_T0L_N1_DBC_71
+#set_property -dict {PACKAGE_PIN N17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T12"   - IO_L1P_T0L_N0_DBC_71
+set_property -dict {PACKAGE_PIN B16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN D16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN C16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT0"      - IO_L23P_T3U_N8_70
+set_property -dict {PACKAGE_PIN C13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[11]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR11"     - IO_L22N_T3U_N7_DBC_AD0N_70
+set_property -dict {PACKAGE_PIN D13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG0"       - IO_L22P_T3U_N6_DBC_AD0P_70
+set_property -dict {PACKAGE_PIN A13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[9]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR9"      - IO_L24N_T3U_N11_70
+set_property -dict {PACKAGE_PIN B13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[12]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR12"     - IO_L24P_T3U_N10_70
+set_property -dict {PACKAGE_PIN A15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[3]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR3"      - IO_L21N_T3L_N5_AD8N_70
+set_property -dict {PACKAGE_PIN B15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR1"      - IO_L21P_T3L_N4_AD8P_70
+set_property -dict {PACKAGE_PIN C14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[4]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR4"      - IO_L20N_T3L_N3_AD1N_70
+set_property -dict {PACKAGE_PIN D14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[10]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR10"     - IO_L20P_T3L_N2_AD1P_70
+set_property -dict {PACKAGE_PIN A14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[5]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR5"      - IO_L19N_T3L_N1_DBC_AD9N_70
+set_property -dict {PACKAGE_PIN B14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[6]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR6"      - IO_L19P_T3L_N0_DBC_AD9P_70
+set_property -dict {PACKAGE_PIN E15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[15]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR15"     - IO_L17N_T2U_N9_AD10N_70
+set_property -dict {PACKAGE_PIN E16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT1"      - IO_L17P_T2U_N8_AD10P_70
+
+#set_property -dict {PACKAGE_PIN G13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C1"     - IO_L16N_T2U_N7_QBC_AD3N_70
+#set_property -dict {PACKAGE_PIN G14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T1"     - IO_L16P_T2U_N6_QBC_AD3P_70
+
+set_property -dict {PACKAGE_PIN D15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[14]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR14"     - IO_T2U_N12_70
+set_property -dict {PACKAGE_PIN F14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[2]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR2"      - IO_L18N_T2U_N11_AD2N_70
+set_property -dict {PACKAGE_PIN F15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[16]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+set_property -dict {PACKAGE_PIN E13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[7]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR7"      - IO_L15N_T2L_N5_AD11N_70
+set_property -dict {PACKAGE_PIN F13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[8]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR8"      - IO_L15P_T2L_N4_AD11P_70
+set_property -dict {PACKAGE_PIN H13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_act_n    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ACT_B"     - IO_L14N_T2L_N3_GC_70
+set_property -dict {PACKAGE_PIN H14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA1"       - IO_L14P_T2L_N2_GC_70
+#set_property -dict {PACKAGE_PIN G15  IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_alert_n  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ALERT_B"  - IO_L11N_T1U_N9_GC_70
+#set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR17"    - IO_L11P_T1U_N8_GC_70
+set_property -dict {PACKAGE_PIN L13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C0"    - IO_L10N_T1U_N7_QBC_AD4N_70
+set_property -dict {PACKAGE_PIN L14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T0"    - IO_L10P_T1U_N6_QBC_AD4P_70
+set_property -dict {PACKAGE_PIN K13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN J13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG1"      - IO_L12N_T1U_N11_GC_70
+set_property -dict {PACKAGE_PIN J14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_parity   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_PAR"      - IO_L12P_T1U_N10_GC_70
+set_property -dict {PACKAGE_PIN J15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA0"      - IO_L9N_T1L_N5_AD12N_70
+set_property -dict {PACKAGE_PIN K16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[13]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR13"    - IO_L9P_T1L_N4_AD12P_70
+#set_property -dict {PACKAGE_PIN M13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[3]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B3"    - IO_L8N_T1L_N3_AD5N_70
+#set_property -dict {PACKAGE_PIN M14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[2]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B2"    - IO_L8P_T1L_N2_AD5P_70
+set_property -dict {PACKAGE_PIN K15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR0"     - IO_L7N_T1L_N1_QBC_AD13N_70
+#set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE1"     - IO_L7P_T1L_N0_QBC_AD13P_70
+#set_property -dict {PACKAGE_PIN N13  IOSTANDARD POD12_DCI     } [get_ports c0_ddr4_dq[66]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ66"     - IO_L5N_T0U_N9_AD14N_70
+#set_property -dict {PACKAGE_PIN N14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[67]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ67"     - IO_L5P_T0U_N8_AD14P_70
+#set_property -dict {PACKAGE_PIN P15  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[8]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_70
+#set_property -dict {PACKAGE_PIN R16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[8]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_70
+#set_property -dict {PACKAGE_PIN M16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[64]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ64"     - IO_L6N_T0U_N11_AD6N_70
+#set_property -dict {PACKAGE_PIN N16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[65]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ65"     - IO_L6P_T0U_N10_AD6P_70
+#set_property -dict {PACKAGE_PIN P13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[70]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ70"     - IO_L3N_T0L_N5_AD15N_70
+#set_property -dict {PACKAGE_PIN P14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[71]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ71"     - IO_L3P_T0L_N4_AD15P_70
+#set_property -dict {PACKAGE_PIN R15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[69]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ69"     - IO_L2N_T0L_N3_70
+#set_property -dict {PACKAGE_PIN T15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[68]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ68"     - IO_L2P_T0L_N2_70
+#set_property -dict {PACKAGE_PIN R13  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C17"  - IO_L1N_T0L_N1_DBC_70
+#set_property -dict {PACKAGE_PIN T13  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T17"  - IO_L1P_T0L_N0_DBC_70        
+##
+
+set_property	PACKAGE_PIN	AM10		[get_ports 	clk_ref_n	] ; 
+set_property	PACKAGE_PIN	AM11		[get_ports 	clk_ref_p	] ;
+
+set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS18       } [get_ports pcie_rst        ]; # Bank 64 VCCO - VCC1V8 Net "PCIE_PERST_LS"       - IO_L23P_T3U_N8_64
+set_property PULLUP true [get_ports pcie_rst];
+
+set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS18    } [get_ports sys_rst_l ]; # Bank 64 VCCO - VCC1V8 Net "CPU_RESET_FPGA"         - IO_L2N_T0L_N3_64_AL20
+
+set_property PACKAGE_PIN AF1 [get_ports pci_exp_rxn[0]  ]; # Bank 227  - MGTYRXN3_227
+set_property PACKAGE_PIN AF2 [get_ports pci_exp_rxp[0]  ]; # Bank 227  - MGTYRXP3_227
+set_property PACKAGE_PIN AG3 [get_ports pci_exp_rxn[1]  ]; # Bank 227  - MGTYRXN2_227
+set_property PACKAGE_PIN AG4 [get_ports pci_exp_rxp[1]  ]; # Bank 227  - MGTYRXP2_227
+set_property PACKAGE_PIN AH1 [get_ports pci_exp_rxn[2]  ]; # Bank 227  - MGTYRXN1_227
+set_property PACKAGE_PIN AH2 [get_ports pci_exp_rxp[2]  ]; # Bank 227  - MGTYRXP1_227
+set_property PACKAGE_PIN AJ3 [get_ports pci_exp_rxn[3]  ]; # Bank 227  - MGTYRXN0_227
+set_property PACKAGE_PIN AJ4 [get_ports pci_exp_rxp[3]  ]; # Bank 227  - MGTYRXP0_227
+set_property PACKAGE_PIN AF6 [get_ports pci_exp_txn[0]  ]; # Bank 227  - MGTYTXN3_227
+set_property PACKAGE_PIN AF7 [get_ports pci_exp_txp[0]  ]; # Bank 227  - MGTYTXP3_227
+set_property PACKAGE_PIN AG8 [get_ports pci_exp_txn[1]  ]; # Bank 227  - MGTYTXN2_227
+set_property PACKAGE_PIN AG9 [get_ports pci_exp_txp[1]  ]; # Bank 227  - MGTYTXP2_227
+set_property PACKAGE_PIN AH6 [get_ports pci_exp_txn[2]  ]; # Bank 227  - MGTYTXN1_227
+set_property PACKAGE_PIN AH7 [get_ports pci_exp_txp[2]  ]; # Bank 227  - MGTYTXP1_227
+set_property PACKAGE_PIN AJ8 [get_ports pci_exp_txn[3]  ]; # Bank 227  - MGTYTXN0_227
+set_property PACKAGE_PIN AJ9 [get_ports pci_exp_txp[3]  ]; # Bank 227  - MGTYTXP0_227
+set_property PACKAGE_PIN AK1 [get_ports pci_exp_rxn[4]  ]; # Bank 226  - MGTYRXN3_226
+set_property PACKAGE_PIN AK2 [get_ports pci_exp_rxp[4]  ]; # Bank 226  - MGTYRXP3_226
+set_property PACKAGE_PIN AL3 [get_ports pci_exp_rxn[5]  ]; # Bank 226  - MGTYRXN2_226
+set_property PACKAGE_PIN AL4 [get_ports pci_exp_rxp[5]  ]; # Bank 226  - MGTYRXP2_226
+set_property PACKAGE_PIN AM1 [get_ports pci_exp_rxn[6]  ]; # Bank 226  - MGTYRXN1_226
+set_property PACKAGE_PIN AM2 [get_ports pci_exp_rxp[6]  ]; # Bank 226  - MGTYRXP1_226
+set_property PACKAGE_PIN AN3 [get_ports pci_exp_rxn[7]  ]; # Bank 226  - MGTYRXN0_226
+set_property PACKAGE_PIN AN4 [get_ports pci_exp_rxp[7]  ]; # Bank 226  - MGTYRXP0_226
+set_property PACKAGE_PIN AK6 [get_ports pci_exp_txn[4]  ]; # Bank 226  - MGTYTXN3_226
+set_property PACKAGE_PIN AK7 [get_ports pci_exp_txp[4]  ]; # Bank 226  - MGTYTXP3_226
+set_property PACKAGE_PIN AL8 [get_ports pci_exp_txn[5]  ]; # Bank 226  - MGTYTXN2_226
+set_property PACKAGE_PIN AL9 [get_ports pci_exp_txp[5]  ]; # Bank 226  - MGTYTXP2_226
+set_property PACKAGE_PIN AM6 [get_ports pci_exp_txn[6]  ]; # Bank 226  - MGTYTXN1_226
+set_property PACKAGE_PIN AM7 [get_ports pci_exp_txp[6]  ]; # Bank 226  - MGTYTXP1_226
+set_property PACKAGE_PIN AN8 [get_ports pci_exp_txn[7]  ]; # Bank 226  - MGTYTXN0_226
+set_property PACKAGE_PIN AN9 [get_ports pci_exp_txp[7]  ]; # Bank 226  - MGTYTXN0_226
\ No newline at end of file
diff --git a/projects/U200/constraints/U200_C1_UDIMM.xdc b/projects/U200/constraints/U200_C1_UDIMM.xdc
new file mode 100644
index 0000000..f9c9f0b
--- /dev/null
+++ b/projects/U200/constraints/U200_C1_UDIMM.xdc
@@ -0,0 +1,221 @@
+set_property DRIVE 8 [get_ports c0_ddr4_reset_n]
+create_clock -period 3.333 [get_ports c0_sys_clk_p]
+set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks]
+create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p]
+set_clock_groups -asynchronous -group [get_clocks refclk_100 -include_generated_clocks]
+
+set_property -dict {PACKAGE_PIN P24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[0]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ0"       - IO_L5P_T0U_N8_AD14P_72
+set_property -dict {PACKAGE_PIN N24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[1]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ1"       - IO_L5N_T0U_N9_AD14N_72
+set_property -dict {PACKAGE_PIN T24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[2]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ2"       - IO_L6P_T0U_N10_AD6P_72
+set_property -dict {PACKAGE_PIN R23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[3]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ3"       - IO_L6N_T0U_N11_AD6N_72
+set_property -dict {PACKAGE_PIN N23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[4]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ4"       - IO_L3N_T0L_N5_AD15N_72
+set_property -dict {PACKAGE_PIN P21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[5]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ5"       - IO_L2N_T0L_N3_72
+set_property -dict {PACKAGE_PIN P23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[6]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ6"       - IO_L3P_T0L_N4_AD15P_72
+set_property -dict {PACKAGE_PIN R21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[7]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ7"       - IO_L2P_T0L_N2_72
+set_property -dict {PACKAGE_PIN R22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C0"    - IO_L4N_T0U_N7_DBC_AD7N_72
+set_property -dict {PACKAGE_PIN T22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T0"    - IO_L4P_T0U_N6_DBC_AD7P_72
+
+#set_property -dict {PACKAGE_PIN G20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[16]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ16"      - IO_L11P_T1U_N8_GC_71
+#set_property -dict {PACKAGE_PIN H17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[17]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ17"      - IO_L12P_T1U_N10_GC_71
+#set_property -dict {PACKAGE_PIN F19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[18]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ18"      - IO_L11N_T1U_N9_GC_71
+#set_property -dict {PACKAGE_PIN G17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[19]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ19"      - IO_L12N_T1U_N11_GC_71
+#set_property -dict {PACKAGE_PIN J20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[20]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ20"      - IO_L9P_T1L_N4_AD12P_71
+#set_property -dict {PACKAGE_PIN L19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[21]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ21"      - IO_L8P_T1L_N2_AD5P_71
+#set_property -dict {PACKAGE_PIN L18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[22]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ22"      - IO_L8N_T1L_N3_AD5N_71
+#set_property -dict {PACKAGE_PIN J19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[23]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ23"      - IO_L9N_T1L_N5_AD12N_71
+#set_property -dict {PACKAGE_PIN K20  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[2] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C2"    - IO_L10N_T1U_N7_QBC_AD4N_71
+#set_property -dict {PACKAGE_PIN L20  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[2] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T2"    - IO_L10P_T1U_N6_QBC_AD4P_71
+#set_property -dict {PACKAGE_PIN K18  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[2]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T14"   - IO_L19P_T3L_N0_DBC_AD9P_71
+
+set_property -dict {PACKAGE_PIN M16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[16]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ64"     - IO_L6N_T0U_N11_AD6N_70
+set_property -dict {PACKAGE_PIN N16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[17]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ65"     - IO_L6P_T0U_N10_AD6P_70
+set_property -dict {PACKAGE_PIN N13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[18]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ66"     - IO_L5N_T0U_N9_AD14N_70
+set_property -dict {PACKAGE_PIN N14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[19]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ67"     - IO_L5P_T0U_N8_AD14P_70
+set_property -dict {PACKAGE_PIN T15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[20]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ68"     - IO_L2P_T0L_N2_70
+set_property -dict {PACKAGE_PIN R15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[21]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ69"     - IO_L2N_T0L_N3_70
+set_property -dict {PACKAGE_PIN P13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[22]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ70"     - IO_L3N_T0L_N5_AD15N_70
+set_property -dict {PACKAGE_PIN P14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[23]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ71"     - IO_L3P_T0L_N4_AD15P_70
+set_property -dict {PACKAGE_PIN P15  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[2]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_70
+set_property -dict {PACKAGE_PIN R16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[2]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_70
+set_property -dict {PACKAGE_PIN T13  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[2]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T17"  - IO_L1P_T0L_N0_DBC_70        
+
+set_property -dict {PACKAGE_PIN H16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_sys_clk_n    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_N" - IO_L13N_T2L_N1_GC_QBC_70
+set_property -dict {PACKAGE_PIN J16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_sys_clk_p    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_P" - IO_L13P_T2L_N0_GC_QBC_70
+
+set_property -dict {PACKAGE_PIN B24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[34]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ34"      - IO_L23N_T3U_N9_72
+set_property -dict {PACKAGE_PIN B25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[35]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ35"      - IO_L23P_T3U_N8_72
+set_property -dict {PACKAGE_PIN A24  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[4] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C4"    - IO_L22N_T3U_N7_DBC_AD0N_72
+set_property -dict {PACKAGE_PIN A25  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[4] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T4"    - IO_L22P_T3U_N6_DBC_AD0P_72
+set_property -dict {PACKAGE_PIN A22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[33]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ33"      - IO_L24N_T3U_N11_72
+set_property -dict {PACKAGE_PIN A23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[32]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ32"      - IO_L24P_T3U_N10_72
+set_property -dict {PACKAGE_PIN C23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[39]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ39"      - IO_L21N_T3L_N5_AD8N_72
+set_property -dict {PACKAGE_PIN C24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[38]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ38"      - IO_L21P_T3L_N4_AD8P_72
+set_property -dict {PACKAGE_PIN B22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[36]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ36"      - IO_L20N_T3L_N3_AD1N_72
+set_property -dict {PACKAGE_PIN C22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[37]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ37"      - IO_L20P_T3L_N2_AD1P_72
+set_property -dict {PACKAGE_PIN N22  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C13"   - IO_L19N_T3L_N1_DBC_AD9N_72
+set_property -dict {PACKAGE_PIN M22  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C10"   - IO_L7N_T1L_N1_QBC_AD13N_72
+# set_property -dict {PACKAGE_PIN D24  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dm_dbi[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T13"   - IO_L19P_T3L_N0_DBC_AD9P_72
+set_property -dict {PACKAGE_PIN E22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[57]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ57"      - IO_L17N_T2U_N9_AD10N_72
+set_property -dict {PACKAGE_PIN F22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[56]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ56"      - IO_L17P_T2U_N8_AD10P_72
+set_property -dict {PACKAGE_PIN E23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C7"    - IO_L16N_T2U_N7_QBC_AD3N_72
+set_property -dict {PACKAGE_PIN F23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T7"    - IO_L16P_T2U_N6_QBC_AD3P_72
+set_property -dict {PACKAGE_PIN G21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[59]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ59"      - IO_L18N_T2U_N11_AD2N_72
+set_property -dict {PACKAGE_PIN G22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[58]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ58"      - IO_L18P_T2U_N10_AD2P_72
+set_property -dict {PACKAGE_PIN E25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[61]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ61"      - IO_L15N_T2L_N5_AD11N_72
+set_property -dict {PACKAGE_PIN F25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[62]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ62"      - IO_L15P_T2L_N4_AD11P_72
+set_property -dict {PACKAGE_PIN F24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[60]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ60"      - IO_L14N_T2L_N3_GC_72
+set_property -dict {PACKAGE_PIN G25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[63]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ63"      - IO_L14P_T2L_N2_GC_72
+set_property -dict {PACKAGE_PIN H19  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[6]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C16"   - IO_L13N_T2L_N1_GC_QBC_72
+set_property -dict {PACKAGE_PIN H23  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[7]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C16"   - IO_L13N_T2L_N1_GC_QBC_72
+#set_property -dict {PACKAGE_PIN H23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[15]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T16"   - IO_L13P_T2L_N0_GC_QBC_72
+set_property -dict {PACKAGE_PIN J23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[9]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ9"       - IO_L11N_T1U_N9_GC_72
+set_property -dict {PACKAGE_PIN J24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[8]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ8"       - IO_L11P_T1U_N8_GC_72
+set_property -dict {PACKAGE_PIN H21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C1"    - IO_L10N_T1U_N7_QBC_AD4N_72
+set_property -dict {PACKAGE_PIN J21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T1"    - IO_L10P_T1U_N6_QBC_AD4P_72
+set_property -dict {PACKAGE_PIN G24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[11]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ11"      - IO_L12N_T1U_N11_GC_72
+set_property -dict {PACKAGE_PIN H24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[10]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ10"      - IO_L12P_T1U_N10_GC_72
+set_property -dict {PACKAGE_PIN L23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[13]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ13"      - IO_L9N_T1L_N5_AD12N_72
+set_property -dict {PACKAGE_PIN L24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[12]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ12"      - IO_L9P_T1L_N4_AD12P_72
+set_property -dict {PACKAGE_PIN K21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[15]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ15"      - IO_L8N_T1L_N3_AD5N_72
+set_property -dict {PACKAGE_PIN K22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[14]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ14"      - IO_L8P_T1L_N2_AD5P_72
+#set_property -dict {PACKAGE_PIN L22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C10"   - IO_L7N_T1L_N1_QBC_AD13N_72
+#set_property -dict {PACKAGE_PIN M22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T10"   - IO_L7P_T1L_N0_QBC_AD13P_72
+#set_property -dict {PACKAGE_PIN N21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C9"    - IO_L1N_T0L_N1_DBC_72
+#set_property -dict {PACKAGE_PIN N22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T9"    - IO_L1P_T0L_N0_DBC_72
+set_property -dict {PACKAGE_PIN B21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[43]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ43"      - IO_L23N_T3U_N9_71
+set_property -dict {PACKAGE_PIN C21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[42]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ42"      - IO_L23P_T3U_N8_71
+set_property -dict {PACKAGE_PIN B17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C5"    - IO_L22N_T3U_N7_DBC_AD0N_71
+set_property -dict {PACKAGE_PIN C17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T5"    - IO_L22P_T3U_N6_DBC_AD0P_71
+# set_property -dict {PACKAGE_PIN D18  IOSTANDARD LVCMOS12       } [get_ports c3_ddr4_event_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_EVENT_B"   - IO_T3U_N12_71
+set_property -dict {PACKAGE_PIN C18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[41]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ41"      - IO_L24N_T3U_N11_71
+set_property -dict {PACKAGE_PIN C19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[40]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ40"      - IO_L24P_T3U_N10_71
+set_property -dict {PACKAGE_PIN A20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[46]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ46"      - IO_L21N_T3L_N5_AD8N_71
+set_property -dict {PACKAGE_PIN B20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[47]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ47"      - IO_L21P_T3L_N4_AD8P_71
+set_property -dict {PACKAGE_PIN A17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[45]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ45"      - IO_L20N_T3L_N3_AD1N_71
+set_property -dict {PACKAGE_PIN A18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[44]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ44"      - IO_L20P_T3L_N2_AD1P_71
+set_property -dict {PACKAGE_PIN N17  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[3]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C14"   - IO_L19N_T3L_N1_DBC_AD9N_71
+set_property -dict {PACKAGE_PIN D24  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[4] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C13"   - IO_L19N_T3L_N1_DBC_AD9N_72
+set_property -dict {PACKAGE_PIN B19  IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dm_dbi_n[5]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C14"   - IO_L19N_T3L_N1_DBC_AD9N_71
+set_property -dict {PACKAGE_PIN E20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[51]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ51"      - IO_L17N_T2U_N9_AD10N_71
+set_property -dict {PACKAGE_PIN F20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[49]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ49"      - IO_L17P_T2U_N8_AD10P_71
+set_property -dict {PACKAGE_PIN F17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[6]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C6"    - IO_L16N_T2U_N7_QBC_AD3N_71
+set_property -dict {PACKAGE_PIN F18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[6]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T6"    - IO_L16P_T2U_N6_QBC_AD3P_71
+set_property -dict {PACKAGE_PIN D21  IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_reset_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_RESET_N"   - IO_T2U_N12_71
+set_property -dict {PACKAGE_PIN E17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[48]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ48"      - IO_L18N_T2U_N11_AD2N_71
+set_property -dict {PACKAGE_PIN E18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[50]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ50"      - IO_L18P_T2U_N10_AD2P_71
+set_property -dict {PACKAGE_PIN D19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[52]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ52"      - IO_L15N_T2L_N5_AD11N_71
+set_property -dict {PACKAGE_PIN D20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[53]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ53"      - IO_L15P_T2L_N4_AD11P_71
+set_property -dict {PACKAGE_PIN H18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[54]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ54"      - IO_L14N_T2L_N3_GC_71
+set_property -dict {PACKAGE_PIN J18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[55]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ55"      - IO_L14P_T2L_N2_GC_71
+#set_property -dict {PACKAGE_PIN G19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C15"   - IO_L13N_T2L_N1_GC_QBC_71
+#set_property -dict {PACKAGE_PIN H19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T15"   - IO_L13P_T2L_N0_GC_QBC_71
+#set_property -dict {PACKAGE_PIN K17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C11"   - IO_L7N_T1L_N1_QBC_AD13N_71
+#set_property -dict {PACKAGE_PIN K18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T11"   - IO_L7P_T1L_N0_QBC_AD13P_71
+set_property -dict {PACKAGE_PIN M19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[24]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ24"      - IO_L5N_T0U_N9_AD14N_71
+set_property -dict {PACKAGE_PIN M20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[25]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ25"      - IO_L5P_T0U_N8_AD14P_71
+set_property -dict {PACKAGE_PIN P18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C3"    - IO_L4N_T0U_N7_DBC_AD7N_71
+set_property -dict {PACKAGE_PIN P19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T3"    - IO_L4P_T0U_N6_DBC_AD7P_71
+set_property -dict {PACKAGE_PIN R17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[27]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ27"      - IO_L6N_T0U_N11_AD6N_71
+set_property -dict {PACKAGE_PIN R18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[26]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ26"      - IO_L6P_T0U_N10_AD6P_71
+set_property -dict {PACKAGE_PIN N18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[30]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ30"      - IO_L3N_T0L_N5_AD15N_71
+set_property -dict {PACKAGE_PIN N19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[31]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ31"      - IO_L3P_T0L_N4_AD15P_71
+set_property -dict {PACKAGE_PIN R20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[28]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ28"      - IO_L2N_T0L_N3_71
+set_property -dict {PACKAGE_PIN T20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[29]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ29"      - IO_L2P_T0L_N2_71
+#set_property -dict {PACKAGE_PIN M17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C12"   - IO_L1N_T0L_N1_DBC_71
+#set_property -dict {PACKAGE_PIN N17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T12"   - IO_L1P_T0L_N0_DBC_71
+set_property -dict {PACKAGE_PIN B16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN D16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN C16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT0"      - IO_L23P_T3U_N8_70
+set_property -dict {PACKAGE_PIN C13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[11]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR11"     - IO_L22N_T3U_N7_DBC_AD0N_70
+set_property -dict {PACKAGE_PIN D13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG0"       - IO_L22P_T3U_N6_DBC_AD0P_70
+#set_property -dict {PACKAGE_PIN D16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B1"     - IO_T3U_N12_70
+set_property -dict {PACKAGE_PIN A13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[9]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR9"      - IO_L24N_T3U_N11_70
+set_property -dict {PACKAGE_PIN B13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[12]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR12"     - IO_L24P_T3U_N10_70
+set_property -dict {PACKAGE_PIN A15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[3]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR3"      - IO_L21N_T3L_N5_AD8N_70
+set_property -dict {PACKAGE_PIN B15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR1"      - IO_L21P_T3L_N4_AD8P_70
+set_property -dict {PACKAGE_PIN C14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[4]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR4"      - IO_L20N_T3L_N3_AD1N_70
+set_property -dict {PACKAGE_PIN D14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[10]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR10"     - IO_L20P_T3L_N2_AD1P_70
+set_property -dict {PACKAGE_PIN A14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[5]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR5"      - IO_L19N_T3L_N1_DBC_AD9N_70
+set_property -dict {PACKAGE_PIN B14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[6]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR6"      - IO_L19P_T3L_N0_DBC_AD9P_70
+set_property -dict {PACKAGE_PIN E15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[15]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR15"     - IO_L17N_T2U_N9_AD10N_70
+set_property -dict {PACKAGE_PIN E16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT1"      - IO_L17P_T2U_N8_AD10P_70
+
+#set_property -dict {PACKAGE_PIN G13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C1"     - IO_L16N_T2U_N7_QBC_AD3N_70
+#set_property -dict {PACKAGE_PIN G14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T1"     - IO_L16P_T2U_N6_QBC_AD3P_70
+
+set_property -dict {PACKAGE_PIN D15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[14]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR14"     - IO_T2U_N12_70
+set_property -dict {PACKAGE_PIN F14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[2]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR2"      - IO_L18N_T2U_N11_AD2N_70
+set_property -dict {PACKAGE_PIN F15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[16]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+#set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+set_property -dict {PACKAGE_PIN E13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[7]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR7"      - IO_L15N_T2L_N5_AD11N_70
+set_property -dict {PACKAGE_PIN F13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[8]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR8"      - IO_L15P_T2L_N4_AD11P_70
+set_property -dict {PACKAGE_PIN H13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_act_n    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ACT_B"     - IO_L14N_T2L_N3_GC_70
+set_property -dict {PACKAGE_PIN H14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA1"       - IO_L14P_T2L_N2_GC_70
+#set_property -dict {PACKAGE_PIN G15  IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_alert_n  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ALERT_B"  - IO_L11N_T1U_N9_GC_70
+#set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR17"    - IO_L11P_T1U_N8_GC_70
+set_property -dict {PACKAGE_PIN L13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C0"    - IO_L10N_T1U_N7_QBC_AD4N_70
+set_property -dict {PACKAGE_PIN L14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T0"    - IO_L10P_T1U_N6_QBC_AD4P_70
+set_property -dict {PACKAGE_PIN K13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN J13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG1"      - IO_L12N_T1U_N11_GC_70
+set_property -dict {PACKAGE_PIN J14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_parity   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_PAR"      - IO_L12P_T1U_N10_GC_70
+set_property -dict {PACKAGE_PIN J15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA0"      - IO_L9N_T1L_N5_AD12N_70
+set_property -dict {PACKAGE_PIN K16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[13]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR13"    - IO_L9P_T1L_N4_AD12P_70
+#set_property -dict {PACKAGE_PIN M13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[3]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B3"    - IO_L8N_T1L_N3_AD5N_70
+#set_property -dict {PACKAGE_PIN M14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[2]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B2"    - IO_L8P_T1L_N2_AD5P_70
+set_property -dict {PACKAGE_PIN K15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR0"     - IO_L7N_T1L_N1_QBC_AD13N_70
+#set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE1"     - IO_L7P_T1L_N0_QBC_AD13P_70
+#set_property -dict {PACKAGE_PIN N13  IOSTANDARD POD12_DCI     } [get_ports c0_ddr4_dq[66]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ66"     - IO_L5N_T0U_N9_AD14N_70
+#set_property -dict {PACKAGE_PIN N14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[67]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ67"     - IO_L5P_T0U_N8_AD14P_70
+#set_property -dict {PACKAGE_PIN P15  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[8]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_70
+#set_property -dict {PACKAGE_PIN R16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[8]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_70
+#set_property -dict {PACKAGE_PIN M16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[64]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ64"     - IO_L6N_T0U_N11_AD6N_70
+#set_property -dict {PACKAGE_PIN N16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[65]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ65"     - IO_L6P_T0U_N10_AD6P_70
+#set_property -dict {PACKAGE_PIN P13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[70]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ70"     - IO_L3N_T0L_N5_AD15N_70
+#set_property -dict {PACKAGE_PIN P14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[71]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ71"     - IO_L3P_T0L_N4_AD15P_70
+#set_property -dict {PACKAGE_PIN R15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[69]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ69"     - IO_L2N_T0L_N3_70
+#set_property -dict {PACKAGE_PIN T15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[68]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ68"     - IO_L2P_T0L_N2_70
+#set_property -dict {PACKAGE_PIN R13  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C17"  - IO_L1N_T0L_N1_DBC_70
+#set_property -dict {PACKAGE_PIN T13  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T17"  - IO_L1P_T0L_N0_DBC_70        
+##
+
+set_property	PACKAGE_PIN	AM10		[get_ports 	clk_ref_n	] ; 
+set_property	PACKAGE_PIN	AM11		[get_ports 	clk_ref_p	] ;
+
+set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS18       } [get_ports pcie_rst        ]; # Bank 64 VCCO - VCC1V8 Net "PCIE_PERST_LS"       - IO_L23P_T3U_N8_64
+set_property PULLUP true [get_ports pcie_rst];
+
+set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS18    } [get_ports sys_rst_l ]; # Bank 64 VCCO - VCC1V8 Net "CPU_RESET_FPGA"         - IO_L2N_T0L_N3_64_AL20
+
+set_property PACKAGE_PIN AF1 [get_ports pci_exp_rxn[0]  ]; # Bank 227  - MGTYRXN3_227
+set_property PACKAGE_PIN AF2 [get_ports pci_exp_rxp[0]  ]; # Bank 227  - MGTYRXP3_227
+set_property PACKAGE_PIN AG3 [get_ports pci_exp_rxn[1]  ]; # Bank 227  - MGTYRXN2_227
+set_property PACKAGE_PIN AG4 [get_ports pci_exp_rxp[1]  ]; # Bank 227  - MGTYRXP2_227
+set_property PACKAGE_PIN AH1 [get_ports pci_exp_rxn[2]  ]; # Bank 227  - MGTYRXN1_227
+set_property PACKAGE_PIN AH2 [get_ports pci_exp_rxp[2]  ]; # Bank 227  - MGTYRXP1_227
+set_property PACKAGE_PIN AJ3 [get_ports pci_exp_rxn[3]  ]; # Bank 227  - MGTYRXN0_227
+set_property PACKAGE_PIN AJ4 [get_ports pci_exp_rxp[3]  ]; # Bank 227  - MGTYRXP0_227
+set_property PACKAGE_PIN AF6 [get_ports pci_exp_txn[0]  ]; # Bank 227  - MGTYTXN3_227
+set_property PACKAGE_PIN AF7 [get_ports pci_exp_txp[0]  ]; # Bank 227  - MGTYTXP3_227
+set_property PACKAGE_PIN AG8 [get_ports pci_exp_txn[1]  ]; # Bank 227  - MGTYTXN2_227
+set_property PACKAGE_PIN AG9 [get_ports pci_exp_txp[1]  ]; # Bank 227  - MGTYTXP2_227
+set_property PACKAGE_PIN AH6 [get_ports pci_exp_txn[2]  ]; # Bank 227  - MGTYTXN1_227
+set_property PACKAGE_PIN AH7 [get_ports pci_exp_txp[2]  ]; # Bank 227  - MGTYTXP1_227
+set_property PACKAGE_PIN AJ8 [get_ports pci_exp_txn[3]  ]; # Bank 227  - MGTYTXN0_227
+set_property PACKAGE_PIN AJ9 [get_ports pci_exp_txp[3]  ]; # Bank 227  - MGTYTXP0_227
+set_property PACKAGE_PIN AK1 [get_ports pci_exp_rxn[4]  ]; # Bank 226  - MGTYRXN3_226
+set_property PACKAGE_PIN AK2 [get_ports pci_exp_rxp[4]  ]; # Bank 226  - MGTYRXP3_226
+set_property PACKAGE_PIN AL3 [get_ports pci_exp_rxn[5]  ]; # Bank 226  - MGTYRXN2_226
+set_property PACKAGE_PIN AL4 [get_ports pci_exp_rxp[5]  ]; # Bank 226  - MGTYRXP2_226
+set_property PACKAGE_PIN AM1 [get_ports pci_exp_rxn[6]  ]; # Bank 226  - MGTYRXN1_226
+set_property PACKAGE_PIN AM2 [get_ports pci_exp_rxp[6]  ]; # Bank 226  - MGTYRXP1_226
+set_property PACKAGE_PIN AN3 [get_ports pci_exp_rxn[7]  ]; # Bank 226  - MGTYRXN0_226
+set_property PACKAGE_PIN AN4 [get_ports pci_exp_rxp[7]  ]; # Bank 226  - MGTYRXP0_226
+set_property PACKAGE_PIN AK6 [get_ports pci_exp_txn[4]  ]; # Bank 226  - MGTYTXN3_226
+set_property PACKAGE_PIN AK7 [get_ports pci_exp_txp[4]  ]; # Bank 226  - MGTYTXP3_226
+set_property PACKAGE_PIN AL8 [get_ports pci_exp_txn[5]  ]; # Bank 226  - MGTYTXN2_226
+set_property PACKAGE_PIN AL9 [get_ports pci_exp_txp[5]  ]; # Bank 226  - MGTYTXP2_226
+set_property PACKAGE_PIN AM6 [get_ports pci_exp_txn[6]  ]; # Bank 226  - MGTYTXN1_226
+set_property PACKAGE_PIN AM7 [get_ports pci_exp_txp[6]  ]; # Bank 226  - MGTYTXP1_226
+set_property PACKAGE_PIN AN8 [get_ports pci_exp_txn[7]  ]; # Bank 226  - MGTYTXN0_226
+set_property PACKAGE_PIN AN9 [get_ports pci_exp_txp[7]  ]; # Bank 226  - MGTYTXP0_226
\ No newline at end of file
diff --git a/projects/U200/constraints/U200_c1.xdc b/projects/U200/constraints/U200_c1.xdc
new file mode 100644
index 0000000..e94eb80
--- /dev/null
+++ b/projects/U200/constraints/U200_c1.xdc
@@ -0,0 +1,203 @@
+set_property DRIVE 8 [get_ports c0_ddr4_reset_n]
+create_clock -period 3.333 [get_ports c0_sys_clk_p]
+set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks]
+create_clock -period 10.000 -name refclk_100 [get_ports clk_ref_p]
+set_clock_groups -asynchronous -group [get_clocks refclk_100 -include_generated_clocks]
+
+set_property -dict {PACKAGE_PIN H16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_sys_clk_n    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_N" - IO_L13N_T2L_N1_GC_QBC_70
+set_property -dict {PACKAGE_PIN J16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_sys_clk_p    ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_P" - IO_L13P_T2L_N0_GC_QBC_70
+
+set_property -dict {PACKAGE_PIN B24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[34]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ34"      - IO_L23N_T3U_N9_72
+set_property -dict {PACKAGE_PIN B25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[35]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ35"      - IO_L23P_T3U_N8_72
+set_property -dict {PACKAGE_PIN A24  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[8] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C4"    - IO_L22N_T3U_N7_DBC_AD0N_72
+set_property -dict {PACKAGE_PIN A25  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[8] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T4"    - IO_L22P_T3U_N6_DBC_AD0P_72
+set_property -dict {PACKAGE_PIN A22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[33]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ33"      - IO_L24N_T3U_N11_72
+set_property -dict {PACKAGE_PIN A23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[32]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ32"      - IO_L24P_T3U_N10_72
+set_property -dict {PACKAGE_PIN C23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[39]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ39"      - IO_L21N_T3L_N5_AD8N_72
+set_property -dict {PACKAGE_PIN C24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[38]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ38"      - IO_L21P_T3L_N4_AD8P_72
+set_property -dict {PACKAGE_PIN B22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[36]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ36"      - IO_L20N_T3L_N3_AD1N_72
+set_property -dict {PACKAGE_PIN C22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[37]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ37"      - IO_L20P_T3L_N2_AD1P_72
+set_property -dict {PACKAGE_PIN D23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[9] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C13"   - IO_L19N_T3L_N1_DBC_AD9N_72
+set_property -dict {PACKAGE_PIN D24  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[9] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T13"   - IO_L19P_T3L_N0_DBC_AD9P_72
+set_property -dict {PACKAGE_PIN E22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[57]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ57"      - IO_L17N_T2U_N9_AD10N_72
+set_property -dict {PACKAGE_PIN F22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[56]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ56"      - IO_L17P_T2U_N8_AD10P_72
+set_property -dict {PACKAGE_PIN E23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[14]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C7"    - IO_L16N_T2U_N7_QBC_AD3N_72
+set_property -dict {PACKAGE_PIN F23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[14]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T7"    - IO_L16P_T2U_N6_QBC_AD3P_72
+set_property -dict {PACKAGE_PIN G21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[59]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ59"      - IO_L18N_T2U_N11_AD2N_72
+set_property -dict {PACKAGE_PIN G22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[58]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ58"      - IO_L18P_T2U_N10_AD2P_72
+set_property -dict {PACKAGE_PIN E25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[61]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ61"      - IO_L15N_T2L_N5_AD11N_72
+set_property -dict {PACKAGE_PIN F25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[62]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ62"      - IO_L15P_T2L_N4_AD11P_72
+set_property -dict {PACKAGE_PIN F24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[60]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ60"      - IO_L14N_T2L_N3_GC_72
+set_property -dict {PACKAGE_PIN G25  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[63]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ63"      - IO_L14P_T2L_N2_GC_72
+set_property -dict {PACKAGE_PIN H22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[15]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C16"   - IO_L13N_T2L_N1_GC_QBC_72
+set_property -dict {PACKAGE_PIN H23  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[15]]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T16"   - IO_L13P_T2L_N0_GC_QBC_72
+set_property -dict {PACKAGE_PIN J23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[9]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ9"       - IO_L11N_T1U_N9_GC_72
+set_property -dict {PACKAGE_PIN J24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[8]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ8"       - IO_L11P_T1U_N8_GC_72
+set_property -dict {PACKAGE_PIN H21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[2] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C1"    - IO_L10N_T1U_N7_QBC_AD4N_72
+set_property -dict {PACKAGE_PIN J21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[2] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T1"    - IO_L10P_T1U_N6_QBC_AD4P_72
+set_property -dict {PACKAGE_PIN G24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[11]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ11"      - IO_L12N_T1U_N11_GC_72
+set_property -dict {PACKAGE_PIN H24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[10]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ10"      - IO_L12P_T1U_N10_GC_72
+set_property -dict {PACKAGE_PIN L23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[13]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ13"      - IO_L9N_T1L_N5_AD12N_72
+set_property -dict {PACKAGE_PIN L24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[12]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ12"      - IO_L9P_T1L_N4_AD12P_72
+set_property -dict {PACKAGE_PIN K21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[15]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ15"      - IO_L8N_T1L_N3_AD5N_72
+set_property -dict {PACKAGE_PIN K22  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[14]   ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ14"      - IO_L8P_T1L_N2_AD5P_72
+set_property -dict {PACKAGE_PIN L22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C10"   - IO_L7N_T1L_N1_QBC_AD13N_72
+set_property -dict {PACKAGE_PIN M22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T10"   - IO_L7P_T1L_N0_QBC_AD13P_72
+set_property -dict {PACKAGE_PIN N24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[1]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ1"       - IO_L5N_T0U_N9_AD14N_72
+set_property -dict {PACKAGE_PIN P24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[0]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ0"       - IO_L5P_T0U_N8_AD14P_72
+set_property -dict {PACKAGE_PIN R22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C0"    - IO_L4N_T0U_N7_DBC_AD7N_72
+set_property -dict {PACKAGE_PIN T22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[0] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T0"    - IO_L4P_T0U_N6_DBC_AD7P_72
+set_property -dict {PACKAGE_PIN R23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[3]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ3"       - IO_L6N_T0U_N11_AD6N_72
+set_property -dict {PACKAGE_PIN T24  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[2]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ2"       - IO_L6P_T0U_N10_AD6P_72
+set_property -dict {PACKAGE_PIN N23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[4]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ4"       - IO_L3N_T0L_N5_AD15N_72
+set_property -dict {PACKAGE_PIN P23  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[6]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ6"       - IO_L3P_T0L_N4_AD15P_72
+set_property -dict {PACKAGE_PIN P21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[5]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ5"       - IO_L2N_T0L_N3_72
+set_property -dict {PACKAGE_PIN R21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[7]    ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQ7"       - IO_L2P_T0L_N2_72
+set_property -dict {PACKAGE_PIN N21  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_C9"    - IO_L1N_T0L_N1_DBC_72
+set_property -dict {PACKAGE_PIN N22  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 72  VCCO - VCC1V2 Net "DDR4_C3_DQS_T9"    - IO_L1P_T0L_N0_DBC_72
+set_property -dict {PACKAGE_PIN B21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[43]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ43"      - IO_L23N_T3U_N9_71
+set_property -dict {PACKAGE_PIN C21  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[42]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ42"      - IO_L23P_T3U_N8_71
+set_property -dict {PACKAGE_PIN B17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[10]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C5"    - IO_L22N_T3U_N7_DBC_AD0N_71
+set_property -dict {PACKAGE_PIN C17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[10]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T5"    - IO_L22P_T3U_N6_DBC_AD0P_71
+#set_property -dict {PACKAGE_PIN D18  IOSTANDARD LVCMOS12       } [get_ports c3_ddr4_event_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_EVENT_B"   - IO_T3U_N12_71
+set_property -dict {PACKAGE_PIN C18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[41]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ41"      - IO_L24N_T3U_N11_71
+set_property -dict {PACKAGE_PIN C19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[40]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ40"      - IO_L24P_T3U_N10_71
+set_property -dict {PACKAGE_PIN A20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[46]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ46"      - IO_L21N_T3L_N5_AD8N_71
+set_property -dict {PACKAGE_PIN B20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[47]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ47"      - IO_L21P_T3L_N4_AD8P_71
+set_property -dict {PACKAGE_PIN A17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[45]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ45"      - IO_L20N_T3L_N3_AD1N_71
+set_property -dict {PACKAGE_PIN A18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[44]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ44"      - IO_L20P_T3L_N2_AD1P_71
+set_property -dict {PACKAGE_PIN A19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[11]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C14"   - IO_L19N_T3L_N1_DBC_AD9N_71
+set_property -dict {PACKAGE_PIN B19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[11]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T14"   - IO_L19P_T3L_N0_DBC_AD9P_71
+set_property -dict {PACKAGE_PIN E20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[51]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ51"      - IO_L17N_T2U_N9_AD10N_71
+set_property -dict {PACKAGE_PIN F20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[49]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ49"      - IO_L17P_T2U_N8_AD10P_71
+set_property -dict {PACKAGE_PIN F17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[12]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C6"    - IO_L16N_T2U_N7_QBC_AD3N_71
+set_property -dict {PACKAGE_PIN F18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[12]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T6"    - IO_L16P_T2U_N6_QBC_AD3P_71
+set_property -dict {PACKAGE_PIN D21  IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_reset_n  ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_RESET_N"   - IO_T2U_N12_71
+set_property -dict {PACKAGE_PIN E17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[48]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ48"      - IO_L18N_T2U_N11_AD2N_71
+set_property -dict {PACKAGE_PIN E18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[50]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ50"      - IO_L18P_T2U_N10_AD2P_71
+set_property -dict {PACKAGE_PIN D19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[52]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ52"      - IO_L15N_T2L_N5_AD11N_71
+set_property -dict {PACKAGE_PIN D20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[53]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ53"      - IO_L15P_T2L_N4_AD11P_71
+set_property -dict {PACKAGE_PIN H18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[54]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ54"      - IO_L14N_T2L_N3_GC_71
+set_property -dict {PACKAGE_PIN J18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[55]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ55"      - IO_L14P_T2L_N2_GC_71
+set_property -dict {PACKAGE_PIN G19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C15"   - IO_L13N_T2L_N1_GC_QBC_71
+set_property -dict {PACKAGE_PIN H19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[13]]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T15"   - IO_L13P_T2L_N0_GC_QBC_71
+set_property -dict {PACKAGE_PIN F19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[18]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ18"      - IO_L11N_T1U_N9_GC_71
+set_property -dict {PACKAGE_PIN G20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[16]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ16"      - IO_L11P_T1U_N8_GC_71
+set_property -dict {PACKAGE_PIN K20  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[4] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C2"    - IO_L10N_T1U_N7_QBC_AD4N_71
+set_property -dict {PACKAGE_PIN L20  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[4] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T2"    - IO_L10P_T1U_N6_QBC_AD4P_71
+set_property -dict {PACKAGE_PIN G17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[19]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ19"      - IO_L12N_T1U_N11_GC_71
+set_property -dict {PACKAGE_PIN H17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[17]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ17"      - IO_L12P_T1U_N10_GC_71
+set_property -dict {PACKAGE_PIN J19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[23]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ23"      - IO_L9N_T1L_N5_AD12N_71
+set_property -dict {PACKAGE_PIN J20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[20]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ20"      - IO_L9P_T1L_N4_AD12P_71
+set_property -dict {PACKAGE_PIN L18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[22]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ22"      - IO_L8N_T1L_N3_AD5N_71
+set_property -dict {PACKAGE_PIN L19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[21]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ21"      - IO_L8P_T1L_N2_AD5P_71
+set_property -dict {PACKAGE_PIN K17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C11"   - IO_L7N_T1L_N1_QBC_AD13N_71
+set_property -dict {PACKAGE_PIN K18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T11"   - IO_L7P_T1L_N0_QBC_AD13P_71
+set_property -dict {PACKAGE_PIN M19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[24]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ24"      - IO_L5N_T0U_N9_AD14N_71
+set_property -dict {PACKAGE_PIN M20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[25]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ25"      - IO_L5P_T0U_N8_AD14P_71
+set_property -dict {PACKAGE_PIN P18  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[6] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C3"    - IO_L4N_T0U_N7_DBC_AD7N_71
+set_property -dict {PACKAGE_PIN P19  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[6] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T3"    - IO_L4P_T0U_N6_DBC_AD7P_71
+set_property -dict {PACKAGE_PIN R17  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[27]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ27"      - IO_L6N_T0U_N11_AD6N_71
+set_property -dict {PACKAGE_PIN R18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[26]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ26"      - IO_L6P_T0U_N10_AD6P_71
+set_property -dict {PACKAGE_PIN N18  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[30]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ30"      - IO_L3N_T0L_N5_AD15N_71
+set_property -dict {PACKAGE_PIN N19  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[31]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ31"      - IO_L3P_T0L_N4_AD15P_71
+set_property -dict {PACKAGE_PIN R20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[28]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ28"      - IO_L2N_T0L_N3_71
+set_property -dict {PACKAGE_PIN T20  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[29]   ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQ29"      - IO_L2P_T0L_N2_71
+set_property -dict {PACKAGE_PIN M17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_C12"   - IO_L1N_T0L_N1_DBC_71
+set_property -dict {PACKAGE_PIN N17  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7] ]; # Bank 71  VCCO - VCC1V2 Net "DDR4_C3_DQS_T12"   - IO_L1P_T0L_N0_DBC_71
+set_property -dict {PACKAGE_PIN B16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN D16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cs_n[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B0"     - IO_L23N_T3U_N9_70
+set_property -dict {PACKAGE_PIN C16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT0"      - IO_L23P_T3U_N8_70
+set_property -dict {PACKAGE_PIN C13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[11]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR11"     - IO_L22N_T3U_N7_DBC_AD0N_70
+set_property -dict {PACKAGE_PIN D13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG0"       - IO_L22P_T3U_N6_DBC_AD0P_70
+#set_property -dict {PACKAGE_PIN D16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B1"     - IO_T3U_N12_70
+set_property -dict {PACKAGE_PIN A13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[9]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR9"      - IO_L24N_T3U_N11_70
+set_property -dict {PACKAGE_PIN B13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[12]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR12"     - IO_L24P_T3U_N10_70
+set_property -dict {PACKAGE_PIN A15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[3]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR3"      - IO_L21N_T3L_N5_AD8N_70
+set_property -dict {PACKAGE_PIN B15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR1"      - IO_L21P_T3L_N4_AD8P_70
+set_property -dict {PACKAGE_PIN C14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[4]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR4"      - IO_L20N_T3L_N3_AD1N_70
+set_property -dict {PACKAGE_PIN D14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[10]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR10"     - IO_L20P_T3L_N2_AD1P_70
+set_property -dict {PACKAGE_PIN A14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[5]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR5"      - IO_L19N_T3L_N1_DBC_AD9N_70
+set_property -dict {PACKAGE_PIN B14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[6]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR6"      - IO_L19P_T3L_N0_DBC_AD9P_70
+set_property -dict {PACKAGE_PIN E15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[15]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR15"     - IO_L17N_T2U_N9_AD10N_70
+set_property -dict {PACKAGE_PIN E16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_odt[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ODT1"      - IO_L17P_T2U_N8_AD10P_70
+
+#set_property -dict {PACKAGE_PIN G13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C1"     - IO_L16N_T2U_N7_QBC_AD3N_70
+#set_property -dict {PACKAGE_PIN G14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[1]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T1"     - IO_L16P_T2U_N6_QBC_AD3P_70
+
+set_property -dict {PACKAGE_PIN D15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[14]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR14"     - IO_T2U_N12_70
+set_property -dict {PACKAGE_PIN F14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[2]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR2"      - IO_L18N_T2U_N11_AD2N_70
+set_property -dict {PACKAGE_PIN F15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[16]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+# set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR16"     - IO_L18P_T2U_N10_AD2P_70
+set_property -dict {PACKAGE_PIN E13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[7]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR7"      - IO_L15N_T2L_N5_AD11N_70
+set_property -dict {PACKAGE_PIN F13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[8]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR8"      - IO_L15P_T2L_N4_AD11P_70
+set_property -dict {PACKAGE_PIN H13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_act_n    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ACT_B"     - IO_L14N_T2L_N3_GC_70
+set_property -dict {PACKAGE_PIN H14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA1"       - IO_L14P_T2L_N2_GC_70
+#set_property -dict {PACKAGE_PIN G15  IOSTANDARD LVCMOS12       } [get_ports c0_ddr4_alert_n  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ALERT_B"  - IO_L11N_T1U_N9_GC_70
+#set_property -dict {PACKAGE_PIN G16  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_adr[17]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR17"    - IO_L11P_T1U_N8_GC_70
+set_property -dict {PACKAGE_PIN L13  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_C0"    - IO_L10N_T1U_N7_QBC_AD4N_70
+set_property -dict {PACKAGE_PIN L14  IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[0]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CK_T0"    - IO_L10P_T1U_N6_QBC_AD4P_70
+set_property -dict {PACKAGE_PIN K13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE0"     - IO_T1U_N12_70
+set_property -dict {PACKAGE_PIN J13  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_bg[1]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BG1"      - IO_L12N_T1U_N11_GC_70
+set_property -dict {PACKAGE_PIN J14  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_parity   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_PAR"      - IO_L12P_T1U_N10_GC_70
+set_property -dict {PACKAGE_PIN J15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_ba[0]    ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_BA0"      - IO_L9N_T1L_N5_AD12N_70
+set_property -dict {PACKAGE_PIN K16  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[13]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR13"    - IO_L9P_T1L_N4_AD12P_70
+#set_property -dict {PACKAGE_PIN M13  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[3]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B3"    - IO_L8N_T1L_N3_AD5N_70
+#set_property -dict {PACKAGE_PIN M14  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cs_n[2]  ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CS_B2"    - IO_L8P_T1L_N2_AD5P_70
+set_property -dict {PACKAGE_PIN K15  IOSTANDARD SSTL12_DCI     } [get_ports c0_ddr4_adr[0]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_ADR0"     - IO_L7N_T1L_N1_QBC_AD13N_70
+#set_property -dict {PACKAGE_PIN L15  IOSTANDARD SSTL12_DCI     } [get_ports c3_ddr4_cke[1]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_CKE1"     - IO_L7P_T1L_N0_QBC_AD13P_70
+set_property -dict {PACKAGE_PIN N13  IOSTANDARD POD12_DCI     } [get_ports c0_ddr4_dq[66]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ66"     - IO_L5N_T0U_N9_AD14N_70
+set_property -dict {PACKAGE_PIN N14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[67]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ67"     - IO_L5P_T0U_N8_AD14P_70
+set_property -dict {PACKAGE_PIN P15  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[16]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C8"   - IO_L4N_T0U_N7_DBC_AD7N_70
+set_property -dict {PACKAGE_PIN R16  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[16]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T8"   - IO_L4P_T0U_N6_DBC_AD7P_70
+set_property -dict {PACKAGE_PIN M16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[64]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ64"     - IO_L6N_T0U_N11_AD6N_70
+set_property -dict {PACKAGE_PIN N16  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[65]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ65"     - IO_L6P_T0U_N10_AD6P_70
+set_property -dict {PACKAGE_PIN P13  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[70]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ70"     - IO_L3N_T0L_N5_AD15N_70
+set_property -dict {PACKAGE_PIN P14  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[71]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ71"     - IO_L3P_T0L_N4_AD15P_70
+set_property -dict {PACKAGE_PIN R15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[69]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ69"     - IO_L2N_T0L_N3_70
+set_property -dict {PACKAGE_PIN T15  IOSTANDARD POD12_DCI      } [get_ports c0_ddr4_dq[68]   ]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQ68"     - IO_L2P_T0L_N2_70
+set_property -dict {PACKAGE_PIN R13  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_C17"  - IO_L1N_T0L_N1_DBC_70
+set_property -dict {PACKAGE_PIN T13  IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[17]]; # Bank 70  VCCO - VCC1V2 Net "DDR4_C3_DQS_T17"  - IO_L1P_T0L_N0_DBC_70        
+##
+
+set_property	PACKAGE_PIN	AM10		[get_ports 	clk_ref_n	] ; 
+set_property	PACKAGE_PIN	AM11		[get_ports 	clk_ref_p	] ;
+
+set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS18       } [get_ports pcie_rst        ]; # Bank 64 VCCO - VCC1V8 Net "PCIE_PERST_LS"       - IO_L23P_T3U_N8_64
+set_property PULLUP true [get_ports pcie_rst];
+
+set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS18    } [get_ports sys_rst_l ]; # Bank 64 VCCO - VCC1V8 Net "CPU_RESET_FPGA"         - IO_L2N_T0L_N3_64_AL20
+
+set_property PACKAGE_PIN AF1 [get_ports pci_exp_rxn[0]  ]; # Bank 227  - MGTYRXN3_227
+set_property PACKAGE_PIN AF2 [get_ports pci_exp_rxp[0]  ]; # Bank 227  - MGTYRXP3_227
+set_property PACKAGE_PIN AG3 [get_ports pci_exp_rxn[1]  ]; # Bank 227  - MGTYRXN2_227
+set_property PACKAGE_PIN AG4 [get_ports pci_exp_rxp[1]  ]; # Bank 227  - MGTYRXP2_227
+set_property PACKAGE_PIN AH1 [get_ports pci_exp_rxn[2]  ]; # Bank 227  - MGTYRXN1_227
+set_property PACKAGE_PIN AH2 [get_ports pci_exp_rxp[2]  ]; # Bank 227  - MGTYRXP1_227
+set_property PACKAGE_PIN AJ3 [get_ports pci_exp_rxn[3]  ]; # Bank 227  - MGTYRXN0_227
+set_property PACKAGE_PIN AJ4 [get_ports pci_exp_rxp[3]  ]; # Bank 227  - MGTYRXP0_227
+set_property PACKAGE_PIN AF6 [get_ports pci_exp_txn[0]  ]; # Bank 227  - MGTYTXN3_227
+set_property PACKAGE_PIN AF7 [get_ports pci_exp_txp[0]  ]; # Bank 227  - MGTYTXP3_227
+set_property PACKAGE_PIN AG8 [get_ports pci_exp_txn[1]  ]; # Bank 227  - MGTYTXN2_227
+set_property PACKAGE_PIN AG9 [get_ports pci_exp_txp[1]  ]; # Bank 227  - MGTYTXP2_227
+set_property PACKAGE_PIN AH6 [get_ports pci_exp_txn[2]  ]; # Bank 227  - MGTYTXN1_227
+set_property PACKAGE_PIN AH7 [get_ports pci_exp_txp[2]  ]; # Bank 227  - MGTYTXP1_227
+set_property PACKAGE_PIN AJ8 [get_ports pci_exp_txn[3]  ]; # Bank 227  - MGTYTXN0_227
+set_property PACKAGE_PIN AJ9 [get_ports pci_exp_txp[3]  ]; # Bank 227  - MGTYTXP0_227
+set_property PACKAGE_PIN AK1 [get_ports pci_exp_rxn[4]  ]; # Bank 226  - MGTYRXN3_226
+set_property PACKAGE_PIN AK2 [get_ports pci_exp_rxp[4]  ]; # Bank 226  - MGTYRXP3_226
+set_property PACKAGE_PIN AL3 [get_ports pci_exp_rxn[5]  ]; # Bank 226  - MGTYRXN2_226
+set_property PACKAGE_PIN AL4 [get_ports pci_exp_rxp[5]  ]; # Bank 226  - MGTYRXP2_226
+set_property PACKAGE_PIN AM1 [get_ports pci_exp_rxn[6]  ]; # Bank 226  - MGTYRXN1_226
+set_property PACKAGE_PIN AM2 [get_ports pci_exp_rxp[6]  ]; # Bank 226  - MGTYRXP1_226
+set_property PACKAGE_PIN AN3 [get_ports pci_exp_rxn[7]  ]; # Bank 226  - MGTYRXN0_226
+set_property PACKAGE_PIN AN4 [get_ports pci_exp_rxp[7]  ]; # Bank 226  - MGTYRXP0_226
+set_property PACKAGE_PIN AK6 [get_ports pci_exp_txn[4]  ]; # Bank 226  - MGTYTXN3_226
+set_property PACKAGE_PIN AK7 [get_ports pci_exp_txp[4]  ]; # Bank 226  - MGTYTXP3_226
+set_property PACKAGE_PIN AL8 [get_ports pci_exp_txn[5]  ]; # Bank 226  - MGTYTXN2_226
+set_property PACKAGE_PIN AL9 [get_ports pci_exp_txp[5]  ]; # Bank 226  - MGTYTXP2_226
+set_property PACKAGE_PIN AM6 [get_ports pci_exp_txn[6]  ]; # Bank 226  - MGTYTXN1_226
+set_property PACKAGE_PIN AM7 [get_ports pci_exp_txp[6]  ]; # Bank 226  - MGTYTXP1_226
+set_property PACKAGE_PIN AN8 [get_ports pci_exp_txn[7]  ]; # Bank 226  - MGTYTXN0_226
+set_property PACKAGE_PIN AN9 [get_ports pci_exp_txp[7]  ]; # Bank 226  - MGTYTXP0_226
\ No newline at end of file
diff --git a/projects/U200/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/custom_parts_ddr4_2016_4_and_above.csv
new file mode 100644
index 0000000..0e96b29
--- /dev/null
+++ b/projects/U200/custom_parts_ddr4_2016_4_and_above.csv
@@ -0,0 +1,9 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/patches/rd_en.patch b/projects/U200/patches/rd_en.patch
new file mode 100644
index 0000000..ea2485a
--- /dev/null
+++ b/projects/U200/patches/rd_en.patch
@@ -0,0 +1,370 @@
+--- U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv
+@@ -114,55 +114,86 @@
+ 
+ reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg                      [18:0]                        rsMask[0:7];
++reg                      [19:0]                        rsMask[0:15];
+ 
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+    input [3:0] diff;
+    input       slot2;
+-case ({diff, slot2})
+-   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+-   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+-   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+-   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++   input       slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++    6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++   6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++    6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++   6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++    6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++   6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++    6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+      default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+ 
+ always @(posedge clk) begin: blk1
+-   reg [3:0] rsNdx;
+-   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+-      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++   reg [4:0] rsNdx;
++   for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+ 
+ always @(*) if (rst) begin
+    rdEn_nxt = 'b0;
+ end else begin
+    rdEn_nxt =   (rdEn >> 4)
+-                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++                | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                 : 'b0);
+ end
+
+
+--- U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv
+@@ -114,55 +114,86 @@
+ 
+ reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg                      [18:0]                        rsMask[0:7];
++reg                      [19:0]                        rsMask[0:15];
+ 
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+    input [3:0] diff;
+    input       slot2;
+-case ({diff, slot2})
+-   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+-   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+-   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+-   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++   input       slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++    6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++   6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++    6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++   6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++    6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++   6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++    6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+      default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+ 
+ always @(posedge clk) begin: blk1
+-   reg [3:0] rsNdx;
+-   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+-      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++   reg [4:0] rsNdx;
++   for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+ 
+ always @(*) if (rst) begin
+    rdEn_nxt = 'b0;
+ end else begin
+    rdEn_nxt =   (rdEn >> 4)
+-                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++                | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                 : 'b0);
+ end
+
+--- U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv
+@@ -114,55 +114,86 @@
+ 
+ reg                      [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg  [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg                      [18:0]                        rsMask[0:7];
++reg                      [19:0]                        rsMask[0:15];
+ 
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+    input [3:0] diff;
+    input       slot2;
+-case ({diff, slot2})
+-   5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+-   5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+-   5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+-   5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+-   5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+-   5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+-   5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+-   5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+-   5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+-   5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+-   5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+-   5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+-   5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+-   5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+-   5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+-   5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++   input       slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++    6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++   6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++    6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++   6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++    6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++   6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++    6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++   6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++    6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++   6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++    6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++   6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++    6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++   6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++    6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++   6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++    6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++   6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++    6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++   6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++    6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++   6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++    6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++   6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++    6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++   6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++    6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++   6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++    6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++   6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++    6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+      default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+ 
+ always @(posedge clk) begin: blk1
+-   reg [3:0] rsNdx;
+-   for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+-      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++   reg [4:0] rsNdx;
++   for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++      rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+ 
+ always @(*) if (rst) begin
+    rdEn_nxt = 'b0;
+ end else begin
+    rdEn_nxt =   (rdEn >> 4)
+-                | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++                | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+                 : 'b0);
+ end
+
diff --git a/projects/U200/patches/write.patch b/projects/U200/patches/write.patch
new file mode 100644
index 0000000..812c13f
--- /dev/null
+++ b/projects/U200/patches/write.patch
@@ -0,0 +1,95 @@
+--- U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register.  These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = (   ALL_WR_LATENCY       / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 =   ( ALL_WR_LATENCY     ) % 4;
++localparam OFFSET_CASSLOT1 =   ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 =   ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 =   ( ALL_WR_LATENCY + 3 ) % 4;
+ 
+ integer i;
+ 
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc.  mccasSlot2 is timing critical.
+ reg  [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone    ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric        = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric        = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++                         (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+ 
+ // tCK offset for mc.  mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++                         (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+ 
+ // Output enable shift register load value for cal and mc.  mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf,   calRank, OFFSET_CASSLOT2[1:0], 1'b1};
+
+
+--- U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register.  These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = (   ALL_WR_LATENCY       / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 =   ( ALL_WR_LATENCY     ) % 4;
++localparam OFFSET_CASSLOT1 =   ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 =   ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 =   ( ALL_WR_LATENCY + 3 ) % 4;
+ 
+ integer i;
+ 
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc.  mccasSlot2 is timing critical.
+ reg  [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone    ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric        = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric        = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++                         (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+ 
+ // tCK offset for mc.  mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++                         (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+ 
+ // Output enable shift register load value for cal and mc.  mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf,   calRank, OFFSET_CASSLOT2[1:0], 1'b1};
+
+
+--- U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register.  These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = (   ALL_WR_LATENCY       / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 =   ( ALL_WR_LATENCY     ) % 4;
++localparam OFFSET_CASSLOT1 =   ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 =   ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 =   ( ALL_WR_LATENCY + 3 ) % 4;
+ 
+ integer i;
+ 
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc.  mccasSlot2 is timing critical.
+ reg  [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone    ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric        = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric        = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++                         (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+ 
+ // tCK offset for mc.  mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++                         (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+ 
+ // Output enable shift register load value for cal and mc.  mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf,   calRank, OFFSET_CASSLOT2[1:0], 1'b1};
+
diff --git a/projects/U200/verilog/ddr4_adapter.v b/projects/U200/verilog/ddr4_adapter.v
new file mode 100644
index 0000000..88eec7e
--- /dev/null
+++ b/projects/U200/verilog/ddr4_adapter.v
@@ -0,0 +1,359 @@
+`include "parameters.vh"
+`include "project.vh"
+// Convert MC emitted DFI signals to a specific DDR4 PHY interface (mem_clock = 4xfab_clk)
+// Note that this is a bit hardcoded, but it could be made more flexible to satisfy
+// wider (can issue more than 4 commands each fab cycle) PHY interfaces.
+// DBUF_WIDTH specifies how many bursts of data will be buffered
+// before being issued to DRAM.
+
+`define ADDR_WIDTH 17
+
+module ddr4_adapter #(parameter CKE_WIDTH = 1, RANK_WIDTH = 1, DQ_WIDTH = 64, DRAM_CMD_SLOTS = 4,
+										DATA_BUF_ADDR_WIDTH = 5, DBUF_WIDTH = 4, DQ_BURST = 8)
+
+(
+  // common signals
+  input                                             clk,
+  input                                             rst,
+  
+  //other control signals
+  input                                             init_calib_complete,
+  //input                                             process_iseq,
+  
+  // ddr_pipeline <-> outer module if
+  input [3:0]                ddr_write,
+  input [3:0]                ddr_read,
+  input [3:0]                ddr_pre,
+  input [3:0]                ddr_act,
+  input [3:0]                ddr_ref,
+  input [3:0]                ddr_zq,
+  input [3:0]                ddr_nop,
+  input [3:0]                ddr_ap,
+  input [3:0]                ddr_half_bl,
+  input [3:0]                ddr_pall,
+  input [4*`BG_WIDTH-1:0]    ddr_bg, 
+  input [4*`BANK_WIDTH-1:0]  ddr_bank,
+  input [4*`COL_WIDTH-1:0]   ddr_col,
+  input [4*`ROW_WIDTH-1:0]   ddr_row,
+  input [511:0]              ddr_wdata,
+  
+  // periodic maintenance signals
+  input                      ddr_maint_read, // next read will be a maintenance read
+  
+  // DDR4-PHY signals
+  output [DATA_BUF_ADDR_WIDTH-1:0]                  dBufAdr,   // Reserved. Should be tied low.
+  output [DQ_WIDTH*8-1:0]                           wrData,    // DRAM write data. There are 8 bits for each DQ lane on the DRAM bus.
+  output [DQ_WIDTH-1:0]                             wrDataMask,// DRAM write DM/DBI port.There is one bit for each byte of the wrData port.
+  input                                             wrDataEn,  // Write data Enable. The Phy will assert this port for one cycle for each write CAS command.
+  output [7:0]                                      mc_ACT_n,  // DRAM ACT_n command signal for four DRAM clock cycles.
+  output [`ADDR_WIDTH*8-1:0]                        mc_ADR,    // DRAM address. There are 8 bits in the fabric interface for each address bit on the DRAM bus.
+  output [`BANK_WIDTH*8-1:0]                        mc_BA,     // DRAM bank address. 8 bits for each DRAM bank address.
+  output [`BG_WIDTH*8-1:0]                          mc_BG,     // DRAM bank group address.
+  output [`CS_WIDTH*8-1:0]                          mc_CS_n,   // DRAM CS_n
+  //output [`ODT_WIDTH*8-1:0]                         mc_ODT,    // DRAM ODT
+  output                                            mcRdCAS,   // Read CAS command issued.
+  output                                            mcWrCAS,   // Write CAS command issued.
+  output [1:0]                                      winRank,   // Target rank for CAS commands. This value indicates which rank a CAS command is issued to.
+  output [4:0]                                      winBuf,    // Optional control signal. When either mcRdCAS or mcWrCAS is asserted, the Phy will store the value on the winBuf signal.
+  // input  [DQ_WIDTH*8-1:0]                           rdData,    // DRAM read data.
+  input                                             rdDataEn,  // Read data valid. This signal asserts for one fabric cycle for each completed read operation.
+  input                                             rdDataEnd,  // Unused.  Tied high.
+  output [1:0]                                      mcCasSlot,
+  output                                            mcCasSlot2,
+  output                                            gt_data_ready,
+  
+  output                                            iss_dummy_read
+  );
+
+  assign winRank  = 2'b0; // single rank -> tie to 0
+  assign winBuf   = 4'b0; // TODO don't know how this could be used
+  assign dBufAdr = {DATA_BUF_ADDR_WIDTH{1'b0}};
+
+  reg [DQ_BURST*DQ_WIDTH-1:0] ddr_wdata_r;
+  
+  reg [2*DQ_BURST*DQ_WIDTH-1:0] wrDataBuf, wrDataBuf_ns;
+  reg slot1_full, slot1_full_ns;
+  reg slot2_full, slot2_full_ns;
+   
+  assign wrData                 = wrDataBuf[0+:DQ_BURST*DQ_WIDTH];
+
+  reg iss_dummy_read_r, iss_dummy_read_ns;
+  reg read_will_be_dummy_r, read_will_be_dummy_ns;
+  
+  assign iss_dummy_read = iss_dummy_read_r;
+
+  reg init_calib_complete_r; // can't issue any commands until this signal is asserted
+
+  reg                           wrDataEn_r; // to delay wrDataEn by one clock cycle
+  reg [7:0]                     ACT_n_ns, ACT_n_r;
+  reg [`ADDR_WIDTH*8-1:0]       ADR_ns, ADR_r;
+  reg [`BANK_WIDTH*8-1:0]       BA_ns, BA_r;
+  reg [`BG_WIDTH*8-1:0]         BG_ns, BG_r;
+  reg [`CS_WIDTH*8-1:0]         CS_n_ns, CS_n_r;
+  reg [`ODT_WIDTH*8-1:0]        ODT_ns, ODT_r;
+  reg                           RdCAS_ns, RdCAS_r;
+  reg                           WrCAS_ns, WrCAS_r;
+
+  reg [1:0]                     mcCasSlot_r, mcCasSlot_ns;
+  reg                           gt_data_ready_r, gt_data_ready_ns;
+  
+  // TODO - PG 150 - page 180
+  // Specifically, the PHY requires the following after calDone asserts:
+  // 1. At least one read command every 1 μs. For a multi-rank system any rank is acceptable.
+  // 2. The gt_data_ready signal is asserted for one system clock cycle after rdDataEn or
+  // per_rd_done signal asserts at least once within each 1 μs interval.
+  // 3. There is a three contiguous system clock cycle period with no read CAS commands
+  // asserted at the PHY interface every 1 μs.
+  // Somehow enforce above requirements to our PHY command stream, if it is not implicitly
+  // handled by the controller's maintenance handler modules.
+  // To drive gt_data_ready
+  assign gt_data_ready        = gt_data_ready_r;
+
+  assign mcCasSlot  = mcCasSlot_r;
+  assign mcCasSlot2 = mcCasSlot[1];
+
+  assign wrDataMask = {DQ_WIDTH{1'b0}};
+  assign mc_ACT_n   = ACT_n_r;
+  assign mc_ADR     = ADR_r;
+  assign mc_BA      = BA_r;
+  assign mc_BG      = BG_r;
+  assign mc_CS_n    = CS_n_r;
+  assign mcRdCAS    = RdCAS_r;
+  assign mcWrCAS    = WrCAS_r;
+
+  integer mc_cmd_i; // iterate over softmc dfi commands
+  integer adr_bit_i; // iterate over dfi address bits
+  integer bank_bit_i; // iterate over bank number bits
+  integer bg_bit_i; // iterate over bank group bits
+  always@* begin
+    wrDataBuf_ns = wrDataBuf;
+    slot1_full_ns = slot1_full;
+		slot2_full_ns = slot2_full;
+    ACT_n_ns = {8{`HIGH}};
+    ADR_ns = {`ROW_WIDTH*8{1'bx}};
+    BA_ns = {`BANK_WIDTH*8{1'bx}};
+    BG_ns = {`BG_WIDTH*8{1'bx}};
+    CS_n_ns = {`CS_WIDTH*8{1'b1}}; // NOP
+    ODT_ns = {`ODT_WIDTH*8{1'bx}};
+    RdCAS_ns = 1'b0;
+    WrCAS_ns = 1'b0;
+    mcCasSlot_ns = 2'b0;
+    iss_dummy_read_ns = iss_dummy_read_r;
+    read_will_be_dummy_ns = ddr_maint_read || read_will_be_dummy_r;
+
+    // assign DDR4 PHY address signals
+    // each pair of bits in a byte corresponds
+    // to each slot's command address bit
+    // e.g. ADR[1:0] is slot0's command address bit 0
+    // ADR[3:2] is slot1's command address bit 0
+    // ADR[9:8] is slot0's command address bit 1...
+
+    // Assume that every command works with column addresses
+    // ACTs will overwrite LSBs later
+    for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin
+      for(adr_bit_i = 0 ; adr_bit_i < `COL_WIDTH ; adr_bit_i = adr_bit_i + 1) begin
+          ADR_ns[adr_bit_i*8 + mc_cmd_i*2 +: 2] =
+                    {2{ddr_col[mc_cmd_i*`COL_WIDTH + adr_bit_i]}};
+      end
+    end
+
+    // ACTs overwriting LSBs here
+    for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin
+      for(adr_bit_i = 0 ; adr_bit_i < `ROW_WIDTH ; adr_bit_i = adr_bit_i + 1) begin
+        if(ddr_act[mc_cmd_i])
+          ADR_ns[adr_bit_i*8 + mc_cmd_i*2 +: 2] =
+                    {2{ddr_row[mc_cmd_i*`ROW_WIDTH + adr_bit_i]}};
+      end
+    end
+
+    // Set bank and bank group signals
+    for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin
+      for(bank_bit_i = 0 ; bank_bit_i < `BANK_WIDTH ; bank_bit_i = bank_bit_i + 1) begin
+        BA_ns[bank_bit_i*8 + mc_cmd_i*2 +: 2] =
+            {2{ddr_bank[mc_cmd_i*`BANK_WIDTH + bank_bit_i]}};
+      end
+    end
+    for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin
+      for(bg_bit_i = 0 ; bg_bit_i < `BG_WIDTH ; bg_bit_i = bg_bit_i + 1) begin
+        BG_ns[bg_bit_i*8 + mc_cmd_i*2 +: 2] =
+            {2{ddr_bg[mc_cmd_i*`BG_WIDTH + bg_bit_i]}};
+      end
+    end
+
+    // Set misc. signals (ap, bl4, precharge all)
+    for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin
+      if(ddr_ap[mc_cmd_i])
+        ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}};
+      else if(ddr_write[mc_cmd_i] | ddr_read[mc_cmd_i])
+        ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};
+      if(ddr_half_bl[mc_cmd_i])
+        ADR_ns[12*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}};
+      else if(ddr_write[mc_cmd_i] | ddr_read[mc_cmd_i])
+        ADR_ns[12*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};
+      if(ddr_pall[mc_cmd_i])
+        ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}};
+      else if(ddr_pre[mc_cmd_i])
+        ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};
+      if(ddr_zq[mc_cmd_i]) // ZQ short
+        ADR_ns[10*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};
+    end
+
+    // For each command slot, decode the commands
+    // and hopefully convert those to Xilinx PHY
+    // compatible commands.
+    for(mc_cmd_i = 0 ; mc_cmd_i < DRAM_CMD_SLOTS ; mc_cmd_i = mc_cmd_i + 1) begin
+      if(ddr_nop[mc_cmd_i]) begin // NOP
+         // set chip select to HI
+        CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {1*2{`HIGH}};
+      end
+      else if(ddr_act[mc_cmd_i]) begin // Activate ROW
+        // There seems to be something wrong with the dfi_cs signal widths
+        // coming from the mc. Consider LSBs as valid CS signals for now
+        CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}};
+        ACT_n_ns[mc_cmd_i*2 +: 2] = {2{`LOW}};
+      end // Activate
+      else if(ddr_read[mc_cmd_i] || ddr_write[mc_cmd_i]) begin // DDR Read or Write
+        mcCasSlot_ns = mc_cmd_i[0 +: 2];
+        CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}};
+        if(ddr_write[mc_cmd_i]) begin // Write burst
+          ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};  // WE
+          ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};  // CAS
+          ADR_ns[`ADDR_WIDTH*8-8   + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~RAS
+          //fifo_wr_en = HIGH;
+          WrCAS_ns = `HIGH;
+        end
+        else begin // Read burst
+          ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~WE
+          ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};  // CAS
+          ADR_ns[`ADDR_WIDTH*8-8   + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~RAS
+          RdCAS_ns = `HIGH;
+          iss_dummy_read_ns = read_will_be_dummy_r;
+          read_will_be_dummy_ns = `LOW;
+        end
+      end // DDR Read-Write
+      else if(ddr_pre[mc_cmd_i]) begin // Precharge
+          CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}};
+          ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};  // WE
+          ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~CAS
+          ADR_ns[`ADDR_WIDTH*8-8   + mc_cmd_i*2 +: 2] = {2{`LOW}};  // RAS
+      end // Precharge
+      else if(ddr_ref[mc_cmd_i]) begin // Refresh
+          CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}};
+          ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}}; // ~WE
+          ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};  // CAS
+          ADR_ns[`ADDR_WIDTH*8-8   + mc_cmd_i*2 +: 2] = {2{`LOW}};  // RAS
+      end
+      else if(ddr_zq[mc_cmd_i]) begin // ZQ Calib
+          CS_n_ns[mc_cmd_i*1*2 +: 1*2] = {2*1{`LOW}};
+          ADR_ns[`ADDR_WIDTH*8-3*8 + mc_cmd_i*2 +: 2] = {2{`LOW}};   // WE
+          ADR_ns[`ADDR_WIDTH*8-2*8 + mc_cmd_i*2 +: 2] = {2{`HIGH}};  // ~CAS
+          ADR_ns[`ADDR_WIDTH*8-8   + mc_cmd_i*2 +: 2] = {2{`HIGH}};  // ~RAS
+      end
+    end // decode block end
+
+    if(WrCAS_r) begin
+        if(slot1_full && slot2_full && wrDataEn_r) begin
+            wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = wrDataBuf[DQ_BURST*DQ_WIDTH +: DQ_BURST*DQ_WIDTH];
+            wrDataBuf_ns[DQ_BURST*DQ_WIDTH+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r;
+        end
+        else if (slot1_full && wrDataEn_r) begin
+            wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r;
+        end
+        else if (slot1_full) begin
+            wrDataBuf_ns[DQ_BURST*DQ_WIDTH+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r;
+            slot2_full_ns = `HIGH;
+        end
+        else begin
+            wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = ddr_wdata_r;
+            slot1_full_ns = `HIGH;
+        end
+    end
+
+		// We handle the cases where a wrDataEn and dfi CAS commands
+		// arrive at the same time
+    if(wrDataEn_r && ~WrCAS_r) begin
+			if(slot1_full && slot2_full) begin
+				wrDataBuf_ns[0+:DQ_BURST*DQ_WIDTH] = wrDataBuf[DQ_BURST*DQ_WIDTH +: DQ_BURST*DQ_WIDTH];
+				slot2_full_ns = `LOW;
+			end
+			else if (slot1_full) begin
+				slot1_full_ns = `LOW;
+			end
+    end
+
+    if(rdDataEn) begin
+      if(RdCAS_r) // issued another CAS read this cycle
+        iss_dummy_read_ns = ddr_maint_read;
+      else
+        iss_dummy_read_ns = `LOW;
+    end
+    
+    gt_data_ready_ns = iss_dummy_read_r & rdDataEn;
+    // this assumes CAS_rw_ctr is either 0, 1 or 2
+    //mcCasSlot_ns[1] = CAS_rw_ctr[DRAM_CMD_SLOTS-1][1];
+    //mcCasSlot_ns[0] = CAS_rw_ctr[DRAM_CMD_SLOTS-1][0];
+  end
+
+  always@(posedge clk) begin
+    if(rst) begin
+      wrDataBuf <= {DQ_WIDTH*DQ_BURST{1'b0}};
+      init_calib_complete_r <= 1'b0;
+      iss_dummy_read_r <= 1'b0;
+      read_will_be_dummy_r <= 1'b0;
+      wrDataEn_r <= 1'b0;
+      ACT_n_r <= {8{`HIGH}};
+      ADR_r <= {`ADDR_WIDTH*8{1'bx}};
+      BA_r <= {`BANK_WIDTH*8{1'bx}};
+      BG_r <= {`BG_WIDTH*8{1'bx}};
+      CS_n_r <= {`CS_WIDTH*8{1'b1}}; //NOP
+      ODT_r <= {`ODT_WIDTH*8{1'bx}};
+      //fifo_wr_en_r <= 1'b0;
+      WrCAS_r <= 1'b0;
+      RdCAS_r <= 1'b0;
+      mcCasSlot_r <= 2'b0;
+      slot1_full <= `LOW;
+      slot2_full <= `LOW;
+      gt_data_ready_r <= 1'b0;
+    end
+    else begin
+      if(init_calib_complete_r) begin
+        ddr_wdata_r <= ddr_wdata;
+        slot1_full <= slot1_full_ns;
+        slot2_full <= slot2_full_ns;
+        wrDataBuf <= wrDataBuf_ns;
+        iss_dummy_read_r <= iss_dummy_read_ns;
+        read_will_be_dummy_r <= read_will_be_dummy_ns;
+        wrDataEn_r <= wrDataEn;
+        ACT_n_r <= ACT_n_ns;
+        ADR_r <= ADR_ns;
+        BA_r <= BA_ns;
+        BG_r <= BG_ns;
+        CS_n_r <= CS_n_ns;
+        ODT_r <= ODT_ns;
+        WrCAS_r <= WrCAS_ns;
+        RdCAS_r <= RdCAS_ns;
+        //fifo_wr_en_r <= fifo_wr_en_ns;
+        mcCasSlot_r <= mcCasSlot_ns;
+        gt_data_ready_r <= gt_data_ready_ns;
+      end
+      else begin
+        slot1_full <= `LOW;
+        slot2_full <= `LOW;
+        wrDataBuf <= {DQ_WIDTH*DQ_BURST{1'b0}};
+        init_calib_complete_r <= init_calib_complete_r | init_calib_complete;
+        iss_dummy_read_r <= `LOW;
+        read_will_be_dummy_r <= `LOW;
+        ACT_n_r <= {8{`HIGH}};
+        ADR_r <= {`ADDR_WIDTH*8{1'b1}};
+        BA_r <= {`BANK_WIDTH*8{1'b1}};
+        BG_r <= {`BG_WIDTH*8{1'b1}};
+        CS_n_r <= {`CS_WIDTH*8{1'b1}};
+        WrCAS_r <= 1'b0;
+        RdCAS_r <= 1'b0;
+        //fifo_wr_en_r <= 1'b0;
+        mcCasSlot_r <= 2'b0;
+        gt_data_ready_r <= 1'b0;
+      end
+    end
+  end
+endmodule
\ No newline at end of file
diff --git a/projects/U200/verilog/ddr4_mc_odt.v b/projects/U200/verilog/ddr4_mc_odt.v
new file mode 100644
index 0000000..fdb5c1f
--- /dev/null
+++ b/projects/U200/verilog/ddr4_mc_odt.v
@@ -0,0 +1,130 @@
+// Auto-generated, DDR4 SDRAM Example Design source
+// small modifications to issue writes from all command slots
+module ddr4_mc_odt #(parameter
+        ODTWR     = 16'h8421
+       ,ODTWRDEL  = 5'd9
+       ,ODTWRDUR  = 4'd6
+       ,ODTWRODEL = 5'd9
+       ,ODTWRODUR = 4'd6
+    
+       ,ODTRD     = 16'h8421
+       ,ODTRDDEL  = 5'd9
+       ,ODTRDDUR  = 4'd6
+       ,ODTRDODEL = 5'd9
+       ,ODTRDODUR = 4'd6
+    
+       ,ODTBITS   = 4
+       ,ODTNOP    = 4'b0000
+       ,TCQ       = 0.1
+    )(
+        input clk
+       ,input rst
+    
+       ,output [ODTBITS*8-1:0] mc_ODT
+    
+       ,input       casSlot2
+       ,input [1:0] casSlot
+       ,input [1:0] rank
+       ,input       winRead
+       ,input       winWrite
+       ,input       tranSentC 
+    );
+    
+    // ==========================================================================================
+    // ODT is a multi-fabric-cycle waveform that needs to assert on the same cycle as write CAS,
+    // and also on the same cycle as read CAS when tCL=tCWL.  This block generates the full
+    // multi-cycle ODT waveform in the same cycle that rdCAS or wrCAS is generated, bypassing
+    // the first 8 bits per ODT pin to mc_ODT combinationally, and flopping the remaining bits
+    // in a shift register which are then sent to the XiPhy 8 bits per pin per cycle.  If CAS
+    // commands are issued so that the current ODT waveform overlaps with the waveform from
+    // previous commands, the waveforms will be OR'd together.
+    // Note:  The original Olympus ODT block had separate timing for the selected rank and
+    // non-target ranks.  This version of the code does not support this.
+    // ==========================================================================================
+    
+    
+    // ==========================================================================================
+    // Signal Declarations
+    // ==========================================================================================
+    
+    // Structures holding multi-fabric-cycle ODT pin waveforms for current CAS transaction
+    wire [31:0] odt_array    [ ODTBITS-1:0 ];
+    wire [31:0] odt_transent [ ODTBITS-1:0 ];
+    
+    // Shift register holding ODT pin waveforms for previous CAS transactions
+    reg  [23:0] odt_shift    [ ODTBITS-1:0 ];
+    wire [23:0] odt_shift_nxt[ ODTBITS-1:0 ];
+    
+    // ODT pin waveform for current fabric cycle, with time going from msb to lsb, reverse for XiPhy order
+    wire [ 7:0] odt_reverse  [ ODTBITS-1:0 ];
+    
+    
+    // ==========================================================================================
+    // Module Code
+    // ==========================================================================================
+    
+    // Set up basic write ODT timing waveform.  Note that time increases moving from msb to lsb.
+    wire [31:0] odt_pulse_wr_slot0 = 32'hff_ff_ff_ff << (32 - 2*ODTWRDUR);
+    wire [31:0] odt_pulse_wr_slot1 = odt_pulse_wr_slot0 >> 2;
+    wire [31:0] odt_pulse_wr_slot2 = odt_pulse_wr_slot0 >> 4;
+    wire [31:0] odt_pulse_wr_slot3 = odt_pulse_wr_slot0 >> 6;
+    
+    // Set up basic read ODT timing waveform.  Note that time increases moving from msb to lsb.
+    wire [31:0] odt_pulse_rd_slot0 = ( 32'hff_ff_ff_ff << (32 - 2*ODTRDDUR) ) >> ( 2*( ODTRDDEL - ODTWRDEL ) );
+    wire [31:0] odt_pulse_rd_slot1 = odt_pulse_rd_slot0 >> 2;
+    wire [31:0] odt_pulse_rd_slot2 = odt_pulse_rd_slot0 >> 4;
+    wire [31:0] odt_pulse_rd_slot3 = odt_pulse_rd_slot0 >> 6;
+    
+    // Select ODT timing waveform based on winning command type and slot position
+    wire [31:0] win_odt_pulse_slot0 = winRead ? odt_pulse_rd_slot0 : odt_pulse_wr_slot0;
+    wire [31:0] win_odt_pulse_slot1 = winRead ? odt_pulse_rd_slot1: odt_pulse_wr_slot1;
+    wire [31:0] win_odt_pulse_slot2 = winRead ? odt_pulse_rd_slot2 : odt_pulse_wr_slot2;
+    wire [31:0] win_odt_pulse_slot3 = winRead ? odt_pulse_rd_slot3 : odt_pulse_wr_slot3;
+    wire [31:0] win_odt_pulse       = casSlot2 ? (casSlot[0] ? win_odt_pulse_slot3 : win_odt_pulse_slot2) 
+                    : (casSlot[0] ? win_odt_pulse_slot1 : win_odt_pulse_slot0);
+    
+    // Select ODT pin pattern based on winning command type and rank
+    wire [15:0] win_odt_cmd_pat = winRead ? ODTRD : ODTWR;
+    wire [ 3:0] win_odt_pat     = { 4 { winRead | winWrite } } & win_odt_cmd_pat[ 4*rank +:4 ]; // spyglass disable W498
+    
+    genvar odt_pin;
+    generate
+       for (odt_pin = 0; odt_pin < ODTBITS; odt_pin = odt_pin + 1) begin
+          // Combine selected waveform and pattern to generate full ODT output for the current winning CAS command
+          assign odt_array[odt_pin]    = { 32 { win_odt_pat[ odt_pin ] } } & win_odt_pulse;
+    
+          // Qualify with tranSendC
+          assign odt_transent[odt_pin] = { 32 { tranSentC } } & odt_array[ odt_pin ];
+    
+          // Parallel load lower 24 bits of qualified ODT output into shift register
+          assign odt_shift_nxt[odt_pin] = odt_transent[odt_pin][23:0] | { odt_shift[odt_pin][15:0], 8'b0 };
+    
+          // Combine the upper 8 bits of the odt output for the new transaction (bypass path) with
+          // the upper 8 bits of the shift register output to generate the odt block's output
+          assign odt_reverse[odt_pin] = odt_transent[odt_pin][31:24] | odt_shift[odt_pin][23:16];
+    
+          // Reverse the msb/lsb order.  XiPhy wants increasing time going from lsb to msb
+          assign mc_ODT[odt_pin*8+:8] = { odt_reverse[odt_pin][0], odt_reverse[odt_pin][1], odt_reverse[odt_pin][2], odt_reverse[odt_pin][3],
+                                          odt_reverse[odt_pin][4], odt_reverse[odt_pin][5], odt_reverse[odt_pin][6], odt_reverse[odt_pin][7] };
+       end
+    endgenerate
+    
+    
+    // ==========================================================================================
+    // Reset flops
+    // ==========================================================================================
+    
+    integer i;
+    always @(posedge clk) begin
+      if (rst) begin
+        for (i = 0; i < ODTBITS; i = i + 1) begin
+          odt_shift[i] <= #TCQ 28'b0;
+        end
+      end else begin
+        for (i = 0; i < ODTBITS; i = i + 1) begin
+          odt_shift[i] <= #TCQ odt_shift_nxt[i];
+        end
+      end
+    end
+    
+endmodule
\ No newline at end of file
diff --git a/projects/U200/verilog/project.vh b/projects/U200/verilog/project.vh
new file mode 100644
index 0000000..8286cbd
--- /dev/null
+++ b/projects/U200/verilog/project.vh
@@ -0,0 +1,31 @@
+`define UDIMM_x8
+
+`ifdef UDIMM_x8
+
+    `define DQ_WIDTH 64
+    `define ODT_WIDTH 2
+    `define CS_WIDTH 2
+    `define CKE_WIDTH 2
+    `define CK_WIDTH 1
+    `define ROW_ADDR_WIDTH 17
+
+`elsif RDIMM_x8
+
+    `define DQ_WIDTH   72
+    `define ODT_WIDTH  2
+    `define CS_WIDTH   2
+    `define CKE_WIDTH  2
+    `define CK_WIDTH   1
+    `define ROW_ADDR_WIDTH 17
+    
+`elsif RDIMM_x4
+
+    `define DQ_WIDTH   72
+    `define ODT_WIDTH  2
+    `define CS_WIDTH   2
+    `define CKE_WIDTH  2
+    `define CK_WIDTH   1
+    `define ROW_ADDR_WIDTH 18
+    
+`endif
+
diff --git a/projects/U200/verilog/softmc_top.v b/projects/U200/verilog/softmc_top.v
new file mode 100644
index 0000000..6d6dfcd
--- /dev/null
+++ b/projects/U200/verilog/softmc_top.v
@@ -0,0 +1,737 @@
+`include "parameters.vh"
+`include "project.vh"
+
+module softmc_top #(parameter tCK = 1500, SIM = "false")
+  (
+  // common signals
+  input c0_sys_clk_p,
+  input c0_sys_clk_n,
+  input sys_rst_l,
+  
+  // iob <> ddr4 sdram ip signals
+  output             c0_ddr4_act_n,
+  output [`ROW_ADDR_WIDTH-1:0]      c0_ddr4_adr,
+  output [1:0]       c0_ddr4_ba,
+  output [1:0]       c0_ddr4_bg,
+  output [`CKE_WIDTH-1:0]       c0_ddr4_cke,
+  output [`ODT_WIDTH-1:0]       c0_ddr4_odt,
+  output [`CS_WIDTH-1:0]        c0_ddr4_cs_n,
+  output [`CK_WIDTH-1:0]       c0_ddr4_ck_t,
+  output [`CK_WIDTH-1:0]       c0_ddr4_ck_c,
+  output             c0_ddr4_reset_n,
+
+  `ifdef RDIMM_x4
+  inout  [17:0]      c0_ddr4_dqs_c,
+  inout  [17:0]      c0_ddr4_dqs_t,
+  inout  [71:0]      c0_ddr4_dq,
+  output             c0_ddr4_parity,
+  `elsif UDIMM_x8
+  inout  [7:0]      c0_ddr4_dqs_c,
+  inout  [7:0]      c0_ddr4_dqs_t,
+  inout  [63:0]     c0_ddr4_dq,
+  inout  [7:0]      c0_ddr4_dm_dbi_n,  
+  output            c0_ddr4_parity,
+  `elsif RDIMM_x8
+  inout  [8:0]      c0_ddr4_dqs_c,
+  inout  [8:0]      c0_ddr4_dqs_t,
+  inout  [71:0]     c0_ddr4_dq,
+  inout  [8:0]      c0_ddr4_dm_dbi_n,
+  output            c0_ddr4_parity,  
+  `endif
+  // xdma signals
+  input clk_ref_p,
+  input clk_ref_n,
+  input pcie_rst,
+  output  [7:0]    pci_exp_txp,
+  output  [7:0]    pci_exp_txn,
+  input   [7:0]    pci_exp_rxp,
+  input   [7:0]    pci_exp_rxn
+
+  );
+  
+  `ifdef RDIMM_x4
+  assign c0_ddr4_odt[1] = 1'b0;
+  assign c0_ddr4_cs_n[1] = 1'b1;
+  assign c0_ddr4_cke[1] = 1'b0;
+  `elsif RDIMM_x8
+  assign c0_ddr4_odt[1] = 1'b0;
+  assign c0_ddr4_cs_n[1] = 1'b1;
+  assign c0_ddr4_cke[1] = 1'b0;
+  //assign c0_ddr4_parity = 1'b0;
+  `elsif UDIMM_x8
+  assign c0_ddr4_odt[1] = 1'b0;
+  assign c0_ddr4_cs_n[1] = 1'b1;
+  assign c0_ddr4_cke[1] = 1'b0;
+  assign c0_ddr4_parity = 1'b0;
+  `endif
+  // Frontend control signals
+  wire softmc_fin;
+  wire user_rst;  
+  
+  // Frontend <-> Fetch signals
+  wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_in;
+  wire                        fr_valid_in;
+  wire [`INSTR_WIDTH-1:0]     fr_data_out;
+  wire                        fr_valid_out;
+  wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_out;
+  wire                        fr_ready_out;
+
+  // Frontend <-> misc. control signals
+  wire                        per_rd_init;
+  wire                        per_zq_init;
+  wire                        per_ref_init;
+  wire                        rbe_switch_mode;
+  wire                        toggle_dll;  
+
+  // AXI streaming ports
+  wire [`XDMA_AXI_DATA_WIDTH-1:0]   m_axis_h2c_tdata_0,xdma_h2c_tdata_0;
+  wire                              m_axis_h2c_tlast_0, xdma_h2c_tlast_0;
+  wire                              m_axis_h2c_tvalid_0, xdma_h2c_tvalid_0;
+  wire                              m_axis_h2c_tready_0, xdma_h2c_tready_0;
+  wire [`XDMA_AXI_DATA_WIDTH/8-1:0] m_axis_h2c_tkeep_0, xdma_h2c_tkeep_0;
+  wire [`XDMA_AXI_DATA_WIDTH-1:0]   s_axis_c2h_tdata_0, xdma_c2h_tdata_0; 
+  wire                              s_axis_c2h_tlast_0, xdma_c2h_tlast_0;
+  wire                              s_axis_c2h_tvalid_0, xdma_c2h_tvalid_0;
+  wire                              s_axis_c2h_tready_0, xdma_c2h_tready_0;
+  wire [`XDMA_AXI_DATA_WIDTH/8-1:0] s_axis_c2h_tkeep_0, xdma_c2h_tkeep_0;
+ 
+  // ddr_pipeline <-> outer module if
+  wire [3:0]                ddr_write;
+  wire [3:0]                ddr_read;
+  wire [3:0]                ddr_pre;
+  wire [3:0]                ddr_act;
+  wire [3:0]                ddr_ref;
+  wire [3:0]                ddr_zq;
+  wire [3:0]                ddr_nop;
+  wire [3:0]                ddr_ap;
+  wire [3:0]                ddr_pall;
+  wire [3:0]                ddr_half_bl;
+  wire [4*`BG_WIDTH-1:0]    ddr_bg;
+  wire [4*`BANK_WIDTH-1:0]  ddr_bank;
+  wire [4*`COL_WIDTH-1:0]   ddr_col;
+  wire [4*`ROW_WIDTH-1:0]   ddr_row;
+  wire [511:0]              ddr_wdata;
+ 
+  // periodic maintenance signals
+  wire                      ddr_maint_read;
+ 
+  // phy <-> ddr adapter and xdma app signals
+  // dlltoggler
+  wire                      clk_sel = 0;
+  wire [7:0]                dllt_mc_ACT_n;
+  wire [135:0]              dllt_mc_ADR;
+  wire [15:0]               dllt_mc_BA;
+  wire [15:0]               dllt_mc_BG;
+  wire [7:0]                dllt_mc_CKE;
+  wire [7:0]                dllt_mc_CS_n;
+  wire                      dllt_done;
+  // ddr adapter 
+  wire [4:0]                dBufAdr;
+  wire [`DQ_WIDTH*8-1:0]    wrData;
+  wire [`DQ_WIDTH-1:0]      wrDataMask;
+  wire [511:0]              rdData;
+  wire [4:0]                rdDataAddr;
+  wire [0:0]                rdDataEn;
+  wire [0:0]                rdDataEnd;
+  wire [0:0]                per_rd_done;
+  wire [0:0]                rmw_rd_done;
+  wire [4:0]                wrDataAddr;
+  wire [0:0]                wrDataEn;
+  wire [7:0]                mc_ACT_n;
+  wire [135:0]              mc_ADR;
+  wire [15:0]               mc_BA;
+  wire [15:0]               mc_BG;
+  wire [`CKE_WIDTH*8-1:0]                mc_CKE;
+  wire [`CS_WIDTH*8-1:0]                mc_CS_n;
+  wire [`ODT_WIDTH*8-1:0]                mc_ODT;
+  wire [0:0]                mcRdCAS;
+  wire [0:0]                mcWrCAS;
+  wire [0:0]                winInjTxn;
+  wire [0:0]                winRmw;
+  wire [4:0]                winBuf;
+  wire [1:0]                winRank;
+  wire [5:0]                tCWL;
+  wire                      dbg_clk;
+  wire                      c0_wr_rd_complete;
+  wire                      c0_ddr4_clk;
+  wire                      c0_ddr4_dll_off_clk;
+  wire                      ddr4_ui_clk;
+  wire                      c0_ddr4_rst;
+  wire [511:0]              dbg_bus;        
+  wire [1:0]                mcCasSlot;
+  wire                      mcCasSlot2;
+  wire                      gt_data_ready;
+  
+  wire         read_seq_incoming; // next few instructions will read from DRAM
+  wire [11:0]  incoming_reads;    // how many reads next few instructions will issue
+  wire [11:0]  buffer_space;      // remaining buffer size
+ 
+  wire sys_rst = ~sys_rst_l; // low active signal
+  wire c0_init_calib_complete;
+  
+  // There is a possibility that these signals are on
+  // the critical path as observed in 
+  // the previous iteration of SoftMC
+  reg c0_init_calib_complete_r, sys_rst_r;
+  wire iq_full, processing_iseq, rdback_fifo_empty;
+  
+  always @(posedge c0_ddr4_clk) begin
+    c0_init_calib_complete_r <= c0_init_calib_complete;
+    sys_rst_r <= sys_rst;  
+  end
+  
+  reg dllt_active = 1'b0;
+  
+  `ifdef ENABLE_DLL_TOGGLER
+  always @(posedge c0_ddr4_clk) begin
+    if(toggle_dll) begin
+      dllt_active <= ~dllt_active;
+    end
+    if(dllt_done) begin
+      dllt_active <= ~dllt_active;
+    end
+  end
+  `endif
+
+  `ifdef RDIMM_x4
+  phy_ddr4 phy_ddr4_i(
+    .sys_rst                  (sys_rst),
+    .c0_sys_clk_p             (c0_sys_clk_p),
+    .c0_sys_clk_n             (c0_sys_clk_n),
+    
+    `ifdef ENABLE_DLL_TOGGLER
+    .c0_ddr4_ui_clk           (ddr4_ui_clk),
+    .addn_ui_clkout1          (c0_ddr4_dll_off_clk),
+    `else
+    .c0_ddr4_ui_clk           (c0_ddr4_clk),
+    `endif
+    .c0_ddr4_ui_clk_sync_rst  (c0_ddr4_rst),
+    .c0_init_calib_complete   (c0_init_calib_complete),
+    .dbg_clk                  (dbg_clk),
+    .c0_ddr4_act_n            (c0_ddr4_act_n),
+    .c0_ddr4_adr              (c0_ddr4_adr),
+    .c0_ddr4_ba               (c0_ddr4_ba),
+    .c0_ddr4_bg               (c0_ddr4_bg),
+    .c0_ddr4_cke              (c0_ddr4_cke[0]),
+    .c0_ddr4_odt              (c0_ddr4_odt[0]),
+    .c0_ddr4_cs_n             (c0_ddr4_cs_n[0]),
+    .c0_ddr4_ck_t             (c0_ddr4_ck_t),
+    .c0_ddr4_ck_c             (c0_ddr4_ck_c),
+    .c0_ddr4_reset_n          (c0_ddr4_reset_n),
+    .c0_ddr4_parity            (c0_ddr4_parity),
+    .c0_ddr4_dq               (c0_ddr4_dq),
+    .c0_ddr4_dqs_c            (c0_ddr4_dqs_c),
+    .c0_ddr4_dqs_t            (c0_ddr4_dqs_t),
+    
+    .dBufAdr                  (dBufAdr),
+    .wrData                   (wrData),
+    .rdData                   (rdData),
+    .rdDataAddr               (rdDataAddr),
+    .rdDataEn                 (rdDataEn),
+    .rdDataEnd                (rdDataEnd),
+    .per_rd_done              (per_rd_done),
+    .rmw_rd_done              (rmw_rd_done),
+    .wrDataAddr               (wrDataAddr),
+    .wrDataEn                 (wrDataEn),
+    
+    .mc_ACT_n                 (dllt_active ? dllt_mc_ACT_n : mc_ACT_n),
+    .mc_ADR                   (dllt_active ? dllt_mc_ADR : mc_ADR),
+    .mc_BA                    (dllt_active ? dllt_mc_BA : mc_BA),
+    .mc_BG                    (dllt_active ? dllt_mc_BG : mc_BG),
+    // DRAM CKE. 8 bits for each DRAM pin. The mc_CKE signal is always set to '1'.
+    .mc_CKE                   (dllt_active ? dllt_mc_CKE : {8{1'b1}}),
+    .mc_CS_n                  (dllt_active ? dllt_mc_CS_n : mc_CS_n),
+    .mc_ODT                   (mc_ODT),
+    // CAS command slot select. Slot0 is enabled for example design.
+    .mcCasSlot                (dllt_active ? 0 : mcCasSlot),
+    // CAS slot 2 select.  mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing 
+    // critical logic in the Phy. Slot0 is enabled for example design.
+    .mcCasSlot2               (dllt_active ? 0 : mcCasSlot2),
+    .mcRdCAS                  (dllt_active ? 0 : mcRdCAS),
+    .mcWrCAS                  (dllt_active ? 0 : mcWrCAS),
+    // Optional read command type indication. The winInjTxn signal is set to '0' for example design.
+    .winInjTxn                ({1{1'b0}}),
+    // Optional read command type indication. The winRmw signal is set to '0' for example design.
+    .winRmw                   ({1{1'b0}}),
+    // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design.
+    // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift.
+    // For more information, Refer to PG150 document.
+    .gt_data_ready            (gt_data_ready),
+    .winBuf                   (winBuf),
+    .winRank                  (winRank),
+    .tCWL                     (tCWL),
+    // Debug Port
+    .dbg_bus                  (dbg_bus)                                    
+  );
+  `elsif UDIMM_x8
+   phy_ddr4_udimm phy_ddr4_i(
+    .sys_rst                  (sys_rst),
+    .c0_sys_clk_p             (c0_sys_clk_p),
+    .c0_sys_clk_n             (c0_sys_clk_n),
+  
+    `ifdef ENABLE_DLL_TOGGLER
+    .c0_ddr4_ui_clk           (ddr4_ui_clk),
+    .addn_ui_clkout1          (c0_ddr4_dll_off_clk),
+    `else
+    .c0_ddr4_ui_clk           (c0_ddr4_clk),
+    `endif
+    .c0_ddr4_ui_clk_sync_rst  (c0_ddr4_rst),
+    .c0_init_calib_complete   (c0_init_calib_complete),
+    .dbg_clk                  (dbg_clk),
+    .c0_ddr4_act_n            (c0_ddr4_act_n),
+    .c0_ddr4_adr              (c0_ddr4_adr),
+    .c0_ddr4_ba               (c0_ddr4_ba),
+    .c0_ddr4_bg               (c0_ddr4_bg),
+    .c0_ddr4_cke              (c0_ddr4_cke),
+    .c0_ddr4_odt              (c0_ddr4_odt),
+    .c0_ddr4_cs_n             (c0_ddr4_cs_n),
+    .c0_ddr4_ck_t             (c0_ddr4_ck_t),
+    .c0_ddr4_ck_c             (c0_ddr4_ck_c),
+    .c0_ddr4_reset_n          (c0_ddr4_reset_n),
+    //.ddr4_par              (c0_ddr4_parity),
+    .c0_ddr4_dq               (c0_ddr4_dq),
+    .c0_ddr4_dqs_c            (c0_ddr4_dqs_c),
+    .c0_ddr4_dqs_t            (c0_ddr4_dqs_t),
+    .c0_ddr4_dm_dbi_n         (c0_ddr4_dm_dbi_n),
+  
+    .dBufAdr                  (dBufAdr),
+    .wrData                   (wrData),
+    .rdData                   (rdData),
+    .rdDataAddr               (rdDataAddr),
+    .rdDataEn                 (rdDataEn),
+    .rdDataEnd                (rdDataEnd),
+    .per_rd_done              (per_rd_done),
+    .rmw_rd_done              (rmw_rd_done),
+    .wrDataAddr               (wrDataAddr),
+    .wrDataEn                 (wrDataEn),
+    .wrDataMask               (wrDataMask),
+    
+    .mc_ACT_n                 (dllt_active ? dllt_mc_ACT_n : mc_ACT_n),
+    .mc_ADR                   (dllt_active ? dllt_mc_ADR : mc_ADR),
+    .mc_BA                    (dllt_active ? dllt_mc_BA : mc_BA),
+    .mc_BG                    (dllt_active ? dllt_mc_BG : mc_BG),
+    // DRAM CKE. 8 bits for each DRAM pin. The mc_CKE signal is always set to '1'.
+    .mc_CKE                   (dllt_active ? dllt_mc_CKE : {8{1'b1}}),
+    .mc_CS_n                  (dllt_active ? dllt_mc_CS_n : mc_CS_n),
+    .mc_ODT                   (mc_ODT),
+    // CAS command slot select. Slot0 is enabled for example design.
+    .mcCasSlot                (dllt_active ? 0 : mcCasSlot),
+    // CAS slot 2 select.  mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing 
+    // critical logic in the Phy. Slot0 is enabled for example design.
+    .mcCasSlot2               (dllt_active ? 0 : mcCasSlot2),
+    .mcRdCAS                  (dllt_active ? 0 : mcRdCAS),
+    .mcWrCAS                  (dllt_active ? 0 : mcWrCAS),
+    // Optional read command type indication. The winInjTxn signal is set to '0' for example design.
+    .winInjTxn                ({1{1'b0}}),
+    // Optional read command type indication. The winRmw signal is set to '0' for example design.
+    .winRmw                   ({1{1'b0}}),
+    // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design.
+    // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift.
+    // For more information, Refer to PG150 document.
+    .gt_data_ready            (gt_data_ready),
+    .winBuf                   (winBuf),
+    .winRank                  (winRank),
+    .tCWL                     (tCWL),
+    // Debug Port
+    .dbg_bus                  (dbg_bus)                                    
+  );
+  `elsif RDIMM_x8
+   phy_rdimm_x8_dual phy_ddr4_i(
+    .sys_rst                  (sys_rst),
+    .c0_sys_clk_p             (c0_sys_clk_p),
+    .c0_sys_clk_n             (c0_sys_clk_n),
+    
+    `ifdef ENABLE_DLL_TOGGLER
+    .c0_ddr4_ui_clk           (ddr4_ui_clk),
+    .addn_ui_clkout1          (c0_ddr4_dll_off_clk),
+    `else
+    .c0_ddr4_ui_clk           (c0_ddr4_clk),
+    `endif
+    .c0_ddr4_ui_clk_sync_rst  (c0_ddr4_rst),
+    .c0_init_calib_complete   (c0_init_calib_complete),
+    .dbg_clk                  (dbg_clk),
+    .c0_ddr4_act_n            (c0_ddr4_act_n),
+    .c0_ddr4_adr              (c0_ddr4_adr),
+    .c0_ddr4_ba               (c0_ddr4_ba),
+    .c0_ddr4_bg               (c0_ddr4_bg),
+    .c0_ddr4_cke              (c0_ddr4_cke[0]),
+    .c0_ddr4_odt              (c0_ddr4_odt[0]),
+    .c0_ddr4_cs_n             (c0_ddr4_cs_n[0]),
+    .c0_ddr4_ck_t             (c0_ddr4_ck_t),
+    .c0_ddr4_ck_c             (c0_ddr4_ck_c),
+    .c0_ddr4_reset_n          (c0_ddr4_reset_n),
+    .c0_ddr4_parity           (c0_ddr4_parity),
+    .c0_ddr4_dq               (c0_ddr4_dq),
+    .c0_ddr4_dqs_c            (c0_ddr4_dqs_c),
+    .c0_ddr4_dqs_t            (c0_ddr4_dqs_t),
+    .c0_ddr4_dm_dbi_n         (c0_ddr4_dm_dbi_n),
+    
+    .dBufAdr                  (dBufAdr),
+    .wrData                   (wrData),
+    .rdData                   (rdData),
+    .rdDataAddr               (rdDataAddr),
+    .rdDataEn                 (rdDataEn),
+    .rdDataEnd                (rdDataEnd),
+    .per_rd_done              (per_rd_done),
+    .rmw_rd_done              (rmw_rd_done),
+    .wrDataAddr               (wrDataAddr),
+    .wrDataEn                 (wrDataEn),
+    .wrDataMask               (wrDataMask),
+    
+    .mc_ACT_n                 (dllt_active ? dllt_mc_ACT_n : mc_ACT_n),
+    .mc_ADR                   (dllt_active ? dllt_mc_ADR : mc_ADR),
+    .mc_BA                    (dllt_active ? dllt_mc_BA : mc_BA),
+    .mc_BG                    (dllt_active ? dllt_mc_BG : mc_BG),
+    // DRAM CKE. 8 bits for each DRAM pin. The mc_CKE signal is always set to '1'.
+    .mc_CKE                   (dllt_active ? dllt_mc_CKE : {8{1'b1}}),
+    .mc_CS_n                  (dllt_active ? dllt_mc_CS_n : mc_CS_n),
+    .mc_ODT                   (mc_ODT),
+    // CAS command slot select. Slot0 is enabled for example design.
+    .mcCasSlot                (dllt_active ? 0 : mcCasSlot),
+    // CAS slot 2 select.  mcCasSlot2 serves a similar purpose as the mcCasSlot[1:0] signal, but mcCasSlot2 is used in timing 
+    // critical logic in the Phy. Slot0 is enabled for example design.
+    .mcCasSlot2               (dllt_active ? 0 : mcCasSlot2),
+    .mcRdCAS                  (dllt_active ? 0 : mcRdCAS),
+    .mcWrCAS                  (dllt_active ? 0 : mcWrCAS),
+    // Optional read command type indication. The winInjTxn signal is set to '0' for example design.
+    .winInjTxn                ({1{1'b0}}),
+    // Optional read command type indication. The winRmw signal is set to '0' for example design.
+    .winRmw                   ({1{1'b0}}),
+    // Update VT Tracking. The gt_data_ready signal is set to '0' in this example design.
+    // This signal must be asserted periodically to keep the DQS Gate aligned as voltage and temperature drift.
+    // For more information, Refer to PG150 document.
+    .gt_data_ready            (gt_data_ready),
+    .winBuf                   (winBuf),
+    .winRank                  (winRank),
+    .tCWL                     (tCWL),
+    // Debug Port
+    .dbg_bus                  (dbg_bus)                                    
+  );  
+  `endif
+  
+  
+  softmc_pipeline pipeline(
+    .clk(c0_ddr4_clk),
+    .rst(c0_ddr4_rst || user_rst),
+   
+    .softmc_end(softmc_fin),
+    .read_size(incoming_reads),
+    .read_seq_incoming(read_seq_incoming),
+    .buffer_space(buffer_space),
+    
+    .addr_out(fr_addr_in),
+    .valid_out(fr_valid_in),
+    .data_in(fr_data_out),
+    .valid_in(fr_valid_out),
+    .addr_in(fr_addr_out),
+    .ready_out(fr_ready_out),
+   
+    .ddr_write(ddr_write),  
+    .ddr_read(ddr_read),  
+    .ddr_pre(ddr_pre),    
+    .ddr_act(ddr_act),    
+    .ddr_ref(ddr_ref),    
+    .ddr_zq(ddr_zq),    
+    .ddr_nop(ddr_nop),    
+    .ddr_ap(ddr_ap),    
+    .ddr_pall(ddr_pall),    
+    .ddr_half_bl(ddr_half_bl),
+    .ddr_bg(ddr_bg),    
+    .ddr_bank(ddr_bank),  
+    .ddr_col(ddr_col),    
+    .ddr_row(ddr_row),    
+    .ddr_wdata(ddr_wdata)
+  );
+ 
+  `ifdef ENABLE_DLL_TOGGLER
+  //BUFGMUX:GeneralClockMuxBuffer
+  //UltraScale
+  //XilinxHDLLibrariesGuide, version2014.4
+  BUFGMUX#(.CLK_SEL_TYPE("SYNC")  //ASYNC,SYNC
+  )BUFGMUX_inst(
+    .O(c0_ddr4_clk),        //1-bitoutput:Clockoutput
+    .I0(ddr4_ui_clk),    //1-bitinput:Clockinput(S=0)
+    .I1(c0_ddr4_dll_off_clk),   //1-bitinput:Clockinput(S=1)
+    .S(clk_sel)            //1-bitinput:Clockselect
+    );
+    //End of BUFGMUX_inst instantiation
+  `endif
+ 
+ 
+  wire frontend_ready;
+  
+  frontend #(.SIM_MEM(SIM)) frontend(
+    .clk(c0_ddr4_clk),
+    .rst(c0_ddr4_rst),
+    
+    .init_calib_complete(c0_init_calib_complete_r),
+    .softmc_fin(softmc_fin),
+    .user_rst(user_rst),
+   
+    .dllt_begin(toggle_dll),
+   
+    // indicates read_back unit is ready for the next iseq
+    .frontend_ready(frontend_ready),
+   
+    // frontend <-> fetch stage if
+    .addr_in(fr_addr_in),
+    .valid_in(fr_valid_in),
+    .data_out(fr_data_out),
+    .valid_out(fr_valid_out),
+    .addr_out(fr_addr_out),
+    .ready_in(fr_ready_out),
+    
+    // frontend <-> xdma interface
+    .h2c_tdata_0(m_axis_h2c_tdata_0),
+    .h2c_tlast_0(m_axis_h2c_tlast_0),
+    .h2c_tvalid_0(m_axis_h2c_tvalid_0),
+    .h2c_tready_0(m_axis_h2c_tready_0),
+    .h2c_tkeep_0(m_axis_h2c_tkeep_0),
+    
+    .per_rd_init(per_rd_init),
+    .per_zq_init(per_zq_init),
+    .per_ref_init(per_ref_init),
+    .rbe_switch_mode(rbe_switch_mode)
+  );
+
+  ddr4_adapter#(
+    .DQ_WIDTH(`DQ_WIDTH)
+  ) ddr4_adapter
+  (
+   .clk(c0_ddr4_clk),
+   .rst(c0_ddr4_rst || user_rst),
+   .init_calib_complete(c0_init_calib_complete_r),
+   //.io_config_strobe,
+   //.io_config,
+   .dBufAdr(dBufAdr),   // Reserved. Should be tied low.
+   .wrData(wrData),    // DRAM write data. There are 8 bits for each DQ lane on the DRAM bus.
+   .wrDataMask(wrDataMask),// DRAM write DM/DBI port.There is one bit for each byte of the wrData port.
+   .wrDataEn(wrDataEn),  // Write data Enable. The Phy will assert this port for one cycle for each write CAS command.
+   .mc_ACT_n(mc_ACT_n),  // DRAM ACT_n command signal for four DRAM clock cycles.
+   .mc_ADR(mc_ADR),    // DRAM address. There are 8 bits in the fabric interface for each address bit on the DRAM bus.
+   .mc_BA(mc_BA),     // DRAM bank address. 8 bits for each DRAM bank address.
+   .mc_BG(mc_BG),     // DRAM bank group address.
+   .mc_CS_n(mc_CS_n),   // DRAM CS_n
+   //.mc_ODT(mc_ODT),    // DRAM ODT
+   .mcRdCAS(mcRdCAS),   // Read CAS command issued.
+   .mcWrCAS(mcWrCAS),   // Write CAS command issued.
+   .winRank(winRank),   // Target rank for CAS commands. This value indicates which rank a CAS command is issued to.
+   .winBuf(winBuf),    // Optional control signal. When either mcRdCAS or mcWrCAS is asserted, the Phy will store the value on the winBuf signal.  
+   //.rdData(rdData),    // DRAM read data.
+   .rdDataEn(rdDataEn),  // Read data valid. This signal asserts for one fabric cycle for each completed read operation.
+   .rdDataEnd(rdDataEnd),  // Unused.  Tied high.
+   .mcCasSlot(mcCasSlot),
+   .mcCasSlot2(mcCasSlot2),
+   .gt_data_ready(gt_data_ready),
+   .ddr_write(ddr_write),  
+   .ddr_read(ddr_read),  
+   .ddr_pre(ddr_pre),    
+   .ddr_act(ddr_act),    
+   .ddr_ref(ddr_ref),    
+   .ddr_zq(ddr_zq),    
+   .ddr_nop(ddr_nop),    
+   .ddr_ap(ddr_ap),    
+   .ddr_pall(ddr_pall),    
+   .ddr_half_bl(ddr_half_bl),
+   .ddr_bg(ddr_bg),    
+   .ddr_bank(ddr_bank),  
+   .ddr_col(ddr_col),    
+   .ddr_row(ddr_row),    
+   .ddr_wdata(ddr_wdata),
+ 
+   .ddr_maint_read(per_rd_init)
+  );
+  
+    localparam          ODTWRDEL                = 5'd9;
+    localparam          ODTWRDUR                = 4'd6;
+    localparam          ODTWRODEL               = 5'd9;
+    localparam          ODTWRODUR               = 4'd6;
+    localparam          ODTRDDEL                = 5'd10;
+    localparam          ODTRDDUR                = 4'd6;
+    localparam          ODTRDODEL               = 5'd9;
+    localparam          ODTRDODUR               = 4'd6;
+    localparam          ODTNOP                  = 16'h0000;
+    localparam        ODTWR                     = 16'h0001;
+    localparam        ODTRD                     = 16'h0000; 
+    
+    wire tranSentC;
+    assign tranSentC = mcRdCAS | mcWrCAS;
+ 
+  //synthesis translate_on
+  //*******************************************************************************
+  ddr4_mc_odt # (
+    .ODTWR     (ODTWR)
+    ,.ODTWRDEL  (ODTWRDEL)
+    ,.ODTWRDUR  (ODTWRDUR)
+    ,.ODTWRODEL (ODTWRODEL)
+    ,.ODTWRODUR (ODTWRODUR)
+   
+    ,.ODTRD     (ODTRD)
+    ,.ODTRDDEL  (ODTRDDEL)
+    ,.ODTRDDUR  (ODTRDDUR)
+    ,.ODTRDODEL (ODTRDODEL)
+    ,.ODTRDODUR (ODTRDODUR)
+   
+    ,.ODTNOP    (ODTNOP)
+    ,.ODTBITS   (`ODT_WIDTH)
+    ,.TCQ       (0.1)
+  )u_ddr_tb_odt(
+    .clk       (c0_ddr4_clk)
+    ,.rst       (c0_ddr4_rst)
+    ,.mc_ODT    (mc_ODT)
+    ,.casSlot   (mcCasSlot)
+    ,.casSlot2  (mcCasSlot2)
+    ,.rank      (winRank)
+    ,.winRead   (mcRdCAS)
+    ,.winWrite  (mcWrCAS)
+    ,.tranSentC (tranSentC)
+  );
+ 
+  wire sys_clk, sys_clk_gt;
+  wire [2:0]    msi_vector_width;
+  wire          msi_enable;
+  wire          user_lnk_up, usr_irq_req, usr_irq_ack;
+
+  IBUFDS_GTE4 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(clk_ref_p), .CEB(1'b0), .IB(clk_ref_n));
+
+  wire axi_clk, axi_rst;
+  
+  xdma xdma_i 
+  (
+    //---------------------------------------------------------------------------------------//
+    //  PCI Express (pci_exp) Interface                                                      //
+    //---------------------------------------------------------------------------------------//
+    .sys_rst_n       ( pcie_rst ),
+    .sys_clk         ( sys_clk ),
+    .sys_clk_gt      ( sys_clk_gt),
+    
+    // Tx
+    .pci_exp_txn     ( pci_exp_txn ),
+    .pci_exp_txp     ( pci_exp_txp ),
+    
+    // Rx
+    .pci_exp_rxn     ( pci_exp_rxn ),
+    .pci_exp_rxp     ( pci_exp_rxp ),
+    
+    // AXI streaming ports
+    .s_axis_c2h_tdata_0(xdma_c2h_tdata_0),  
+    .s_axis_c2h_tlast_0(xdma_c2h_tlast_0),
+    .s_axis_c2h_tvalid_0(xdma_c2h_tvalid_0), 
+    .s_axis_c2h_tready_0(xdma_c2h_tready_0),
+    .s_axis_c2h_tkeep_0(xdma_c2h_tkeep_0),
+    .m_axis_h2c_tdata_0(xdma_h2c_tdata_0),
+    .m_axis_h2c_tlast_0(xdma_h2c_tlast_0),
+    .m_axis_h2c_tvalid_0(xdma_h2c_tvalid_0),
+    .m_axis_h2c_tready_0(xdma_h2c_tready_0),
+    .m_axis_h2c_tkeep_0(xdma_h2c_tkeep_0),
+    
+    .usr_irq_req       (1'b0),
+    .usr_irq_ack       (usr_irq_ack),
+    .msi_enable        (msi_enable),
+    .msi_vector_width  (msi_vector_width),
+    
+    
+    // Config managemnet interface
+    .cfg_mgmt_addr  ( 19'b0 ),
+    .cfg_mgmt_write ( 1'b0 ),
+    .cfg_mgmt_write_data ( 32'b0 ),
+    .cfg_mgmt_byte_enable ( 4'b0 ),
+    .cfg_mgmt_read  ( 1'b0 ),
+    .cfg_mgmt_read_data (),
+    .cfg_mgmt_read_write_done (),
+
+    
+    //-- AXI Global
+    .axi_aclk        (axi_clk), // AXI i-face clock driven from pcie clk
+    .axi_aresetn     (axi_rst), // reset synchronous to axi_clk
+    
+    .user_lnk_up     ( user_lnk_up )
+  );
+  
+    // Clock converter for the c2h interface
+  axis_clock_converter axis_clk_conv_i0
+  (
+    .s_axis_tvalid(s_axis_c2h_tvalid_0),
+    .s_axis_tlast(s_axis_c2h_tlast_0),
+    .s_axis_tdata(s_axis_c2h_tdata_0),
+    .s_axis_tkeep(s_axis_c2h_tkeep_0),
+    .s_axis_tready(s_axis_c2h_tready_0),
+    .m_axis_tvalid(xdma_c2h_tvalid_0),
+    .m_axis_tlast(xdma_c2h_tlast_0),
+    .m_axis_tdata(xdma_c2h_tdata_0),
+    .m_axis_tkeep(xdma_c2h_tkeep_0),
+    .m_axis_tready(xdma_c2h_tready_0),
+    .s_axis_aresetn(~c0_ddr4_rst),
+    .s_axis_aclk(c0_ddr4_clk),
+    .m_axis_aresetn(axi_rst),
+    .m_axis_aclk(axi_clk)
+  );
+  
+  // Clock converter for the h2c interface
+  axis_clock_converter axis_clk_conv_i1
+  (
+    .m_axis_tvalid(m_axis_h2c_tvalid_0),
+    .m_axis_tlast(m_axis_h2c_tlast_0),
+    .m_axis_tdata(m_axis_h2c_tdata_0),
+    .m_axis_tkeep(m_axis_h2c_tkeep_0),
+    .m_axis_tready(m_axis_h2c_tready_0),
+    .s_axis_tvalid(xdma_h2c_tvalid_0),
+    .s_axis_tlast(xdma_h2c_tlast_0),
+    .s_axis_tdata(xdma_h2c_tdata_0),
+    .s_axis_tkeep(xdma_h2c_tkeep_0),
+    .s_axis_tready(xdma_h2c_tready_0),
+    .m_axis_aresetn(~c0_ddr4_rst),
+    .m_axis_aclk(c0_ddr4_clk),
+    .s_axis_aresetn(axi_rst),
+    .s_axis_aclk(axi_clk)
+  );
+  
+  readback_engine rbe(
+    
+  // common signals
+  .clk(c0_ddr4_clk),
+  .rst(c0_ddr4_rst || user_rst),
+  
+  // other ctrl signals
+  .flush(frontend_ready),
+  .switch_mode(rbe_switch_mode),
+  .read_seq_incoming(read_seq_incoming), // next few instructions will read from DRAM
+  .incoming_reads(incoming_reads),    // how many reads next few instructions will issue
+  .buffer_space(buffer_space),      // remaining buffer size
+  // DRAM <-> engine if
+  .rd_data(rdData),
+  .rd_valid(rdDataEn),
+   
+  // rbe <-> rf interface  
+  .ddr_wdata(ddr_wdata),
+  
+  .per_rd_init(per_rd_init),
+  .per_zq_init(per_zq_init),
+  .per_ref_init(per_ref_init),
+  
+  // rbe <-> xdma if
+  .c2h_tdata_0(s_axis_c2h_tdata_0),  
+  .c2h_tlast_0(s_axis_c2h_tlast_0),
+  .c2h_tvalid_0(s_axis_c2h_tvalid_0),
+  .c2h_tready_0(s_axis_c2h_tready_0),
+  .c2h_tkeep_0(s_axis_c2h_tkeep_0)
+  
+  );
+
+  `ifdef ENABLE_DLL_TOGGLER
+  dll_toggler dllt
+   (
+     .clk(c0_ddr4_clk),
+     .rst(c0_ddr4_rst || user_rst || ~c0_init_calib_complete_r),
+     .toggle_valid(toggle_dll),
+     .mc_ACT_n(dllt_mc_ACT_n),  // DRAM ACT_n command signal for four DRAM clock cycles.
+     .mc_ADR(dllt_mc_ADR),    // DRAM address. There are 8 bits in the fabric interface for each address bit on the DRAM bus.
+     .mc_BA(dllt_mc_BA),     // DRAM bank address. 8 bits for each DRAM bank address.
+     .mc_BG(dllt_mc_BG),     // DRAM bank group address.
+     .mc_CS_n(dllt_mc_CS_n),   // DRAM CS_n    
+     .mc_CKE(dllt_mc_CKE),
+     .clk_sel(clk_sel),
+     .dllt_done(dllt_done)
+   );
+   `endif
+endmodule
-- 
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